ESD protection device with embedded MIM structure and preparation method

Abstract

The invention provides an ESD protection device with an embedded MIM structure. The ESD protection device comprises an ESD structure; and the MIM capacitor structure is positioned on the unused area of the ESD structure. The ESD protection device is a transverse ESD protection device. The MIM capacitor structure comprises an interlayer insulating layer located on the ESD structure and the isolation groove filling area, a contact hole located in the interlayer insulating layer, a contact hole metal filling area for filling the contact hole, a first metal layer located on the interlayer insulating layer, and a dielectric layer which is located on the first metal layer and corresponds to an unused area of the ESD structure. The first metal layer is located on the dielectric layer, the second metal layer is located on the dielectric layer, the third metal layer is located on the second metal layer, the dielectric layer is located on the third metal layer and the first metal layer, the first metal column is located in the dielectric layer, the second metal column is located in the dielectric layer, and the fourth metal layer is located on the dielectric layer. According to the invention, the ESD device has an anti-EMI electromagnetic interference function, and the anti-static impact performance is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to an ESD protection device with an embedded MIM structure and a preparation method thereof. Background Art

[0002] The circuit system is frequently attacked by ESD (electrostatic discharges), which originates from the outside of the circuit system, such as overload current and voltage caused by system power on and off, electrostatic contact, bypass shutdown, etc. It will cause irreversible damage to the circuit system circuits, and the vulnerable components are usually MOS power devices, transistors and integrated circuits (IC). The circuit system is also often harmed by EMI, which will generate spike voltages and electromagnetic interference inside the circuit system, which will also cause irreversible damage to sensitive ICs or affect the normal operation of the circuit.

[0003] ESD protection devices (ESD devices for short) are widely used in circuit protection. ESD devices have large current discharge capabilities and can clamp the voltage within a safe range in a very short time to keep the core circuit in a normal working state.

[0004] Conventional ESD devices protect circuits by connecting the ESD devices in parallel with the protected circuits. When subjected to external electrostatic surges, the diodes reversely break down in a short period of time to provide a large current path, ensuring that the protected circuits can still operate normally. Conventional ESD devices are helpless when large electromagnetic interference (EMI) occurs. Large EMI electromagnetic interference will generate pulsed spike voltages inside the circuit system, impacting the core IC devices in the circuit, and causing irreversible damage to the circuit system over time.

[0005] Conventional ESD devices are usually divided into two structures: vertical structure and horizontal structure. Compared with the vertical structure, the overcurrent capability of the horizontal structure ESD device is generally smaller because the effective area of ​​the horizontal structure ESD device is lower.

[0006] It can be seen that the existing lateral ESD devices in the prior art do not have the ability to resist electromagnetic interference and have low anti-static ability. Summary of the invention

[0007] The invention provides an ESD protection device with an embedded MIM structure and a preparation method thereof, so as to enable the ESD device to have the ability to resist electromagnetic interference and improve the antistatic ability of the ESD device.

[0008] According to a first aspect of the present invention, an ESD protection device with an embedded MIM structure is provided, wherein the ESD protection device is a lateral ESD protection device, comprising:

[0009] ESD structure;

[0010] MIM capacitor structure located on the unused area of ​​the ESD structure.

[0011] Optionally, the ESD protection device is a unidirectional low-capacitance ESD protection device.

[0012] Optionally, the ESD structure includes: a silicon substrate, an N-type epitaxial layer located on the silicon substrate, a P-type lightly doped region located in the N-type epitaxial layer, a first SN region located in the N-type epitaxial layer, a first SP region located in the N-type epitaxial layer, a second SN region located in the P-type lightly doped region, and an isolation trench for avoiding mutual interference between diodes, wherein the isolation trench passes through the N-type epitaxial layer and the bottom of the trench is located in the silicon substrate.

[0013] Optionally, there are two first SN regions, two first SP regions, and two second SN regions, one first SN region and one first SP region are located on one side of the P-type lightly doped region, and are used to form a first diode, another first SN region and another first SP region are located on the other side of the P-type lightly doped region, and are used to form a second diode, and the two second SN regions and the P-type lightly doped region are used to form an avalanche diode.

[0014] Optionally, a first SP region, a first SN region, a second SN region, another second SN region, another first SP region and another first SN region are arranged in sequence, the first SN region is electrically connected to the second SN region, and the another second SN region is electrically connected to the another first SP region.

[0015] Optionally, the MIM capacitor structure includes: an isolation groove filling area that fills the isolation groove, an interlayer insulating layer located on the ESD structure and the isolation groove filling area, a contact hole located in the interlayer insulating layer, a contact hole metal filling area that fills the contact hole, a first metal layer located on the interlayer insulating layer and the contact hole metal filling area, a dielectric layer on the first metal layer and corresponding to an unused area of ​​the ESD structure, an upper plate located on the dielectric layer, a dielectric layer located on the upper plate, a first metal column located in the dielectric layer, a second metal column located in the dielectric layer, a fourth metal layer located on the dielectric layer, and a passivation layer located on the dielectric layer and the fourth metal layer; one end of the contact hole contacts the first SN area, the first SP area, and the second SN area, and the other end of the contact hole contacts the first metal layer, the first metal layer is arranged corresponding to the unused area of ​​the ESD structure and the contact hole metal filling area, the dielectric layer is also located on the interlayer insulating layer, the bottom end of the first metal column contacts the first metal layer, and the top end contacts the fourth metal layer, and the bottom end of the second metal column contacts the upper plate, and the top end contacts the fourth metal layer.

[0016] Optionally, the upper plate includes a second metal layer located on the dielectric layer, and a third metal layer located on the second metal layer, wherein the dielectric layer is located on the third metal layer, and the bottom end of the second metal column contacts the third metal layer.

[0017] Optionally, materials of the first metal layer, the second metal layer, the third metal layer and the fourth metal layer are AlCu, titanium, titanium nitride and AlSiCu respectively.

[0018] Optionally, the materials of the first metal pillar and the second metal pillar both include titanium, titanium nitride and tungsten.

[0019] According to a second aspect of the present invention, a method for preparing an ESD protection device with an embedded MIM structure is provided, comprising:

[0020] preparing an ESD structure;

[0021] A MIM capacitor structure is fabricated on the unused area of ​​the ESD structure.

[0022] Optionally, the preparing the ESD structure includes:

[0023] preparing a P-type silicon substrate;

[0024] Depositing an N-type epitaxial layer on a silicon substrate;

[0025] A first SN region, a first SP region, a second SN region and an isolation trench are formed in the N-type epitaxial layer to form an ESD structure.

[0026] Optionally, forming an SN region, an SP region and an isolation trench in the N-type epitaxial layer to form an ESD structure includes:

[0027] Preparing a P-type well region on the N-type epitaxial layer;

[0028] A P-type lightly doped region located in the N-type epitaxial layer is obtained by heating the P-type well region;

[0029] forming a first SN region, a first SP region, and a second SN region by photolithography and ion implantation;

[0030] An isolation groove is made to form an ESD structure.

[0031] Optionally, preparing a MIM capacitor structure on an unused area of ​​the ESD structure includes:

[0032] Filling the isolation groove to obtain an isolation groove filling area;

[0033] Depositing an interlayer insulating layer to serve as an insulating layer between the ESD structure and the MIM capacitor structure;

[0034] preparing a contact hole, wherein the bottom of the contact hole contacts the first SN region, the first SP region and the second SN region;

[0035] Filling the contact hole to obtain a contact hole metal filling area;

[0036] On the interlayer insulating layer, a first metal layer is prepared corresponding to the unused area of ​​the ESD structure and the metal filling area of ​​the contact hole;

[0037] preparing a third silicon oxide layer to fill the gaps between the first metal layers;

[0038] Depositing a dielectric layer on the first metal layer corresponding to an unused area of ​​the ESD structure;

[0039] Depositing a second metal layer of the upper electrode on the dielectric layer, and depositing a third metal layer on the second metal layer;

[0040] Depositing a fourth silicon oxide layer, the fourth silicon oxide layer is located on the upper plate and the third silicon oxide layer, and preparing a dielectric layer, the dielectric layer includes the third silicon oxide layer and the fourth silicon oxide layer;

[0041] Etching a first VIA hole and a second VIA hole on the dielectric layer, wherein the first VIA hole contacts the first metal layer, and the second VIA hole contacts the third metal layer;

[0042] Filling metal in the first VIA hole to form a first metal column, and filling metal in the second VIA hole to form a second metal column;

[0043] A fourth metal layer is formed on the dielectric layer, wherein the fourth metal layer contacts the top of the first metal column and the top of the second metal column;

[0044] Deposit a passivation layer.

[0045] In the ESD protection device and preparation method with embedded MIM structure provided by the present invention, by adding a structural idea of ​​a MIM capacitor into a conventional ESD device, the MIM capacitor structure is directly prepared on the ESD structure using an unused area, so that the ESD device has the function of anti-EMI electromagnetic interference. Compared with the existing conventional ESD, the effective area of ​​the lateral structure ESD protection device is increased, so the anti-static impact performance is improved, that is, the anti-static performance is improved; the MIM capacitor structure will not increase or increase the area of ​​the die too much, and the area of ​​the ESD protection device with embedded MIM structure of the present invention is smaller than the area of ​​the conventional ESD device in parallel with the existing MIM capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0047] Figure 1 is a circuit schematic diagram of the present invention;

[0048] Figure 2 It is a schematic diagram of the actual layout of the die;

[0049] Figure 3 It is a structural schematic diagram of the ESD structure of the present invention;

[0050] Figure 4 It is a structural schematic diagram of the ESD protection device of the present invention;

[0051] Figure 5 It is a schematic flow diagram of the preparation method of the present invention.

[0052] Description of reference numerals:

[0053] 100 denotes an ESD protection device with an embedded MIM structure, 10 denotes an ESD structure, 11 denotes a silicon substrate, 12 denotes an N-type epitaxial layer, 13 denotes a second N-type heavily doped region, 14 denotes a second P-type heavily doped region, 15 denotes a second SN region, 16 denotes a P-type lightly doped region, 17 denotes an isolation trench, 18 denotes a first N-type heavily doped region, and 19 denotes a first P-type heavily doped region; 21 denotes a contact hole, 22 denotes an interlayer insulating layer, 23 denotes a first metal layer, 24 denotes a dielectric layer, 25 denotes an upper plate, 26 denotes a dielectric layer, 27 denotes a first metal column, 28 denotes a second metal column, and 29 denotes a fourth metal layer. DETAILED DESCRIPTION

[0054] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0055] Unless otherwise defined, the technical terms or scientific terms used in this disclosure should be understood by people with ordinary skills in the field to which the invention belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. The words "include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0056] The technical solution of the present invention is described in detail with specific embodiments below. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0057] Since the existing ESD devices in the prior art do not have the ability to resist electromagnetic interference and the anti-static impact performance needs to be improved, the present invention designs an ESD protection device 100 with an embedded MIM structure, a preparation method, a circuit and an electronic device.

[0058] The present invention is applicable to ESD devices with a lateral structure, that is, the positive and negative electrodes of the ESD protection device are located on the same side of the ESD device wafer. It is applicable to unidirectional low-capacitance ESD protection devices and bidirectional low-capacitance ESD protection devices, and is particularly applicable to unidirectional low-capacitance ESD devices. The junction capacitance of the low-capacitance ESD protection device is not higher than 10pF.

[0059] Here, the circuit principle and working mechanism of the ESD protection device 100 with an embedded MIM structure of the present invention are first described.

[0060] In the prior art, MIM capacitors (Metal-Insulator-Metal Capacitors) are used to solve the problem that ESD devices cannot resist electromagnetic interference. MIM capacitors are connected in parallel with circuits to have filtering and temporary charging and discharging functions. When external electromagnetic interference passes through the circuit system, MIM capacitors provide a path to discharge the electromagnetic interference so that it will not cause disturbance and damage to the circuit system. In addition, connecting MIM capacitors and ESD devices in parallel will also reduce the impact of transient current and transient voltage on ESD devices, and in a short period of time, take away a part of the surge or electrostatic impact energy that was originally borne entirely by the ESD devices with horizontal structures, thereby improving the anti-static ability of the ESD devices with horizontal structures.

[0061] See also Figure 1 , as an example, Figure 1 is a circuit diagram of a unidirectional ESD protection device in the present invention, Figure 1 The right part is a low-capacitance ESD device, two diodes are connected in series with a low breakdown voltage avalanche diode, the first diode, the avalanche diode and the second diode are connected in sequence, and the first diode and the second diode are ordinary diodes. When a surge ESD event occurs, the avalanche diode quickly breaks down and clamps the voltage at a predetermined value, providing a strong current path, thereby preventing the circuit from being damaged and enabling the circuit to work normally. Figure 1 The left side of the circuit is a MIM capacitor. When EMI comes to the circuit, the capacitor provides an electromagnetic interference path to prevent the circuit from being affected by electromagnetic interference. It reduces circuit noise, and the MIM capacitor absorbs part of the surge energy, improving the current discharge capacity of the ESD device.

[0062] Since the dielectric materials and plate materials used in the preparation process of MIM capacitors are compatible with ordinary ESD devices, the MIM capacitor structure can be prepared in ESD devices.

[0063] ESD protection devices include several diodes. When a unidirectional low capacitance ESD device uses a double-layer metal process, the diode area and the avalanche diode area are on the same plane, so the dummy area is inevitable in the layout. The area of ​​the dummy area will account for 40% of the die area. Therefore, under the premise of not affecting the performance and area of ​​the die, making full use of the dummy area (unused area) will help with the die area design and performance improvement. The actual die layout can be seen in Figure 2 , Figure 2 The figure is a top view of a preferred unidirectional low capacitance ESD protection device die layout.

[0064] Figure 2In the figure, area A and area D are dummy areas, area B and area E are diode areas and electrode areas, and area C is an avalanche diode area. It can be seen that the dummy area accounts for about 40% of the die area. If the dummy area is utilized, the die area will not be increased, and the performance of the ESD device can be improved, killing two birds with one stone. The present invention prepares a MIM capacitor structure in the dummy area, which can provide a discharge path for electromagnetic interference, thereby improving the anti-electromagnetic interference performance of the circuit.

[0065] Please refer to Figure 1 , Figure 3 and Figure 4 , Figure 3 for Figure 2 Section along FF, Figure 4 for Figure 2 In the cross-sectional view along line GG, an embodiment of the present invention provides an ESD protection device 100 with an embedded MIM structure, and the ESD protection device is a lateral ESD protection device, including:

[0066] ESD structure 10;

[0067] The MIM capacitor structure is located on the unused area of ​​the ESD structure 10 .

[0068] For existing ESD protection devices, if there is a sufficiently large unused area of ​​the ESD structure 10, such as a unidirectional ESD protection device, the MIM capacitor structure is entirely located on the unused area of ​​the ESD structure 10. If the area is insufficient, such as a bidirectional ESD protection device, a larger substrate is used.

[0069] As a preferred embodiment, the ESD protection device is a unidirectional low-capacitance ESD protection device, and the MIM capacitor structure is entirely located on an unused area of ​​the ESD structure 10 .

[0070] In this embodiment, the ESD structure 10 includes: a silicon substrate 11; an N-type epitaxial layer 12 located on the silicon substrate 11; a P-type lightly doped region 16, a first SN region and a first SP region located in the N-type epitaxial layer 12; a second SN region 15 located in the P-type lightly doped region 16; and an isolation trench 17 for preventing mutual interference between diodes of the ESD structure 10. The isolation trench 17 penetrates the N-type epitaxial layer 12 and the bottom of the trench is located in the silicon substrate 11.

[0071] It can be understood that one first SN region and one first SP region are used to form a diode, and two second SN regions 15 are used to form an avalanche diode.

[0072] In a specific embodiment of a unidirectional ESD protection device, the ESD structure 10 is an ESD structure 10 having a first diode, a second diode, and an avalanche diode;

[0073] There are two first SN regions and two first SP regions, the two first SN regions are located on both sides of the P-type lightly doped region 16, the two first SP regions are located on both sides of the P-type lightly doped region 16, and isolation trenches 17 are provided on both sides of the P-type lightly doped region 16. There are two second SN regions 15, the second SN regions 15 and the P-type lightly doped region 16 are used to form an avalanche diode, the first SN region and the first SP region located on one side of the P-type lightly doped region 16 are used to form a diode, i.e., a first diode, and the first SN region and the first SP region located on one side of the P-type lightly doped region 16 are used to form another diode, i.e., a second diode;

[0074] Among them, a first SP region, a first SN region, a second SN region 15, another second SN region 15, another first SP region and another first SN region are sequentially arranged, the first SN region is electrically connected to the second SN region 15, and the other second SN region 15 is electrically connected to the other first SP region. The isolation trench 17 is used to isolate the first diode from the avalanche diode, and isolate the second diode from the avalanche diode.

[0075] Figure 3 From left to right in the figure, they are: a first P-type heavily doped region 19 (a first SP region), a first N-type heavily doped region 18 (a first SN region), a first N-type heavily doped injection region (a second SN region 15), a second N-type heavily doped injection region (another second SN region 15), a second P-type heavily doped region 14 (another first SP region), and a second N-type heavily doped region 13 (another first SN region). The first N-type heavily doped injection region and the second N-type heavily doped injection region are located in the P-type lightly doped region 16, and the first P-type heavily doped region 19, the first N-type heavily doped region 18, the second P-type heavily doped region 14, and the second N-type heavily doped region 13 are located in the N-type epitaxial layer 12. The second N-type heavily doped region 13 has an extraction electrode as a cathode.

[0076] In this embodiment, the MIM capacitor structure includes: an isolation groove filling area filling the isolation groove 17, an interlayer insulating layer 22 located on the ESD structure 10 and the isolation groove filling area, a contact hole 21 located in the interlayer insulating layer 22, a contact hole metal filling area filling the contact hole 21, a first metal layer 23 located on the interlayer insulating layer 22 and the contact hole metal filling area, a dielectric layer 24 on the first metal layer 23 and corresponding to the unused area of ​​the ESD structure 10, an upper plate 25 located on the dielectric layer 24, a dielectric layer 26 located on the upper plate 25, a first metal column 27 located in the dielectric layer 26, and a second metal column 27 located in the dielectric layer 26. a metal pillar 28, a fourth metal layer 29 located on the dielectric layer 26, and a passivation layer located on the dielectric layer 26 and the fourth metal layer 29; one end of the contact hole 21 contacts the first SN region, the first SP region, and the second SN region 15, and the other end of the contact hole 21 contacts the first metal layer 23, the first metal layer 23 is arranged corresponding to the unused area of ​​the ESD structure 10 and the metal filling area of ​​the contact hole, the dielectric layer 26 is also located on the interlayer insulating layer 22, the bottom end of the first metal pillar 27 contacts the first metal layer 23, and the top end contacts the fourth metal layer 29, the bottom end of the second metal pillar 28 contacts the upper plate 25, and the top end contacts the fourth metal layer 29.

[0077] It is understandable that the first metal layer 23 can be divided into two parts, one part is located on the metal filling area of ​​the contact hole, and the other part is not located on the metal filling area of ​​the contact hole. Optionally, it can be arranged that the part located on the metal filling area of ​​the contact hole is provided with a dielectric layer 26 instead of the dielectric layer 24, and the upper surface of the part of the first metal layer 23 not located on the metal filling area of ​​the contact hole is provided with the dielectric layer 24.

[0078] In one embodiment, the upper electrode 25 includes a second metal layer located on the dielectric layer 24 and a third metal layer located on the second metal layer. The dielectric layer 26 is located on the third metal layer, and the bottom end of the second metal column 28 contacts the third metal layer.

[0079] Furthermore, the materials of the first metal layer 23 , the second metal layer, the third metal layer and the fourth metal layer 29 are AlCu, titanium, titanium nitride and AlSiCu respectively.

[0080] In one embodiment, the materials of the first metal pillar 27 and the second metal pillar 28 both include titanium, titanium nitride and tungsten.

[0081] Please refer to Figure 3 , Figure 4 and Figure 5 The embodiment of the present invention provides a method for preparing an ESD protection device 100 with an embedded MIM structure, comprising:

[0082] Preparation of ESD structures 10

[0083] Fabricate MIM capacitors on the dummy area of ​​ESD structure 10

[0084] The specific process of this preparation method is as follows:

[0085] S1, preparing a P-type low-resistivity silicon substrate 11;

[0086] Use P-type low-resistivity silicon as the substrate; the resistivity of P-type silicon wafer is about 10 -2 Ω·cm.

[0087] S2, depositing an N-type epitaxial layer 12 on the silicon substrate 11;

[0088] A 20 μm thick N-type epitaxial layer 12 is deposited on the substrate material.

[0089] S3, forming a first SN region, a first SP region, and a second SN region 15 in the N-type epitaxial layer 12, and making an isolation trench 17 to form an ESD structure 10;

[0090] S3.1. Prepare a P-type well region on the N-type epitaxial layer 12. Usually, the N-type epitaxial layer 12 is located in the middle, corresponding to the avalanche diode region. Specifically, prepare a P-type well region on the N-type epitaxial layer 12; perform photolithography on the P-type well region, inject a P-type doping element (boron), and remove the photoresist;

[0091] S3.2, heating to activate the implanted ions and push them to a proper depth, controlling the temperature at 1100°C, and pushing them forward for 60 minutes in a pure nitrogen atmosphere, to obtain a P-type lightly doped region 16 in the N-type epitaxial layer 12;

[0092] S3.3, forming a first SN region, a first SP region and a second SN region 15 by photolithography and ion implantation;

[0093] An SN photolithography process is required to inject N-type doping elements (phosphorus) and remove the photoresist; an SP photolithography process is required to inject P-type doping elements (boron) and remove the photoresist.

[0094] S3.4, making an isolation groove 17, obtaining a first diode, a second diode and an avalanche diode, and thus forming an ESD structure 10;

[0095] It can be understood that the isolation trench 17 penetrates the N-type epitaxial layer 12 from top to bottom and the bottom of the trench is located in the silicon substrate 11;

[0096] S3.41, depositing a first silicon oxide layer as a masking layer for deep trench etching, and then performing a deep trench photolithography process to first etch away the silicon oxide where the deep trench needs to be etched;

[0097] S3.42, remove the remaining photoresist, and then start etching the silicon wafer, that is, etching the N-type epitaxial layer 12 and the silicon substrate 11. At this time, the first silicon oxide layer serves as an etching barrier. After etching the silicon to a certain depth (here the depth is selected to be 25 μm), the isolation groove 17 is prepared;

[0098] The isolation trench 17 may be formed by a deep trench etching process;

[0099] S3.43, forming an electrical connection between the diodes;

[0100] connecting the first SN region and the second SN region 15 to form an electrical connection between different diodes;

[0101] Specifically, a first SN area is connected to a second SN area 15 , and another first SN area is connected to another second SN area 15 .

[0102] That is, for a unidirectional ESD device, the first N-type heavily doped region 18 and the first N-type heavily doped injection region are connected, and the second N-type heavily doped injection region and the second P-type heavily doped region 14 are connected, that is, the first diode, the avalanche diode and the second diode are connected in sequence, and the ESD structure 10 is thus completed. Figure 3 .

[0103] S4, filling the isolation groove 17 to obtain an isolation groove filling area;

[0104] The first silicon oxide layer remaining in the step of making the isolation groove 17 is removed by a wet process, and a first sacrificial silicon oxide layer with a thickness of about 200 Å is generated by rapid thermal oxidation on the ESD structure 10. The first sacrificial silicon oxide layer is then etched away by a wet process, and then a second silicon oxide layer with a thickness of about 500 Å is generated by a wet process. The second silicon oxide layer obtained in this step is not removed, and then the isolation groove 17 just dug is filled with a three-step furnace process.

[0105] When deep grooves are carved, dislocations will form on the silicon sidewalls and impurities will be easily introduced. The purpose of growing the first sacrificial silicon oxide layer is to eat up dislocations and crystal orientation errors.

[0106] The second silicon oxide layer plays a protective role and will subsequently fill the isolation trench 17. The second silicon oxide layer is prepared to achieve a better deep trench filling effect.

[0107] S5, depositing an interlayer insulating layer 22 on the upper surface of the device obtained in S4;

[0108] S5.1. Deposit a layer of silicon oxide as an ILD layer (interlayer insulating layer 22) with a thickness of 2.0 μm on the upper surface of the device obtained in S4; as an insulating layer between metal and silicon, that is, as an insulating layer between the ESD structure 10 and the MIM capacitor structure.

[0109] S5.2. Perform heat treatment in a nitrogen atmosphere at a temperature of 800° C. for 60 min to planarize the ILD film layer.

[0110] S6, preparing a contact hole 21, wherein the bottom of the contact hole 21 contacts the first SN region, the first SP region, and the second SN region 15, the contact hole 21 and the electrodes of all diodes are arranged one by one, and the contact hole 21 is filled to obtain a contact hole metal filling region; that is, the bottom of the contact hole metal filling region contacts the first SN region and the first SP region, or the bottom contacts the second SN region 15;

[0111] S6.1, perform photolithography of the contact hole 21, etch the ILD layer, and need to etch to the ESD structure 10. Figure 1 and Figure 3 The structure shown has a total of 6 contact holes 21, which are specifically etched to the first SN region, the first SP region and the second SN region 15, so as to form a good ohmic contact, and the depth of over-etching silicon is about 500A.

[0112] S6.2, depositing a layer of titanium with a thickness of 15 nm in the contact hole 21, covering the inner wall of the contact hole 21, and then depositing a layer of titanium nitride with a thickness of 30 nm, also covering the inner wall of the contact hole 21;

[0113] S6.3. Deposit 500 nm of metal tungsten to fill the contact hole 21 . Use chemical mechanical grinding and polishing to remove excess tungsten, leaving only the tungsten in the contact hole 21 .

[0114] S7. On the interlayer insulating layer 22, corresponding to the unused area of ​​the ESD structure 10 and the metal filling area of ​​the contact hole, prepare a first metal layer 23, the first metal layer 23 serving as the lower plate of the MIM capacitor structure; specifically, the first metal layer 23 is located on the metal filling area of ​​the contact hole and is in contact relationship.

[0115] S7.1. Deposit a 2.5 μm thick AlCu layer on the device being prepared as the first metal layer, which serves as the ESD structure 10 and interconnection, and also serves as the lower plate of the MIM capacitor.

[0116] S7.2, photolithography of the first metal layer, the metal in a specific area is retained, and the metal in other areas is removed by a dry etching process to obtain a first metal layer 23.

[0117] S8, preparing a third silicon oxide layer to fill the gaps between the first metal layers 23;

[0118] A silicon oxide layer is deposited using the HDP process; then a portion of the silicon oxide deposited in the previous step is removed using the CMP process to completely expose the first metal layer to obtain a third silicon oxide layer, which is located on the interlayer insulating layer 22 and in the gap between the first metal layers 23.

[0119] S9, depositing a silicon nitride layer on the first metal layer 23, corresponding to the unused area of ​​the ESD structure 10;

[0120] That is, a dielectric layer 24 of the MIM capacitor structure is deposited, and the silicon nitride layer is 150 nm thick.

[0121] The silicon nitride layer is heat treated in a nitrogen atmosphere at a temperature of 350°C-400°C for 30 minutes. The purpose of this process is to release the stress of the wafer.

[0122] S10, preparing the upper electrode plate 25 of the MIM capacitor, the upper electrode plate 25 includes a second metal layer and a third metal layer, a titanium metal layer is deposited on the silicon nitride layer, and a titanium nitride layer is deposited on the titanium metal layer, and the titanium metal layer and the titanium nitride layer constitute the upper electrode plate 25. The titanium metal layer is called the second metal layer, and the titanium nitride layer is called the third metal layer.

[0123] After the MIM capacitor dielectric process is completed, the upper plate 25 of the MIM capacitor is prepared next, a 30 nm thick titanium metal Ti layer is deposited, and a 150 nm thick titanium nitride layer is deposited on the titanium metal Ti.

[0124] After the deposition of the upper electrode plate 25 of the MIM capacitor, a heat treatment step is still required. The heat treatment is performed in a nitrogen atmosphere with the temperature controlled at 350° C.-400° C. for 30 minutes.

[0125] The next process step is MIM photolithography to remove unnecessary parts of the MIM top plate 25 .

[0126] S11, depositing a fourth silicon oxide layer, and the dielectric layer 26 is prepared.

[0127] Depositing a 2.2 μm thick silicon oxide layer as a fourth silicon oxide layer to cover the obtained structure, the fourth silicon oxide layer is located on the third metal layer, the third silicon oxide layer and a portion of the first metal layer 23 (the first metal layer 23 without the dielectric layer 24 thereon), and is used not only to fill the gaps between the dielectric layers 24, the gaps between the second metal layers and the gaps between the third metal layers, but also to cover the third metal layer to form a plane;

[0128] Then, the CMP process is used to remove 0.2um of silicon oxide to flatten the surface.

[0129] The dielectric layer 26 is prepared and is located on the third metal layer, the first metal layer 23 and the interlayer insulating layer 22 and in the gap of the MIM capacitor structure. The dielectric layer 26 includes a third silicon oxide layer and a fourth silicon oxide layer.

[0130] S12, etching a first VIA hole and a second VIA hole on the dielectric layer 26, the first VIA hole contacts the first metal layer 23, and the second VIA hole contacts the third metal layer; the first VIA hole and the second VIA hole are used as contact holes between two metal layers of the capacitor;

[0131] The lithography and etching of VIA holes are particularly important because, on the one hand, the VIA holes need to be etched to contact the first layer of metal, and on the other hand, the titanium nitride on the MIM upper plate 25 needs to be etched. Here, the height difference between the two is 330nm, and the etching speed of silicon oxide and silicon nitride needs to be much greater than the etching speed of titanium nitride.

[0132] S13, filling metal in the first VIA hole and the second VIA hole to form a first metal column 27 and a second metal column 28 respectively;

[0133] Depositing a layer of titanium with a thickness of 15 nm to cover the inner walls of the first VIA hole and the second VIA hole, and then depositing a layer of titanium nitride with a thickness of 30 nm to also cover the inner walls of the first VIA hole and the second VIA hole;

[0134] 500nm of metal tungsten is deposited to fill the first VIA hole and the second VIA hole. The metal tungsten on the surface is ground away using a CMP process, and the metal tungsten in the first VIA hole and the second VIA hole is retained.

[0135] S14 , preparing a fourth metal layer 29 on the dielectric layer 26 , wherein the fourth metal layer 29 contacts the top of the first metal pillar 27 and the top of the second metal pillar 28 .

[0136] A 4 μm thick AlSiCu layer is deposited as the second metal layer. Next, the second metal layer is photolithographically processed to remove the metal in a designated area to obtain a fourth metal layer 29 .

[0137] S15, depositing a passivation layer, specifically depositing a 500nm thick silicon oxide layer as the passivation layer, the passivation layer is deposited on the top of the device, that is, above the dielectric layer 26 and the fourth metal layer 29. The passivation layer is photolithographically processed, and a window of the passivation layer is opened to serve as an electrode of the ESD protection device 100 with an embedded MIM structure, and the ESD protection device 100 with an embedded MIM structure is completed.

[0138] When a surge ESD event impacts the circuit, the MIM capacitor will go through a charging and discharging process. At this time, the MIM capacitor absorbs part of the energy and stores it in the MIM capacitor. The larger the MIM capacitor, the more energy it absorbs, thereby improving the current discharge capacity of the ESD. Another function is to provide a discharge path for electromagnetic interference. Usually, the capacitance of the MIM capacitor structure is larger than that of the ESD device. The MIM capacitor can release the alternating electrical signal generated in the circuit, thereby reducing the phenomenon of electromagnetic interference (EMI). Therefore, the capacitance size of the MIM capacitor structure needs to fully consider the circuit's requirements for electromagnetic interference and the discharge capacity of surge ESD events. It is very necessary to comprehensively consider these two factors to determine the capacitance size of the MIM capacitor structure.

[0139] The capacitance calculation formula of the MIM capacitor is: C=εS / 4πkd. ε represents the dielectric constant, which is related to the dielectric material between the upper and lower plates of the MIM capacitor, S represents the relative area of ​​the two plates, k represents the electrostatic force constant, and d represents the distance between the upper and lower plates. It is not difficult to derive the method for adjusting the capacitance of the MIM capacitor from this formula. It can be started from the dielectric material between the upper and lower plates / the distance between the plates / the relative area of ​​the upper and lower plates. The dielectric material between the upper and lower plates of the present invention uses silicon nitride, and the dielectric constant of silicon nitride is 6-9, and the silicon nitride material and process are compatible with the preparation process of the ESD device. According to the above formula, the capacitance size of the MIM capacitor structure of the present invention can be designed.

[0140] The embodiment of the present invention further provides a circuit, including a method for preparing the ESD protection device 100 with an embedded MIM structure involved in the above optional solution.

[0141] An embodiment of the present invention further provides an electronic device, the circuit involved in the above optional solution.

[0142] In summary, it can be seen that in the ESD protection device 100 with an embedded MIM structure and the preparation method provided by the present invention, by adding a MIM capacitor structural concept into a conventional ESD device, a MIM capacitor structure is directly prepared on the ESD structure 10 using an unused area, so that the ESD device has the function of resisting EMI electromagnetic interference. Compared with the existing conventional ESD, the effective area of ​​the ESD protection device is increased, thereby improving the anti-static impact performance, that is, the anti-static performance is improved; the MIM capacitor structure will not increase or increase the area of ​​the excessive tube core. The area of ​​the ESD protection device 100 with an embedded MIM structure of the present invention is smaller than the area of ​​a conventional ESD device in parallel with an existing MIM capacitor.

[0143] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An ESD protection device with an embedded MIM structure, wherein the ESD protection device is a lateral ESD protection device, characterized in that: include: ESD structure; A MIM capacitor structure is located on the unused area of ​​the ESD structure.

2. The ESD protection device with embedded MIM structure according to claim 1, characterized in that: The ESD protection device is a unidirectional low capacitance ESD protection device.

3. The ESD protection device with embedded MIM structure according to claim 1, characterized in that: The ESD structure includes: a silicon substrate, an N-type epitaxial layer located on the silicon substrate, a P-type lightly doped region located in the N-type epitaxial layer, a first SN region located in the N-type epitaxial layer, a first SP region located in the N-type epitaxial layer, a second SN region located in the P-type lightly doped region, and an isolation groove for avoiding mutual interference between diodes, wherein the isolation groove passes through the N-type epitaxial layer and the bottom of the groove is located in the silicon substrate.

4. The ESD protection device with embedded MIM structure according to claim 3, characterized in that: There are two first SN regions, two first SP regions, and two second SN regions. One first SN region and one first SP region are located on one side of the P-type lightly doped region to form a first diode. Another first SN region and another first SP region are located on the other side of the P-type lightly doped region to form a second diode. The two second SN regions and the P-type lightly doped region are used to form an avalanche diode.

5. The ESD protection device with embedded MIM structure according to claim 4, characterized in that: A first SP region, a first SN region, a second SN region, another second SN region, another first SP region and another first SN region are sequentially arranged, the one first SN region is electrically connected to the one second SN region, and the another second SN region is electrically connected to the another first SP region.

6. The ESD protection device with embedded MIM structure according to any one of claims 3 to 5, characterized in that: The MIM capacitor structure includes: an isolation groove filling area filling the isolation groove, an interlayer insulating layer located on the ESD structure and the isolation groove filling area, a contact hole located in the interlayer insulating layer, a contact hole metal filling area filling the contact hole, a first metal layer located on the interlayer insulating layer and the contact hole metal filling area, a dielectric layer on the first metal layer and corresponding to an unused area of ​​the ESD structure, an upper plate located on the dielectric layer, a dielectric layer located on the upper plate, a first metal column located in the dielectric layer, a second metal column located in the dielectric layer, a fourth metal layer located on the dielectric layer, and a passivation layer located on the dielectric layer and the fourth metal layer; one end of the contact hole contacts the first SN area, the first SP area, and the second SN area, and the other end of the contact hole contacts the first metal layer, the first metal layer is arranged corresponding to the unused area of ​​the ESD structure and the contact hole metal filling area, the dielectric layer is also located on the interlayer insulating layer, the bottom end of the first metal column contacts the first metal layer, and the top end contacts the fourth metal layer, and the bottom end of the second metal column contacts the upper plate, and the top end contacts the fourth metal layer.

7. The ESD protection device with embedded MIM structure according to claim 6, characterized in that: The upper electrode plate includes a second metal layer located on the dielectric layer and a third metal layer located on the second metal layer. The dielectric layer is located on the third metal layer, and the bottom end of the second metal column contacts the third metal layer.

8. The ESD protection device with embedded MIM structure according to claim 7, characterized in that: The materials of the first metal layer, the second metal layer, the third metal layer and the fourth metal layer are AlCu, titanium, titanium nitride and AlSiCu respectively.

9. The ESD protection device with embedded MIM structure according to claim 6, characterized in that: The materials of the first metal pillar and the second metal pillar both include titanium, titanium nitride and tungsten.

10. A method for preparing an ESD protection device with an embedded MIM structure, characterized in that: include: preparing an ESD structure; A MIM capacitor structure is fabricated on the unused area of ​​the ESD structure.

11. The method for preparing an ESD protection device with an embedded MIM structure according to claim 10, characterized in that: The preparation of the ESD structure comprises: preparing a P-type silicon substrate; Depositing an N-type epitaxial layer on a silicon substrate; A first SN region, a first SP region, a second SN region and an isolation trench are formed in the N-type epitaxial layer to form an ESD structure.

12. The method for preparing an ESD protection device with an embedded MIM structure according to claim 11, characterized in that: The forming of the SN region, the SP region and the isolation trench in the N-type epitaxial layer to form the ESD structure includes: Preparing a P-type well region on the N-type epitaxial layer; A P-type lightly doped region located in the N-type epitaxial layer is obtained by heating the P-type well region; forming a first SN region, a first SP region, and a second SN region by photolithography and ion implantation; An isolation groove is made to form an ESD structure.

13. The method for preparing an ESD protection device with an embedded MIM structure according to claim 12, characterized in that: The step of preparing the P-type lightly doped region on the N-type epitaxial layer specifically comprises: preparing a P-type well region on the N-type epitaxial layer, performing photolithography on the P-type well region, injecting a P-type doping element, and removing the photoresist to obtain the P-type lightly doped region; The method of obtaining the P-type lightly doped region in the N-type epitaxial layer by heating the P-type well region is specifically as follows: The ions injected into the P-type well region are activated and pushed to a certain depth by heating the P-type well region at a temperature of 1100°C and pushing the region for 60 minutes in a pure nitrogen atmosphere to obtain a P-type lightly doped region in the N-type epitaxial layer. The first SN region, the first SP region and the second SN region are formed by photolithography and ion implantation. Specifically, the first SN region and the first SP region are formed on the N-type epitaxial layer by photolithography and ion implantation, and the second SN region is formed on the P-type lightly doped region by photolithography and ion implantation.

14. The method for preparing an ESD protection device with an embedded MIM structure according to claim 12, characterized in that: The specific steps of making the isolation groove and forming the ESD structure include: Deposit a layer of silicon oxide as a masking layer for deep trench etching, perform deep trench photolithography, and etch away the silicon oxide where deep trenches need to be etched; Removing the remaining photoresist, etching the N-type epitaxial layer and the silicon substrate to obtain an isolation groove, wherein the bottom of the isolation groove is located in the silicon substrate; An electrical connection is formed between the diodes.

15. The method for preparing an ESD protection device with an embedded MIM structure according to claim 12, characterized in that: The step of preparing a MIM capacitor structure on an unused area of ​​the ESD structure comprises: Filling the isolation groove to obtain an isolation groove filling area; Depositing an interlayer insulating layer to serve as an insulating layer between the ESD structure and the MIM capacitor structure; preparing a contact hole, wherein the bottom of the contact hole contacts the first SN region, the first SP region and the second SN region; Filling the contact hole to obtain a contact hole metal filling area; On the interlayer insulating layer, a first metal layer is prepared corresponding to the unused area of ​​the ESD structure and the metal filling area of ​​the contact hole; preparing a third silicon oxide layer to fill the gaps between the first metal layers; Depositing a dielectric layer on the first metal layer corresponding to an unused area of ​​the ESD structure; Depositing a second metal layer of the upper electrode on the dielectric layer, and depositing a third metal layer on the second metal layer; Depositing a fourth silicon oxide layer, the fourth silicon oxide layer is located on the upper electrode plate and the third silicon oxide layer, and preparing a dielectric layer, the dielectric layer includes the third silicon oxide layer and the fourth silicon oxide layer; Etching a first VIA hole and a second VIA hole on the dielectric layer, wherein the first VIA hole contacts the first metal layer, and the second VIA hole contacts the third metal layer; Filling metal in the first VIA hole to form a first metal column, and filling metal in the second VIA hole to form a second metal column; A fourth metal layer is formed on the dielectric layer, wherein the fourth metal layer contacts the top of the first metal column and the top of the second metal column; Deposit a passivation layer.

16. The method for preparing an ESD protection device with an embedded MIM structure according to claim 15, characterized in that: Filling the isolation trench to obtain the isolation trench filling area comprises: generating a first sacrificial silicon oxide layer on the ESD structure; etching away the first sacrificial silicon oxide layer using a wet process; Wet-forming a second silicon oxide layer; A three-step furnace tube process is performed to fill the isolation slots.

17. The method for preparing an ESD protection device with an embedded MIM structure according to claim 15, characterized in that: Filling the contact hole to obtain the contact hole metal filling area comprises: Depositing a layer of titanium in the contact hole to cover the inner wall of the contact hole, and then depositing a layer of titanium nitride to cover the inner wall of the contact hole; Deposit metal tungsten to fill the contact holes; The excess tungsten is removed by chemical mechanical grinding and polishing process, leaving only the tungsten in the contact holes.

18. The method for preparing an ESD protection device with an embedded MIM structure according to claim 15, characterized in that: The depositing of the upper electrode plate on the dielectric layer includes: depositing a second metal layer of the upper electrode plate on the dielectric layer, and depositing a third metal layer on the second metal layer.

19. The method for preparing an ESD protection device with an embedded MIM structure according to claim 18, characterized in that: The depositing of the interlayer insulating layer specifically comprises: depositing a layer of silicon oxide as the interlayer insulating layer on the upper surface of the device; performing a heat treatment on the interlayer insulating layer in a nitrogen atmosphere to flatten the interlayer insulating layer; The preparation of the first metal layer specifically comprises: depositing a layer of AlCu on the device, performing photolithography on the metal of the AlCu layer, retaining the metal in a specific area, and removing the metal in other areas by a dry etching process, thereby obtaining the first metal layer; The preparation of the third silicon oxide layer specifically comprises: depositing a silicon oxide layer by using a HDP process, and grinding away a portion of the silicon oxide layer by using a CMP process to completely expose the first metal layer, thereby obtaining the third silicon oxide layer; Depositing the dielectric layer specifically includes: depositing silicon nitride as the dielectric layer of the MIM capacitor structure, and performing heat treatment in a nitrogen atmosphere as the dielectric of the MIM capacitor structure to release the stress of the wafer; The method of depositing a second metal layer on the dielectric layer and depositing a third metal layer on the second metal layer is specifically as follows: depositing a titanium metal layer on the dielectric of the MIM capacitor structure and depositing a titanium nitride layer on the titanium metal; heat treating the titanium nitride layer in a nitrogen atmosphere; and removing the titanium metal layer and the titanium nitride layer that are not needed as the upper plate of the MIM capacitor structure by a photolithography process to obtain the second metal layer and the third metal layer. The depositing of the fourth silicon oxide layer specifically includes: depositing the fourth silicon oxide layer to fill the gaps between the dielectric layers, the gaps between the second metal layers and the gaps between the third metal layers, and covering the third metal layer to form a plane; and using a CMP process to flatten the surface of the fourth silicon oxide layer.

20. The method for preparing an ESD protection device with an embedded MIM structure according to claim 15, characterized in that: The method of filling the first VIA hole with metal to form the first metal column and the method of filling the second VIA hole with metal to form the second metal column specifically comprises: depositing a layer of titanium to cover the inner walls of the first VIA hole and the second VIA hole, and then depositing a layer of titanium nitride to cover the inner walls of the first VIA hole and the second VIA hole; depositing metal tungsten to fill the first VIA hole and the second VIA hole; and using a CMP process to grind away the metal tungsten on the surface, leaving only the metal tungsten in the first VIA hole and the second VIA hole; The preparation of the fourth metal layer on the dielectric layer specifically comprises: depositing AlSiCu, and performing photolithography on the AlSiCu to remove the metal in the designated area to obtain the fourth metal layer; The depositing of the passivation layer specifically comprises: depositing silicon oxide as the passivation layer; and photolithography the passivation layer to open a window of the passivation layer as an electrode of the ESD protection device embedded with the MIM structure.

Images