Preparation method of back contact battery piece and back contact battery piece

Abstract

The invention provides a preparation method of a back contact battery piece and the back contact battery piece. The preparation method comprises the following steps: preparing a silicon wafer; performing laser grooving on the back surface of the silicon wafer to form a first connecting groove, so that part of the surface of the second passivation contact structure can be exposed through the first connecting groove; arranging an insulating layer on the back surface of the silicon wafer, and enabling the insulating layer to cover the bottom wall and the side wall of the first connecting groove and the surface of the first passivation contact structure; performing laser grooving on the back surface of the silicon wafer, removing a part of the insulating layer on the surface of the first passivation contact structure, forming a second connecting groove, and enabling a part of the surface of the first passivation contact structure to be exposed through the second connecting groove; the insulating layer on the bottom wall of the first connecting groove is removed, so that the second passivation contact structure in the first connecting groove is exposed again; grid lines are arranged on the back face of the silicon wafer, first grid lines electrically connected with the exposed second passivation contact structures and second grid lines electrically connected with the exposed first passivation contact structures are formed, and the preparation process of the back contact battery piece can be simplified through the preparation method.

Description

Technical Field

[0001] The present application relates to the technical field of photovoltaic cells, and in particular to a method for preparing a back-contact cell sheet and a back-contact cell sheet. Background Art

[0002] The positive and negative grid lines of the back-contact solar cell are set on the back, and there is no grid line blocking the front. Compared with conventional photovoltaic cells, it can reduce the light energy loss caused by grid line blocking and has a higher photoelectric conversion efficiency.

[0003] Since the positive and negative grid lines of the back-contact cell are located on the back side, it is necessary to set mutually insulated P-type doping regions (P+ regions) and N-type doping regions (N+ regions) on the back doping layer of the back-contact cell. As a result, the preparation process of the back-contact cell is complicated and difficult, which is not conducive to improving the production efficiency of the back-contact cell and the product yield. Summary of the invention

[0004] In view of this, the present application provides a method for preparing a back-contact cell and a back-contact cell, so as to solve the problem of complex preparation process of back-contact cell in the prior art.

[0005] In a first aspect, an embodiment of the present application provides a method for preparing a back-contact cell, the back-contact cell comprising a silicon wafer and a gate line arranged on the back side of the silicon wafer, the gate line comprising a first gate line and a second gate line, the silicon wafer comprising a first silicon substrate and a second silicon substrate, the back side of the first silicon substrate being provided with a first passivation contact structure, the back side of the second silicon substrate being provided with a second passivation contact structure, the second passivation contact structure being bonded to the front side of the first silicon substrate, and the polarity of the first passivation contact structure is opposite to that of the second passivation contact structure; the preparation method comprises: preparing the silicon wafer, performing laser grooving on the back side of the silicon wafer to form a first connection groove, so that a portion of the surface of the second passivation contact structure can be exposed through the first connection groove; providing an insulating layer on the back side of the silicon wafer, so that the insulating layer covers the first connection groove; The bottom wall, side wall and surface of the first passivation contact structure of the connection groove are connected to the bottom wall of the connection groove, so that the first passivation contact structure is insulated from the second passivation contact structure; laser grooving is performed on the back side of the silicon wafer again to remove part of the insulating layer located on the surface of the first passivation contact structure to form a second connection groove spaced apart from the first connection groove, so that part of the surface of the first passivation contact structure can be exposed through the second connection groove; the insulating layer located on the bottom wall of the first connection groove is also removed to expose the second passivation contact structure in the first connection groove again; gate lines are set on the back side of the silicon wafer to form the first gate line located in the first connection groove and electrically connected to the exposed second passivation contact structure, and the second gate line located in the second connection groove and electrically connected to the exposed first passivation contact structure.

[0006] In a possible implementation, when preparing the silicon wafer, the preparation method specifically includes: providing a first sub-silicon wafer as the first silicon substrate, and setting the first passivation contact structure on the back side of the first silicon substrate; providing a second sub-silicon wafer as the second silicon substrate, and setting the second passivation contact structure on the back side of the second silicon substrate; setting an oxidized bonding layer on the back side of the second passivation contact structure; laminating the front side of the first silicon substrate with the oxidized bonding layer to form a stacked structure; and heat treating the stacked structure to bond the first silicon substrate to the oxidized bonding layer.

[0007] In a possible implementation, when the laminated structure is heat treated, the preparation method specifically includes: placing the laminated structure in a heat treatment furnace, gradually heating it to 800° C. to 1200° C., and continuously heating it for 1 h to 2 h.

[0008] In one possible implementation, the first passivation contact structure includes a first tunneling oxide layer and a first doped layer, and the second passivation contact structure includes a second tunneling oxide layer and a second doped layer; when setting the first passivation contact structure, the preparation method specifically includes: setting the first tunneling oxide layer on the back side of the first silicon substrate; setting the first doped layer on the back side of the first tunneling oxide layer; and / or, when setting the second passivation contact structure, the preparation method specifically includes: setting the second tunneling oxide layer on the back side of the second silicon substrate; setting the second doped layer on the back side of the second tunneling oxide layer.

[0009] In a possible implementation manner, one of the first doping layer and the second doping layer is doped with at least one element of the third main group, and the other is doped with at least one element of the fifth main group.

[0010] In a possible implementation, the preparation method of the first sub-silicon wafer specifically includes: providing a target sub-silicon wafer; injecting hydrogen ions into the target sub-silicon wafer by ion implantation to form a hydrogen bubble layer in the target sub-silicon wafer; heating the target sub-silicon wafer to above 1000° C. to cause the hydrogen in the hydrogen bubble layer to expand and burst, so that the target sub-silicon wafer is cracked along the hydrogen bubble layer to obtain the first sub-silicon wafer.

[0011] In a possible implementation, after the first sub-silicon wafer is obtained by cleavage, the preparation method further includes: polishing the surface of the first sub-silicon wafer.

[0012] In a possible implementation, when an insulating layer is provided on the back side of the silicon wafer, the preparation method specifically includes: using atomic layer deposition technology to deposit the insulating layer on the bottom wall, side wall of the first connecting groove and the surface of the first passivation contact structure.

[0013] In a possible implementation, the preparation method further includes: disposing a third doping layer on the front side of the second silicon substrate; disposing a passivation film on the front side of the third doping layer; and disposing an anti-reflection film on the front side of the passivation film.

[0014] In a second aspect, an embodiment of the present application provides a back-contact solar cell, including a silicon wafer and a gate line, wherein the silicon wafer includes a first silicon substrate and a second silicon substrate, and the gate line includes a first gate line and a second gate line; a first passivation contact structure is provided on the back side of the first silicon substrate, a first sub-insulating layer is provided on the back side of the first passivation contact structure, a second passivation contact structure is provided on the back side of the second silicon substrate, the second passivation contact structure is bonded to the front side of the first silicon substrate through an oxide bonding layer, and the polarity of the first passivation contact structure is opposite to that of the second passivation contact structure; a first connection groove and a second connection groove are formed on the back side of the silicon wafer, and a first connection groove and a second connection groove are formed on the back side of the silicon wafer; The first connection groove penetrates the first sub-insulating layer, the first passivation contact structure, the first silicon substrate and the oxide bonding layer, the sidewall of the first connection groove is provided with a second sub-insulating layer, and a part of the surface of the second passivation contact structure is exposed through the first connection groove; the second connection groove penetrates the first sub-insulating layer, and a part of the surface of the first passivation contact structure is exposed through the second connection groove; at least a part of the first gate line is located in the first connection groove and is electrically connected to the exposed second passivation contact structure; at least a part of the second gate line is located in the second connection groove and is electrically connected to the exposed first passivation contact structure.

[0015] The preparation method of the back-contact cell provided in the present application only requires setting a protective film layer (insulating layer) once and performing two laser grooving steps to achieve the separation of the P+ region and the N+ region. Compared with the prior art method that requires multiple settings of protective film layers, multiple cleanings, and multiple laser groovings, the present application can simplify the preparation method and reduce multiple preparation steps, which is beneficial to reducing the difficulty of the preparation process of the back-contact cell, improving the preparation efficiency of the back-contact cell, and reducing the preparation cost of the back-contact cell.

[0016] It should be understood that the foregoing general description and the following detailed description are exemplary only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0018] Figure 1 A schematic diagram of the structure of a back contact cell provided in this application;

[0019] Figure 2 A flow chart of a method for preparing a back contact cell provided in this application;

[0020] Figure 3 for Figure 1 Schematic diagram of the structure of the silicon wafer;

[0021] Figure 4 for Figure 1 Schematic diagram of the preparation process of silicon wafer;

[0022] Figure 5 for Figure 1 Flow chart of the method for preparing a silicon wafer;

[0023] Figure 6 is a flow chart of a method for preparing a first sub-silicon wafer;

[0024] Figure 7 This is a schematic diagram of the preparation process of the first sub-silicon wafer;

[0025] Figure 8 for Figure 1 A schematic structural diagram of a back contact cell in another embodiment;

[0026] Fig. 9 for Figure 8 Flow chart of the method for preparing a back contact battery cell.

[0027] Reference numerals:

[0028] 100-silicon wafer;

[0029] 200-grid line;

[0030] 210-first grid line;

[0031] 220-second grid line;

[0032] 300-target silicon wafer;

[0033] 301-hydrogen bubble layer;

[0034] 302-first sub-silicon wafer;

[0035] 10-first connecting groove;

[0036] 20- second connecting groove;

[0037] 1-a first silicon substrate;

[0038] 2-second silicon substrate;

[0039] 3-first passivation contact structure;

[0040] 31-a first tunnel oxide layer;

[0041] 32- a first doping layer;

[0042] 4-second passivation contact structure;

[0043] 41- a second tunneling oxide layer;

[0044] 42- a second doping layer;

[0045] 5-oxidized bonding layer;

[0046] 6-Insulation layer;

[0047] 61- a first sub-insulating layer;

[0048] 62- a second sub-insulating layer;

[0049] 7- third doping layer;

[0050] 8- passivation film;

[0051] 9- Anti-reflection film. DETAILED DESCRIPTION

[0052] In order to better understand the technical solution of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0053] It should be clear that the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0054] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms "a", "said" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0055] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0056] In a first aspect, an embodiment of the present application provides a method for preparing a back-contact battery cell. The structure of the back-contact battery cell is as follows: Figure 1 As shown, it includes a silicon wafer 100 and a gate line 200 arranged on the back side of the silicon wafer 100, the gate line 200 includes a first gate line 210 and a second gate line 220, one of the first gate lines 210 is a positive gate line, and the other is a negative gate line. Since there is no gate line blocking the front side of the back contact solar cell, it can have a higher photoelectric conversion efficiency.

[0057] refer to Figure 2As shown, the method for preparing the back contact cell specifically includes the following steps:

[0058] Step S1: preparing a silicon wafer 100 .

[0059] In this step, if Figure 3 As shown, the prepared silicon wafer 100 includes a first silicon substrate 1 and a second silicon substrate 2, a first passivation contact structure 3 is arranged on the back side of the first silicon substrate 1, a second passivation contact structure 4 is arranged on the back side of the second silicon substrate 2, and the second passivation contact structure 4 is bonded to the front side of the first silicon substrate 1, that is, the silicon wafer 100 is a structure with a second passivation contact structure 4 pre-buried in the middle.

[0060] Among them, the first silicon substrate 1 and the second silicon substrate 2 are both N-type silicon substrates or both P-type silicon substrates. The first silicon substrate 1 and the second silicon substrate 2 together constitute the silicon base of the silicon wafer 100, which is used to receive incident light and generate photogenerated carriers. The embodiment of the present application takes the first silicon substrate 1 and the second silicon substrate 2 as N-type silicon substrates as an example to introduce the back contact cell 100 and its preparation method.

[0061] The polarity of the first passivation contact structure 3 is opposite to that of the second passivation contact structure 4, wherein the first passivation contact structure 3 includes a first tunneling oxide layer 31 and a first doping layer 32, wherein the first tunneling oxide layer 31 can chemically passivate the surface of the first silicon substrate 1, and can reduce the recombination center of the contact surface between the first tunneling oxide layer 31 and the first silicon substrate 1, so as to reduce the recombination rate of carriers at the contact surface between the first silicon substrate 1 and the first tunneling oxide layer 31; the first doping layer 32 is used to form a field passivation layer, which can reduce the concentration of minority carriers and realize the selective transmission of majority carriers, thereby reducing the carrier recombination rate. Similarly, the second passivation contact structure 4 includes a second tunneling oxide layer 41 and a second doping layer 42. The second tunneling oxide layer 41 can chemically passivate the surface of the second silicon substrate 2, and can reduce the recombination center of the contact surface between the second tunneling oxide layer 41 and the second silicon substrate 2, so as to reduce the recombination rate of carriers at the contact surface between the second silicon substrate 2 and the second tunneling oxide layer 41; the second doping layer 42 is used to form a field passivation layer, which can reduce the minority carrier concentration and realize the selective transmission of the majority carriers, thereby reducing the carrier recombination rate. Therefore, the first passivation contact structure 3 and the second passivation contact structure 4 are provided to improve the photoelectric conversion efficiency and output power of the back contact cell.

[0062] Among them, one of the first doping layer 32 and the second doping layer 42 is doped with at least one N-type dopant (for example, V group elements such as phosphorus (P), arsenic (As), bismuth (Bi), antimony (Sb)), etc.) to form an N+ region electrically connected to the positive electrode grid line, and the other is doped with at least one P-type dopant (for example, III group elements such as boron (B), aluminum (Al), gallium (Ga), indium (In), etc.) to form a P+ region electrically connected to the negative electrode grid line. The embodiment of the present application is described by taking the first doping layer 32 doped with at least one N-type dopant and the second doping layer 42 doped with at least one P-type dopant as an example.

[0063] Step S2 : performing laser grooving on the back side of the silicon wafer 100 to form a first connection groove 10 , so that a portion of the surface of the second passivation contact structure 4 can be exposed through the first connection groove 10 .

[0064] In this step, if Figure 4 As shown, the back side of the silicon wafer 100 is grooved by laser grooving, a portion of the structural layer on the back side of the second passivation contact structure 4 is removed and a first connection groove 10 is formed, so that the second doping layer 42 can be exposed through the first connection groove 10, thereby forming a P+ region. The specific pattern of the first connection groove 10 formed on the back side of the silicon wafer 100 can be changed according to the actual design, and this embodiment does not limit this.

[0065] Step S3 : disposing an insulating layer 6 on the back side of the silicon wafer 100 , so that the insulating layer 6 covers the bottom wall and the side wall of the first connection groove 10 and the surface of the first passivation contact structure 3 , so as to insulate the first passivation contact structure 3 from the second passivation contact structure 4 .

[0066] In this step, if Figure 4 As shown, the insulating layer 6 includes a first sub-insulating layer 61 covering the back surface of the first passivation contact structure 3 and a second sub-insulating layer 62 covering the bottom wall and the side wall of the first connection groove 10. Since the first connection groove 10 penetrates the first passivation contact structure 3 when the first connection groove 10 is opened in step S2, resulting in the first passivation contact structure 3 being exposed through the side wall of the first connection groove 10, it is necessary to provide the second sub-insulating layer 62 to prevent the gate line 200 from being electrically connected to the first passivation contact structure 3 and the second passivation contact structure 4 at the same time, thereby avoiding a short circuit.

[0067] Atomic layer deposition (ALD) is a method that can deposit a material layer by layer on the surface of a substrate in the form of a single atomic film. The thin film structure deposited by the atomic layer deposition process has excellent mechanical properties and chemical stability. In this step, the atomic layer deposition technology can be used to deposit the first sub-insulating layer 61 and the second sub-insulating layer 62 on the bottom wall, side wall and surface of the first passivation contact structure 3 of the first connection groove 10 to form a complete insulating layer 6. Since the atomic layer deposition process has a good step coverage effect, the preparation effect of the insulating layer 6 can be improved. In this step, the bottom wall, side wall and surface of the first passivation contact structure 3 of a connection groove 10 can be insulated and protected by only one deposition, and there is no need to set the protective layer multiple times, which correspondingly reduces the additional protective layer cleaning steps, can simplify the preparation process of the back contact battery cell, and is conducive to improving the preparation efficiency of the back contact battery cell and reducing the preparation cost of the back contact battery cell.

[0068] Among them, the insulating layer 6 should be prepared from a material with strong step coverage ability to ensure that the insulating layer 6 can evenly cover the step formed by the opening of the first connecting groove 10 to ensure the structural integrity of the insulating layer 6. At the same time, the material with strong step coverage ability can also ensure the thickness consistency of the insulating layer 6. The insulating layer 6 can be specifically prepared from silicon nitride, aluminum oxide or other materials with strong step coverage ability, and this embodiment does not limit this.

[0069] Step S4: Laser grooving is performed again on the back side of the silicon wafer 100 to remove part of the insulating layer 6 located on the surface of the first passivation contact structure 3 to form a second connection groove 20 spaced apart from the first connection groove 10, so that part of the surface of the first passivation contact structure 3 can be exposed through the second connection groove 20; at the same time, the laser grooving is also used to remove the insulating layer 6 located on the bottom wall of the first connection groove 10, so that the second passivation contact structure 4 in the first connection groove 10 can be exposed again.

[0070] In this step, if Figure 4As shown, the back side of the silicon wafer 100 is grooved again by laser grooving. On the one hand, the second grooving also needs to remove the second sub-insulating layer 62 located on the bottom wall of the first connecting groove 10, so that the second passivation contact structure 4 in the first connecting groove 10 can be exposed again, that is, the P+ region covered by the second sub-insulating layer 62 can be exposed again; on the other hand, the second grooving needs to remove part of the first sub-insulating layer 61 on the back side of the first passivation contact layer 3 and form a second connecting groove 20, so that the first doping layer 32 can be exposed through the second connecting groove 20, thereby forming an N+ region. Among them, the specific pattern of the second connecting groove 20 formed on the back side of the silicon wafer 100 can be changed according to the actual design, and this embodiment does not limit this, but the second connecting groove 20 should be spaced apart from the first connecting groove 10 to ensure that the N+ region and the P+ region are separated and insulated from each other.

[0071] Step S5: Arrange the gate line 200 on the back side of the silicon wafer 100 to form a first gate line 210 located in the first connection groove 10 and electrically connected to the exposed second passivation contact structure 4, and a second gate line 220 located in the second connection groove 20 and electrically connected to the exposed first passivation contact structure 3.

[0072] In this step, the gate line 200 can be set on the back of the silicon wafer 100 by screen printing or slurry printing, and then the first gate line 210 and the second gate line 220 are formed by conventional steps such as drying and sintering, and this embodiment does not limit this. Among them, since the P+ region is formed in the first connecting groove 10, the first gate line 210 located in the first connecting groove 10 can be electrically connected to the P+ region, and the first gate line 210 constitutes the positive gate line of the back contact battery cell; since the N+ region is formed in the second connecting groove 20, the second gate line 220 located in the second connecting groove 20 can be electrically connected to the N+ region, and the second gate line 220 constitutes the negative gate line of the back contact battery cell.

[0073] In summary, the preparation method of the back-contact battery cell provided in the present application only requires setting a protective film layer (insulating layer) once and performing two laser grooving steps to achieve the separation of the P+ region and the N+ region. Compared with the prior art method that requires multiple settings of the protective film layer, multiple cleanings, and multiple laser groovings, the present application can simplify the preparation method and reduce multiple preparation steps, which is beneficial to reducing the difficulty of the preparation process of the back-contact battery cell, improving the preparation efficiency of the back-contact battery cell, and reducing the preparation cost of the back-contact battery cell.

[0074] In a specific embodiment, Figure 5 As shown, for step S1, the specific method for preparing the silicon wafer 100 includes:

[0075] Step A1: providing a first sub-silicon wafer (302) as a first silicon substrate 1, and disposing a first passivation contact structure 3 on the back side of the first silicon substrate 1.

[0076] In this step, it is necessary to sequentially and layer by layer arrange the first tunnel oxide layer 31 and the first doping layer 32 on the back side of the first silicon substrate 1. Specifically, the first tunnel oxide layer 31 can be deposited on the back side of the first silicon substrate 1 by using plasma enhanced chemical vapor deposition (PECVD), and / or, the first doping layer 32 can be deposited on the back side of the first tunnel oxide layer 31 by using plasma enhanced chemical vapor deposition. The deposition rate of the plasma enhanced chemical vapor deposition technology is fast, and the thickness and composition uniformity of the formed structural layer are good, which is conducive to improving the stability and preparation efficiency of the first passivation contact structure 3. Among them, the first tunnel oxide layer 31 can be specifically a silicon oxide layer, and the first doping layer 32 can be specifically a polysilicon layer doped with at least one N-type dopant.

[0077] In addition, a first tunneling oxide layer 31 may be deposited on the back side of the first silicon substrate 1 by using low pressure chemical vapor deposition technology (LPCVD) or plasma enhanced atomic layer deposition technology (PEALD); similarly, a first doping layer 32 may be deposited on the back side of the first tunneling oxide layer 31 by using low pressure chemical vapor deposition technology (LPCVD) or plasma enhanced atomic layer deposition technology (PEALD), and this embodiment does not impose any restrictions on this.

[0078] Step A2: providing a second silicon sub-wafer as a second silicon substrate 2 , and disposing a second passivation contact structure 4 on the back side of the second silicon substrate 2 .

[0079] In this step, it is necessary to sequentially and layer by layer arrange the second tunneling oxide layer 41 and the second doping layer 42 on the back side of the second silicon substrate 2. Specifically, the second tunneling oxide layer 41 can be formed by deposition on the back side of the second silicon substrate 2 using plasma enhanced chemical vapor deposition technology, and / or, the second doping layer 42 can be formed by deposition on the back side of the second tunneling oxide layer 41 using plasma enhanced chemical vapor deposition technology. The deposition rate of the plasma enhanced chemical vapor deposition technology is fast, and the thickness and composition uniformity of the formed structural layer are good, which is conducive to improving the stability and preparation efficiency of the second passivation contact structure 4. Among them, the second tunneling oxide layer 41 can be specifically a silicon oxide layer, and the second doping layer 42 can be specifically a polysilicon layer doped with at least one P-type dopant.

[0080] In addition, a second tunneling oxide layer 41 may be formed by depositing on the back side of the second silicon substrate 2 using low pressure chemical vapor deposition technology (LPCVD) or plasma enhanced atomic layer deposition technology (PEALD); similarly, a second doping layer 42 may be formed by depositing on the back side of the second tunneling oxide layer 41 using low pressure chemical vapor deposition technology (LPCVD) or plasma enhanced atomic layer deposition technology (PEALD), and this embodiment does not impose any restrictions on this.

[0081] Step A3: Arrange an oxide bonding layer 5 on the back side of the second passivation contact structure 4 .

[0082] In this step, a plasma enhanced chemical vapor deposition technique may be used to deposit an oxide bonding layer 5 on the back side of the second doping layer 42 , which is beneficial to improving the stability and preparation efficiency of the oxide bonding layer 5 . Specifically, the oxide bonding layer 5 may be a silicon oxide layer.

[0083] It should be noted that the above-mentioned step A3 needs to be performed after step A2, but there is no fixed implementation order between step A1 and steps A2 and A3. Step A1 can be performed first, and then steps A2 and A3; steps A2 and A3 can be performed first, and then step A1; or step A1 and steps A2 and A3 can be performed simultaneously.

[0084] Step A4: Laminating the front surface of the first silicon substrate 1 to the oxide bonding layer 5 to form a stacked structure.

[0085] Step A5: heat-treating the stacked structure to bond the first silicon substrate 1 to the oxide bonding layer 5 .

[0086] Step A4 and step A5 are used to form a silicon wafer 100. First, the front side of the first silicon substrate 1 and the back side of the oxide bonding layer 5 are bonded to each other to achieve positioning, and then the combined laminated structure is placed in a heat treatment furnace, gradually heated to 800°C to 1200°C, and continuously heated for 1h to 2h to achieve silicon-to-silicon oxide bonding between the first silicon substrate 1 and the oxide bonding layer 5, thereby achieving a fixed connection between the first silicon substrate 1 and the oxide bonding layer 5 to obtain the silicon wafer 100. In the heat treatment process, a certain pressure can also be applied to the laminated structure to ensure that the front side of the first silicon substrate 1 and the back side of the oxide bonding layer 5 can be tightly bonded; after step A5, the prepared silicon wafer 100 needs to be gradually cooled to room temperature to prevent cracks from occurring in the material due to a sudden drop in temperature.

[0087] In addition, before step A5, the front side of the first silicon substrate 1 can be hydrogenated to form a layer of silicon-hydrogen bonds (Si-H bonds) on the front side of the first silicon substrate 1. The silicon-hydrogen bonds can serve as an intermediate layer to improve the interface properties between silicon and silicon oxide and improve the quality and stability of the oxide bonding layer.

[0088] It should be noted that the first sub-silicon wafer 302 in step A1 needs to be prepared separately, while the second sub-silicon wafer in step A2 is a conventional silicon wafer used in preparing photovoltaic cells.

[0089] In a specific embodiment, Figure 6 and Figure 7 As shown, the preparation method of the first silicon sub-wafer 302 is specifically as follows:

[0090] Step B1: providing a target sub-silicon wafer 300 .

[0091] In this step, the target sub-silicon wafer 300 is a conventional silicon wafer used in preparing photovoltaic cells.

[0092] Step B2: injecting hydrogen ions into the target sub-silicon wafer 300 by ion implantation to form a hydrogen bubble layer 301 in the target sub-silicon wafer 300 .

[0093] In this step, hydrogen ions are implanted at appropriate positions of the target silicon sub-wafer 300 according to the thickness of the first silicon sub-wafer 302 to be prepared, so as to form a hydrogen bubble layer 301 rich in hydrogen thereat, and the hydrogen bubble layer 301 will serve as the starting point for subsequent cracking.

[0094] Step B3: heating the target sub-silicon wafer 300 to above 1000° C. to expand and rupture the hydrogen in the hydrogen bubble layer 301 , so that the target sub-silicon wafer 300 is cracked along the hydrogen bubble layer 301 to obtain the first sub-silicon wafer 302 .

[0095] In this step, the bubbles in the hydrogen bubble layer 301 will expand and then rupture during the heating process, so that the target sub-silicon wafer 300 can be cracked along the hydrogen bubble layer 301 under the action of longitudinal stress, thereby obtaining the first sub-silicon wafer 302 of the required thickness. Since the surface of the first sub-silicon wafer 302 obtained by cracking is relatively rough, the surface of the first sub-silicon wafer 302 can be polished after step B3 to improve the smoothness and cleanliness of the first sub-silicon wafer 302 and reduce its surface defects, thereby improving the surface flatness of the first sub-silicon wafer 302, providing a good foundation for subsequent processes.

[0096] Specifically, the surface of the first sub-silicon wafer 302 can be polished by chemical alkali polishing, chemical polishing or mechanical polishing. Only the rough surface on one side of the first sub-silicon wafer 302 formed by cracking can be polished, or both sides of the first sub-silicon wafer 302 can be polished. This embodiment does not limit this.

[0097] Specifically, the thickness of the processed first sub-silicon wafer 302 can be 1μm to 10μm, specifically 1μm, 3μm, 5μm, 7μm, 10μm, 12μm, 15μm, 18μm or 20μm, or other values ​​within the above range, which is not limited in this embodiment.

[0098] In addition, since the first sub-silicon wafer 302 undergoes a high-temperature treatment during the preparation process and undergoes a high-temperature treatment again during the subsequent bonding process, the annealing effect of the first silicon substrate 1 can be improved and the defects of the first silicon substrate 1 can be eliminated, which is beneficial to reducing and improving the photoelectric conversion efficiency of the back contact solar cell.

[0099] In a specific embodiment, Figure 8 As shown, the structure of the back contact cell also includes a third doping layer 7, a passivation film 8, and an anti-reflection film 9 arranged on the front side of the second silicon substrate 2. Specifically, as shown in FIG. Fig. 9 As shown, the method for preparing the back contact cell also includes:

[0100] Step C1: Disposing a third doping layer 7 on the front surface of the second silicon substrate 2 .

[0101] In this step, the third doping layer 7 can be doped with at least one N-type dopant, or doped with at least one layer of P-type dopant. If the third doping layer 7 is doped with N-type dopant, the concentration of the N-type dopant is greater than the concentration of the N-type dopant doped in the second silicon substrate 2.

[0102] Step C2: a passivation film 8 is provided on the front surface of the third doping layer 7 .

[0103] In this step, the passivation film 8 mainly plays the role of reducing reflectivity and increasing the incidence rate of light incident on the second silicon substrate 2, so as to increase the rate at which the second silicon substrate 2 generates carriers, thereby improving the photoelectric conversion efficiency and output power of the back contact cell.

[0104] Step C3: Arrange an anti-reflection film 9 on the front surface of the passivation film 8 .

[0105] In this step, the anti-reflection film 9 can reduce the reflection of light and increase the incidence rate of light incident on the second silicon substrate 2 by using thin film interference. The anti-reflection film 9 can specifically be a silicon oxide layer or an aluminum oxide layer.

[0106] It should be noted that steps C1, C2, and C3 may be located between step S1 and step S2, or after step S5, or after step A5 of step S1, and this embodiment does not impose any limitation on this.

[0107] In addition, before step C1, the front surface of the second silicon substrate 2 can be textured to reduce light reflection, so as to increase the incidence rate of light entering the second silicon substrate 2, thereby improving the photoelectric conversion efficiency of the back contact cell. Accordingly, the third doping layer 7, the passivation film 8 and the anti-reflection film 9 are covered on the texture surface to cooperate with the texture structure.

[0108] A second aspect of the present application provides a back contact cell, such as Figure 1 As shown, the back contact cell comprises a silicon wafer 100 and a gate line 200 arranged on the back side of the silicon wafer 100, wherein the silicon wafer 100 comprises a first silicon substrate 1 and a second silicon substrate 2, a first passivation contact structure 3 is arranged on the back side of the first silicon substrate 1, a first sub-insulating layer 61 is arranged on the back side of the first passivation contact structure 3, a second passivation contact structure 4 is arranged on the back side of the second silicon substrate 2, and the second passivation contact structure 4 is bonded to the front side of the first silicon substrate 1 through an oxidized bonding layer 5; the gate line 200 comprises a first gate line 210 and a second gate line 220; the back side of the silicon wafer 100 (i.e., the back side of the first silicon substrate 1) is formed with first connection grooves 10 arranged at intervals. and the second connection groove 20, the first connection groove 10 penetrates the first sub-insulating layer 61, the first passivation contact structure 3, the first silicon substrate 1 and the oxide bonding layer 5, the sidewall of the first connection groove 10 is provided with the second sub-insulating layer 62, part of the surface of the second passivation contact structure 4 is exposed through the first connection groove 10, the second connection groove 20 penetrates the first sub-insulating layer 61, and part of the surface of the first passivation contact structure 3 is exposed through the second connection groove 20; at least part of the first gate line 210 is located in the first connection groove 10 and is electrically connected to the exposed second passivation contact structure 4; at least part of the second gate line 220 is located in the second connection groove 20 and is electrically connected to the exposed first passivation contact structure 3.

[0109] Specifically, the first silicon substrate 1 and the second silicon substrate 2 may both be N-type silicon substrates or P-type silicon substrates; the first passivation contact structure 3 may specifically include a first tunneling oxide layer 31 disposed on the back side of the first silicon substrate 1 and a first doping layer 32 disposed on the back side of the first tunneling oxide layer 31; the second passivation contact structure 4 may specifically include a second tunneling oxide layer 41 disposed on the back side of the second silicon substrate 2 and a second doping layer 42 disposed on the back side of the second tunneling oxide layer 41; one of the first doping layer 32 and the second doping layer 42 is doped with at least one N-type dopant, and the other is doped with at least one P-type dopant, so that the first passivation contact structure 3 and the second passivation contact structure 4 present opposite polarities, so that one of the first gate line 210 and the second gate line 220 forms a positive gate line, and the other forms a negative gate line. Further, as Figure 8 As shown, the front side of the second silicon substrate 2 may also be provided with a third doping layer 7, a passivation film 8 and an anti-reflection film 9 in sequence. The back contact cell may be prepared by the method for preparing the back contact cell described above.

[0110] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for preparing a back contact battery cell, characterized in that: The back-contact cell comprises a silicon wafer (100) and a gate line (200) arranged on the back side of the silicon wafer (100), the gate line (200) comprising a first gate line (210) and a second gate line (220), the silicon wafer (100) comprising a first silicon substrate (1) and a second silicon substrate (2), the back side of the first silicon substrate (1) being provided with a first passivation contact structure (3), the back side of the second silicon substrate (2) being provided with a second passivation contact structure (4), the second passivation contact structure (4) being bonded to the front side of the first silicon substrate (1), the first passivation contact structure (3) and the second passivation contact structure (4) having opposite polarities; The preparation method comprises: preparing the silicon wafer (100); Laser grooving is performed on the back side of the silicon wafer (100) to form a first connection groove (10), so that a portion of the surface of the second passivation contact structure (4) can be exposed through the first connection groove (10); An insulating layer (6) is provided on the back side of the silicon wafer (100), so that the insulating layer (6) covers the bottom wall and the side wall of the first connection groove (10) and the surface of the first passivation contact structure (3), so that the first passivation contact structure (3) is insulated from the second passivation contact structure (4); Laser grooving is performed again on the back side of the silicon wafer (100) to remove a portion of the insulating layer (6) located on the surface of the first passivation contact structure (3) to form a second connection groove (20) spaced apart from the first connection groove (10), so that a portion of the surface of the first passivation contact structure (3) can be exposed through the second connection groove (20); and the insulating layer (6) located on the bottom wall of the first connection groove (10) is also removed to expose the second passivation contact structure (4) in the first connection groove (10) again; A gate line (200) is arranged on the back side of the silicon wafer (100) to form the first gate line (210) located in the first connection groove (10) and electrically connected to the exposed second passivation contact structure (4), and the second gate line (220) located in the second connection groove (20) and electrically connected to the exposed first passivation contact structure (3).

2. The method for preparing a back contact cell according to claim 1, characterized in that: When preparing the silicon wafer (100), the preparation method specifically comprises: Providing a first sub-silicon wafer (302) as the first silicon substrate (1), and arranging the first passivation contact structure (3) on the back side of the first silicon substrate (1); Providing a second sub-silicon wafer as the second silicon substrate (2), and arranging the second passivation contact structure (4) on the back side of the second silicon substrate (2); Providing an oxidized bonding layer (5) on the back side of the second passivation contact structure (4); Laminating the front surface of the first silicon substrate (1) to the oxidized bonding layer (5) to form a laminated structure; The stacked structure is subjected to heat treatment so as to bond the first silicon substrate (1) to the oxide bonding layer (5).

3. The method for preparing a back contact cell according to claim 2, characterized in that: When the laminated structure is heat treated, the preparation method specifically includes: placing the laminated structure in a heat treatment furnace, gradually heating it to 800° C. to 1200° C., and continuously heating it for 1 hour to 2 hours.

4. The method for preparing a back contact cell according to claim 2, characterized in that: The first passivation contact structure (3) comprises a first tunneling oxide layer (31) and a first doping layer (32), and the second passivation contact structure (4) comprises a second tunneling oxide layer (41) and a second doping layer (42); When the first passivation contact structure (3) is provided, the preparation method specifically comprises: The first tunneling oxide layer (31) is provided on the back side of the first silicon substrate (1); The first doping layer (32) is arranged on the back side of the first tunneling oxide layer (31); And / or, when the second passivation contact structure (4) is provided, the preparation method specifically comprises: The second tunneling oxide layer (41) is provided on the back side of the second silicon substrate (2); The second doping layer (42) is arranged on the back side of the second tunneling oxide layer (41).

5. The method for preparing a back contact cell according to claim 4, characterized in that: One of the first doping layer (32) and the second doping layer (42) is doped with at least one element of the third main group, and the other is doped with at least one element of the fifth main group.

6. The method for preparing a back contact cell according to claim 2, characterized in that: The method for preparing the first silicon wafer (302) specifically comprises: Providing a target sub-silicon wafer (300); Using ion implantation to inject hydrogen ions into the target sub-silicon wafer (300) to form a hydrogen bubble layer (301) in the target sub-silicon wafer (300); The target sub-silicon wafer (300) is heated to above 1000° C., so that the hydrogen in the hydrogen bubble layer (301) expands and ruptures, so that the target sub-silicon wafer (300) is cracked along the hydrogen bubble layer (301) to obtain the first sub-silicon wafer (302).

7. The method for preparing a back contact cell according to claim 6, characterized in that: After the first sub-silicon wafer (302) is obtained by cleavage, the preparation method further comprises: polishing the surface of the first sub-silicon wafer (302).

8. The method for preparing a back contact cell according to claim 1, characterized in that: When an insulating layer (6) is provided on the back side of the silicon wafer (100), the preparation method specifically comprises: using atomic layer deposition technology to deposit the insulating layer (6) on the bottom wall and side wall of the first connection groove (10) and the surface of the first passivation contact structure (3).

9. The method for preparing a back contact cell according to claim 1, characterized in that: The preparation method further comprises: A third doping layer (7) is provided on the front surface of the second silicon substrate (2); A passivation film (8) is provided on the front surface of the third doping layer (7); An anti-reflection film (9) is arranged on the front surface of the passivation film (8).

10. A back contact battery cell, characterized in that: It comprises a silicon wafer (100) and a gate line (200), wherein the silicon wafer (100) comprises a first silicon substrate (1) and a second silicon substrate (2), and the gate line (200) comprises a first gate line (210) and a second gate line (220); A first passivation contact structure (3) is arranged on the back side of the first silicon substrate (1), a first sub-insulating layer (61) is arranged on the back side of the first passivation contact structure (3), a second passivation contact structure (4) is arranged on the back side of the second silicon substrate (2), the second passivation contact structure (4) is bonded to the front side of the first silicon substrate (1) via an oxidized bonding layer (5), and the first passivation contact structure (3) and the second passivation contact structure (4) have opposite polarities; A first connection groove (10) and a second connection groove (20) are formed on the back side of the silicon wafer (100), the first connection groove (10) passes through the first sub-insulating layer (61), the first passivation contact structure (3), the first silicon substrate (1) and the oxidized bonding layer (5), a second sub-insulating layer (62) is provided on the side wall of the first connection groove (10), and a part of the surface of the second passivation contact structure (4) is exposed through the first connection groove (10); The second connection groove (20) penetrates the first sub-insulating layer (61), and a portion of the surface of the first passivation contact structure (3) is exposed through the second connection groove (20); At least a portion of the first gate line (210) is located in the first connection groove (10) and is electrically connected to the exposed second passivation contact structure (4); At least a portion of the second gate line (220) is located in the second connection groove (20) and is electrically connected to the exposed first passivation contact structure (3).

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