A preparation process of a piezoelectric MEMS chip

Abstract

The present invention discloses a preparation process of a piezoelectric MEMS chip, which includes the steps of: growing a piezoelectric layer on the front surface of a substrate; etching the piezoelectric layer to pattern the piezoelectric layer; growing a mask layer on the surface of the piezoelectric layer away from the substrate, etching the mask layer to pattern the mask layer; etching the back surface of the substrate to form a back cavity; etching the front surface of the substrate to pattern the front surface of the substrate; and stripping the mask layer. Compared with the traditional process, the preparation process of the piezoelectric MEMS chip of the present invention adds a mask layer, which increases the stability of the fragile structure of the piezoelectric MEMS chip through the mask layer, prevents fracture during etching, and improves the yield rate; at the same time, when stripping the mask layer, the material of the mucous layer is Si3N4, and when the mucous layer is formed in an environment of high temperature and large stress, the mask layer is naturally stripped to form the final piezoelectric MEMS chip.

Description

Technical Field

[0001] The present invention relates to the technical field of the preparation of piezoelectric MEMS chips, and particularly relates to a preparation process of piezoelectric MEMS chips. Background Art

[0002] Currently, in the traditional preparation process of piezoelectric MEMS chips, after etching the piezoelectric layer to pattern the piezoelectric layer, the back of the substrate is then etched to form a back cavity to provide a vibration space for the diaphragm. However, after the piezoelectric layer is patterned, the piezoelectric layer will be hollowed out, making the entire chip structure relatively fragile. When etching the top silicon, usually through a dry process, the chip will undergo a series of operations such as rotation, spin coating, and etching. The fragile structure in the middle of the piezoelectric layer will be subjected to external forces, and structural fractures often occur, resulting in a decrease in the yield of the entire process line.

[0003] The patent document with the application number 201810685353.8 discloses a high-sensitivity piezoelectric MEMS sensor and its preparation method. The piezoelectric MEMS sensor includes a substrate and a piezoelectric stack structure; the substrate includes a substrate bottom layer, a substrate intermediate layer, and a substrate top layer from bottom to top in sequence; a back cavity is provided in the substrate bottom layer, and regularly distributed hollow grooves are provided in the substrate top layer; the piezoelectric stack structure is provided with a plurality of release holes that penetrate the piezoelectric stack structure and communicate with the hollow grooves.

[0004] In the piezoelectric MEMS sensor in its solution, when the piezoelectric stack structure, the substrate top layer, and the substrate intermediate layer are deformed, due to the existence of the hollow grooves, the flexural deformation of the piezoelectric film is increased, the strain degree of the piezoelectric film is strengthened, and a stronger electrical signal is output, thereby improving the sensitivity of the piezoelectric sensor.

[0005] However, its MEMS sensor preparation method also has the problem that after the piezoelectric layer is patterned, the piezoelectric layer will be hollowed out, making the entire chip structure relatively fragile. Through the dry process, the chip will undergo a series of operations such as rotation, spin coating, and etching. The fragile structure in the middle of the piezoelectric layer will be subjected to external forces, and structural fractures often occur, resulting in a decrease in the yield of the entire process line.

[0006] In reality, a preparation process of piezoelectric MEMS chips is needed to increase the structural stability of the piezoelectric layer before etching the top silicon. Summary of the Invention

[0007] In view of the above problems, the purpose of the present invention is to provide a preparation process of piezoelectric MEMS chips, which grows a mask layer on the piezoelectric layer to increase the structural stability of the piezoelectric layer and improve the yield of the entire process line.

[0008] The purpose of the present invention can be achieved through the following technical solutions: A preparation process of piezoelectric MEMS chips includes the steps:

[0009] S1. Grow a piezoelectric layer on the front side of the substrate;

[0010] S2. Etch the piezoelectric layer to pattern the piezoelectric layer;

[0011] S3. Grow a mask layer on the surface of the piezoelectric layer away from the substrate,

[0012] S4. Etch the mask layer to pattern the mask layer;

[0013] S5. Etch the back side of the substrate to form a back cavity;

[0014] S6. Etch the front side of the substrate to pattern the front side of the substrate;

[0015] S7. Strip the mask layer.

[0016] As a further aspect of the present invention: the substrate is an SOI substrate, and the SOI substrate includes a bottom silicon, a buried oxide layer, and a top silicon stacked.

[0017] As a further aspect of the present invention: the thickness of the top silicon is 1 - 3 μm.

[0018] As a further aspect of the present invention: the piezoelectric layer includes a bottom electrode, a piezoelectric thin film, and a top electrode grown in layers, and the growth steps of the piezoelectric layer include:

[0019] S11. Sputter - grow a bottom electrode on the front side of the substrate;

[0020] S12. Sputter - grow a piezoelectric thin film on the surface of the bottom electrode away from the substrate;

[0021] S13. Sputter - grow a top electrode on the surface of the piezoelectric thin film away from the substrate.

[0022] As a further aspect of the present invention: the etching of the piezoelectric layer in S2 includes the following steps:

[0023] S21. Use dry etching to pattern the top electrode;

[0024] S22. Use dry etching to pattern the piezoelectric thin film;

[0025] S23. Use dry etching to pattern the bottom electrode.

[0026] As a further aspect of the present invention: the material of the mask layer is SiO2.

[0027] As a further aspect of the present invention: when growing the mask layer on the surface of the piezoelectric layer away from the substrate in S3, the PECVD process is used, where the stress in the PECVD process is 10 - 50 MPa and the temperature is 150 - 250 °C.

[0028] As a further aspect of the present invention: The stripping mask layer in S7 includes:

[0029] S71. Grow a mucosal layer on the surface of the mask layer away from the substrate;

[0030] S72. During the process of growing the mucosal layer, the mask layer is stripped under the action of stress.

[0031] As a further aspect of the present invention: The material of the mucosal layer is Si3N4, and the thickness of the mucosal layer is 300 - 700 nm.

[0032] As a further aspect of the present invention: The mucosal layer is grown by PECVD process. The stress during this PECVD process is 300 - 500 MPa, and the temperature is 650 - 800 °C.

[0033] Advantages of the present invention:

[0034] 1. Compared with the traditional process, the preparation process of the piezoelectric MEMS chip of the present invention adds a mask layer, which increases the stability of the fragile structure of the piezoelectric MEMS chip through the mask layer, prevents fracture during etching, and improves the yield rate.

[0035] 2. When stripping the mask layer in the present invention, a mucosal layer is grown on the surface of the mask layer by PECVD process. The material of the mask layer is SiO2, the material of the mucosal layer is Si3N4, and the material of the top electrode is a metal element such as aluminum or gold, and an alloy or compound such as an aluminum - copper alloy. Therefore, by utilizing the fact that the adhesion between SiO2 and Si3N4 is greater than the adhesion between SiO2 and the metal, and by adjusting the parameters of PECVD, the mucosal layer is formed under high - temperature and high - stress environments, and the mask layer is naturally stripped to form the final piezoelectric MEMS chip. Description of the Drawings

[0036] Figure 1 It is a partial process schematic diagram of the preparation process using a silicon wafer substrate in Embodiment 1 of the present invention;

[0037] Figure 2 It is a partial process schematic diagram of the preparation process using a silicon wafer substrate in Embodiment 1 of the present invention;

[0038] Figure 3 It is a partial process schematic diagram of the preparation process using a SOI silicon wafer substrate in Embodiment 2 of the present invention;

[0039] Figure 4 It is a partial process schematic diagram of the preparation process using a SOI silicon wafer substrate in Embodiment 2 of the present invention;

[0040] Figure 5Schematic diagram of a process for stripping a mask layer using a silicon wafer substrate in Embodiment 3 of the present invention;

[0041] Figure 6 Schematic diagram of a process for stripping a mask layer using an SOI silicon wafer substrate in Embodiment 3 of the present invention.

[0042] 10. Substrate;

[0043] 100. SOI substrate; 110. Bottom silicon; 120. Buried oxide layer; 130. Top silicon;

[0044] 200. Piezoelectric layer;

[0045] 300. Mask layer;

[0046] 400. Mucosal layer. Specific embodiments

[0047] The embodiments of the present invention will be described in detail below. Examples of the embodiments are shown in the drawings, where the same or similar symbols represent the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the drawings are exemplary and are only used to explain the present invention and should not be construed as a limitation of the present invention.

[0048] Embodiment 1:

[0049] As Figure 1 shown, the substrate 10 uses a silicon wafer substrate. The substrate 10 has opposite front and back sides. First, a piezoelectric layer 200 is grown on the front side of the substrate 10, and the piezoelectric layer 200 is etched to pattern the piezoelectric layer 200.

[0050] The piezoelectric layer 200 includes a bottom electrode, a piezoelectric thin film, and a top electrode grown in layers. The growth steps of the piezoelectric layer 200 include: first, sputtering and growing a bottom electrode on the front side of the substrate 10, then sputtering and growing a piezoelectric thin film on the surface of the bottom electrode away from the substrate 10, and then sputtering and growing a top electrode on the surface of the piezoelectric thin film away from the substrate 10.

[0051] When etching the piezoelectric layer 200, the following steps can be taken: first, dry-etching the top electrode to pattern the top electrode, then dry-etching the piezoelectric thin film to pattern the piezoelectric thin film, and then dry-etching the bottom electrode to pattern the bottom electrode.

[0052] After the piezoelectric layer 200 is patterned, the back surface of the substrate 10 needs to be etched to form a back cavity to provide a vibration space for the diaphragm. However, after the piezoelectric layer 200 is patterned, the entire chip structure becomes relatively fragile due to the hollowing of the piezoelectric layer 200. During the etching process, through a dry process, the chip will undergo a series of operations such as rotation, spin coating, and etching. The fragile structure in the middle of the piezoelectric layer 200 will be affected by external forces, and structural fractures often occur, resulting in a decrease in the yield of the entire process line.

[0053] To address the above problems, a low-temperature, low-stress PECVD process can be used to grow a mask layer 300 on the surface of the piezoelectric layer 200. The mask layer 300 is used to improve the strength of the entire chip structure and reduce the occurrence of structural fractures during the process.

[0054] The material of the mask layer 300 can be SiO2, which is generated by the PECVD process. Among them, the stress during the PECVD process is controlled at 10 - 50 MPa, and the temperature is controlled at 150 - 250 °C.

[0055] As Figure 2 shown, after the mask layer 300 is generated, the mask layer 300 is etched to pattern the mask layer 300, and then the back surface of the substrate 10 is etched to form a back cavity; then the front surface of the substrate 10 is etched to pattern the front surface of the substrate 10, and finally the mask layer 300 is peeled off to complete the preparation of the piezoelectric MEMS chip.

[0056] Example 2:

[0057] Based on Example 1, the substrate 10 uses an SOI wafer substrate 100. The SOI substrate 100 includes a bottom silicon 110, a buried oxide layer 120, and a top silicon 130. Preferably, the thickness of the top silicon 130 is 1 - 3 μm.

[0058] As Figure 3 shown, a piezoelectric layer 200 is grown on the front surface of the SOI substrate 100, and then the piezoelectric layer 200 is etched to pattern the piezoelectric layer 200. Then, a mask layer 300 is grown on the surface of the piezoelectric layer 200 away from the substrate 10.

[0059] As Figure 4 shown, the mask layer 300 is etched to pattern the mask layer 300, and then the back surface of the substrate 10 is etched to form a back cavity, and then the front surface of the substrate 10 is etched to pattern the front surface of the substrate 10.

[0060] When using the SOI substrate 100, the back surface of the substrate 10 is etched to form a back cavity. The structure within the longitudinal projection range of the back cavity is the diaphragm. The specific steps are as follows: The bottom silicon 110 and the buried oxide layer 120 on the back surface of the substrate 10 are etched by a dry process to release the vibration space of the diaphragm. Then, when etching the top silicon 130 of the SOI substrate 100, IBE can be used to etch the top silicon 130 to pattern the top silicon 130.

[0061] Example 3:

[0062] Based on Example 1 or 2, as Figure 5 and Figure 6 shown, when stripping the mask layer 300, a mucosal layer 400 can be grown on the surface of the mask layer 300 away from the substrate 10. During the growth of the mucosal layer 400, the mask layer 300 is stripped under the stress of the mucosal layer 400.

[0063] The PECVD process is used to grow the mucosal layer 400 on the surface of the mask layer 300. The material of the mucosal layer 400 can be Si3N4. The thickness of the mucosal layer 400 is controlled at 300 - 700 nm. The mucosal layer 400 is grown using the PECVD process during growth. The stress during the PECVD process is controlled at 300 - 500 MPa, and the temperature is controlled at 650 - 800 °C.

[0064] By growing the mucosal layer 400, the adhesion between the mucosal layer 400 and the mask layer 300 is greater than the adhesion between the mask layer 300 and the top electrode of the piezoelectric layer 200. Due to the difference in process parameters, in a high-temperature environment, during the PECVD process with large stress and high temperature, the stress will cause the mucosal layer 400 to gradually strip the mask layer 300 during growth, causing the mask layer 300 to fall off, achieving the purpose of stripping the mask layer 300 and completing the preparation of the piezoelectric MEMS chip.

[0065] Through the processes of Example 1, Example 2, or Example 3 of the present invention, compared with the traditional process, the stability of the fragile structure of the piezoelectric MEMS chip is increased through the mask layer 300, preventing fracture during etching and improving the yield.

[0066] At the same time, when stripping the mask layer 300, the PECVD process is used to grow the mucosal layer 400 on the surface of the mask layer 300. The material of the mask layer 300 is SiO2, the material of the mucosal layer 400 is Si3N4, and the material of the top electrode is a metal element such as aluminum or gold, and an alloy or compound such as an aluminum-copper alloy. Therefore, the adhesion between SiO2 and Si3N4 is greater than the adhesion between SiO2 and the metal. By adjusting the parameters of the PECVD, the mucosal layer 400 is carried out in an environment of high temperature and large stress, so that the mask layer 300 is naturally stripped to form the final piezoelectric MEMS chip.

[0067] In the growth process of the mucosal layer 400 in the present invention, it is carried out in a high-temperature environment. In the high-temperature environment, the piezoelectric MEMS chip can be annealed, making the crystallinity of the piezoelectric material better, and the piezoelectric MEMS chip completes stress release, eliminating the need for a separate annealing operation and simplifying the operation.

[0068] The above are only the preferred specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention, according to the technical solution and inventive concept of the present invention, making equivalent substitutions or changes, shall be covered by the protection scope of the present invention.

Claims

1. A preparation process of a piezoelectric MEMS chip, characterized in that, Including the steps: S1. Grow a piezoelectric layer (200) on the front side of a substrate (10); S2. Etch the piezoelectric layer (200) to pattern the piezoelectric layer (200), and form holes penetrating the piezoelectric layer; S3. Grow a mask layer (300) on the surface of the piezoelectric layer (200) away from the substrate (10); S4. Etch the mask layer (300) to pattern the mask layer (300), and the patterned mask layer (300) is located on the upper surface of the piezoelectric layer (200); S5. Etch the back side of the substrate (10) to form a back cavity; S6. Etch the front side of the substrate (10) to pattern the front side of the substrate (10); S7. Strip the mask layer (300); Among them, when growing the mask layer (300) on the surface of the piezoelectric layer (200) away from the substrate (10) in S3, the PECVD process is adopted; among them, the stress in the PECVD process is 10 - 50 MPa, and the temperature is 150 - 250 °C.

2. The manufacturing process of the piezoelectric MEMS chip according to claim 1, characterized in that, The substrate (10) is an SOI substrate (100), and the SOI substrate (100) includes a bottom silicon (110), a buried oxide layer (120), and a top silicon (130) which are stacked.

3. The manufacturing process of the piezoelectric MEMS chip according to claim 2, characterized in that, The thickness of the top silicon (130) is 1 - 3 μm.

4. The preparation process of the piezoelectric MEMS chip according to claim 1 or 2, characterized in that, The piezoelectric layer (200) includes a bottom electrode, a piezoelectric thin film, and a top electrode which are grown in layers, and the growth steps of the piezoelectric layer (200) include: S11. Sputter and grow a bottom electrode on the front side of the substrate (10); S12. Sputter and grow a piezoelectric thin film on the surface of the bottom electrode away from the substrate (10); S13. Sputter and grow a top electrode on the surface of the piezoelectric thin film away from the substrate (10).

5. The preparation process of the piezoelectric MEMS chip according to claim 1 or 2, characterized in that: The etching of the piezoelectric layer (200) in S2 includes the following steps: S21. Adopt dry etching to pattern the top electrode; S22. Adopt dry etching to pattern the piezoelectric thin film; S23. Adopt dry etching to pattern the bottom electrode.

6. The preparation process of the piezoelectric MEMS chip according to claim 1 or 2, characterized in that: The material of the mask layer (300) is SiO2.

7. The preparation process of the piezoelectric MEMS chip according to claim 1 or 2, characterized in that, The stripping of the mask layer (300) in S7 includes: S71. Grow an adhesive layer (400) on the surface of the mask layer (300) away from the substrate (10); S72. During the growth of the adhesive layer (400), the mask layer (300) is stripped under the action of stress by the adhesive layer (400).

8. The manufacturing process of the piezoelectric MEMS chip according to claim 7, wherein: The material of the adhesive layer (400) is Si3N4, and the thickness of the adhesive layer (400) is 300 - 700 nm.

9. The preparation process of the piezoelectric MEMS chip according to claim 7, wherein: The adhesive layer (400) is grown by the PECVD process, and the stress in this PECVD process is 300 - 500 MPa, and the temperature is 650 - 800 °C.

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