Metal-insulating layer-metal capacitor and manufacturing method thereof
By using the combination of super crystal layers and negative capacitor silicon dioxide layers in the metal-insulation layer-metal capacitance, the problem of building a high-capacitance capacitance structure in a limited area has been solved, and The effect of significantly enhanced electricity values.
Patent Information
- Application Number
- CN202310908666.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-07-24
- Publication Date
- 2025-01-24
AI Technical Summary
The prior art is difficult to construct a capacitance structure with high capacitance value in a limited area, especially in the condition that component sizes are constantly shrinking, the method of increasing the conductive plate area to increase the capacitance value does not meet the requirements of today's circuit components.
The capacitance layer of the metal-insulating layer-metal capacitance is used as a super crystal layer. The nitrogen-containing material with a high-energy band gap and a silicon of a negative capacitance voltage coefficient is set on the basis of the perovskin mineral layer. Form the capacitor structure with high -agency constant.
Under the condition that the capacitance volume is not increased, the capacitance value is significantly improved, and the problem of building a high -capacitor value capacitance structure in the limited area is solved. At the same time, the problem of leakage and charging and discharge of the perovskite -type material layer is avoided.
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Figure CN119365066A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a Metal-Insulator-Metal (MIM) capacitor, and in particular to a Metal-Insulator-Metal capacitor using a perovskite superlattice layer as a capacitor dielectric layer. Background Art
[0002] The ability of a capacitor to store charge depends on the size of the dielectric constant, the distance between the two conductive plates, and the area of the conductive plates. In order to increase the circuit integration and reduce costs, capacitors must develop towards high capacitance density to increase the circuit integration. Under the condition that materials with higher dielectric constants have not yet been found and the distance between the conductive plates cannot be shortened any further, the only way to increase the storage charge is to increase the area of the conductive plates. However, under the current process technology requirements of high integration and the continuous reduction of component size, increasing the area of the conductive plates must increase the component size, which does not meet the current requirements for circuit components. Therefore, how to construct a capacitor structure with high capacitance value in a limited area has become an important research topic. Summary of the invention
[0003] In view of this, the present invention uses a superlattice layer as a capacitor dielectric layer of a metal-insulator-metal capacitor to increase the capacitance value without increasing the capacitor volume.
[0004] According to a preferred embodiment of the present invention, a metal-insulator-metal capacitor includes a lower electrode, a dielectric layer, a superlattice layer, a silicon dioxide layer and an upper electrode stacked from bottom to top, wherein the superlattice layer contacts the dielectric layer and the silicon dioxide layer, and the silicon dioxide layer has a negative voltage coefficient of capacitance (VCC).
[0005] According to another preferred embodiment of the present invention, a method for manufacturing a metal-insulator-metal capacitor includes sequentially forming a lower electrode, a dielectric layer, a superlattice layer, a silicon dioxide layer and an upper electrode stacked from bottom to top, wherein the superlattice layer contacts the dielectric layer and the silicon dioxide layer, and the silicon dioxide layer has a negative voltage coefficient of capacitance.
[0006] In order to make the above-mentioned objectives, features and advantages of the present invention more clearly understood, the following is a detailed description of the preferred embodiments and the accompanying drawings. However, the following preferred embodiments and the accompanying drawings are only for reference and explanation, and are not intended to limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS
[0007] Figures 1 to 7A method for manufacturing a metal-insulator-metal capacitor is illustrated according to a preferred embodiment of the present invention.
[0008]
Main component symbol description
[0009] 10: Base
[0010] 12: Interlayer dielectric layer
[0011] 14: Lower electrode
[0012] 16: Dielectric layer
[0013] 18: Superlattice layer
[0014] 18a: Strontium Titanium Oxide
[0015] 18b: Barium Titanium Oxide
[0016] 20:Silicon dioxide layer
[0017] 22: Upper electrode
[0018] 24: Intermetallic dielectric layer
[0019] 26: Upper electrode contact plug
[0020] 28: Lower electrode contact plug
[0021] 100: Metal-insulator-metal capacitor DETAILED DESCRIPTION
[0022] Figures 1 to 7 A method for manufacturing a metal-insulator-metal capacitor is illustrated according to a preferred embodiment of the present invention.
[0023] like Figure 1 As shown, a substrate 10 is first provided, on which a transistor (not shown) can be selectively formed, and then an interlayer dielectric layer 12 is formed to cover the substrate 10, and in the interlayer dielectric layer 12, a metal interconnect (not shown) can be selectively formed to connect the aforementioned transistor.
[0024] like Figure 2 As shown, a lower electrode 14 is formed to cover and contact the interlayer dielectric layer 12. The lower electrode 14 is formed by physical vapor deposition, chemical vapor deposition, atomic layer deposition or other deposition methods. Since the lower electrode 14 is composed of a columnar grain structure, the lower electrode 14 has a concave and convex upper surface. The lower electrode 14 includes TiN, Al, Ta, Cu, Ti or Ta.
[0025] like Figure 3As shown, a dielectric layer 16 is formed to cover and contact the lower electrode 14. The dielectric layer 16 is preferably a nitrogen-containing material with a high energy band gap, such as aluminum nitride (AlN x ) or boron nitride (BN x ), the dielectric layer 16 is formed by physical vapor deposition, chemical vapor deposition, atomic layer deposition or other deposition methods. Since the lower electrode 14 has a concave and convex upper surface, the dielectric layer 16 can fill the concave and convex positions of the lower electrode 14, and the dielectric layer 16 is used to provide a flat surface on the lower electrode 14. In other words, the surface of the dielectric layer 16 is flat, so that the subsequently formed material layers can be stacked on the flat surface.
[0026] like Figure 4 As shown, a superlattice layer 18 is formed to contact the dielectric layer 16. In this embodiment, the superlattice layer 18 is formed by periodically stacking at least two perovskite material layers. In different embodiments, more than two perovskite material layers can also be stacked. The perovskite material layer can be formed by physical vapor deposition, chemical vapor deposition, atomic layer deposition or other deposition methods at a temperature ranging from 350°C to 450°C. In addition, the perovskite material layer includes strontium titanium oxide (SrTiO x ), barium titanium oxide (BaTiO x ), calcium titanium oxide (CaTiO x ), magnesium titanium oxide (CaMgO x ) or lead titanium oxide (PbTiO x ), in addition, the superlattice layer 18 needs to have at least 5 layers of perovskite material layers, and the total number of perovskite material layers of the superlattice layer 18 is preferably between 5 and 20 layers. According to a preferred embodiment of the present invention, the superlattice layer 18 can be formed by periodically alternating stacking of strontium titanium oxide 18a / barium titanium oxide 18b. Furthermore, the superlattice layer 18 has a positive voltage coefficient of capacitance (VCC).
[0027] According to another preferred embodiment of the present invention, the superlattice layer 18 can also be made of metal-doped titanium oxide material, for example, by periodically and alternately stacking two different metal-doped titanium oxides, or by periodically and alternately stacking titanium oxides doped with the same metal but with different concentrations.
[0028] like Figure 5As shown, a silicon dioxide layer 20 is formed to cover and contact the superlattice layer 18. It is noteworthy that the silicon dioxide layer 20 has a negative voltage coefficient of capacitance, and the silicon dioxide layer 20 is annealed, polarized and amorphous silicon dioxide. According to a preferred embodiment of the present invention, the manufacturing method of the silicon dioxide layer 20 includes forming an amorphous silicon silicon dioxide layer 20 by physical vapor deposition, chemical vapor deposition or atomic layer deposition, and then performing an annealing process on the silicon dioxide layer 20 at a temperature of 400°C, so that the silicon dioxide layer 20 is transformed into a polarized layer with a negative voltage coefficient of capacitance.
[0029] Then, an upper electrode 22 is formed to cover and contact the silicon dioxide layer 20. The upper electrode 22 is formed by physical vapor deposition, chemical vapor deposition, atomic layer deposition or other deposition methods. Since the upper electrode 22 is composed of a columnar grain structure, the upper electrode 22 has a concave and convex upper surface. The upper electrode 22 includes TiN, Al, Ta, Cu, Ti or Ta.
[0030] like Figure 6 As shown, an etching process is performed, using the dielectric layer 16 as an etching stop layer to remove a portion of the upper electrode 22, the silicon dioxide layer 20, and the superlattice layer 18. At this time, a portion of the dielectric layer 16 is exposed, and then a metal interlayer dielectric layer 24 is formed to cover the upper electrode 22, the silicon dioxide layer 20, the superlattice layer 18, the dielectric layer 16, and the lower electrode 14.
[0031] like Figure 7 As shown, an upper electrode contact plug 26 is formed through the intermetallic dielectric layer 24 to contact the upper electrode 22, and a lower electrode contact plug 28 is formed through the intermetallic dielectric layer 24 and the dielectric layer 16 to contact the lower electrode 14. At this point, the metal-insulator-metal capacitor 100 of the present invention has been completed.
[0032] According to another preferred embodiment of the present invention, the present invention provides a metal-insulator-metal capacitor. Figure 7 As shown, a metal-insulator-metal capacitor 100 is disposed on a substrate 10, and an interlayer dielectric layer 12 is disposed on the substrate 10. The interlayer dielectric layer 12 is sandwiched between the metal-insulator-metal capacitor 100 and the substrate 10. The metal-insulator-metal capacitor 100 includes a lower electrode 14, a dielectric layer 16, a superlattice layer 18, a silicon dioxide layer 20 and an upper electrode 22 stacked from bottom to top, wherein the superlattice layer 18 contacts the dielectric layer 16 and the silicon dioxide layer 20, and the silicon dioxide layer 20 has a negative voltage coefficient of capacitance. An upper electrode contact plug 26 contacts the upper electrode 22, and a lower electrode contacts the lower electrode 14. The upper electrode contact plug 26 and the lower electrode contact plug 28 are both located on the upper surface of the same side of the substrate 10.
[0033] The substrate 10 comprises a silicon substrate, a germanium substrate, a gallium arsenide substrate, a silicon germanium substrate, an indium phosphide substrate, a gallium nitride substrate, a silicon carbide substrate or a silicon-on-insulator substrate. The lower electrode 14 and the upper electrode 22 each independently comprise TiN, Al, Ta, Cu, Ti or Ta. The dielectric layer 16 is preferably a nitrogen-containing material having a high energy bandgap, such as aluminum nitride (AlN x ) or boron nitride (BN x ), due to the high energy band gap, the dielectric layer 16 has a good anti-leakage function.
[0034] The superlattice layer 18 comprises at least two perovskite material layers stacked alternately and periodically. The superlattice layer 18 needs to have at least 5 layers. Preferably, the total number of perovskite material layers of the superlattice layer 18 is preferably between 5 and 20 layers. The thickness of each perovskite material layer is between 10 nanometers and 60 nanometers. The total thickness of the superlattice layer 18 is between 100 nanometers and 2400 nanometers. The perovskite material layer comprises strontium titanium oxide (SrTiO x ), barium titanium oxide (BaTiO x ), calcium titanium oxide (CaTiO x ), magnesium titanium oxide (CaMgO x ) or lead titanium oxide (PbTiO x ), the super lattice layer preferably uses a low crystallinity perovskite material layer. For example, the super lattice layer 18 can be composed of strontium titanium oxide 18a / barium titanium oxide 18b periodically and alternately stacked in 5 or more layers. In addition, the silicon dioxide layer 20 is annealed, polarized and amorphous silicon dioxide.
[0035] Since the perovskite material layer has a high dielectric constant, the present invention uses the perovskite material layer as the dielectric layer of the capacitor, but the energy band gap of the perovskite material layer is small so it is easy to leak electricity, and the voltage coefficient of the capacitor of the perovskite material layer is positive, so the charging and discharging at low voltage and high voltage is nonlinear. Therefore, the present invention arranges a nitrogen-containing material with a high energy band gap below the superlattice layer made of the perovskite material layer to prevent the perovskite material layer from leaking electricity, and further arranges a silicon dioxide layer with a negative voltage coefficient of capacitance above the superlattice layer made of the perovskite material layer to balance the voltage coefficient of the positive capacitance. In this way, the metal-insulating layer-metal capacitor of the present invention can have the advantage of the high dielectric constant of the perovskite material layer, and avoid the problem of leakage of the perovskite material layer and nonlinear charging and discharging.
[0036] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.
Claims
1. A metal-insulator-metal capacitor, comprising: The lower electrode, the dielectric layer, the superlattice layer, the silicon dioxide layer and the upper electrode are stacked from bottom to top; wherein the superlattice layer contacts the dielectric layer and the silicon dioxide layer, and the silicon dioxide layer has a negative voltage coefficient of capacitance (VCC).
2. The metal-insulator-metal capacitor of claim 1, wherein the silicon dioxide layer is annealed and polarized silicon dioxide. 3 . The metal-insulator-metal capacitor as claimed in claim 1 , wherein the silicon dioxide layer is amorphous silicon dioxide.
4. The metal-insulator-metal capacitor as claimed in claim 1, wherein the superlattice layer comprises more than 5 layers of perovskite material.
5. The metal-insulator-metal capacitor as claimed in claim 1, wherein the superlattice layer comprises more than 5 perovskite material layers, and the thickness of each perovskite material layer is between 10 nanometers and 60 nanometers.
6. The metal-insulator-metal capacitor of claim 1, wherein the superlattice layer comprises strontium titanium oxide (SrTiO x ), barium titanium oxide (BaTiO x ), calcium titanium oxide (CaTiO x ), magnesium titanium oxide (CaMgO x ) or lead titanium oxide (PbTiO x ). 7 . The metal-insulator-metal capacitor of claim 1 , wherein the superlattice layer has a positive capacitance voltage coefficient.
8. The metal-insulator-metal capacitor of claim 1, wherein the dielectric layer comprises aluminum nitride (AlN x ) or boron nitride (BN x ).
9. The metal-insulator-metal capacitor of claim 1, wherein the top electrode comprises TiN, Al, Ta, Cu, Ti or Ta, and the bottom electrode comprises TiN, Al, Ta, Cu, Ti or Ta. 10 . The metal-insulator-metal capacitor as claimed in claim 1 , wherein the upper electrode contacts the silicon dioxide layer, and the lower electrode contacts the dielectric layer.
11. A method for manufacturing a metal-insulator-metal capacitor, comprising: A lower electrode, a dielectric layer, a superlattice layer, a silicon dioxide layer and an upper electrode are stacked from bottom to top in sequence; wherein the superlattice layer contacts the dielectric layer and the silicon dioxide layer, and the silicon dioxide layer has a negative voltage coefficient of capacitance (VCC).
12. A method for manufacturing a metal-insulator-metal capacitor as claimed in claim 11, wherein the manufacturing method of the superlattice layer includes utilizing a deposition process to periodically and alternately stack perovskite material layers at a process temperature of 350° C. to 450° C.
13. The method for manufacturing a metal-insulator-metal capacitor as claimed in claim 12, wherein the deposition process comprises atomic layer deposition, chemical vapor deposition or physical vapor deposition.
14. The method for manufacturing a metal-insulator-metal capacitor as claimed in claim 11, wherein the manufacturing method of the silicon dioxide layer comprises: depositing the silicon dioxide layer; and The silicon dioxide layer is subjected to an annealing process at a temperature of 400° C. 15 . The method for manufacturing a metal-insulator-metal capacitor as claimed in claim 11 , wherein the silicon dioxide layer is amorphous silicon and polarized silicon dioxide. 16 . The method for manufacturing a metal-insulator-metal capacitor as claimed in claim 11 , wherein the superlattice layer comprises more than 5 layers of perovskite material.
17. The method for manufacturing a metal-insulator-metal capacitor as claimed in claim 11, wherein the superlattice layer comprises more than 5 layers of perovskite material layers, and the thickness of each perovskite material layer is between 10 nanometers and 60 nanometers.
18. The method for manufacturing a metal-insulator-metal capacitor as claimed in claim 11, wherein the superlattice layer comprises strontium titanium oxide (SrTiO x ), barium titanium oxide (BaTiO x ), calcium titanium oxide (CaTiO x ), magnesium titanium oxide (CaMgO x ) or lead titanium oxide (PbTiO x ). 19 . The method for manufacturing a metal-insulator-metal capacitor as claimed in claim 11 , wherein the superlattice layer has a positive capacitance voltage coefficient.
20. The method for manufacturing a metal-insulator-metal capacitor as claimed in claim 11, wherein the dielectric layer comprises aluminum nitride (AlN x ) or boron nitride (BN x ).