Low power island for display interface

Abstract

A mobile communication device includes: a first physical layer circuit powered by a first power source and configured to communicate a first data frame to a display controller through a first serial bus in a high speed mode, and suppress communication through the first serial bus when the display controller is operating in a low power mode; a second physical layer circuit powered by a second power source and configured to communicate a second data frame to the display controller over a second serial bus at a second data rate in the low power mode; a first processor powered by the first power source and configured to generate the first data frame; and a second processor powered by the second power source and configured to provide the second data frame to the second physical layer circuitry when the display controller operates in the low power mode.

Description

Technical Field

[0001] The present disclosure relates generally to serial communications over a serial bus in a wireless communication device, and more particularly to a low power mode for communications for a display subsystem interface. Background Art

[0002] Mobile communication devices typically include various components, such as circuit boards, integrated circuit (IC) devices, application specific integrated circuit (ASIC) devices, and / or system on chip (SoC) devices. Types of these components may include processing circuits, user interface components, storage devices, and other peripheral components that communicate via a serial bus. The serial bus may operate according to a standardized protocol or a proprietary protocol. In one example, the serial bus may operate according to an Inter-Integrated Circuit (I2C or I 2 C) communication protocol. The I2C bus is configured as a multi-drop bus and was developed to connect low-speed peripheral devices to processors. The two wires of the I2C bus include a serial data line (SDA) that carries the data signal and a serial clock line (SCL) that carries the clock signal.

[0003] In another example, the serial bus can operate according to a serial peripheral interface (SPI) communication protocol, in which a clock signal controls a synchronous serial data exchange between a master device and a slave device. The SPI protocol enables the use of two or more data lines of the serial bus to communicate data and allows the serial bus to be configured for multi-station operation. Since one or more of the data lines can be shared by a receiving device, a select signal provided to a device coupled to the bus is used to control access to the shared data lines.

[0004] In another example, the serial bus may be operated according to a multi-master protocol so that one or more devices may be designated as a bus master or host device for the serial bus. The device may be used as a bus master in some transmissions or as a slave or subordinate device in other transmissions. In one example, an improved inter-integrated circuit bus (I3C) protocol may be used to control operations on the serial bus. The I3C protocol is defined by the Mobile Industry Processor Interface (MIPI) Alliance and derives certain specific implementation aspects from the I2C protocol. In another example, the radio frequency front end (RFFE) interface defined by the MIPI Alliance provides a communication interface for controlling various radio frequency (RF) front-end devices, including power amplifiers (PA), low noise amplifiers (LNA), antenna tuners, filters, sensors, power management devices, switches, etc. These devices may be collocated in a single IC device or provided in multiple IC devices. Multiple antennas and radio transceivers may be provided in a mobile communication device to support multiple concurrent RF links. In another example, the system power management interface (SPMI) defined by the MIPI Alliance provides a hardware interface that can be implemented between a baseband or application processor and peripheral components. SPMI may be used to support power management and other operations within a device or system.

[0005] A number of standards are defined for interconnecting certain types of components in a mobile communication device. For example, there are multiple types of interfaces defined for communication between an application processor and a display or camera component in a mobile communication device. Some components employ interfaces that conform to one or more standards or protocols specified by the MIPI Alliance, including standards or protocols for the Camera Serial Interface (CSI) and the Display Serial Interface (DSI).

[0006] MIPI Alliance DSI, DSI-2 (individually or collectively referred to herein as DSI) and CSI and CSI-2 (individually or collectively referred to herein as CSI) standards define wired interfaces that can be deployed within an IC or between some combination of an IC device and a SoC device. The CSI protocol can be used to couple a camera and an application processor. The DSI protocol can be used to couple an application processor and a display subsystem. The low-level physical layer (PHY) interface in each of these applications can be implemented according to the MIPI Alliance C-PHY or D-PHY standards and protocols. High-speed modes and low-power modes of communication are defined for C-PHY interfaces and D-PHY interfaces. The C-PHY high-speed mode uses low-voltage multi-phase signals sent in different phases on a 3-wire link. The D-PHY high-speed mode uses multiple 2-wire channels to carry low-voltage differential signals. The low-power modes of the C-PHY interface and the D-PHY interface provide lower rates than the high-speed mode and send signals at higher voltages.

[0007] As device technology improves, the combination of the need for higher data rates on the serial bus and the use of multi-mode display panels tends to increase power consumption. Display subsystems and related circuits exchange data at high data rates and consume a significant portion of the power available in mobile communication devices and other portable devices. There is a continuing need to improve power conservation in mobile communication devices and other portable devices. Summary of the invention

[0008] Certain aspects of the present disclosure relate to systems, apparatus, methods, and techniques that enable mobile communication devices and other portable devices to idle data communication links between and within processors and display subsystems, and to enable larger portions of mobile communication devices and other portable devices to enter sleep modes when displays are dormant.

[0009] In various aspects of the present disclosure, a mobile communication device includes: a display controller coupled to a display panel; a first physical layer circuit powered by a first power supply; a second physical layer circuit powered by a second power supply; a first processor powered by the first power supply; and a second processor powered by the second power supply. The first physical layer circuit is configured to communicate a first data frame to the display controller via a first serial bus at a first data rate when the display controller operates in a high-speed mode, and to suppress communication via the first serial bus when the display controller operates in a low-power mode. The second physical layer circuit is configured to communicate a second data frame to the display controller via a second serial bus at a second data rate when the display controller operates in the low-power mode. The first processor is configured to generate the first data frame, and the second processor is configured to provide the second data frame to the second physical layer circuit when the display controller operates in the low-power mode.

[0010] In various aspects of the present disclosure, a method for operating a display in a mobile communication device includes: configuring a first physical layer circuit powered by a first power supply to: communicate a first data frame to a display controller at a first data rate via a first serial bus when the display controller operates in a high-speed mode, and suppressing communication via the first serial bus when the display controller operates in a low-power mode. The method also includes configuring a second physical layer circuit powered by a second power supply to communicate a second data frame to the display controller at a second data rate via a second serial bus when the display controller operates in the low-power mode. The method also includes: configuring a first processor to generate the first data frame, the first processor being powered by the first power supply; and configuring a second processor to provide the second data frame to the second physical layer circuit when the display controller operates in the low-power mode, the second processor being powered by the second power supply.

[0011] In various aspects of the present disclosure, a device includes a component for communicating with a display controller and a component for providing display data to the component for communicating with the display controller. The component for communicating with the display controller includes: a first physical layer circuit, the first physical layer circuit is powered by a first power supply and is operable to communicate a first data frame to the display controller at a first data rate through a first serial bus when the display controller operates in a high-speed mode, and when the display controller operates in a low-power mode, suppress communication through the first serial bus; and a second physical layer circuit, the second physical layer circuit is powered by a second power supply and is operable to communicate a second data frame to the display controller at a second data rate through a second serial bus when the display controller operates in the low-power mode. The component for providing display data to the component for communicating with the display controller includes: a first processor, the first processor is powered by the first power supply and is configured to generate the first data frame; and a second processor, the second processor is powered by the second power supply and is configured to provide the second data frame to the second physical layer circuit when the display controller operates in the low-power mode.

[0012] In various aspects of the present disclosure, a processor-readable storage medium includes code for: configuring a first physical layer circuit powered by a first power supply to: communicate a first data frame to a display controller at a first data rate via a first serial bus when the display controller operates in a high-speed mode, and suppressing communication via the first serial bus when the display controller operates in a low-power mode. The method also includes configuring a second physical layer circuit powered by a second power supply to communicate a second data frame to the display controller at a second data rate via a second serial bus when the display controller operates in the low-power mode. The method also includes: configuring a first processor to generate the first data frame, the first processor being powered by the first power supply; and configuring a second processor to provide the second data frame to the second physical layer circuit when the display controller operates in the low-power mode, the second processor being powered by the second power supply.

[0013] In some aspects, the first power supply provides power at a voltage higher than the voltage provided by the second power supply in the high-speed mode. When the display controller operates in a low-power mode, the voltage provided by the first power supply may be reduced. When the display controller operates in a low-power mode, one or more devices or circuits powered by the first power supply may enter an idle, dormant, sleep, or static mode. For example, the first processor may be configured to enter a dormant mode when the display controller operates in a low-power mode. In another example, the first physical layer circuit may be configured to enter a dormant mode when the display controller operates in a low-power mode. When the physical layer circuit enters the dormant mode, a low-power serial bus coupled to the first physical layer circuit may be idle.

[0014] In some aspects, the first physical layer circuit can be configured to operate according to the MIPI Alliance DSI protocol. In one example, the DSI protocol can follow or be compatible with the C-PHY protocol. In another example, the DSI protocol can follow or be compatible with the D-PHY protocol.

[0015] In some aspects, the second physical layer circuit may be configured to operate according to a serial data communication protocol. In one example, the physical layer circuit is configured to operate according to an SPI protocol. In another example, the physical layer circuit is configured to operate according to a CCI protocol. In another example, the physical layer circuit is configured to operate according to an I2C protocol. In another example, the physical layer circuit is configured to operate according to an I3C protocol. In another example, the physical layer circuit is configured to operate according to an SPMI protocol.

[0016] In some aspects, the second processor is configured to communicate with a touch panel interface associated with the display panel through the second physical layer circuit. The second processor can be configured to manage and control the operation of the touch panel interface. The second processor can be configured to communicate with the touch panel interface when the display controller operates in a high-speed mode. The second processor can be configured to communicate with the touch panel interface when the display controller operates in a low-power mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 An apparatus is illustrated that employs a data link between IC devices and selectively operates according to a standard or proprietary protocol.

[0018] Figure 2 Examples of interface circuits that may be adapted according to certain aspects of the present disclosure are illustrated.

[0019] Figure 3 A system architecture of an apparatus employing a data link between IC devices is illustrated.

[0020] Figure 4An example of a C-PHY interface that may be adapted according to certain aspects disclosed herein is illustrated.

[0021] Figure 5 An example of a D-PHY interface that may be adapted according to certain aspects disclosed herein is illustrated.

[0022] Figure 6 Certain aspects of a 2-data-wire serial peripheral interface that may be adapted according to certain aspects disclosed herein are illustrated.

[0023] Figure 7 Certain aspects of a quad serial peripheral interface that may be adapted according to certain aspects disclosed herein are illustrated.

[0024] Figure 8 Systems that include a display subsystem interface and that may be adapted according to certain aspects of the present disclosure are illustrated.

[0025] Fig. 9 A system operating in a low power mode according to certain aspects of the present disclosure is illustrated.

[0026] Fig.10 Illustrated Fig. 9 Certain aspects of high-speed mode operation of the system illustrated in FIG.

[0027] Fig.11 One example of an apparatus employing processing circuitry that may be adapted according to certain aspects disclosed herein is illustrated.

[0028] Fig.12 is a flow chart illustrating a method for operating a display in a mobile communication device according to certain aspects disclosed herein.

[0029] Fig.13 A first example of a hardware implementation of a communication device adapted according to certain aspects disclosed herein is illustrated. DETAILED DESCRIPTION

[0030] The specific embodiments described below in conjunction with the accompanying drawings are intended as descriptions of various configurations and are not intended to represent the only configurations with which the concepts described herein can be practiced. In order to provide a thorough understanding of the various concepts, the specific embodiments include specific details. However, it is obvious to those skilled in the art that these concepts can be practiced without these specific details. In some instances, in order to avoid blurring such concepts, known structures and components are shown in block diagram form.

[0031] Several aspects of the present invention will now be described with reference to various devices and methods. These devices and methods will be described in the following detailed description and illustrated in the accompanying drawings by various blocks, modules, components, circuits, steps, processes, algorithms, etc. (collectively referred to as "elements"). These elements can be implemented using electronic hardware, computer software, or any combination thereof. Whether these elements are implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system.

[0032] Data communication links employed by SoCs and other IC devices to connect processors with modems and other peripherals may operate according to industry or proprietary standards or protocols associated with certain functions or types of devices. In the example of display panels, display subsystems, and display drivers, communication standards and protocols defined by the MIPI Alliance are often used. For example, the Display Serial Interface Provides C-PHY and D-PHY standards and protocols for defining, configuring, and controlling high-speed serial interfaces between a host processor and a display module. Control and management protocols may be used to operate other serial buses coupling the host processor and the display module, which may include SPMI, I2C, I3C, and / or other protocols.

[0033] Mobile communication handsets typically support a low-power operating mode that can be initiated when the handset is idle. In conventional handsets that use the DSI protocol to manage certain serial data links, there is almost no difference between the high-speed and low-power operating modes of the serial data link. Therefore, when the handset is idle and the DSI protocol is used to manage the serial data link, it may be difficult or impossible to allow a processor in a host device that includes the serial data link or related circuitry to enter a low-power mode. According to certain aspects of the present disclosure, when the low-power mode is activated, data communications between the host device and the display driver can be transmitted to the low-power serial data link. The DSI physical layer circuit can be idle, and the processor in the host device can enter a sleep mode.

[0034] Example of a device using a serial data link

[0035] According to certain aspects of the present disclosure, a serial data link may be used to interconnect electronic devices that are subcomponents of devices such as: a cellular phone, a smartphone, a Session Initiation Protocol (SIP) phone, a laptop, a notebook, a netbook, a smartbook, a personal digital assistant (PDA), a satellite radio, a Global Positioning System (GPS) device, a smart home device, smart lighting, a multimedia device, a video device, a digital audio player (e.g., an MP3 player), a camera, a game console, an entertainment device, a vehicle component, a wearable computing device (e.g., a smart watch, a health or fitness tracker, glasses, etc.), an appliance, a sensor, a security device, a vending machine, a smart meter, a drone, a multi-rotor helicopter, or any other similarly functional device.

[0036] Figure 1 An example of an apparatus 100 employing a data communication bus is illustrated. The apparatus 100 may include a processing circuit 102 having a plurality of circuits or devices 104, 106, and / or 108, which may be implemented in one or more ASICs or in a SoC. In one example, the apparatus 100 may be a communication device, and the processing circuit 102 may include a processing device provided in the ASIC 104, one or more peripheral devices 106, and a transceiver 108 that enables the apparatus to communicate with a radio access network, a core access network, the Internet, and / or another network via an antenna 124.

[0037] ASIC 104 may have one or more processors 112, one or more modems 110, onboard memory 114, bus interface circuit 116, and / or other logic circuits or functions. Processing circuit 102 may be controlled by an operating system, which may provide an application programming interface (API) layer that enables one or more processors 112 to execute software modules residing in onboard memory 114 or other processor-readable storage 122 provided on processing circuit 102. Software modules may include instructions and data stored in onboard memory 114 or processor-readable storage 122. ASIC 104 may access its onboard memory 114, processor-readable storage 122, and / or storage devices external to processing circuit 102. Onboard memory 114, processor-readable storage 122 may include read-only memory (ROM) or random access memory (RAM), electrically erasable programmable ROM (EEPROM), flash cards, or any memory device that may be used in processing systems and computing platforms. The processing circuit 102 may include, implement, or access a local database or other parameter storage device that can maintain operating parameters and other information for configuring and operating the device 100 and / or the processing circuit 102. The local database may be implemented using registers, database modules, flash memory, magnetic media, EEPROM, floppy disk or hard disk, etc. The processing circuit 102 may also be operatively coupled to external devices such as an antenna 124, a display 126, operator controls (such as switches or buttons 128, 130 and / or an integrated or external keyboard 132), and other components. The user interface module may be configured to operate with the display 126, external keyboard 132, etc., through a dedicated communication link or through one or more serial data interconnects.

[0038] The processing circuit 102 may provide one or more buses 118a, 118b, 120 that enable two or more devices 104, 106, and / or 108 to communicate. In one example, the ASIC 104 may include one or more bus interface circuits 116 that include a combination of circuits, counters, timers, control logic, and other configurable circuits or modules. In one example, the bus interface circuit 116 may be configured to operate according to a communication specification or protocol defined by a standard. The processing circuit 102 may include or control power management functions that configure and manage the operation of the device 100.

[0039] Figure 2Examples of interface circuits that may be adopted or adapted according to certain aspects of the present disclosure are illustrated. The first interface circuit is configured as a camera subsystem 200, and the second interface circuit is configured as a display subsystem 250. For example, the interface circuit may be deployed in a mobile communication device. The camera subsystem 200 may include a CSI-2 defined communication link between an image sensor 202 and an application processor 212. The communication link may include a high data rate data transmission link 210 used by the image sensor 202 to send image data to the application processor 212 using a transmitter 206. The high data rate data transmission link 210 may be configured and operated according to a D-PHY or C-PHY protocol. The application processor 212 may include a crystal oscillator (XO 214) or other clock source to generate a clock signal 222 that controls the operation of the transmitter 206. The clock signal 222 may be processed by a phase-locked loop (PLL) 204 in the image sensor 202. In some cases, the clock signal 222 may also be used by a D-PHY or C-PHY receiver 216 in the application processor 212. The communication link may include a camera control interface (CCI), which is similar in nature to an inter-integrated circuit bus (I2C) interface. The CCI bus may include a serial clock (SCL) line that carries a clock signal and a serial data (SDA) line that carries data. The CCI link 220 may be bidirectional and may operate at a lower data rate than the high data rate data transmission link 210. The application processor 212 may use the CCI link 220 to exchange control and configuration information with the image sensor 202. The application processor 212 may include a CCI bus master 218, and the image sensor 202 may include a CCI slave 208.

[0040] The display subsystem 250 may include a unidirectional data link 258 that may be configured and operated according to a D-PHY or C-PHY protocol. In the application processor 252, a clock source such as a PLL 254 may be used to generate a bit clock signal used by a D-PHY or C-PHY receiver 256 to control transmissions on the data link 258. At the display driver 260, a D-PHY or C-PHY receiver 262 may extract embedded clock information from a symbol sequence transmitted on the data link or from a clock channel provided in the data link 258.

[0041] Certain aspects disclosed herein relate to systems, devices, and methods that support a wide range of interface protocols and can operate using different physical media. Figure 2As shown, for example, the camera subsystem 200 and / or the display subsystem 250 may communicate high data rate information using the D-PHY or C-PHY protocol. In some configurations, the camera subsystem 200 and / or the display subsystem 250 may communicate using a reverse channel (e.g., CCI link 220) for configuring the image sensor 202 or other devices. In some cases, a low power operating mode may be defined for a link using either the D-PHY or C-PHY protocol.

[0042] Figure 3 An example of an apparatus 300 employing a data link that can be used to communicatively couple two or more devices, subassemblies, or circuits is illustrated. Here, the apparatus 300 includes a plurality of devices 302 and 3220-322 coupled to a two-wire serial bus 320. N . Devices 302 and 3220-322 N The devices 302 and 3220-322 may be implemented in one or more semiconductor IC devices such as application processors, SoCs, or ASICs. N Some of the devices in the example may include, support, or operate as a modem, a signal processing device, a display driver, a camera, a user interface, a sensor, a sensor controller, a media player, a transceiver, and / or other such components or devices. In some examples, one or more devices 3220-322 N To control, manage or monitor the sensor device. Devices 302 and 3220-322 N Communications between the serial bus 320 are controlled by a bus master 302. Some types of buses may support multiple bus masters 302.

[0043] In one example, bus master 302 may include interface controller 304, which can manage access to serial bus, configure dynamic address for slave device and / or generate clock signal 328 to be sent on clock line 318 of serial bus 320. Bus master 302 may include configuration register 306 or other storage device 324 and other control logic 312 configured to process protocol and / or higher level functions. Control logic 312 may include processing circuit such as state machine, sequencer, signal processor or general processor. Bus master 302 includes transceiver 310 and line driver / receiver 314a and 314b. Transceiver 310 may include receiver, transmitter and common circuit, wherein common circuit may include timing, logic and storage circuit and / or device. In one example, transmitter encodes and sends data based on the timing in clock signal 328 provided by clock generation circuit 308. Control logic 312 and other functions, circuits or modules may use other timing clock 326.

[0044] At least one device 3220-322 N It can be configured to operate as a slave device on the serial bus 320, and may include circuits and modules that support displays, image sensors, and / or control one or more sensors that measure environmental conditions and communicate with the one or more sensors. In one example, the device 3220 configured to operate as a slave device can provide a control function, a physical layer circuit 332, which includes circuits and modules for supporting displays, image sensors, and / or control one or more sensors that measure environmental conditions and communicate with them. In this example, the device 3220 may include a configuration register 334 or other storage device 336, a control logic 342, a transceiver 340, and line drivers / receivers 344a and 344b. The control logic 342 may include processing circuits such as a state machine, a sequencer, a signal processor, or a general processor. The transceiver 340 may include a receiver, a transmitter, and a common circuit, wherein the common circuit may include timing, logic, and storage circuits and / or devices. In one example, the transmitter encodes and sends data based on the timing in the clock signal 348 provided by the clock generation and / or recovery circuit 346. In some cases, clock signal 348 may be derived from a signal received from clock line 318. Other timing clocks 338 may be used by control logic 342 and other functions, circuits, or modules.

[0045] The serial bus 320 may operate according to RFFE, I2C, I3C, SPI, SPMI, or another suitable protocol. In some cases, two or more devices 302, 3220-322 N The device 300 may be configured to operate as a bus master on the serial bus 320. In some cases, the device 300 includes multiple serial buses 320, 352a, and / or 352b that couple the devices 302, 3220-322 N Two or more devices or devices 302, 3220-322 N A device in the embodiment of the present invention and a peripheral device such as a display or camera 350 or a radio frequency IC (RFIC). In some examples, a slave device 3220 is configured to operate as a display or camera coupled to the display or camera 350. The latter slave device 3220 may include a physical layer circuit 332 configured to operate as a C-PHY or D-PHY interface controller that communicates with the display or camera 350 via a serial bus 352a or 352b that operates according to the C-PHY protocol or the D-PHY protocol.

[0046] In certain aspects of the present disclosure, systems and devices may use multi-phase data encoding and decoding interface methods to communicate between IC devices. A multi-phase encoder can drive multiple conductors (i.e., 3 conductors). Each conductor may be referred to as a wire, but the conductor may include a conductive trace on a circuit board or a trace or interconnect within a conductive layer of a semiconductor IC device. In one example, a physical layer interface (i.e., a C-PHY interface) implemented using C-PHY technology and protocols defined by the MIPI Alliance can be used to connect a camera or display to an application processor. The C-PHY interface uses three-phase symbol encoding to send data symbols on a 3-wire channel or "triplet", where each triplet includes an embedded clock. Triplet may be referred to as a channel in this article. Multiple triplets can be used to establish a multi-channel C-PHY communication channel to carry data exchanged between a pair of devices, where each channel includes a triplet carrying a portion of the data, which can be independently encoded according to the C-PHY protocol.

[0047] The C-PHY interface provides a three-phase encoding scheme for three-wire systems, which can define three phase states and two polarities, providing six states and five possible transitions for each state. Deterministic voltage and / or current changes can be detected and decoded to extract data from the three wires.

[0048] Figure 4 Illustrate a method that can be used to implement Figure 3 4. A C-PHY interface 400 that illustrates certain aspects of the serial bus 352a or 352b depicted in FIG. 4. The illustrated example may involve a three-wire link configured to carry three-phase polarity encoded data in accordance with the DSI protocol. The use of 3-phase polarity encoding provides high-speed data transmission and may consume half the power or less of other interfaces at a desired operating frequency because fewer than 3 drivers are active at any time in the C-PHY link. The C-PHY interface uses 3-phase polarity encoding to encode multiple bits for each symbol transition on the three-wire link. In one example, a combination of three-phase encoding and polarity encoding may be used to support a wide video graphics array (WVGA), 80 frames per second liquid crystal display driver IC without a frame buffer, delivering pixel data at 810 Mbps over three or more wires for display refresh.

[0049] In the depicted C-PHY interface 400, three-phase polarity encoding is used to control the signaling state of connectors, wires, traces and other interconnects providing communication channels. In the illustrated example, a combination of three wires (triplet 420) is used to provide a single unidirectional channel or channel. Each wire of the triplet 420 can be undriven, positively driven or negatively driven in any symbol transmission interval. In some cases, the undriven signal line of the triplet 420 can be in a high impedance state. In some cases, the undriven signal line of the triplet 420 can be driven or pulled to a voltage level substantially located between the positive voltage level and the negative voltage level provided on the driving signal line. In some cases, the undriven signal line of the triplet 420 may have no current flowing through it. The driver 408 of the signal line coupled to the triplet 420 is controlled so that only one wire of the triplet 420 is in each state in three states (expressed as +1, -1 or 0) in each symbol interval.

[0050] In one example, the driver 408 may include a cell-level current mode driver. In another example, the driver 408 may drive opposite polarity voltages on two signals transmitted on two signal lines of the triplet 420, while the third signal line is at high impedance and / or pulled to ground. For each transmit symbol interval, at least one signal is in an undriven (0) state, while one signal is driven positive (+1 state) and one signal is driven negative (-1 state), so that the sum of the currents flowing to the receiver is always zero. For each symbol, the state of at least one signal line of the triplet 420 changes from the symbol transmitted in the previous transmit interval.

[0051] In the C-PHY interface 400, a mapper 402 may receive a 16-bit input data word 418, and the mapper 402 may map the input data word 418 to 7 symbols 412 for sequential transmission over the signal lines of a triplet 420. An M-line, N-phase encoder 406 configured for three-line, three-phase encoding receives the 7 symbols 412 generated by the mapper one input symbol 414 at a time, and calculates the state of each signal line of the triplet 420 for each symbol interval based on the previous state of the signal line of the triplet 420. The 7 symbols 412 may be serialized using, for example, a parallel-to-serial converter 404. The encoder 406 provides a control signal 416 to define the output of a driver 408. The encoder 406 selects the state of the signal line of the triplet 420 based on the input symbol 414 and the previous state of the signal line of the triplet 420, and may provide the control signal 416 to cause the driver 408 to generate the desired signaling state on the triplet 420.

[0052] The use of three-wire, three-phase encoding allows multiple bits to be encoded in multiple symbols where the number of bits per symbol is not an integer. In the example of a three-wire, three-phase system, there are 3 available combinations of 2 wires that can be driven simultaneously, and 2 possible polarity combinations on a pair of wires driven simultaneously, resulting in 6 possible states. Since each transition starts from the current state, 5 of the 6 states are available at each transition. For 5 states, each symbol transition can encode Therefore, the mapper can accept a 16-bit word and convert it into 7 symbols, because 7 symbols with 2.32 bits per symbol can encode 16.24 bits. In other words, the combination of seven symbols encoding five states has 5 7 (78,125) permutations. Therefore, 7 symbols can be used to represent 16 bits of 2 16 (65,536) permutations are encoded.

[0053] The C-PHY interface 400 includes a receiver including a comparator 422 and a decoder 424 configured to provide a digital representation of the state of each of the three signal lines of the triplet 420 and the change in the state of the three signal lines compared to the state transmitted in the previous symbol period. Seven consecutive states are combined by a serial-to-parallel converter 426 and used to produce a set of 7 symbols to be processed by a demapper 428 to obtain 16 bits of data that can be buffered in a first-in-first-out (FIFO) storage device 430, which can be implemented using, for example, registers.

[0054] According to certain aspects disclosed herein, systems and devices can use a certain combination of differential encoding and single-ended encoding to communicate between IC devices. In one example, the "D-PHY" physical layer interface technology defined by the MIPI Alliance can be used to connect cameras and display devices to application processors. The D-PHY interface can switch between differential (high-speed) mode and single-ended low-power (LP) mode in real time as needed to facilitate the transmission of large amounts of data or save power and extend battery life. The D-PHY interface can operate in a simplex or duplex configuration with a single data channel or multiple data channels with a unidirectional (master to slave) clock channel. In one example, a single wire is used to implement the data channel. The single-wire channel can be used at a lower data rate, which is used to generate a data signal that can be sent with limited loss, so that the receiver can easily decode the data carried on the data channel. The two-wire channel carrying differentially encoded clock and data signals provides common-mode suppression of electromagnetic interference and can limit the attenuation of higher frequency components in the signal sent on the channel.

[0055] Figure 55. A generalized example of a D-PHY interface 500 is illustrated, which includes a bus master device 502 and a slave device 504 coupled using a set of conductors 510, the set of conductors being used to provide a clock channel 506 and one or more data channels 5081-508 N For high-speed operation, clock channel 506 and data channels 5081-508 N Each may be configured using a pair of conductors to carry a differential signal. In one example, the slave device 504 is provided in a display driver IC (DDIC) associated with a display panel, and the bus master device 502 is included in an application processor or provided by another processing circuit.

[0056] In the illustrated example, a clock signal is sent on a clock lane 506 and data is sent on one or more data lanes 5081-508 N The bus master 502 includes a clock generation circuit 512 that can be configured to generate a clock signal 514 that is sent on the clock channel 506 to control the data channels 5081-508 N The frequency of the clock signal 514 may be configured during system initialization or configuration and / or may be dynamically configured based on the operating mode of the D-PHY interface 500, application requirements, the amount of data to be transmitted, and power conservation requirements. Data channels 5081-508 set up or active in the device N The number of may be configured during system initialization or configuration and / or may be dynamically configured based on the operating mode of the D-PHY interface 500, application requirements, the amount of data to be transmitted, and power conservation needs.

[0057] Serial Peripheral Interface Example

[0058] According to certain aspects of the present disclosure, a serial bus operating according to the SPI protocol can be used to provide a simple, low-power communication interface. In one example, the SPI interface can be used primarily to exchange data between a processing circuit and a touch panel of a display. The SPI interface can be coupled to a serial bus having a clock line, two data lines (a master-in-slave-out (MISO) line, a master-out-slave-in (MOSI) line) and a chip select (CS) for each slave device. The presence of the MISO line and the MOSI line enables full-duplex operation. Figure 6Certain aspects related to the operation of the two-data-line SPI 600 are illustrated. In some cases, the master device 602 may be incorporated into a SoC that acts as an application processor, a host processor, or other functional components of an apparatus or system. The master device 602 uses a multi-line bus 610 to couple to a plurality of slave devices 604, 606, 608. The master device 602 drives data to the slave devices 604, 606, 608 through the master-out slave-in line (MOSI line 616) of the multi-line bus 610. The slave devices 604, 606, 608 can each drive data to the master device 602 through the shared master-in slave-out line (MISO line 614) of the multi-line bus 610.

[0059] The multi-line bus 610 includes at least one slave select line 618, 620, 622 for each slave device 604, 606, 608. As illustrated, a first slave select line 618 (SS1) controls bus access for the first slave device 604, a second slave select line 620 (SS2) controls bus access for the second slave device 606, and a third slave select line 622 (SS3) controls bus access for the third slave device 604. The master device 602 may assert the slave select lines 618, 620, 622 to cause the corresponding slave device 604, 606, 608 to receive data via the MOSI line 616, and / or grant permission to the corresponding slave device 604, 606, 608 to transmit on the MISO line 614.

[0060] In one example, when a low voltage level is applied to the slave select lines 618, 620, 622, the slave select lines 618, 620, 622 are not asserted, and the slave select lines 618, 620, 622 are asserted by driving the slave select lines 618, 620, 622 to a high voltage level (e.g., toward a power supply level). In another example, when a high voltage level (e.g., a power supply level) is applied to the slave select lines 618, 620, 622, the slave select lines 618, 620, 622 are not asserted, and the slave select lines 618, 620, 622 are asserted by driving the slave select lines 618, 620, 622 to a low voltage level. For each slave select line 618 , 620 , 622 , a driver in the master device 602 may be operated to charge and discharge the slave select line 618 , 620 , 622 based on the desired asserted state of the slave select line 618 , 620 , 622 .

[0061] Data is transmitted between the master device 602 and the slave devices 604, 606, 608 according to a clock signal provided on a clock line 612 of the multi-line bus 610. Data signaling is unidirectional on the MISO line 614 and on the MOSI line 616. The direction of data transmission on the MISO line 614 is opposite to the direction of data transmission on the MOSI line 616. The data transmission on the MISO line 614 and the MOSI line 616 is synchronized with the clock signal provided on the clock line 612.

[0062] Figure 7 Certain aspects of a quad serial peripheral interface (QSPI) 700 are illustrated. A master device 702 may be incorporated into a SoC that functions as an application processor, a host processor, or other functional component of an apparatus or system. The master device 702 is coupled to a plurality of slave devices 704, 706, 708 via a multi-wire bus 710. The master device 702 exchanges data with the slave devices 704, 706, 708 via a data channel 714 of the multi-wire bus 710, wherein the data channel 714 includes two data lines in each direction (master-slave and slave-master). The data channel 714 may be used to provide a ratio Figure 6 The two-wire unidirectional signaling scheme illustrated in FIG. 4 has a greater data transmission rate.

[0063] The multi-line bus 710 includes at least one slave select line for each slave device 704, 706, 708. As illustrated, a first slave select line 716 (SS1) controls bus access for the first slave device 704, a second slave select line 718 (SS2) controls bus access for the second slave device 706, and a third slave select line 720 (SS3) controls bus access for the third slave device 704. The master device 702 may assert the slave select lines 716, 718, 720 to allow and / or cause the corresponding slave devices 704, 706, 708 to send or receive data over the data channel 714.

[0064] In one example, when a low voltage level is applied to the slave select lines 716, 718, 720, the slave select lines 716, 718, 720 are not asserted, and the slave select lines 716, 718, 720 are asserted by driving the slave select lines 716, 718, 720 to a high voltage level (e.g., toward a power supply level). In another example, when a high voltage level (e.g., a power supply level) is applied to the slave select lines 716, 718, 720, the slave select lines 716, 718, 720 are not asserted, and the slave select lines 716, 718, 720 are asserted by driving the slave select lines 716, 718, 720 to a low voltage level. For each slave select line 716 , 718 , 720 , a driver in the master device 702 may be operated to charge and discharge the slave select line 716 , 718 , 720 based on the desired asserted state of the slave select line 716 , 718 , 720 .

[0065] Data is transmitted between the master device 702 and the slave devices 704, 706, 708 according to a clock signal provided on a clock line 712 of the multi-line bus 710. Data transmission on the data channel 714 is synchronized with the clock signal provided on the clock line 712.

[0066] In many portable or mobile devices, the display subsystem consumes a significant portion of the power budget defined for the device. For example, the power budget of a cellular phone may be defined with the goal of maximizing the available operating time between battery charging events and minimizing heat generation and heat mitigation issues. The power budget may be defined based on a trade-off between the power requirements associated with wireless communication scheduling and the requirement to maintain a responsive user interface. Certain elements of the display subsystem in a portable or mobile device operate in high-speed mode, including when the display is ignored or idle. In one example, the DSI circuit consumes similar power levels when the portable or mobile device operates in an active mode (e.g., "always display") or a static mode (such as "sleep," "hibernation," "display idle," or "smart watch display" mode). When the DSI circuit operates continuously in high-speed mode, it is typically necessary to operate other circuits in the SoC or IC in high-speed mode, thereby increasing power consumption when the portable or mobile device operates in static mode.

[0067] Certain aspects of the present disclosure can reduce power consumption attributable to the display subsystem when the display is in a static, sleep, or idle mode. In one aspect, a high-speed data link operating in a high-speed active mode according to the DSI protocol can be operated by replacing the high-speed data link with a low-power data link in a static, sleep, or idle mode. The physical interface and other circuits associated with the low-power data link can be located in a low-power domain or low-power island of the SoC or IC, allowing other circuits in the SoC or IC to be idle or placed in a sleep mode. In one example, the SoC or IC provides a high-speed power domain and a low-power domain / island, wherein the high-speed power domain can operate at a reduced power level during a static, sleep, or idle period.

[0068] Figure 8A system 800 including a display subsystem interface and adaptable according to certain aspects of the present disclosure is illustrated. The illustrated system 800 includes a SoC 802 and a display subsystem 804 that are communicatively coupled using a high-speed serial bus 806 and a low-power serial bus 808. The SoC 802 includes a plurality of processors, the plurality of processors including a central processing unit (CPU 812) and a digital signal processor (DSP 816). For the purposes of the present disclosure, examples of high-speed serial data links are generally described as being controlled and managed using a DSI protocol, while examples of low-speed serial data links are generally described as being controlled and managed using an SPI protocol. In other examples, other types of communication protocols may be used to control or manage high-speed serial data links and low-speed serial data links. In the illustrated example, the SoC 802 includes a DSI physical interface (DSIPHY 814) and an SPI physical interface (SPIPHY 818).

[0069] In one aspect of the present disclosure, at least two power domains are defined for the SoC 802, including a high-speed power domain and a low-power domain, wherein the low-power domain may be implemented or referred to herein as a low-power island 810. The high-speed power domain may support, supply and / or be included in a section of an IC or SoC that performs various functions, including storing data (memory), managing stored data, performing certain logic functions, processing specific functions, encryption, image processing, wireless and wired communications, etc. More than one section of an IC may operate as a high-speed power domain. In the illustrated example, the CPU 812 and the DSI PHY 814 operate within the high-speed power domain.

[0070] In many examples, devices and / or circuits in the high-speed power domain may be configured to support operation at the highest possible operating frequency enabled by the process technology. In some examples, the operating frequency of circuits in the high-speed power domain may be constrained by a power budget, and the operating frequency of some circuits may be configured to operate at the highest frequency that can be supported under the power budget. Lower power consumption in high-speed circuits may be achieved by reducing the operating voltage of the high-speed power domain.

[0071] In some examples, the low power island 810 may support, supply, and / or be included in a section of an IC or SoC that performs real-time, low frequency, and / or low data rate communications and includes processing circuits associated with the performance of real-time, low frequency, and / or low data rate communications. In one example, the low power island 810 may power circuits and devices used for communication and processing functions associated with certain types of sensors. In another example, the low power island may power circuits and devices used for low data rate communications and processing.

[0072] In some conventional systems, a dedicated display processing unit (DPU) for configuring, controlling, and managing the display subsystem 804 is deployed within the high-speed power domain. In some cases, support circuits for an "always-on" camera may operate at least partially within the low-power island 810. Circuits in the high-speed power domain may be used to provide a communication link for the camera because the camera typically sends image data when a user is actively interacting with the portable device or mobile device and the system 800 has entered a high-speed operating mode. In the latter example, the camera, the DSIPHY used to communicate with the camera, and associated circuits may be idle when the portable device or mobile device is dormant.

[0073] Display subsystem 804 includes display driver circuitry that can be implemented in a display driver IC (DDIC 822) to drive display panel 830. Display subsystem 804 can include a touch panel interface 832 associated with display panel 830. In some cases, touch panel interface 832 is included in DDIC 822.

[0074] The DDIC 822 includes a DSI physical interface (DSIPHY 824) configured as a receive interface coupled to the high-speed serial bus 806. The illustrated DDIC 822 also includes a low-power serial bus 808. The touch panel interface 832 includes an SPI physical interface (not shown) coupled to the low-power serial bus 808, which can support bidirectional full-duplex operation (see Figure 6 and Figure 7 ). The touch panel interface 832 can be communicatively coupled to the DSP 816 via the low power serial bus 808. The DSP 816 can be configured to support a user interface. For example, the DSP 816 can be configured to detect user contact with the display panel 830, multi-point contact, and movement that can be decoded as user gestures. The DSP 816 can be configured to wake up the system 800 from an idle or sleep mode when activity or new user contact or movement is detected.

[0075] In a conventional mobile device or portable device, when the display subsystem 804 is in an idle or other static mode, the display subsystem maintains an active high-speed data communication link between the SoC 802 and the display subsystem 804. Circuits that implement and support an active high-speed data communication link are not suitable for inclusion in the low-power island 810. The operation of the DSIPHY 824 in the low-power display mode remains substantially unchanged compared to its operation in the high-speed mode. The continued operation of the DSIPHY 824 prevents the CPU 812 and / or the DPU from entering a deep sleep mode. The level of power consumption attributable to the DSIPHY 824, DPU or CPU 812 and associated circuitry during the static mode may make it infeasible to include it in the low-power island 810 due to cost and complexity.

[0076] Certain aspects of the present disclosure relate to a display subsystem that can operate in a low power mode with significant power consumption reduction compared to a conventional display subsystem. Power savings can be obtained by disabling the DSI PHY during low power mode. The high speed CPU or DPU is relieved of the responsibility of servicing the DSIPHY and can enter a deep sleep mode. The display subsystem is managed by a secondary low power communication link and can be serviced by a low power processor. The low power communication link and the low power processor can reside in a low power island.

[0077] Fig. 9 A system 900 operating in a low power mode according to certain aspects of the present disclosure is illustrated. The system 900 corresponds in some aspects to Figure 8 800 is illustrated in the example of FIG. 800. For example, system 900 includes a SoC 902 and a display subsystem 904 that are communicatively coupled using a high-speed serial bus 906 and a low-power serial bus 908. 808. SoC 802 includes multiple processors, including a central processing unit (CPU 912) and a digital signal processor (DSP 916). For the purposes of this disclosure, examples of high-speed serial data links are generally described as being controlled and managed using a DSI protocol, while examples of low-speed serial data links are generally described as being controlled and managed using an SPI protocol. In other examples, other types of communication protocols may be used to control or manage high-speed serial data links and low-speed serial data links. In the illustrated example, SoC 902 includes a DSI physical layer interface (DSIPHY 914) and a SPI physical layer interface (SPIPHY 918).

[0078] In one aspect of the present disclosure, at least two power domains are defined for the SoC 902, including a high-speed power domain and a low-power domain, wherein the low-power domain may be referred to herein as a low-power island 910. The high-speed power domain may support, supply, and / or be included in a section of an IC or SoC that performs various functions, including storing data (memory), managing stored data, performing certain logic functions, processing specific functions, encryption, image processing, wireless and wired communications, etc. More than one section of an IC may operate as a high-speed power domain. In the illustrated example, the CPU 912 and the DSIPHY 914 operate within the high-speed power domain.

[0079] In some examples, the low power island 910 may support, supply, and / or be included in a segment of an IC or SoC that performs real-time, low frequency, and / or low data rate communications and includes associated processing circuits. In one example, the low power island 910 may power circuits and devices used for communication and processing functions associated with certain types of sensors. In another example, the low power island may power circuits and devices used for low data rate communications and processing. In some systems, a dedicated display processing unit (DPU) is used to configure, control, and manage the display subsystem 904, and the DPUs in these systems are deployed in the high-speed power domain.

[0080] The display subsystem 904 includes display driver circuitry that can be implemented in a display driver IC (DDIC 922) to drive a display panel 930. The display subsystem 904 can include a touch panel interface 932 associated with the display panel 930. In some implementations, the touch panel interface 932 is included in the DDIC 922.

[0081] DDIC 922 includes a DSI physical interface (DSIPHY 924), an SPI physical interface (SPI PHY 926), and a selection circuit represented by a selector 928. DSIPHY 924 is configured as a receive interface and is coupled to high speed serial bus 906. In the illustrated example, SPIPHY 926 is coupled to low power serial bus 908, which is configured to support multiple devices and can be configured for bidirectional communication (see Figure 6 and Figure 7 ).

[0082] The touch panel interface 932 includes an SPI physical layer interface (not shown) coupled to the low power serial bus 908. In other examples, the DDIC 922 and the touch panel interface 932 may share a common SPI physical layer interface. The touch panel interface 932 is communicatively coupled to the DSP 916 via the low power serial bus 908. The DSP 916 may be configured to support a user interface. For example, the DSP 916 may be configured to detect user contact with the display panel 930, multi-point contact, and movement that can be decoded as a user gesture. The DSP 916 may be configured to wake up the system 900 from an idle or sleep mode when an activity or new user contact or movement is detected.

[0083] In the illustrated example, DDIC 922 includes a selector 928 configured to select between output 934 of DSIPHY 924 and output 936 of SPIPHY 926 to supply display data for driving display panel 930. In high-speed mode, selector 928 selects DSIPHY 924 to supply display data. In low-speed mode, selector 928 selects SPIPHY 926 to supply display data. Fig.10 Configuration 1000 is illustrated in which system 900 is configured for a high-speed mode of operation, in accordance with certain aspects of the present disclosure.

[0084] The selector 928 may be implemented using a switch, a multiplexer, or a combination of logic gates or drivers. In some implementations, the selector 928 represents a virtual switch, wherein, for example, the DDIC 922 selects between different buffers or memory regions based on the operating mode of the system 900. In the latter example, the display data received by the DSIPHY 924 is written to a first storage device, and the display data received and addressed to the display panel 930 by the SPIPHY 926 is written to a second storage device. When operating in high-speed mode, the DDIC 922 drives the display panel 930 using the data stored in the first storage device, and when the display subsystem 904 operates in low-speed mode, the DDIC 922 drives the display panel 930 using the data stored in the second storage device. In some cases, the DDIC 922 drives the display panel 930 using the data stored in the common storage device written by the currently active PHY 924 or 926.

[0085] According to one aspect of the present disclosure, when the display subsystem 904 operates in a low-speed mode, the DSIPHY 914 in the SoC 902 and the DSIPHY 924 in the DDIC 922 may be disabled or placed in a low-power, sleep, or static mode. When the DSIPHY 914 in the SoC 902 is not operating, the CPU 912 may also be disabled or placed in a low-power, sleep, or static mode.

[0086] In low speed mode, management and control of the display panel 930 may be performed using components resident in the low power island 910 and the low power serial bus 908. In one example, the DSP 916 may transmit display data and commands to the DDIC 922 via the low power serial bus 908. The display data may be provided in any suitable format and may define pixel settings within a display frame. In one example, the display data is stored in a frame buffer. The display data may be retrieved from a cache resident in the low power island 910 or otherwise accessible in low power mode.

[0087] The cache may be implemented in a storage device and may be used to store and supply display data generated by a CPU or another high-speed processor. In one example, when the display subsystem 904 operates in a low-speed mode, cached display data may be retrieved in each frame refresh cycle. In some implementations, the cache is filled before entering the low-power mode. In some implementations, the DSP 916 may update the cache during the low-power mode. In some implementations, the DSP 916 may merge the display data received from the cache with the data generated by the DSP 916 during the low-power mode. For example, the DSP 916 may cause the display of date or time information, battery charge level, and / or other status information during the low-power mode.

[0088] It is expected that the rate of refreshing the display panel 930 changes between high-speed mode and low-power mode. For example, some mobile devices or portable devices have high-resolution displays, which have high bit depth per pixel and are refreshed between 30 and 120 frames per second (FPS) when operating in normal, high-speed mode. In some specific implementations, the display refresh rate can be limited to 1FPS or less using the low-power serial bus 908 in low-power mode. Other protocols or serial bus configurations can be used to obtain higher display refresh rates. In some specific implementations, partial frame refresh can be implemented in low-power mode. When the entire display is not subject to change during low-power mode, partial frame refresh can be used. For example, a mobile device or portable device can change the displayed date and time information by refreshing the predefined area of ​​the display where the date and time are displayed, thereby reducing the amount of data to be transmitted on the low-power serial bus 908.

[0089] In low power mode, in addition to transmitting display data, the low power serial bus 908 can also be used to manage the touch panel interface 932. In many cases, the highest FPS rate available through the low power serial bus 908 is a priority target, and the touch panel interface 932 may experience an increased bus delay that may affect the responsiveness of the touch panel. Bus delay may affect the ability of the serial bus to handle high priority, real-time and / or other time-constrained messages. In one example, the bus delay may be measured as the time elapsed between the time when a message becomes available for transmission and the delivery of the message or the start of the transmission of the message in some instances. Other measurements of bus delay may be used. Bus delays are typically included in the delays incurred when sending higher priority data or messages, interrupt processing, the time required to terminate the datagram in the process on the serial bus, the time to send a command that turns the bus between the transmission mode and the reception mode, bus arbitration and / or the command transmission specified by the protocol. In conventional systems, a full touch interface is not supported in low power mode. Detection of a touch event causes DSP 916 to notify CPU 912 or another processor or controller in SoC 902 of the event and thereby initiate a switch to high-speed mode.

[0090] Examples of Processing Circuits and Methods

[0091] Fig.11 1100 is a diagram illustrating an example of a hardware implementation for a device 1100. In some examples, the device 1100 may perform one or more functions disclosed herein. According to various aspects of the present disclosure, a processing circuit 1102 may be used to implement an element, any part of an element, or any combination of elements disclosed herein. The processing circuit 1102 may include one or more processors 1104 controlled by a certain combination of hardware modules and software modules. Examples of processors 1104 include microprocessors, microcontrollers, digital signal processors (DSPs), SoCs, ASICs, field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, sequencers, gated logic, discrete hardware circuits, and other appropriate hardware configured to perform various functionalities described throughout the present disclosure. One or more processors 1104 may include special-purpose processors that perform specific functions and may be configured, enhanced, or controlled by one of the software modules 1116. One or more processors 1104 may be configured by a combination of software modules 1116 loaded during initialization, and may also be configured by loading or unloading one or more software modules 1116 during operation.

[0092] In the illustrated example, the processing circuit 1102 may be implemented with a bus architecture, which is generally represented by a bus 1110. Depending on the specific application of the processing circuit 1102 and the overall design constraints, the bus 1110 may include any number of interconnecting buses and bridges. The bus 1110 links various circuits (including one or more processors 1104 and storage devices 1106) together. The storage device 1106 may include a memory device and a mass storage device, and may be referred to as a computer-readable medium and / or a processor-readable medium in this article. The bus 1110 may also link various other circuits, such as timing sources, timers, peripherals, voltage regulators, and power management circuits. The bus interface 1108 may provide an interface between the bus 1110 and one or more transceivers 1112a, 1112b. Transceivers 1112a, 1112b may be provided for each networking technology supported by the processing circuit. In some cases, multiple networking technologies may share some or all circuits or processing modules found in transceivers 1112a, 1112b. Each transceiver 1112a, 1112b provides a means for communicating with various other devices via a transmission medium. In one example, the transceiver 1112a can be used to couple the device 1100 to a multi-line bus. In another example, the transceiver 1112b can be used to connect the device 1100 to a radio access network. Depending on the nature of the device 1100, a user interface 1118 (e.g., a keypad, a display, a speaker, a microphone, a joystick) may also be provided and may be communicatively coupled to the bus 1110 directly or via the bus interface 1108.

[0093] The processor 1104 may be responsible for managing the bus 1110 and for general processing, which may include executing software stored in a computer-readable medium, which may include a storage device 1106. In this regard, the processing circuit 1102 (including the processor 1104) may be used to implement any of the methods, functions, and techniques disclosed herein. The storage device 1106 may be used to store data that is manipulated by the processor 1104 when executing the software, and the software may be configured to implement certain methods disclosed herein.

[0094] One or more processors 1104 in the processing circuit 1102 may execute software. Software should be interpreted broadly to mean instructions, instruction sets, codes, code segments, program codes, programs, subroutines, software modules, applications, software applications, software packages, routines, subroutines, objects, executable files, threads of execution, procedures, functions, algorithms, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. The software may reside in a computer-readable form within the storage device 1106 or in an external computer-readable medium. The external computer-readable medium and / or the storage device 1106 may include a non-transitory computer-readable medium. For example, non-transitory computer-readable media include magnetic storage devices (e.g., hard disks, floppy disks, magnetic strips), optical disks (e.g., compact disks (CDs) or digital versatile disks (DVDs)), smart cards, flash memory devices (e.g., "flash drives," cards, sticks, or key drives), RAM, ROM, programmable read-only memory (PROM), erasable PROM (EPROM, including EEPROM), registers, removable disks, and any other suitable medium for storing software and / or instructions that can be accessed and read by a computer. The computer-readable medium and / or storage device 1106 may also include, for example, carrier waves, transmission lines, and any other suitable medium for transmitting software and / or instructions that can be accessed and read by a computer. The computer-readable medium and / or storage device 1106 may reside in the processing circuit 1102, in the processor 1104, external to the processing circuit 1102, or distributed across multiple entities including the processing circuit 1102. The computer-readable medium and / or storage device 1106 may be embodied as a computer program product. For example, a computer program product may include a computer-readable medium in packaging materials. Those skilled in the art will recognize how best to implement the described functionality presented throughout this disclosure depending on the particular application and the overall design constraints imposed on the overall system.

[0095] The storage device 1106 may maintain software maintained and / or organized in loadable code segments, modules, applications, programs, etc., which may be referred to herein as software modules 1116. Each of the software modules 1116 may include instructions and data that, when installed or loaded into the processing circuit 1102 and executed by the one or more processors 1104, contribute to a runtime image 1114 that controls the operation of the one or more processors 1104. Certain instructions, when executed, may cause the processing circuit 1102 to perform functions according to certain methods, algorithms, and processes described herein.

[0096] Some of the software modules 1116 may be loaded during initialization of the processing circuit 1102, and these software modules 1116 may configure the processing circuit 1102 to enable the various functions disclosed herein to be performed. For example, some of the software modules 1116 may configure the internal devices and / or logic circuits 1122 of the processor 1104, and may manage access to external devices such as transceivers 1112a, 1112b, bus interface 1108, user interface 1118, timers, math coprocessors, etc. The software modules 1116 may include a control program and / or operating system that interacts with interrupt handlers and device drivers and controls access to various resources provided by the processing circuit 1102. Resources may include memory, processing time, access to transceivers 1112a, 1112b, user interface 1118, etc.

[0097] The one or more processors 1104 of the processing circuit 1102 may be multifunctional, whereby some of the software modules 1116 are loaded and configured to perform different functions or different instances of the same function. The one or more processors 1104 may additionally be adapted to manage background tasks initiated in response to inputs such as from a user interface 1118, transceivers 1112a, 1112b, and device drivers. In order to support the execution of multiple functions, the one or more processors 1104 may be configured to provide a multitasking environment, whereby each of the multiple functions is implemented as a set of tasks served by one or more processors 1104 as needed or desired. In one example, a time sharing program 1120 that transfers control of the processor 1104 between different tasks may be used to implement a multitasking environment, whereby each task returns control of the one or more processors 1104 to the time sharing program 1120 when any pending operations are completed and / or in response to inputs such as interrupts. When a task controls one or more processors 1104, the processing circuit is effectively specialized for the purpose of being solved by the function associated with the control task. The time sharing program 1120 may include an operating system, a main loop that transmits control on a cycle basis, functions that allocate control of one or more processors 1104 based on the priority of the functions, and / or an interrupt-driven main loop that responds to external events by providing control of one or more processors 1104 to processing functions.

[0098] Fig.121200 is a flow chart of a method for operating a display subsystem configured according to certain aspects of the present disclosure. The method may be implemented in a mobile communication device including a display subsystem. In one example, the mobile communication device includes a first serial data link operating according to a DSI protocol and a second serial data link operating according to an SPI protocol. Other combinations of protocols may be used to operate the serial data links. The method may be performed using a combination of suitable processors such as a controller, a finite state machine, a digital signal processor, a DPU, and / or a CPU.

[0099] In the illustrated method, at block 1202, the first physical layer circuit may be configured to communicate a first data frame to a display controller via a first serial bus at a first data rate when the display controller operates in a high-speed mode. The first physical layer circuit may be further configured to inhibit communication via the first serial bus when the display controller operates in a low-power mode. The first physical layer circuit may be powered by a first power supply.

[0100] At block 1204, the second physical layer circuit may be configured to communicate a second data frame to the display controller via a second serial bus at a second data rate when the display controller operates in a low power mode. The second physical layer circuit may be powered by a second power supply. The second data rate may be lower than the first data rate. In some examples, the first data rate may support a frame refresh rate between 30 FPS and 120 FPS. In some examples, the second data rate may support a frame refresh rate of 1 FPS or less.

[0101] At block 1206, the first processor may be configured to generate a first data frame. The first processor may be powered by a first power supply. In some implementations, the first processor may be configured to generate a data frame when the display controller operates in a high-speed mode, and to suppress generation of a data frame when the display controller operates in a low-power mode. The data frame generated by the first processor may be stored in a cache or a frame buffer. In one example, the first processor is a CPU in a SoC.

[0102] At block 1208, the second processor may be configured to provide a second data frame to the second physical layer circuit when the display controller is operating in a low power mode. The second processor may be powered by a second power supply. The cache or frame buffer may be accessed by the second processor, including when the display controller is operating in a low power mode. The second processor may be configured to change or add to the frame retrieved from the cache or frame buffer to obtain a second frame. In some implementations, the second processor may write the frame to the cache or frame buffer.

[0103] In some embodiments, the first power supply provides power at a voltage higher than the voltage provided by the second power supply in the high-speed mode. When the display controller operates in the low-power mode, the voltage provided by the first power supply may be reduced. When the display controller operates in the low-power mode, one or more devices or circuits powered by the first power supply may enter an idle, dormant, sleep, or static mode. For example, the first processor may be configured to enter a dormant mode when the display controller operates in the low-power mode. In another example, the first physical layer circuit may be configured to enter a dormant mode when the display controller operates in the low-power mode. When the physical layer circuit enters the dormant mode, a low-power serial bus coupled to the first physical layer circuit may be idle.

[0104] The first physical layer circuit may be configured to operate according to the MIPI Alliance DSI protocol. In one example, the DSI protocol may follow or be compatible with the C-PHY protocol. In another example, the DSI protocol may follow or be compatible with the D-PHY protocol.

[0105] The second physical layer circuit may be configured to operate according to a serial data communication protocol. In one example, the physical layer circuit is configured to operate according to an SPI protocol. In another example, the physical layer circuit is configured to operate according to a CCI protocol. In another example, the physical layer circuit is configured to operate according to an I2C protocol. In another example, the physical layer circuit is configured to operate according to an I3C protocol. In another example, the physical layer circuit is configured to operate according to an SPMI protocol.

[0106] In some specific implementations, the second processor is configured to communicate with a touch panel interface associated with the display panel through the second physical layer circuit. The second processor can be configured to manage and control the operation of the touch panel interface. The second processor can be configured to communicate with the touch panel interface when the display controller operates in a high-speed mode. The second processor can be configured to communicate with the touch panel interface when the display controller operates in a low-power mode.

[0107] Fig.131314. The processing circuitry typically has one or more microprocessors, microcontrollers, digital signal processors, sequencers, and / or state machines, generally represented by processor 1316. The processing circuitry 1302 may be implemented with a bus architecture, generally represented by bus 1320. Depending on the specific application of the processing circuitry 1302 and the overall design constraints, the bus 1320 may include any number of interconnecting buses and bridges. The bus 1320 links together various circuits including multiple processors 1316, modules or circuits 1304, 1306, and 1308, and processor-readable storage media 1318. Bus interface circuits and / or modules 1314 may be provided to support communications over multiple serial data links 1312. The bus 1320 may also link various other circuits such as timing sources, peripherals, voltage regulators, and power management circuits, which are well known in the art and therefore will not be described further.

[0108] The processor 1316 may be responsible for general processing, including the execution of software, code, and / or instructions stored on the processor-readable storage medium 1318. The processor-readable storage medium 1318 may include a non-transitory storage medium. The software, when executed by the processor 1316, causes the processing circuit 1302 to perform the various functions described above for any particular device. The processor-readable storage medium may be used to store data manipulated by the processor 1316 when executing the software. The processing circuit 1302 also includes at least one of the modules 1304, 1306, and 1308. The modules 1304, 1306, and 1308 may be software modules running in the processor 1316, resident / stored in the processor-readable storage medium 1318, one or more hardware modules coupled to the processor 1316, or some combination thereof. The modules 1304, 1306, and 1308 may include microcontroller instructions, state machine configuration parameters, or some combination thereof.

[0109] In one configuration, the device 1300 includes modules and / or circuits 1304 adapted to control the operation of bus interface circuits and / or modules 1314 and locate and route display data to a display driver via one of the serial data links 1312. The device 1300 may include modules and / or circuits 1306 adapted to monitor and respond to changes in operating modes, including operating modes that cause the display controller to operate in a high-speed mode and operating modes that cause the display controller to operate in a low-power mode. The device 1300 may include modules and / or circuits 1308 adapted to generate, modify, configure, store, and retrieve display data. The display data may be stored in a frame buffer or in a cache memory.

[0110] The device 1300 may include a component for communicating with a display controller, the component including: a first physical layer circuit powered by a first power supply and operable to communicate a first data frame to the display controller at a first data rate through a first serial bus when the display controller operates in a high-speed mode, and to suppress communication through the first serial bus when the display controller operates in a low-power mode; and a second physical layer circuit powered by a second power supply and operable to communicate a second data frame to the display controller at a second data rate through a second serial bus when the display controller operates in the low-power mode. The device 1300 may include a component for providing display data to the component for communicating with the display controller, the component including: a first processor powered by the first power supply and configured to generate the first data frame; and a second processor powered by the second power supply and configured to provide the second data frame to the second physical layer circuit when the display controller operates in the low-power mode.

[0111] In some embodiments, the first power supply provides power at a voltage higher than the voltage provided by the second power supply in the high-speed mode. When the display controller operates in the low-power mode, the voltage provided by the first power supply may be reduced. When the display controller operates in the low-power mode, one or more devices or circuits powered by the first power supply may enter an idle, dormant, sleep, or static mode. For example, the first processor may be configured to enter a dormant mode when the display controller operates in the low-power mode. In another example, the first physical layer circuit may be configured to enter a dormant mode when the display controller operates in the low-power mode. When the physical layer circuit enters the dormant mode, a low-power serial bus coupled to the first physical layer circuit may be idle.

[0112] The first physical layer circuit may be configured to operate according to the MIPI Alliance DSI protocol. In one example, the DSI protocol may follow or be compatible with the C-PHY protocol. In another example, the DSI protocol may follow or be compatible with the D-PHY protocol.

[0113] The second physical layer circuit may be configured to operate according to a serial data communication protocol. In one example, the physical layer circuit is configured to operate according to an SPI protocol. In another example, the physical layer circuit is configured to operate according to a CCI protocol. In another example, the physical layer circuit is configured to operate according to an I2C protocol. In another example, the physical layer circuit is configured to operate according to an I3C protocol. In another example, the physical layer circuit is configured to operate according to an SPMI protocol.

[0114] In some specific implementations, the second processor is configured to communicate with a touch panel interface associated with the display panel through the second physical layer circuit. The second processor can be configured to manage and control the operation of the touch panel interface. The second processor can be configured to communicate with the touch panel interface when the display controller operates in a high-speed mode. The second processor can be configured to communicate with the touch panel interface when the display controller operates in a low-power mode.

[0115] In one example, the apparatus 1300 is configured to operate as a mobile communication device having a wireless transceiver configured to send and receive RF signals through one or more antennas, a bus interface circuit and / or module 1314 configured to couple the apparatus 1300 to a serial data link, and a controller or other processor. In this example and other examples, the apparatus 1300 includes a display system interface. The display system interface has a physical layer circuit coupled to a serial bus and a controller. The display system interface can be configured to operate according to the MIPI Alliance DSI standard or specification.

[0116] The device 1300 may include a display controller coupled to the display panel. The device 1300 may include a first physical layer circuit configured to communicate a first data frame to the display controller via a first serial bus at a first data rate when the display controller operates in a high-speed mode. The first physical layer circuit may be further configured to suppress communication via the first serial bus when the display controller operates in a low-power mode. The first physical layer circuit may be powered by a first power supply. The device 1300 may include a second physical layer circuit configured to communicate a second data frame to the display controller via a second serial bus at a second data rate when the display controller operates in a low-power mode. The second physical layer circuit may be powered by a second power supply. The second data rate may be lower than the first data rate. In some examples, the first data rate may support a frame refresh rate between 30FPS and 120FPS. In some examples, the second data rate may support a frame refresh rate of 1FPS or less.

[0117] The device 1300 may include a first processor configured to generate a first data frame. The first processor may be powered by a first power supply. In some specific implementations, the first processor may be configured to generate a data frame when the display controller operates in a high-speed mode, and to suppress the generation of a data frame when the display controller operates in a low-power mode. The data frame generated by the first processor may be stored in a cache or a frame buffer. In one example, the first processor is a CPU in a SoC. The device 1300 may include a second processor, which is configured to provide a second data frame to a second physical layer circuit when the display controller operates in a low-power mode. The second processor may be powered by a second power supply. The cache or frame buffer may be accessed by the second processor, including when the display controller operates in a low-power mode. The second processor may be configured to change or add a frame retrieved from the cache or frame buffer to obtain a second frame. In some specific implementations, the second processor may write a frame to the cache or frame buffer.

[0118] In some embodiments, the first power supply provides power at a voltage higher than the voltage provided by the second power supply in the high-speed mode. When the display controller operates in the low-power mode, the voltage provided by the first power supply may be reduced. When the display controller operates in the low-power mode, one or more devices or circuits powered by the first power supply may enter an idle, dormant, sleep, or static mode. For example, the first processor may be configured to enter a dormant mode when the display controller operates in the low-power mode. In another example, the first physical layer circuit may be configured to enter a dormant mode when the display controller operates in the low-power mode. When the physical layer circuit enters the dormant mode, a low-power serial bus coupled to the first physical layer circuit may be idle.

[0119] The first physical layer circuit may be configured to operate according to the MIPI Alliance DSI protocol. In one example, the DSI protocol may follow or be compatible with the C-PHY protocol. In another example, the DSI protocol may follow or be compatible with the D-PHY protocol.

[0120] The second physical layer circuit may be configured to operate according to a serial data communication protocol. In one example, the physical layer circuit is configured to operate according to an SPI protocol. In another example, the physical layer circuit is configured to operate according to a CCI protocol. In another example, the physical layer circuit is configured to operate according to an I2C protocol. In another example, the physical layer circuit is configured to operate according to an I3C protocol. In another example, the physical layer circuit is configured to operate according to an SPMI protocol.

[0121] In some specific implementations, the second processor is configured to communicate with a touch panel interface associated with the display panel through the second physical layer circuit. The second processor can be configured to manage and control the operation of the touch panel interface. The second processor can be configured to communicate with the touch panel interface when the display controller operates in a high-speed mode. The second processor can be configured to communicate with the touch panel interface when the display controller operates in a low-power mode.

[0122] The processor readable storage medium 1318 may include instructions that cause the processing circuit 1302 to configure the first physical layer circuit to perform the following operations: when the display controller operates in a high-speed mode, communicate a first data frame to the display controller at a first data rate via the first serial bus. The first physical layer circuit may be further configured to inhibit communication via the first serial bus when the display controller operates in a low-power mode. The first physical layer circuit may be powered by a first power supply.

[0123] The processor readable storage medium 1318 may include instructions that cause the processing circuit 1302 to configure the second physical layer circuit to perform the following operations: when the display controller operates in a low power mode, communicate a second data frame to the display controller via a second serial bus at a second data rate. The second physical layer circuit may be powered by a second power supply. The second data rate may be lower than the first data rate. In some examples, the first data rate may support a frame refresh rate between 30 FPS and 120 FPS. In some examples, the second data rate may support a frame refresh rate of 1 FPS or less.

[0124] The processor readable storage medium 1318 may include instructions for causing the processing circuit 1302 to perform the following operations: Generate a first data frame. The first processor may be powered by a first power supply. In some specific implementations, the first processor may be configured to generate a data frame when the display controller operates in a high-speed mode, and to suppress the generation of a data frame when the display controller operates in a low-power mode. The data frame generated by the first processor may be stored in a cache or a frame buffer. In one example, the first processor is a CPU in a SoC.

[0125] The processor readable storage medium 1318 may include instructions that cause the processing circuit 1302 to configure the second processor to perform the following operations: when the display controller operates in a low power mode, provide a second data frame to the second physical layer circuit. The second processor may be powered by a second power supply. The cache or frame buffer may be accessed by the second processor, including when the display controller operates in a low power mode. The second processor may be configured to change or add to the frame retrieved from the cache or frame buffer to obtain a second frame. In some specific implementations, the second processor may write the frame to the cache or frame buffer.

[0126] In some embodiments, the first power supply provides power at a voltage higher than the voltage provided by the second power supply in the high-speed mode. When the display controller operates in the low-power mode, the voltage provided by the first power supply may be reduced. When the display controller operates in the low-power mode, one or more devices or circuits powered by the first power supply may enter an idle, dormant, sleep, or static mode. For example, the first processor may be configured to enter a dormant mode when the display controller operates in the low-power mode. In another example, the first physical layer circuit may be configured to enter a dormant mode when the display controller operates in the low-power mode. When the physical layer circuit enters the dormant mode, a low-power serial bus coupled to the first physical layer circuit may be idle.

[0127] The first physical layer circuit may be configured to operate according to the MIPI Alliance DSI protocol. In one example, the DSI protocol may follow or be compatible with the C-PHY protocol. In another example, the DSI protocol may follow or be compatible with the D-PHY protocol.

[0128] The second physical layer circuit may be configured to operate according to a serial data communication protocol. In one example, the physical layer circuit is configured to operate according to an SPI protocol. In another example, the physical layer circuit is configured to operate according to a CCI protocol. In another example, the physical layer circuit is configured to operate according to an I2C protocol. In another example, the physical layer circuit is configured to operate according to an I3C protocol. In another example, the physical layer circuit is configured to operate according to an SPMI protocol.

[0129] In some specific implementations, the second processor is configured to communicate with a touch panel interface associated with the display panel through the second physical layer circuit. The second processor can be configured to manage and control the operation of the touch panel interface. The second processor can be configured to communicate with the touch panel interface when the display controller operates in a high-speed mode. The second processor can be configured to communicate with the touch panel interface when the display controller operates in a low-power mode.

[0130] Some specific implementation examples are described in the following numbered clauses:

[0131] 1. A mobile communication device, the mobile communication device comprising: a display controller, the display controller is coupled to a display panel; a first physical layer circuit, the first physical layer circuit is powered by a first power supply and is configured to communicate a first data frame to the display controller at a first data rate through a first serial bus when the display controller operates in a high-speed mode, and to suppress communication through the first serial bus when the display controller operates in a low-power mode; a second physical layer circuit, the second physical layer circuit is powered by a second power supply and is configured to communicate a second data frame to the display controller at a second data rate through a second serial bus when the display controller operates in the low-power mode; a first processor, the first processor is powered by the first power supply and is configured to generate the first data frame; and a second processor, the second processor is powered by the second power supply and is configured to provide the second data frame to the second physical layer circuit when the display controller operates in the low-power mode.

[0132] 2. The mobile communication device of clause 1, wherein the first power source provides power at a voltage higher than a voltage provided by the second power source in the high speed mode.

[0133] 3. A mobile communication device according to clause 1 or clause 2, wherein when the display controller operates in the low power mode, the voltage at which the first power source provides power is reduced.

[0134] 4. A mobile communication device according to any one of clauses 1 to 3, wherein the first processor is further configured to enter a sleep mode when the display controller operates in the low power mode.

[0135] 5. A mobile communication device according to any of clauses 1 to 4, wherein the first physical layer circuit is further configured to enter a sleep mode when the display controller operates in the low power mode.

[0136] 6. A mobile communications device according to any of clauses 1 to 5, wherein the first physical layer circuit is further configured to operate according to the Mobile Industry Processor Interface (MIPI) Alliance Display Serial Interface (DSI) protocol.

[0137] 7. A mobile communication device according to any one of clauses 1 to 6, wherein the second physical layer circuit is further configured to operate according to a serial peripheral interface (SPI) protocol, a camera control interface (CCI) protocol, an inter-integrated circuit (I2C) protocol, an improved inter-integrated circuit (I3C) protocol, or a system power management interface (SPMI) protocol.

[0138] 8. A mobile communication device according to any of clauses 1 to 7, wherein the second processor is further configured to communicate with a touch panel interface via the second physical layer circuit.

[0139] 9. A method for operating a display in a mobile communication device, the method comprising:

[0140] A first physical layer circuit powered by a first power supply is configured to: communicate a first data frame to the display controller at a first data rate through a first serial bus when the display controller operates in a high-speed mode, and suppress communication through the first serial bus when the display controller operates in a low-power mode; a second physical layer circuit powered by a second power supply is configured to communicate a second data frame to the display controller at a second data rate through a second serial bus when the display controller operates in the low-power mode; a first processor is configured to generate the first data frame, and the first processor is powered by the first power supply; and a second processor is configured to provide the second data frame to the second physical layer circuit when the display controller operates in the low-power mode, and the second processor is powered by the second power supply.

[0141] 10. The method of clause 9, wherein the first power source provides power at a voltage higher than a voltage at which the second power source provides power in the high speed mode.

[0142] 11. The method of clause 9 or clause 10, wherein when the display controller operates in the low power mode, a voltage at which the first power source provides power is reduced.

[0143] 12. The method of any of clauses 9 to 11, further comprising configuring the first processor to enter a sleep mode when the display controller operates in the low power mode.

[0144] 13. The method of any of clauses 9 to 12, further comprising configuring the first physical layer circuit to enter a sleep mode when the display controller operates in the low power mode.

[0145] 14. The method of any of clauses 9 to 13, further comprising configuring the first physical layer circuit to operate in accordance with a Mobile Industry Processor Interface (MIPI) Alliance Display Serial Interface (DSI) protocol.

[0146] 15. According to any one of clauses 9 to 14, the method further includes: configuring the second physical layer circuit to operate according to a serial peripheral interface (SPI) protocol, a camera control interface (CCI) protocol, an inter-integrated circuit (I2C) protocol, an improved inter-integrated circuit (I3C) protocol or a system power management interface (SPMI) protocol.

[0147] 16. The method of any of clauses 9 to 15, further comprising configuring the second processor to communicate with a touch panel interface via the second physical layer circuit.

[0148] 17. A device, comprising: a component for communicating with a display controller, the component comprising: a first physical layer circuit, the first physical layer circuit being powered by a first power supply and being operable to communicate a first data frame to the display controller at a first data rate through a first serial bus when the display controller operates in a high-speed mode, and to suppress communication through the first serial bus when the display controller operates in a low-power mode; and a second physical layer circuit, the second physical layer circuit being powered by a second power supply and being operable to communicate a second data frame to the display controller at a second data rate through a second serial bus when the display controller operates in the low-power mode; a component for providing display data to the component for communicating with the display controller, the component comprising: a first processor, the first processor being powered by the first power supply and being configured to generate the first data frame; and a second processor, the second processor being powered by the second power supply and being configured to provide the second data frame to the second physical layer circuit when the display controller operates in the low-power mode.

[0149] 18. An apparatus according to clause 17, wherein the first power supply provides power at a voltage higher than the voltage provided by the second power supply in the high-speed mode, and wherein the voltage provided by the first power supply is reduced when the display controller operates in the low-power mode.

[0150] 19. The apparatus of clause 17 or clause 18, wherein the first processor is configured to enter a sleep mode when the display controller operates in the low power mode.

[0151] 20. An apparatus as recited in any of clauses 17 to 19, wherein the first physical layer circuit is configured to enter a sleep mode when the display controller operates in the low power mode.

[0152] 21. An apparatus according to any of clauses 17 to 20, wherein the first physical layer circuit is further configured to operate in accordance with the Mobile Industry Processor Interface (MIPI) Alliance Display Serial Interface (DSI) protocol.

[0153] 22. An apparatus according to any one of clauses 17 to 21, wherein the second physical layer circuit is configured to operate according to a serial peripheral interface (SPI) protocol, a camera control interface (CCI) protocol, an inter-integrated circuit (I2C) protocol, an improved inter-integrated circuit (I3C) protocol, or a system power management interface (SPMI) protocol.

[0154] 23. An apparatus as described in any of clauses 17 to 22, wherein the second processor is configured to communicate with a touch panel interface through the second physical layer circuit.

[0155] 24. A processor-readable storage medium, the processor-readable storage medium comprising code for: configuring a first physical layer circuit powered by a first power supply to: communicate a first data frame to the display controller at a first data rate via a first serial bus when the display controller operates in a high-speed mode, and suppress communication via the first serial bus when the display controller operates in a low-power mode; configuring a second physical layer circuit powered by a second power supply to communicate a second data frame to the display controller at a second data rate via a second serial bus when the display controller operates in the low-power mode; configuring a first processor to generate the first data frame, the first processor being powered by the first power supply; and configuring a second processor to provide the second data frame to the second physical layer circuit when the display controller operates in the low-power mode, the second processor being powered by the second power supply.

[0156] 25. The storage medium of clause 24, wherein the first power source provides power at a voltage higher than a voltage provided by the second power source in the high speed mode, and wherein the voltage provided by the first power source is reduced when the display controller operates in the low power mode.

[0157] 26. The storage medium of clause 24 or clause 25, further comprising configuring the first processor to enter a sleep mode when the display controller operates in the low power mode.

[0158] 27. The storage medium according to any one of clauses 24 to 26, further comprising:

[0159] The first physical layer circuit is configured to enter a sleep mode when the display controller operates in the low power mode.

[0160] 28. The storage medium according to any one of clauses 24 to 27, further comprising:

[0161] The first physical layer circuit is configured according to the mobile industry processor interface (MIPI)

[0162] The Alliance Display Serial Interface (DSI) protocol operates.

[0163] 29. The storage medium according to any one of clauses 24 to 28, further comprising:

[0164] The second physical layer circuit is configured to operate according to a serial peripheral interface (SPI) protocol, a camera control interface (CCI) protocol, an inter-integrated circuit (I2C) protocol, a modified inter-integrated circuit (I3C) protocol, or a system power management interface (SPMI) protocol.

[0165] 30. The storage medium according to any one of clauses 24 to 29, further comprising:

[0166] The second processor is configured to communicate with a touch panel interface through the second physical layer circuit.

[0167] It should be understood that the specific order or hierarchy of steps in the disclosed processes is an illustration of an exemplary method. It should be understood that the specific order or hierarchy of steps in these processes can be rearranged according to design preferences. In addition, some steps can be combined or omitted. The attached method claims present the elements of multiple steps in a sample order and are not meant to be limited to the specific order or hierarchy presented.

[0168] The foregoing description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects. Therefore, the claims are not intended to be limited to the aspects shown herein, but to conform to the full scope consistent with the language claims, wherein the elements mentioned in the singular are not intended to represent "one and only one", unless specifically so stated, but "one or more". Unless otherwise specified, the term "some" refers to one or more. All structural and functional equivalents of the elements of the various aspects described throughout the present disclosure that are known or will be known to a person of ordinary skill in the art are expressly incorporated herein by reference, and are intended to be covered by the claims. In addition, nothing disclosed herein is intended to be dedicated to the public, regardless of whether such disclosure is explicitly stated in the claims. Any claim element cannot be interpreted as a component plus function unless the element is explicitly stated using the phrase "component for..."

Claims

1. A mobile communication device, comprising: a display controller coupled to the display panel; A first physical layer circuit, the first physical layer circuit is powered by a first power supply and is configured as follows: When the display controller operates in a high-speed mode, communicating a first data frame to the display controller at a first data rate via a first serial bus, and inhibiting communications over the first serial bus when the display controller is operating in a low power mode; a second physical layer circuit powered by a second power supply and configured to communicate a second data frame at a second data rate to the display controller via a second serial bus when the display controller operates in the low power mode; a first processor, the first processor being powered by the first power supply and configured to generate the first data frame; and A second processor is powered by the second power supply and is configured to provide the second data frame to the second physical layer circuit when the display controller operates in the low power mode. 2 . The mobile communication device according to claim 1 , wherein the first power source supplies power at a voltage higher than a voltage at which the second power source supplies power in the high speed mode. 3 . The mobile communication device of claim 1 , wherein when the display controller operates in the low power mode, a voltage at which the first power source provides power is reduced. 4 . The mobile communication device of claim 1 , wherein the first processor is further configured to enter a sleep mode when the display controller operates in the low power mode. 5 . The mobile communication device of claim 1 , wherein the first physical layer circuit is further configured to enter a sleep mode when the display controller operates in the low power mode.

6. The mobile communication device of claim 1, wherein the first physical layer circuit is further configured to operate according to a Mobile Industry Processor Interface (MIPI) Alliance Display Serial Interface (DSI) protocol.

7. A mobile communication device according to claim 1, wherein the second physical layer circuit is further configured to operate according to a serial peripheral interface (SPI) protocol, a camera control interface (CCI) protocol, an inter-integrated circuit (I2C) protocol, an improved inter-integrated circuit (I3C) protocol or a system power management interface (SPMI) protocol.

8. The mobile communication device of claim 1, wherein the second processor is further configured to communicate with a touch panel interface through the second physical layer circuit.

9. A method for operating a display in a mobile communication device, the method comprising: The first physical layer circuit powered by the first power supply is configured as follows: When the display controller operates in a high-speed mode, communicating a first data frame to the display controller at a first data rate via a first serial bus, and inhibiting communications over the first serial bus when the display controller is operating in a low power mode; configuring a second physical layer circuit powered by a second power supply to communicate a second data frame at a second data rate to the display controller via a second serial bus when the display controller operates in the low power mode; configuring a first processor to generate the first data frame, the first processor being powered by the first power supply; as well as A second processor is configured to provide the second data frame to the second physical layer circuit when the display controller operates in the low power mode, the second processor being powered by the second power supply. 10 . The method of claim 9 , wherein the first power source provides power at a voltage higher than a voltage provided by the second power source in the high speed mode.

11. The method of claim 9, wherein when the display controller operates in the low power mode, a voltage at which the first power supply provides power is reduced.

12. The method according to claim 9, further comprising: The first processor is configured to enter a sleep mode when the display controller is operating in the low power mode.

13. The method according to claim 9, further comprising: The first physical layer circuit is configured to enter a sleep mode when the display controller operates in the low power mode.

14. The method according to claim 9, further comprising: The first physical layer circuit is configured to operate according to a Mobile Industry Processor Interface (MIPI) Alliance Display Serial Interface (DSI) protocol.

15. The method according to claim 9, further comprising: The second physical layer circuit is configured to operate according to a serial peripheral interface (SPI) protocol, a camera control interface (CCI) protocol, an inter-integrated circuit (I2C) protocol, a modified inter-integrated circuit (I3C) protocol, or a system power management interface (SPMI) protocol.

16. The method according to claim 9, further comprising: The second processor is configured to communicate with a touch panel interface through the second physical layer circuit.

17. A device, comprising: A component for communicating with a display controller, the component comprising: a first physical layer circuit powered by a first power supply and operable to communicate a first data frame to the display controller at a first data rate via a first serial bus when the display controller operates in a high-speed mode; and inhibiting communications over the first serial bus when the display controller is operating in a low power mode; and a second physical layer circuit powered by a second power supply and operable to communicate a second data frame at a second data rate to the display controller via a second serial bus when the display controller operates in the low power mode; Means for providing display data to the means for communicating with the display controller, the means comprising: a first processor powered by the first power supply and configured to generate the first data frame; and A second processor is powered by the second power supply and is configured to provide the second data frame to the second physical layer circuit when the display controller operates in the low power mode.

18. The apparatus of claim 17, wherein the first power supply provides power at a higher voltage than a voltage provided by the second power supply in the high speed mode, and wherein the voltage provided by the first power supply is reduced when the display controller operates in the low power mode.

19. The apparatus of claim 17, wherein the first processor is configured to enter a sleep mode when the display controller operates in the low power mode.

20. The apparatus of claim 17, wherein the first physical layer circuit is configured to enter a sleep mode when the display controller operates in the low power mode.

21. The apparatus of claim 17, wherein the first physical layer circuit is configured to operate according to a Mobile Industry Processor Interface (MIPI) Alliance Display Serial Interface (DSI) protocol.

22. An apparatus according to claim 17, wherein the second physical layer circuit is configured to operate according to a serial peripheral interface (SPI) protocol, a camera control interface (CCI) protocol, an inter-integrated circuit (I2C) protocol, an improved inter-integrated circuit (I3C) protocol, or a system power management interface (SPMI) protocol.

23. The apparatus of claim 17, wherein the second processor is configured to communicate with a touch panel interface through the second physical layer circuit.

24. A processor-readable storage medium comprising code for: The first physical layer circuit powered by the first power supply is configured as follows: When the display controller operates in a high-speed mode, communicating a first data frame to the display controller at a first data rate via a first serial bus, and inhibiting communications over the first serial bus when the display controller is operating in a low power mode; configuring a second physical layer circuit powered by a second power supply to communicate a second data frame at a second data rate to the display controller via a second serial bus when the display controller operates in the low power mode; configuring a first processor to generate the first data frame, the first processor being powered by the first power supply; as well as A second processor is configured to provide the second data frame to the second physical layer circuit when the display controller operates in the low power mode, the second processor being powered by the second power supply.

25. The storage medium of claim 24, wherein the first power supply provides power at a higher voltage than the second power supply in the high speed mode, and wherein the voltage of the power provided by the first power supply is reduced when the display controller operates in the low power mode.

26. The storage medium according to claim 24, further comprising: The first processor is configured to enter a sleep mode when the display controller is operating in the low power mode.

27. The storage medium according to claim 24, further comprising: The first physical layer circuit is configured to enter a sleep mode when the display controller operates in the low power mode.

28. The storage medium according to claim 24, further comprising: The first physical layer circuit is configured to operate according to a Mobile Industry Processor Interface (MIPI) Alliance Display Serial Interface (DSI) protocol.

29. The storage medium according to claim 24, further comprising: The second physical layer circuit is configured to operate according to a serial peripheral interface (SPI) protocol, a camera control interface (CCI) protocol, an inter-integrated circuit (I2C) protocol, a modified inter-integrated circuit (I3C) protocol, or a system power management interface (SPMI) protocol.

30. The storage medium according to claim 24, further comprising: The second processor is configured to communicate with a touch panel interface through the second physical layer circuit.

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