On-chip pulse interconnect single packet multicast

Abstract

A method for routing pulses in a neuromorphic processor that includes a plurality of neuromorphic array cores, each core having an associated router. The method includes generating pulse data representing pulses generated by neurons in a source neuromorphic array kernel. A pulse data packet is generated, the pulse data packet containing pulse data, a destination vector, and a source core identification. The pulsed data packets are sent to one or more routers. Based on the destination vector, it is determined whether the receiving neuromorphic array core is a destination. If so, the pulse data is sent to a receiving neuromorphic array core. Further, it is determined whether there is an additional destination. If so, the destination vector is updated. Further, one or more next destinations are determined; and sending the pulsed data packet or a copy of the pulsed data packet to one or more output ports of the router.

Description

Technical Field

[0001] The present disclosure relates generally to neuromorphic processors, and more particularly to a neuromorphic array forming pulse / spike interconnects on a chip, and a routing method for communicating between different cores of a neuromorphic array. Background Art

[0002] Neuromorphic computing is a type of computing inspired by the structure and function of the human brain. In biological neural network models, individual neurons communicate asynchronously through sparse events, or spikes. In this event-based spiking neural network (SNN), only neurons that change state generate spikes, which can trigger signal processing in subsequent layers, saving computing resources.

[0003] SNNs encode information in the form of these one or more precisely timed (voltage) pulses, rather than as integers or real-valued vectors. The computations used for inference (i.e., reasoning about the presence of a certain feature in the input signal) are performed efficiently in the analog and time domains. For this reason, SNNs are typically implemented in hardware as full-custom mixed-signal integrated circuits. This enables them to perform inference functions with energy consumption orders of magnitude lower than their artificial neural network counterparts.

[0004] Therefore, neuromorphic processors typically include an array of spiking neurons and synapses. Thus, a spiking neuron receives input from one or more synapses and generates a spike when the input reaches a certain predetermined threshold. The exact timing of the spike depends on the strength and sequence of the input stimulus.

[0005] SNNs consist of a network of spiking neurons interconnected by synapses, which determine the strength of the connections between spiking neurons. This strength is represented as a weight that regulates the influence of the output of the presynaptic neuron on the input of the postsynaptic neuron. Typically, these weights are set during a training process that involves exposing the network to a large amount of labeled input data and gradually adjusting the weights of the synapses until the desired network output is achieved.

[0006] SNN can be directly applied to pattern recognition and sensor data fusion. The principle is that the amplitude domain features, time domain features and frequency domain features in the input signal can be encoded into unique spatial and temporal encoded pulse sequences.

[0007] The generation of these sequences relies on the use of one or more spiking neuron ensembles, which are groups of cooperating neurons. Each ensemble performs a specific signal processing function, such as feature encoding, conditioning, filtering, data fusion, and classification. Each ensemble consists of one or more interconnected layers of spiking neurons, with connections within and between layers following a specific topology. The size of each ensemble (number of neurons), their connectivity (topology and number of synapses), and their configuration (weights and number of layers) depend on the characteristics of the input signal, such as the dynamic range, bandwidth, time scale, or complexity of the features in the input signal.

[0008] In general, as the complexity of the features to be recognized in the input signal increases, the size of the swarm required to process these features also increases. Spiking neural network hardware can utilize configurable arrays of spiking neurons and synapses connected using a programmable interconnect fabric that facilitates the implementation of arbitrary connection topologies. However, to achieve large swarms, the underlying SNN hardware must have at least as many neurons and synapses as required.

[0009] The need for on-chip network architectures stems from the efficiency of the communication channels between neuronal arrays (implementation-independent, and therefore valid for analog or digital / discrete implementations of these arrays), where communication throughput efficiency is evaluated based on specific criteria such as channel capacity, latency, time dispersion (i.e., delay distribution), and channel integrity (i.e., the success rate of pulses being delivered to the correct destination).

[0010] In PCT / EP2019 / 081662, it is proposed to divide the SNN into multiple sub-networks. Each sub-network includes a subset of spiking neurons connected to receive synaptic output signals from a subset of synaptic elements. In addition, each sub-network is adapted to generate a sub-network output pattern signal in response to a sub-network input pattern signal applied to the sub-network. In addition, each sub-network forms part of one or more cores in a core array, each core including a programmable spiking neuron network implemented in hardware or a combination of hardware and software, and communication between the cores in the core array is arranged through a programmable interconnect structure.

[0011] The resulting neuromorphic processors can form a neuromorphic array, which can include multiple interconnected neuromorphic array (NMA) cores. Such interconnections can form a network of cores, which can be located on a single chip, forming a network on a chip (NoC).

[0012] By dividing a large spiking neural network into smaller sub-networks and implementing each sub-network on one or more cores, the number of neurons in each core can be kept small, and these cores can communicate with each other via a NoC.

[0013] The sub-networks or neuron groups forming a cooperative group may, for example, form a classifier, a group of classifiers, a neuron group handling data transformation, feature encoding or only classification, and the like.

[0014] In this state, the large swarm network is partitioned and mapped onto an array of cores, each containing a programmable network of spiking neurons. Thus, each core implements a single swarm, multiple small swarms (related to the number of neurons and synapses in the core), or, in the case of a large swarm, only a portion of a single swarm, with the remaining portions implemented on other cores in the array. The mapping method determines how the swarm is partitioned and mapped onto the cores.

[0015] The mapping method may include constraint-driven partitioning, but other mapping methods are also possible. The constraints may be performance metrics related to the functionality of each respective sub-network. The performance metric may depend on the number of hops a packet travels between cores, the minimum distance between cores, power region constraints, memory structure, memory access, time constants, biases, technology limitations, resilience, acceptable mismatch levels, and / or network or physical artifacts.

[0016] The periphery of the array includes multiple rows of synaptic circuits that mimic the action of the soma and axon hillock of biological neurons. In addition, each neurosynaptic core in the array has a local router that communicates with the routers of other cores within a dedicated real-time reconfigurable on-chip network.

[0017] The local routers and their connections form a programmable interconnect structure between the cores of the core array. The cores can be connected via a switchable matrix. Thus, different cores of the core array are connected via the programmable interconnect structure. Specifically, different parts of the spiking neural network implemented on different cores of the core array are interconnected via the programmable interconnect structure. In this way, quantum effects and external noise only act on each core individually, rather than on the entire network. Therefore, these effects (if relevant) can be mitigated.

[0018] Spiking neural networks implemented on core arrays can have high modularity, in the sense that they have dense connections between neurons within a core, but sparse connections between different cores. In this way, noise and quantum effects between cores are further reduced while still allowing subnetworks to improve, for example, classification accuracy by allowing high complexity.

[0019] Communication between neurons in a neuromorphic array consists of spike events. A spike event can be simply encoded as the identifier of the neuron where the spike occurred, or additionally, as a relative timestamp of when the event was generated (e.g., relative to a previous spike that occurred) and the amplitude of the impulse response generated by the neuron. In all modalities, every time a spike occurs, it needs to be delivered to all synapses to which the spike neuron is connected. Spike events are relayed to other cores in the form of data packets (called spike packets).

[0020] A pulse packet is a unit of communication between NMA cores, which generates pulses and also consumes different pulses.

[0021] The programmable interconnect fabric can form a packet-switched network between the cores in the core array. These connections can form a digital network. Data can be output, for example, from one of the subnetworks of a spiking neural network partitioned and implemented on one or more cores in the core array.

[0022] Routing these pulse packets involves drawing a path with multiple pulse routers and physical links along which the pulse packet is forwarded from the source node to the destination node, depending on the routing algorithm. The pulse routers present in each node can have multiple input and output ports. Each pulse router has an ID, and the pulse packet can contain the destination pulse router ID, which is used by intermediate pulse routers to route the pulse packet to the desired destination, based on the routing algorithm.

[0023] Some examples of known routing techniques are presented below.

[0024] The first example is deterministic routing, where the path between the source and destination is predetermined. This technique preserves packet order and can avoid deadlocks. This approach does not utilize all the ports of the routers and other interconnected connections (paths) to balance the network.

[0025] A second example of a routing technique is dimensional sequential routing, which calculates the shortest deterministic path between the source and destination in the three topologies mentioned above. The packet is first routed in a specific direction, then in another direction, until it reaches the desired destination. For example, in a 2D mesh, according to the XY dimensional routing algorithm, the packet is routed in the X dimension until it reaches the X coordinate of the destination router (which is the final destination router), and then it is routed in the Y dimension until it reaches the Y coordinate of the destination router.

[0026] A neural network mapped onto a multicore NMA chip can have several different properties; it can be fully connected, partially connected, recursively connected, skip-connected, and so on. Therefore, it may be necessary to send spikes from one core to multiple cores. The mapping of neural network neurons to the NMA determines the flow of spike packets across the interconnect. The one-to-many nature of neural networks requires that spike packets be multicast to different NMA cores.

[0027] Sending burst packets from one core to multiple cores is called multicast communication, which can be based on unicast. In this method, multicast operations are performed by duplicating the payload for each destination or a subset of destinations. The packets contain the same payload but different destination IDs. If there are N destinations, this method sends N packets. This method has significant network latency and high power consumption.

[0028] The current technology of multicast communication is based on unicast, which Figure 3 This approach can generate a large number of packets in the interconnect and can cause congestion. Furthermore, generating unnecessary extra bursts of packets can burden the source node. Therefore, new routing techniques are needed. Summary of the Invention

[0029] In one aspect, the present invention includes a method for routing pulses in a neuromorphic processor. The neuromorphic processor includes a plurality of neuromorphic array cores, each core having an associated router. The neuromorphic array cores may each include a spiking neural network including a plurality of neurons connected via synapses. The method includes: generating pulse data representing one or more pulses generated by one or more neurons in a source neuromorphic array core among the plurality of neuromorphic array cores; generating a pulse data packet, the pulse data packet including the pulse data, a destination vector indicating one or more destinations for the pulse packet, and a source identifier indicating the source neuromorphic array core; sending the pulse data packet to one or more routers of the neuromorphic processor; receiving the pulse data packet in a router of a receiving neuromorphic array core among the plurality of neuromorphic array cores; reading the destination vector of the received pulse data packet; and determining, based on the destination vector, whether the receiving neuromorphic array core is the destination of the pulse data packet. , and if so, sending the pulse data to the receiving neuromorphic array core; and based on the destination vector, determining whether the pulse data packet has one or more other destinations in addition to the receiving neuromorphic array core, and if so, (a) if the receiving neuromorphic array core is indicated as a destination in the destination vector, updating the destination vector to remove the receiving neuromorphic array core as a destination for the pulse data packet, (b) based on the destination vector and a routing algorithm of the router, determining one or more next destinations for the pulse data packet, and (c) based on the determined one or more next destinations, sending the pulse data packet or a copy of the pulse data packet to one or more output ports of the router.

[0030] This provides a multicast routing method that relieves the source neuromorphic array core of the burden of generating multiple packets and facilitates modifying the packet at each router if the neuromorphic array core associated with the router is one of the destination nodes. The proposed method allows intermediate routers to use simple router logic, forward packets without routing tables in the router, and reduce the latency of burst transmission.

[0031] The routing method may include determining only one next destination for the pulse data packet based on a destination vector; and sending the pulse data packet or a copy of the pulse data packet to one output port based on the determined next destination. If the destination vector is updated, the updated destination vector may be included in the pulse data packet or the copy of the pulse data packet sent to the output port. The method may be described as a single packet multicast method, in which a single pulse data packet is transmitted through the neuromorphic processor without duplicating the packet. This reduces congestion in the neuromorphic processor because there are not a large number of packets with the same payload and different destinations. The method also preserves the order of the pulse data as received in the destination neuromorphic array core and uses simple router logic for low-latency transmission.

[0032] Alternatively, the routing method may further include: when more than one next destination for the pulse data packet is determined, deriving a plurality of new destination vectors from the destination vector, wherein the destinations indicated in the destination vector are divided among the plurality of new destination vectors, and each pulse data packet sent to the output port includes one of the new destination vectors. This method further reduces packet transmission latency caused by the presence of multiple pulse data packets with the same pulse data payload and different destination vectors (which are dynamically generated by the router). A deterministic routing algorithm (e.g., an XY routing algorithm) may also be used to preserve the order in which the pulse data is received.

[0033] The pulse data contained in the pulse data packet can indicate which neurons in the source neuromorphic array core generated a pulse during a specific time period. The pulse data can include coded data, such as binary coded data, wherein each bit of the binary coded data indicates whether the corresponding neuron generated a pulse during the time period. In addition, each pulse data packet can include timing data indicating the time period during which the pulse was generated. The timing data can indicate the time (e.g., a timestamp) at which one or more neurons generated one or more pulses, and can be a relative time.

[0034] The destination vector may be a destination bit vector including a plurality of bits, each bit indicating whether a corresponding one of the neuromorphic array cores of the neuromorphic processor is the destination of the pulse data packet. The position of each bit of the destination bit vector may be assigned to indicate whether the corresponding neuromorphic array core is the destination of the pulse data packet. For example, a bit at a certain bit position may be set to "1" to indicate that the corresponding neuromorphic array core is the destination of the pulse data packet. The number of bits in the destination bit vector may be equal to the number of neuromorphic array cores in the neuromorphic processor.

[0035] The routing method may further include: if the destination vector indicates that the receiving neuromorphic array core is the destination of the pulse data packet, then, based on the source identification, sending at least a portion of the pulse data to one or more neurons in the receiving neuromorphic array core. Sending the pulse data to the neuromorphic array core may include: sending the pulse data packet or a copy of the pulse data packet to a local output port of the router. The method may further include: generating one or more pulses based on the pulse data packet; and sending the one or more pulses to the one or more neurons in the neuromorphic array core.

[0036] The next destination of a pulse data packet can be determined using an XY dimensional routing algorithm, a selection algorithm based on a cost function, or a selection algorithm based on a fixed priority. In addition to the destination bit vector, each pulse packet can also include data about the next destination of the pulse data packet. This allows the router to forward the packet to the preferred destination.

[0037] In another aspect, the present invention provides a router for routing pulses in a neuromorphic processor, the neuromorphic processor comprising a plurality of neuromorphic array cores, each core having an associated router. The router may be used in the methods described herein. The router is configured to: receive a pulse data packet containing pulse data representing one or more pulses generated by one or more neurons in a source neuromorphic array core among a plurality of neuromorphic array cores and containing a destination vector indicating one or more destinations of the pulse data packet and a source identification indicating the source neuromorphic array core; read the destination vector of the received pulse data packet; determine, based on the destination vector, whether a neuromorphic array core associated with the router is the destination of the pulse data packet, and if so, send the pulse data to the neuromorphic array core; and determine, based on the destination vector, whether the pulse data packet has one or more other destinations in addition to the neuromorphic array core, and if so, (a) if the neuromorphic array core is indicated as the destination in the destination vector, update the destination vector to remove the neuromorphic array core as the destination of the pulse data packet; (b) determine one or more next destinations of the pulse data packet based on the destination vector and a routing algorithm of the router; and (c) send the pulse data packet or a copy of the pulse data packet to one or more output ports of the router based on the determined one or more next destinations.

[0038] The router may be configured to: determine only one next destination for the pulse data packet based on the destination vector; and send the pulse data packet or a copy of the pulse data packet to one output port based on the determined next destination. If the destination vector is updated, the updated destination vector may be included in the pulse data packet or the copy of the pulse data packet sent to the output port.

[0039] Alternatively, the router may be configured to derive a plurality of new destination vectors from the destination vector when more than one next destination for the pulse data packet is determined, wherein the destinations indicated in the destination vector are divided among the plurality of new destination vectors and each pulse data packet sent to an output port includes one of the new destination vectors.

[0040] In yet another aspect of the present invention, an interconnect for multicasting pulses in a neuromorphic processor is provided, wherein the interconnect comprises a plurality of routers as described herein and a plurality of communication links connecting the routers, wherein the routers are arranged in a two-dimensional mesh.

[0041] In yet another aspect of the present invention, a neuromorphic processor includes a plurality of neuromorphic array cores, each neuromorphic array core including a spiking neural network and having an associated router, the neuromorphic processor further comprising an interconnect and router as described herein. The neuromorphic processor can be implemented as a single integrated circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Embodiments will now be described, by way of example only, with reference to the accompanying drawings, in which corresponding reference characters indicate corresponding parts, and in which:

[0043] Figure 1 is a schematic diagram of a neuromorphic processor having a mesh topology, wherein each neuromorphic array core includes a router;

[0044] Figure 2 is a schematic diagram of a router according to the present invention and its connections to a neuromorphic array core assigned thereto or to other routers of a neuromorphic array;

[0045] Figure 3 is a schematic overview of routing techniques, specifically unicast-based multicast communications as known in the art;

[0046] Figure 4 It is a schematic overview of routing technology, specifically single-packet multicast communication;

[0047] Figure 5 is a schematic diagram of the pulse routing concept of a router for single-packet multicast communication;

[0048] Figure 6is a flow chart describing a single-packet multicast communication method;

[0049] Figure 7 is a flow chart describing the address modifier method;

[0050] Figure 8 It is a schematic overview of routing technology, specifically multi-packet chain reaction multicast communication;

[0051] Figure 9 is a schematic diagram of the pulse routing concept of a router for multi-packet multicast communication;

[0052] Figure 10 is a schematic diagram illustrating a flow chart of a multi-packet multicast communication method; and

[0053] Figure 11 is a diagram illustrating a flow chart of a destination vector segmentation algorithm. DETAILED DESCRIPTION

[0054] Certain embodiments will be described in more detail below. However, it should be understood that these embodiments should not be interpreted as limiting the scope of protection of the present disclosure.

[0055] Figure 1 FIG2 is a schematic diagram of a neuromorphic processor comprising a neuromorphic array partitioned into a plurality of neuromorphic array cores interconnected in a 2D mesh topology, wherein each neuromorphic array core 4 has a router 1. Other topologies are possible and fall within the scope of the present invention. The router 1 and core 4 together form a node of the neuromorphic array. Each core may include a programmable network of spiking neurons and synapses. Each router 1 may be used for inter-node communication.

[0056] A group is a sub-network of neurons that forms a cooperative group, which can form, for example, a classifier, a group of classifiers, a group of neurons that handles data transformation, feature encoding, or only classification, etc.

[0057] The swarm network can be partitioned and mapped onto the core array. Thus, each core implements a single swarm, multiple small swarms (related to the number of neurons and synapses in the core), or, in the case of a large swarm, only a portion of a single swarm is implemented, with the remaining portions implemented on other cores of the array. The manner in which the swarms are partitioned and mapped onto the cores can be determined by mapping methods that are beyond the scope of this invention.

[0058] Thus, each core comprises (at least a portion of) a spiking neural network comprising one or more neurons and one or more synapses (also referred to as synaptic elements). The neurons and synapses are at least partially or entirely implemented in hardware. Neuron 1 and synaptic element 2 can be implemented in hardware, for example using analog circuit elements or digital hard-wired logic circuits. They can also be implemented partially in hardware and partially in software. Preferably, they are implemented in hardware or at least partially in hardware, i.e., hardware circuits or elements are used to perform the functions of the individual neurons, rather than using a large processor to execute software (wherein the software mimics the individual neurons). These (partial) hardware implementations enable faster processing, for example, faster pattern recognition and event-driven processing (wherein blocks of neurons and synaptic elements are activated only when needed).

[0059] A typical router 1 may have, for example, five input ports and five output ports. The ports may be local, i.e., between the router 1 of a node 4 and different hardware structures within that node 4 (e.g., toward a spiking neural network formed in the node core); or the ports may be non-local, i.e., between routers 1 of different nodes 4. The number of input ports and output ports may be the same or different.

[0060] In this embodiment, each node has one local input port (L_in) and one local output port (L_out). In addition, the four non-local input ports shown are the north input port N_in, the south input port S_in, the west input port W_in, and the east input port E_in. The name of each input port indicates the input signal (11 N、S、W、E ) to the nodes in the mesh. The four non-local output ports shown are the North, South, West, and East output ports, indicated by N_out, S_out, W_out, and E_out, respectively. Similarly, for the output ports, the name of each output port indicates the node in the mesh that sends the output signal (12 N、S、W、E ) direction.

[0061] The mesh in this embodiment has a total of 16 nodes, but more or fewer nodes are also contemplated. Routers at the edge of the mesh may use fewer than four non-local input and output ports. For example, a router in a node located in the southeast corner of the mesh may only require input / output to the north and west. The exemplary mesh shown is a 2D mesh, but 1D or 3D meshes linked in a similar manner are also contemplated. While the exemplary mesh shown only shows connections between adjacent nodes, it is contemplated that routers may also connect to diagonally adjacent nodes, or to nodes that are not directly adjacent.

[0062] Figure 2is a schematic diagram of a router according to the present invention and its input and output ports to and from different routers within the mesh. It provides e.g. Figure 1 A more detailed overview of the router(s) 1 is shown in FIG.

[0063] Local input port 22 L and local output port 21 L As shown. As mentioned, these are used for communication between the router and the rest of the node to which the router is assigned. Non-local input ports 21 N、S、W、E and output port 22 N、S、W、E Arranges communication with other routers in the mesh.

[0064] Signals arriving at a router may pass through buffers 25. Buffers are memory blocks that can handle data (e.g., pulse packets) during the network routing process. As data flows through different nodes in the network, different transmission rates may occur between routers, potentially causing network congestion. Buffers 25 compensate for speed variations and temporarily store (e.g., pulse) packets to handle high-volume bursts during data transmission. The arriving signal may then pass through control logic point 23. Control logic point 23 reads the data in the pulse packet and determines whether the pulse packet should be sent or absorbed by the node. The control logic point may also include a routing algorithm module that applies a routing algorithm to determine whether the pulse packet should be sent to a local or non-local port and calculate the next destination. The control logic point may also modify information in the pulse packet, as described below with respect to, for example, the destination vector. The control logic point may also control the flow from the buffers to the crossbar switch. For example, multiple pulse packets may remain in a router's buffer until they are transmitted. The arriving signal (which may be adjusted) then reaches crossbar switch 24, which redirects input 21 to output 22, which may be a local or non-local output. Crossbar switch 24 configures the connections between input ports and output ports to establish the desired path for each packet.

[0065] Figure 3 The schematic overview of the known unicast-based multicast communication is shown in FIG. Nodes (cores) are arranged in a mesh topology. Figure 3Each box in the figure represents a neuromorphic array core (node) with a router. To send a pulse packet from a source node S to four destinations (A, B, C, and D), this method requires sending four separate pulse packets, one for each destination. These pulse packets are visualized by four different arrow types. Each pulse packet consists of the pulse data and the address of the destination node (A, B, C, or D) to which the pulse packet (SP) is directed, and its general form is SP = [<spike_data> ,<destination_node_address> ], which results in the following pulse grouping:

[0066] 1) SP1 = [<spike_data> ,<destination_node_address(A)> ];

[0067] 2) SP2 = [<spike_data> ,<destination_node_address(B)> ];

[0068] 3) SP3 = [<spike_data> ,<destination_node_address(C)> ];

[0069] 4) SP4 = [<spike_data> ,<destination_node_address(D)> ].

[0070] exist Figure 3 In this method, each arrow from the source node S is a pulse packet, and each packet can be sent sequentially or in parallel through the E_out port according to the XY dimensional routing algorithm. In this method, multicast is implemented over multiple unicast packets. This method generates a large number of packets in the interconnect and can cause congestion. Furthermore, the pulse data may be identical for all pulse packets SP1 to SP4, resulting in unnecessary copies of the same data. The present invention overcomes the shortcomings of the multi-packet unicast method by using single-packet multicast communication, as described in detail below.

[0071] In addition to unicast-based communication, other forms of multicast communication are path-based and tree-based multicast communication.

[0072] In path-based communication, pulse packets are forwarded sequentially to each destination along a path determined by a routing algorithm. In tree-based communication, the source node is considered the root of the tree, packets are sent down the tree, and pulse packets can be replicated at branches to a single set of destination nodes as needed. The methods of the present invention are both path-based and tree-based multicast communications. These are explained below.

[0073] Figure 4is a schematic overview of single packet multicast communication. In the proposed method, in order to send the same pulse data to four different destination nodes, a destination bit vector (DBV) is used. The destination bit vector can be a vector with a length equal to the number of nodes in the network. In this example, the number of nodes is 16, so the width of the DBV is 16 bits. Each bit position in the DBV represents a node / router ID. In this example, the node identified by the letter S is the source node, while A, B, C and D represent the destination nodes. In this method, only one SP is sent: Pulse Packet (SP) = [<spike_data> ,<destination_bit_vector> ,<next_destination> ]. Note that the next destination field is optional, and may be necessary for certain routing algorithms.

[0074] In this particular example, the source node S sets the destination bit vector to [1000010001000010] and the next destination to node A. According to the XY-dimensional routing algorithm in each router, the packet consisting of the pulse data and the destination bit vector is routed, taking the following path. First, the packet arrives at node A, where the pulse data is copied and absorbed, and the destination bit vector and next destination fields are modified. Next, according to the XY-dimensional routing algorithm, the packet is sent to the next router. This process is followed for all listed destination nodes. When the packet reaches the last node (in this case, node D), the packet is routed to the local port and is not sent further to the next router.

[0075] If a particular bit position in the DBV is set to 1, it indicates that the node ID corresponding to that bit position is one of the packet's destinations. In this example, Node A, whose node / router ID is 1, is one of the destinations for the pulse data. When the packet arrives at Node A, after the packet is copied and the original packet is absorbed, Bit Position 1 is cleared, i.e., set to 0. This process continues for each destination node until the final destination, Node D, where the packet is not copied but simply absorbed.

[0076] The method allows intermediate destination nodes to replicate the pulses, thereby alleviating the burden of the source node generating multiple packets. The method also facilitates modification of the packet at each input port (if the current node is one of the destination nodes). The proposed method allows intermediate nodes to forward packets without routing tables in the routers. It also reduces congestion in the network because there are not a large number of packets with the same payload but different destination IDs. Not only does this method preserve the pulse ordering in the destination nodes, but DBV also allows for the creation of simple router logic. The latter reduces the latency of the pulse transmission. To implement this pulse multicast technique, one can use e.g. Figure 5Pulse routing concept shown.

[0077] Figure 5 Schematic diagram of the pulse routing concept of a router for single-packet multicast communication. The network interface block 512 of the neuromorphic array 511 is responsible for determining the destination address / ID for the packet. The address modifier block 54 is responsible for modifying the destination bit vector.

[0078] From the N_in, S_in, W_in, and E_in non-local input ports (51 N、S、W、E ) receives the packet. The packet may pass through a buffer 53, which can temporarily store incoming packets in the event of congestion or other reasons, etc. After passing through the buffer 53, the packet may reach an address modifier block 54. The address modifier block may have a plurality of blocks for these ports 51. N、S、W、E Each of the sub-blocks 54 N、S、W、E , these sub-blocks act on packets received through their corresponding ports. There can also be a single address modifier block that acts on packets received through all input ports. The address modifier block checks whether the final destination node of the packet is the current node. If so, the packet can be absorbed and not copied. If the node is not the final destination, but is one of the destinations, the packet can be copied and the destination bit vector of the copied packet modified by clearing the bit position corresponding to the current node address / ID. The original packet is absorbed and, according to the routing algorithm, a copy is sent to the next router.

[0079] This is Figure 4 , where an incoming pulse packet to node A has a destination bit vector equal to [1000010001000010]. The router in node A copies the pulse packet, and the address modifier block of the router in node A modifies the destination bit vector to [1000010001000000]. That is, the destination bit vector is modified so that it no longer indicates node A as the destination of the pulse packet. The original packet payload can be routed to the local port of the router in node A.

[0080] If the current node is not the destination, the packet may be sent onward to the next node according to the routing algorithm without changing the destination bit vector of the pulse packet.

[0081] The absorption of the original packet can be done by the following steps. First, from each port (54 N、S、W、E ) of the address modifier block can pass through each buffer 55 N、S、W、Eis passed to the arbiter 56. The arbiter 56 can generate one output from all of these inputs, or the pulse data from all inputs can be stored separately. The output of the arbiter is called the local output 52 L . Local output as network interface local input 51 NI_L Enter the network interface block 512 of the neuromorphic array 511. Then, the network interface local input 51 NI_L can reach the neuromorphic array 511 and can be used as a pulse input to the neuromorphic array.

[0082] Network interface local input 51 NI_L The pulse data may indicate, for example, which synapse or synapses of the neuromorphic array the pulse represented by the pulse data is to reach. For example, the pulse data may indicate which neuron or neurons, for example, in the source node S, the pulse represented by the pulse data originates from. The pulse data may additionally or alternatively indicate one or more target synapses or neurons in the neuromorphic array 511 that the one or more pulses represented by the pulse data are to affect.

[0083] The neuromorphic array core 511 may have neurons that generate spatiotemporal spike trains, for which it is necessary to send (at least a portion of) spike data to neurons or synapses in different nodes. This may be done by local input from the network interface 511. NI_L Therefore, the neuromorphic array outputs pulses or pulse data, which the network interface block 512 can use to generate the network interface local output 52 NI_L , the output is used as local input 51 L Enter the router. Enter 51 L Contains information about the destination address / ID of the data packet, which can be generated by the neuromorphic array or the network interface.

[0084] Different methods can be used to calculate the next destination field in the pulse packet. The first method can be a destination selection based on a cost function. In this method, the total number of hops for each destination node is calculated, and one of several methods can be used to decide the next destination, such as by (a) selecting the destination corresponding to the least number of hops as the next destination, or (b) selecting the destination corresponding to the most hops as the next destination. The second method can be a destination selection based on fixed priorities. A priority can be assigned to each destination bit vector bit position. If a bit position in the destination bit vector is set to 1, this can mean that the node with the ID / address corresponding to that bit position is one of the destinations. Among these destinations, the next destination can be selected based on the priority.

[0085] Input 51 Land from 54 N、S、W、E The output can be temporarily stored in the corresponding buffer 57 L、N、S、W、E The routing algorithm 58 uses the information in the buffer 57 to determine the next hop on the path the packet should take to reach its destination.

[0086] The routing decision is then passed to the switch dispatcher 59 which considers the available resources and schedules the packet to be routed to a specific output port (52 N、S、W、E ) is transmitted. The switch distributor relays this information to the crossbar switch 510. The crossbar switch 510 configures the buffer 57 N、S、W、E and output port 52 N、S、W、E The packet is then forwarded to the output port 52 via the crossbar switch. N、S、W、E , where it can be forwarded to the next router. The crossbar switch can also be used to send the spike data to the neuromorphic array via the local input port.

[0087] Figure 6 FIG6 is a schematic diagram of a flow chart according to one manner of performing a single-packet multicast communication method. The flow chart begins at step 60. At step 61, one or more pulse packets may be collected from one or more input ports at one or more nodes. At step 62, the node address / ID of the node from which the pulse packets were collected and the destination bit vector of the pulse packets collected at the node are obtained.

[0088] At step 63, it is then determined whether the node address / ID is present in the destination bit vector. For example, whether the bit associated with the node in the destination bit vector is set to a particular value.

[0089] If the node address / ID does not exist in the destination bit vector, then route 63 is followed. b Step 68 is reached where the burst packet is routed according to the routing algorithm without absorbing the burst data at the node. The flow chart of this iteration of the single packet multicast communication method then ends at step 69.

[0090] On the other hand, if the node address / ID is present in the destination bit vector, then route 63 is followed. a Step 64 is reached where it is checked whether the node is the final destination node.

[0091] If the node is the final destination node ( Figure 4 Node D in the network) then follows route 64 a , and at step 65, the pulse packet / payload is absorbed by the local port, and at step 69, the flowchart ends.

[0092] If the node is not the final destination node, then follow route 64 b Step 66 is reached where a copy of the pulse packet is created. Subsequently, the original or the copy of the pulse packet is absorbed via the local port. Then, in step 67, the copy or the original of the pulse packet is obtained, respectively, and the next destination of the pulse packet is determined based on the preferred destination using the above-described destination selection method.

[0093] The packet is therefore routed according to the routing algorithm at step 68. It is also possible that a copy of the pulse packet is made after the payload has been absorbed / ejected by a local port (eg at a network interface).

[0094] Figure 7 is a schematic diagram of a flow chart according to one way of performing the address modifier method.After start 70, in step 71 the method requires obtaining the node address / ID of the node to which the pulse packet arrives and the destination bit vector for the pulse packet.

[0095] At step 72 , it is checked whether the current node address / ID position in the destination bit vector is set to a specific value, such as 1.

[0096] If the current node address / ID position in the destination bit vector is not set to a specific value, this means that the node is not the destination of the pulse packet and the route 72 is followed. b Step 77 is reached where the packet is routed according to the routing algorithm.

[0097] However, if the current node address / ID position in the destination bit vector is set to a specific value, then route 72 is followed. a Go to step 73. In step 73, the payload is copied, resulting in two payloads: the original and the copy. The original or copy payload follows route 73 a Step 74 is reached where the payload is received via the local port. The copy or original payload follows route 73 b Step 75 is reached where the current node ID position in the destination bit vector is set to 0. Then, in step 76, the destination selection method is used to determine the next destination field value based on the next preferred destination. Thereafter, in step 77, the packet is routed according to the routing algorithm.

[0098] Figure 8is a schematic overview of multi - group chain - reaction multicast communication. In the proposed method, to send a packet to M destinations, intermediate nodes replicate the packet during routing, creating up to (M - 1) new packets, each with a different destination bit - vector and next - destination field value. For a network of N nodes, for example, a destination bit - vector of length equal to the number of nodes in the network is employed. In this case, for example, each bit - position in the destination bit - vector represents a node or router address / ID. In this particular embodiment, there are M = 4 destinations and N = 16. To send pulse data to 4 destinations, the source node sends a packet, and, where appropriate, intermediate nodes split the destination vector into two vectors. Intermediate nodes can replicate the packet and create one or more new packets with different destination bit - vectors and next - destination field values. In this example, only one copy of the original packet is made at node A, so at least two pulse packets containing the original pulse data are sent from node A.

[0099] Figure 8 shows the proposed method, where node S is the source node and A, B, C, D are destination nodes. In this method, only one pulse packet is sent from the source node: Pulse Packet (SP)=[<spike_data>,<destination_bit_vector>,<next_destination>]. Also, the next - destination field is optional.

[0100] The source node S creates a pulse packet with a destination bit - vector of [1000010001000010], so, SP = [<spike_data>,<1000010>001000010>,<node A>]. Then, the pulse packet can be routed according to, for example, the XY - Routing algorithm and follows the following path. When the packet arrives at node A, since node A is a destination node of the pulse packet, the pulse data contained in the spike_data field is absorbed. The absorption can be carried out according to the above description. Next, according to the Destination Vector Split (DVS) method (further disclosed in Figure 11 ), the packet can be replicated and the destination bit - vector modified, and then the packet is passed according to the XY - routing algorithm. Note that the packet can be replicated before or after being absorbed at the node. Thus, at node A, two packets with different destination bit - vectors are created / modified, one packet (p1) is designated to node B and the other packet (p2) is designated to nodes C and D.

[0101] According to the XY algorithm, the pulse packet p1 is routed to node B. At node 2, the packet does not need to be duplicated because there is only one destination in the destination bit vector. In addition, at node 2, the packet does not need to be absorbed because it is not the destination node.

[0102] According to the XY algorithm, pulse packet p2 is routed to node 5. At this node 5, the packet is duplicated, and the destination bit vector is modified according to the destination vector splitting method. The new packet p2_1 is routed to node C, while another new packet p2_2 is routed to destination D. At nodes 6 and 9, pulse packets are not duplicated because DVB only has one destination. After reaching each packet's final destination, the packet is absorbed and not replicated again.

[0103] Figure 8 The node or router ID / address of all nodes / routers numbered between 0 and 15 is shown. The bit position in the destination bit vector can indicate the router ID. If the value of a particular bit position in the destination bit vector is set to "1", it indicates that the node ID equal to that bit position is one of the destinations of the packet.

[0104] In this example, Node A has a node or router ID / address of 1, and it is one of the destinations. When a packet arrives at Node A, bit position 1 is cleared (i.e., set to 0) before or after the packet is duplicated and originally absorbed. The next destination in each new pulse packet is set according to one of the Destination Selection Methods (DSMs). Each intermediate destination node follows this method until the final destination node for each pulse packet, where the packet is not duplicated and is simply routed through the local input port without further forwarding.

[0105] As mentioned above, the pulse packet may also be replicated into two or more copies. Whether the pulse packet needs to be replicated and the destination bit vector split between destinations may depend on the routing algorithm used. For example, in certain XY-routing algorithms, splitting may occur if multiple destinations exist in the same row. Other ways of determining whether splitting is necessary are also within the scope of the present invention. Whether the original packet is absorbed depends on whether the node is the destination node.

[0106] The proposed method allows intermediate nodes to replicate the pulse packet, thereby alleviating the burden on the source node to generate multiple packets. Furthermore, the method also facilitates modifying the packet at each input port if the current node is one of the intermediate nodes and the destination bit vector has, for example, more than one destination bit set.

[0107] The proposed method also allows intermediate nodes to forward packets without routing tables in their routers. This method reduces packet delivery delays caused by the presence of a large number of packets with the same payload but different destination IDs (which are dynamically created in the network). This method preserves the ordering of pulses (which form the basis of the pulse packets) at the destination node according to deterministic routing algorithms (e.g., the XY algorithm).

[0108] Additionally, the destination bit vector allows for the creation of simple router logic, thereby reducing the latency of burst transmissions. The next destination field allows the router to forward the packet to a preferred next destination.

[0109] Figure 9 is a diagram illustrating the pulse routing concept of a router for multi-packet multicast communication. Figure 9 The examples in Figure 5 The main difference between the embodiments is that Figure 9 The embodiment includes a destination vector splitting (DVS) block 94, which is responsible for modifying the destination bit vector.

[0110] From the N_in, S_in, W_in, and E_in non-local input ports (91 N、S、W、E ) receives the packet. The pulse packet may then pass through a buffer 93 which can temporarily store incoming packets in the event of congestion or other reasons, etc. Each port may have its own dedicated buffer. After passing through the buffer 93, the packet may reach a DVS block 94. The DVS block 94 may be a single functional module or may be subdivided into blocks (94) for each non-local input port. N、S、W、E ). The DVS block 94 may check whether the final destination node of the packet is the current node. If so, the packet is absorbed and no copy of the packet is created.

[0111] If the node is not the final destination but one of the intermediate destination nodes, two or more copies of the packet are made and the destination bit vectors and next destination fields of these copies are modified by clearing the bit positions corresponding to the current node ID / address and setting the next destination accordingly using the Destination Selection Method (DSM). The original packet is absorbed and the copies are transmitted to the next router according to the routing algorithm.

[0112] Absorbs the original packet and transmits a copy according to the routing algorithm to Figure 5 Absorption and transmission are also carried out in a similar way. Figure 8In the visualization, the packet input to node A has a destination bit vector equal to [0010010001000010], two new packets p1 and p2 have destination bit vectors [0000000001000000] and [0010010000000000] respectively, and the original packet payload is routed to the local input port of the router in node A. If the current node is the final destination, the packet is not transmitted further, if not, the packet is transmitted according to the routing algorithm. This process is repeated for all intermediate nodes of the pulse packet.

[0113] Figure 10 FIG1 is a schematic diagram of a flow chart describing a multi-packet multicast communication method. After starting 101, pulse packets can be collected from an input port of a particular node at step 102, and a node address / ID and a destination bit vector are obtained for the pulse packets in the node at step 103. Next, at step 104, a comparison is made to determine whether the node address / ID exists in the destination bit vector, e.g., by indicating a value of "1" in the destination bit vector.

[0114] If the node address / ID does not exist in the destination bit vector, then follow route 104 b Step 107 is reached, where one or more copies of the packet with different destination bit vectors can be created (if necessary) according to a destination vector splitting (DVS) algorithm. At step 108, a destination selection method can be used to determine the next destination based on the preferred destination. Thus, at step 109, the pulse packet can be routed according to the routing algorithm. At step 110, the method ends.

[0115] If the node address / ID is present in the destination bit vector, then route 104 is followed a Step 105 is reached where it is checked whether the particular node is the final destination node. If the node is the final destination node, then the route 105 may be followed. a , and in step 106a, the packet / payload is absorbed / ejected through the local port, and in step 110, the method ends. If the node is not the final destination node, then the route 105 is followed bStep 107 is reached, where one or more copies of the packet with different destination bit vectors can be created according to a destination vector splitting (DVS) algorithm. Next, at step 106b, the (original) packet / payload can be absorbed / evicted via the local port. Next, at step 108, a destination selection method can be used to determine the next destination for the copy based on the preferred destination. The copied pulse packet can then be routed according to a routing algorithm 109, and the method ends at step 110. It is also possible that the packet is copied after the payload has been absorbed / evicted via the local port, meaning that 106a / 106b will precede 105 in this method.

[0116] Figure 11 is a schematic diagram of a flow chart describing a destination vector splitting algorithm. The flow chart begins at the top: Start 111. In step 112, each input packet having an N-bit destination bit vector is obtained. In step 113, it is checked whether the processing of the previous burst packet has been completed.

[0117] If the processing of the previous burst packet has not been completed, follow route 113 a Step 114 is reached where the method waits until processing is complete.

[0118] However, if routing is already done, then follow route 113 b Step 115 is reached where the new burst packet is processed. After processing the packet's N-bit destination bit vector, step 116 divides the packet into two DBVs, A and B, in the middle of the original DBV, such that DBV A = DBV[N / 2:0] and DBV B = DBV[N-1:(N / 2)+1]. Figure 8 An example of this division is provided in FIGURE 1 for DBV[0010010001000010], N=16. This DBV is split into DBV A and DBV B, with DBV A containing the first half of the number ([8:0]) DBV A=[00100100] and DBV B containing the second half of the number ([15:9]) DBV B=[01000000]. Note that the bit position corresponding to node A is cleared, i.e., set to 0, because the node where the split occurred is node A, so when this split occurred, the pulse packet had already arrived. Figure 8 Destination A in.

[0119] At step 117, it is checked whether DBV A and DBV B are both not equal to zero. If they are not equal to zero, then route 117a is followed to step 118 where two copies of the pulse packet are created with A and B being the destination bit vectors, where A and B may be vectors with zeros appended so that the original length of these destination bit vectors is again equal to the number of nodes in the mesh, for example. Thus, at Figure 8 In this case, DBV A=[0010010000000000] and DBV B=[0000000001000000], and in step 1115, the splitting of the packet is completed.

[0120] If either DBV A or DBV B is equal to zero, then route 117b is followed to step 119. At step 119, a check is made to see if DBV A is equal to zero. If DBV A contains only zeros, then route 119a is followed to step 1110a, where a check is made to see if N is equal to 1. If N is not equal to 1, then route 1110aa is followed to step 1112, where the destination bit vector is set to DBVB and N is set to N / 2 (since this is the length of DVB B), and the flowchart is then traversed again starting at step 116, but using DVB B in place of the original destination bit vector. If N is equal to 1, then no further partitioning can be performed, and route 1110ab is followed to step 1111, where a duplicate pulse packet is sent out with the new DBV B (appended with zeros if necessary).

[0121] If DVB A does not contain only zeros, this means that DVB B contains only zeros. Thus, route 119b is followed to step 1110b, where a check is made to see if N is equal to 1. If N is not equal to 1, route 1110ba is followed to step 1113, where the destination bit vector is set to DBV A and N is set to N / 2 (since this is the length of DVB A). The flowchart is then traversed again, starting at step 116, but using DVB A in place of the original destination bit vector. If N is equal to 1, no further partitioning is possible, and route 1110bb is followed to step 1114, where a duplicate packet with the new DBV A (appended with zeros if necessary) is sent out.

[0122] Note that in all of the above examples, the destination neuron within the destination node can be unaware of the spike order and the time differences between the arrivals of different spikes, as long as the time differences are less than the neuron's decay period (or at least a certain fraction thereof). Since the neuron's decay period is typically programmable, the amount by which the destination neuron is independent of spike order can be adjusted to some extent.

[0123] Note that in all of the above examples, at each source node, the pulses can be encoded in binary format (e.g., a bit vector indicating which neuron within the source node has fired a pulse), optionally along with a timestamp of the pulse / pulse group when the pulse occurred. This can be a relative time, such as relative to the previous pulse. This can be entered into the pulse data field of the pulse packet. Thus, a pulse packet can contain information about a single pulse for a single neuron within a source node, but it can also contain information about pulses for a group of neurons or all neurons within the source node.

[0124] This can be achieved by detecting one or more pulses at the source node and, optionally, taking a snapshot of the timer value and then restarting the timer. Thereafter, the detected pulses can be encoded into a representation, such as a binary representation as described above, where a bit vector indicates, for each bit position, whether a neuron was fired. This encoded data (optionally with a timestamp) can then be placed in a pulse packet as pulse data. The pulse data can also include other information about the pulse that occurred.

[0125] In all embodiments, the pulse packet may also contain the source node or source router address / ID along with the pulse data. Additionally, as previously described, a destination bit vector may be included that encodes the destination node address / ID.

[0126] Although destination bit vectors were used previously, more generally, the disclosed method may use a destination vector that carries information about the intended recipient of the pulse packet (e.g., the intended router, node, or neuron). The destination vector may encode the destination node in bit form by setting a "0" to a "1" in the destination bit vector at the bit position corresponding to the address / ID of the particular node or router. However, other ways of encoding such information are also contemplated. For example, the destination vector may be a list of node or router addresses or IDs. The destination vector may also indicate a particular destination neuron, and the router may check whether such a destination neuron exists in the neuromorphic array core connected to the router. The destination vector may also indicate a source neuron, and each router may check whether the following neurons exist in the neuromorphic array core connected to the router that should receive the corresponding pulse data due to the excitation of such a source neuron.

[0127] Optionally, in addition to the pulse data, source node ID, and destination vector, the pulse packet may also include a next destination field, although this is not required. The value of the next destination field may be required based on a particular routing algorithm. For example, static or dynamic routing may be used, and depending on the routing algorithm, a next destination field value may be required. Therefore, although the above embodiments illustrate pulse packets with a next destination field, this value is not required for the implementation of the present invention and is merely optional.

[0128] Typically, dynamic routing can be used to account for data traffic between cores in a mesh and route packets through less busy routers. The routing algorithm then accounts for the data load on each router and updates the next destination field, for example, after each hop between routers in the mesh.

[0129] In all described embodiments, a source ID decoder may be present within the destination node. The source ID decoder decodes the source node ID information present in the pulse packet. Based on the decoded source ID, the destination node can decide which pre-synapse or group of pre-synapses will receive the incoming pulse / pulse set. A lookup table can be used to match the decoded source ID with the intended destination pre-synapse(s).

[0130] Decoding can be performed at the level of each presynapse, however this will result in a larger lookup table, thus consuming more chip area. In a preferred embodiment, the decoded source ID is matched to a specific set of presynapses. For example, each node includes 32 neurons and 128 presynapses connected to these 32 neurons. The information about which of the 32 neurons sent a pulse is encoded as pulse data, which is encapsulated in a pulse packet. After the pulse packet is routed to the destination node, the destination group of, for example, 32 presynapses can be selected by matching the decoded source node ID via a lookup table. Therefore, in this example, the destination node has four groups of 32 presynapses, which can be matched to the decoded source node ID via a lookup table. Any number of presynapses, neurons, or groups of presynapses can be used. In addition, multiple layers of neurons and synapses can be used within the same core.

[0131] Typically, for each incoming packet, the encoded pulse data in the packet can be decoded, and pre-synaptic data can be formed based on the decoded pulse data. This pre-synaptic data can then be sent to the pre-synapse in parallel (i.e., simultaneously). The incoming pulses can be digital pulses (e.g., edge detector circuits). The proposed on-chip network design is independent of whether the neuromorphic array is an analog array or a digital array. For a digital array, the pulses can be represented as bit values, and then a standard multiplier-accumulator module within the pre-synapse applies weights to the pulses.

[0132] Thus, the present invention discloses a mesh of neuromorphic array nodes, each with its own router. The present invention focuses on the routing techniques used between these routers. The inventors' overall inventive concept is to use pulse packets. These pulse packets typically include pulse data and a destination vector. The pulse packet may indicate the source node ID from which the pulse data originated. The pulse data carries pulse information about a single neuron within the source node or a group of neurons within the source node. The destination router has the information to map the pulse data to the correct portion of the neuromorphic array contained within its associated neuromorphic array core, or the pulse packet contains this information.

[0133] Any of the embodiments disclosed above may be combined in any suitable manner.

Claims

1. A method for routing pulses in a neuromorphic processor, the neuromorphic processor comprising a plurality of neuromorphic array cores, each core having an associated router, the method comprising: generating spike data representing one or more spikes generated by one or more neurons in a source neuromorphic array core among the plurality of neuromorphic array cores; generating a pulse data packet comprising the pulse data, a destination vector indicating one or more destinations for the pulse data packet, and a source identification indicating the source neuromorphic array core; sending the pulse data packets to one or more routers of the neuromorphic processor; receiving the pulse data packet in a router of a receiving neuromorphic array core among the plurality of neuromorphic array cores; Reading the destination vector of the received pulse data packet; determining, based on the destination vector, whether the receiving neuromorphic array core is a destination for the pulse data packet, and if so, sending the pulse data to the receiving neuromorphic array core; as well as Based on the destination vector, determining whether the pulse data packet has one or more other destinations besides the receiving neuromorphic array core, and if so, (a) if the receiving neuromorphic array core is indicated as a destination in the destination vector, updating the destination vector to remove the receiving neuromorphic array core as a destination for the pulse data packet; (b) determining one or more next destinations of the pulse data packet based on the destination vector and a routing algorithm of the router; as well as (c) sending the pulse data packet or a copy of the pulse data packet to one or more output ports of the router based on the determined one or more next destinations.

2. The method according to claim 1, wherein: Based on the destination vector, only one next destination of the pulse data packet is determined, and based on the determined next destination, the pulse data packet or a copy of the pulse data packet is sent to one output port.

3. The method according to claim 2, wherein: If the destination vector is updated, the updated destination vector is included in the burst data packet or a copy of the burst data packet sent to the output port.

4. The method according to claim 1, further comprising: deriving a plurality of new destination vectors from the destination vector when more than one next destination of the burst data packet is determined, wherein the destination indicated in the destination vector is divided among the plurality of new destination vectors, and Wherein each pulse data packet sent to the output port includes one of the new destination vectors.

5. The method according to any one of claims 1 to 4, wherein: The spike data contained in the spike data packet indicates which neurons in the source neuromorphic array core generated spikes within a specific time period.

6. The method according to any one of claims 1 to 5, wherein: Each pulse data packet includes timing data indicating the time period during which the pulses are generated.

7. The method according to any one of claims 1 to 6, wherein: The destination vector is a destination bit vector including a plurality of bits, each bit indicating whether a corresponding one of the neuromorphic array cores of the neuromorphic processor is a destination of the pulse data packet.

8. The method according to any one of claims 1 to 7, further comprising: If the destination vector indicates that the receiving neuromorphic array core is the destination for the pulse data packet, then based on the source identification, at least a portion of the pulse data is sent to one or more neurons in the receiving neuromorphic array core.

9. The method according to any one of claims 1 to 8, wherein: Each pulse data packet comprises, in addition to the destination bit vector, data regarding the next destination of the pulse data packet.

10. A router for routing pulses in a neuromorphic processor, the neuromorphic processor comprising a plurality of neuromorphic array cores, each core having an associated router, the router being configured to: receiving a pulse data packet including pulse data representing one or more pulses generated by one or more neurons in a source neuromorphic array core among the plurality of neuromorphic array cores and including a destination vector indicating one or more destinations of the pulse data packet and a source identification indicating the source neuromorphic array core; Reading the destination vector of the received pulse data packet; determining, based on the destination vector, whether a neuromorphic array core associated with the router is a destination for the pulse data packet, and if so, sending the pulse data to the neuromorphic array core; as well as Based on the destination vector, determining whether the pulse data packet has one or more other destinations besides the neuromorphic array core, and if so, (a) if the neuromorphic array core is indicated as a destination in the destination vector, updating the destination vector to remove the neuromorphic array core as a destination for the pulse data packet; (b) determining one or more next destinations of the pulse data packet based on the destination vector and a routing algorithm of the router; as well as (c) sending the pulse data packet or a copy of the pulse data packet to one or more output ports of the router based on the determined one or more next destinations.

11. The router according to claim 10, wherein: Based on the destination vector, only one next destination of the pulse data packet is determined, and based on the determined next destination, the pulse data packet or a copy of the pulse data packet is sent to one output port.

12. The router according to claim 11, wherein: If the destination vector is updated, the updated destination vector is included in the burst data packet or a copy of the burst data packet sent to the output port.

13. The router according to claim 10, further configured to: deriving a plurality of new destination vectors from the destination vector when more than one next destination of the burst data packet is determined, in, dividing the destinations indicated in the destination vector among the plurality of new destination vectors, and Wherein each pulse data packet sent to the output port includes one of the new destination vectors.

14. The router according to any one of claims 10 to 13, wherein: The spike data contained in the spike data packet indicates which neurons in the source neuromorphic array core generated spikes within a specific time period.

15. The router according to any one of claims 10 to 14, wherein: Each pulse data packet includes timing data indicating the time period during which the pulses are generated.

16. The router according to any one of claims 10 to 15, wherein: The destination vector is a destination bit vector including a plurality of bits, each bit indicating whether a corresponding one of the neuromorphic array cores of the neuromorphic processor is a destination of the pulse data packet.

17. The router according to any one of claims 1 to 7, further configured to: If the destination vector indicates that the receiving neuromorphic array core is the destination for the pulse data packet, then based on the source identification, at least a portion of the pulse data is sent to one or more neurons in the receiving neuromorphic array core.

18. The router according to any one of claims 10 to 17, wherein: Each pulse data packet comprises, in addition to the destination bit vector, data regarding the next destination of the pulse data packet.

19. An interconnect for multicasting pulses in a neuromorphic processor, wherein: The interconnect comprises a plurality of routers according to any one of claims 10-18 and a plurality of communication links connecting the routers.

20. A neuromorphic processor comprising a plurality of neuromorphic array cores, each neuromorphic array core comprising a spiking neural network and having an associated router, the neuromorphic processor further comprising the interconnect of claim 19, and wherein, The router is a router according to any one of claims 10-18.

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