Systems and methods for reducing noise effects on solid state quantum processors

Abstract

Systems and methods for reducing the impact of high energy radiation or charge noise on a solid state quantum processor are disclosed. According to an aspect of the present disclosure, there is provided a quantum computing system comprising: a semiconductor substrate comprising a body layer and a qubit layer; and a dielectric forming an interface with the semiconductor substrate. One or more qubits are formed in the qubit layer. The system further includes a shielding structure formed between the bulk layer and the qubit layer or between the qubit layer and the interface. The shielding structure is configured to shield the qubit layer from an electric field generated in the bulk layer due to high energy radiation or shield the qubit layer from charge noise generated in the interface.

Description

Technical Field

[0001] Aspects of the present disclosure relate generally to quantum computing, and more particularly to reducing the effects of high-energy radiation noise on solid-state quantum processors.

[0002] Other aspects of the present disclosure relate to reducing the effects of charge noise on solid-state processors. Background Art

[0003] Quantum computers perform calculations that classical supercomputers cannot run, such as efficiently factoring prime numbers or using quantum chemistry to figure out how molecules bond together. Such problems can only be solved by embedding the algorithms into large quantum computers running quantum error correction. However, error correction fails when the errors in the physical quantum bits (qubits) are large or correlated.

[0004] Quantum computers have intrinsic errors, so algorithms can be run locally, typically with only a few hundred to a few thousand logic operations. To run the most powerful and useful algorithms (e.g., with millions to billions of logic gates), errors should be reduced to the parts-per-million or parts-per-billion range, or lower. This can be achieved using quantum error correction. The basic idea of ​​quantum error correction is to redundantly encode the qubit states in many physical qubits in a manner similar to classical error correction, so that errors in the physical qubit states can be selectively measured, decoded, and corrected. For example, a surface code error correction scheme uses about 1000 physical qubits to encode a protected "logical" state. If the physical errors are small (about 0.1%) and occur randomly and independently among these 1000 qubits, the logical errors can be less than 0.1 parts per billion. However, if the errors are large or correlated, appearing together in time or together in space across the chip, error correction will fail. When the logical errors are large, the quantum computer's memory is lost and the algorithm fails.

[0005] It is therefore desirable to reduce large or correlated errors in quantum computers. Summary of the invention

[0006] According to one aspect of the present disclosure, a quantum computing system is provided, the quantum computing system comprising: a semiconductor substrate including a body layer and a qubit layer; one or more qubits formed in the qubit layer; and a shielding structure formed between the body layer and the qubit layer, the shielding structure being configured to shield the qubit layer from an electric field generated in the body layer due to high-energy radiation.

[0007] The shielding structure is also configured to recombine, absorb or extract electron-hole pairs generated in the bulk layer due to high energy radiation.

[0008] In some embodiments, the shielding structure includes a single layer of n-type semiconductor. In addition, in some examples, the n-type semiconductor is silicon doped with phosphorus. In such examples, the concentration of the dopant in the n-type semiconductor is approximately between 30% and 50%.

[0009] In some embodiments, the shielding structure has a thickness in a range of 10 nanometers to 500 nanometers.

[0010] In some other embodiments, the shielding structure comprises multiple layers of n-type semiconductor material alternating with one or more spacer layers of intrinsic silicon material. In such embodiments, the shielding structure comprises 2 to 50 layers of n-type semiconductor material. The thickness of each shielding layer is between 10 and 500 nanometers.

[0011] In some embodiments, the shielding structure further includes an electrode disposed at a bottom of the bulk layer, the electrode being negatively charged to attract holes in the electron-hole pairs.

[0012] In some other embodiments, the shielding structure further includes a metal plate disposed at the bottom of the bulk layer to attract holes in the electron-hole pairs.

[0013] According to another aspect of the present disclosure, a method for manufacturing a quantum processing device is provided. The method comprises: preparing a bulk layer of a semiconductor substrate; preparing a clean crystal surface of the bulk layer; exposing the clean crystal surface of the bulk layer to dopant molecules, thereby including a layer of dopant molecules on the exposed surface; annealing the exposed surface to remove at least one of the dopant molecules.

[0014] some dopant atoms are incorporated into the semiconductor and form a ground plane; and a qubit layer is prepared, the qubit layer being formed of isotopically inert silicon and comprising a plurality of qubits.

[0015] In some embodiments, generating the ground plane further comprises preparing a multi-layer ground plane alternating with one or more spacer layers of undoped semiconductor.

[0016] The thickness of the ground plane is 10 nanometers to 500 nanometers, and the dopant is any one of phosphorus or aluminum. In addition, the concentration of dopant atoms in the ground plane may be between 30% and 50%.

[0017] In some embodiments, the manufacturing method further comprises the step of adding a negatively charged electrode at the bottom of the bulk layer. In other embodiments, the manufacturing method may further comprise the step of providing a metal plate at the bottom of the bulk layer.

[0018] According to yet another aspect of the present disclosure, a quantum processor is provided, comprising: a semiconductor substrate including a qubit layer; a dielectric material forming an interface with the semiconductor substrate; one or more qubits formed in the qubit layer; and a shielding structure formed between the interface and the qubit layer, the shielding structure being configured to shield the qubit layer from charge noise generated in the interface between the dielectric material and the semiconductor substrate.

[0019] In some embodiments, the shielding structure comprises a single layer of n-type semiconductor. In other embodiments, the shielding structure comprises multiple layers of n-type semiconductor material alternating with one or more spacer layers of intrinsic silicon material.

[0020] The n-type semiconductor may be silicon doped with phosphorus. In some embodiments, the concentration of phosphorus in the n-type semiconductor is approximately between 30% and 50%. In addition, the thickness of the shielding structure may be in the range of 10 nanometers to 500 nanometers.

[0021] When the shield structure includes multiple layers, it may include between two and fifty layers of n-type semiconductor material and the thickness of each shield layer may be approximately 10 to 500 nanometers.

[0022] According to another aspect of the present disclosure, a method for manufacturing a quantum processing device is provided. The method includes the following steps: preparing a bulk layer of a semiconductor substrate; preparing a clean crystalline surface of the bulk layer; preparing a qubit layer, the qubit layer being formed of isotopically inert silicon and including a plurality of qubits; growing a semiconductor layer above the qubit layer; exposing the semiconductor layer to dopant molecules to generate a layer of dopant molecules on the exposed surface; annealing the exposed surface to incorporate at least some dopant atoms of the dopant molecules into the semiconductor and form a ground plane.

[0023] Generating the ground plane may further include preparing a multi-layer ground plane alternating with one or more spacer layers of undoped semiconductor. In some embodiments, the ground plane is between the qubit layer and an interface formed between the semiconductor substrate and a dielectric.

[0024] The thickness of the ground plane can be from 1 atomic monolayer up to 500 nanometers.

[0025] Further aspects of the invention and further embodiments of the aspects described in the preceding paragraphs will become apparent from the following description, which is given by way of example and with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a cross-sectional representation of a typical quantum processor.

[0027] Figure 2 is a cross-sectional representation of a quantum processing device with a ground plane to mitigate the effects of cosmic / gamma-ray events in accordance with an embodiment of the present disclosure.

[0028] Figure 3 is an example for making Figure 2 A flow chart of an example method for a quantum processing device.

[0029] Figure 4 is a cross-sectional representation of a quantum processing device with multiple ground planes according to an embodiment of the present disclosure.

[0030] Figure 5A is a cross-sectional representation of a quantum processing device having negatively charged electrodes according to some embodiments of the present disclosure.

[0031] Figure 5B is a cross-sectional representation of a quantum processing device with a metal plate according to some embodiments of the present disclosure.

[0032] Figure 6 is a cross-sectional representation of a quantum processing device with a ground plane to mitigate the effects of charge noise according to an embodiment of the present disclosure.

[0033] Figure 7 is shown for manufacturing Figure 6 A flow chart of an example method for a quantum processing device.

[0034] Figure 8 is a cross-sectional representation of a quantum processing device with multiple ground planes according to an embodiment of the present disclosure.

[0035] The accompanying drawings depict various embodiments of the present invention for purposes of illustration only. Those skilled in the art will readily recognize from the following discussion that alternative embodiments of the structures and methods shown herein may be used without departing from the principles of the invention described herein. DETAILED DESCRIPTION

[0036] Mitigating the effects of high-energy radiation

[0037] High-energy radiation, such as cosmic rays, occurs naturally when energetic particles from space strike the atmosphere, where they are converted into muon particles that penetrate deeply into all matter on the Earth's surface. The effects of high-energy radiation are well known for conventional electronic devices. In such electronic devices, radiation generates charge carriers that move through the device and alter its electrical properties, producing both temporary (impulsive) and permanent changes.

[0038] In quantum computing chips, and in particular in superconducting quantum chips, it has been found that high-energy radiation can produce large and correlated errors. When cosmic ray muons travel through superconducting quantum chips, they deposit a large amount of energy (about 200 keV) in the substrate of the superconducting quantum processor and then briefly "heat" the chip. In currently designed superconducting quantum chips, this results in a short storage time for the qubit (about 1% to 10% of the usual storage time), both spatially (across the chip) and over a longer duration (about 10ms). Therefore, the qubit errors during this event are so large and correlated that error correction stops working and the stored logical qubit state is destroyed. Since cosmic ray muons hit the quantum chip every few seconds, they will make any reasonably powerful algorithms running on superconducting quantum computers unable to run.

[0039] Some techniques have been proposed to mitigate the effects of cosmic rays on quantum chips, especially superconducting quantum chips. For example, one proposed technique is to operate a quantum computer deep underground or in a specially built laboratory. However, this is not a good commercial solution. In addition, there is always natural background radiation (from the decay of heavy elements such as uranium) to generate similar energy events, which deposit energy into the quantum chip and destroy the state of the qubit. Other technologies propose to shield the quantum chip with thick lead bricks (roughly 10 cm thick) outside the cryostat to reduce the effects of external radiation on the quantum chip and increase the coherence number of the qubit. Although this shielding technology can protect the chip from the effects of cosmic rays, it is not very useful in terms of shielding background radiation. In addition, this technology is impractical for future scalable quantum computers.

[0040] Therefore, solid-state quantum chips need to be redesigned.

[0041] The inventors of the present disclosure have discovered that, unlike superconducting qubits / processors, solid-state qubits / processors are not susceptible to phonon energy generated by background radiation events, and are not susceptible to "hot pulses" of phonon energy. In contrast, in solid-state quantum processors (such as processors fabricated using semiconductors such as silicon and / or germanium), background radiation events such as cosmic rays and gamma rays can generate electron-hole pairs in the device. Over time, these electron-hole pairs are trapped and accumulate within the semiconductor substrate, resulting in a charged background (also known as "charge offset"). The charge offset / background charge can affect the qubit (e.g., during initialization, operation, and readout) and gate operation resulting in errors in the associated qubit. This effect becomes more prominent as more and more electron-hole pairs are generated.

[0042] Furthermore, solid-state quantum chips need to be cooled at milliKelvin temperatures for their optimal operation. At such low temperatures, electron-hole pairs (or charge excursions) created by cosmic / gamma-ray events are even more problematic (compared to room temperature) because the electron-hole pairs tend to freeze because they are unlikely to move around or be able to recombine within the semiconductor substrate at such low temperatures.

[0043] Although the problem of electron-hole pair accumulation is well known for classical electronic transistors at room temperature, it has not been discussed or solved for solid-state quantum systems, and it is desirable to eliminate correlated qubit errors caused by electron-hole accumulation from solid-state quantum processors comprising a large number of qubits.

[0044] Embodiments of the present disclosure attempt to solve this problem. In particular, some embodiments of the present disclosure provide a new solid-state quantum processor chip architecture that helps reduce or eliminate the impact of cosmic rays, gamma rays or other background rays on the qubits / gates of the solid-state quantum processor.

[0045] Typically, a solid-state quantum processor includes a semiconductor substrate, such as a silicon substrate. The qubits are typically positioned / fabricated in the top portion of the semiconductor substrate. Figure 1 One such semiconductor-based quantum processing device 100 is illustrated. Device 100 includes a semiconductor substrate 102 and a dielectric 104. In this example, the semiconductor substrate is silicon 28, and the dielectric is silicon dioxide. In other embodiments, the semiconductor substrate may be natural silicon or isotopically purified silicon 28 or any other semiconductor material such as germanium. Semiconductor substrate 102 and dielectric 104 form an interface 105, which in this example is a Si / SiO2 interface. In addition, device 100 includes a plurality of qubits formed in semiconductor substrate 102 below interface 105. In this example, device 100 includes five qubits, namely, 106A to 106E. Gates 108A to 108E that control qubits 106A to 106E are fabricated on top of dielectric 104.

[0046] In the present disclosure, the portion of semiconductor substrate 102 in which qubits are formed is referred to as qubit layer 103 and the remaining portion of the semiconductor substrate is referred to as bulk layer 107. The thickness of qubit layer 103 may depend on the qubit size, the depth from interface 105 where the qubits are formed, etc. It should be understood that the layers of device 100 in this figure are not drawn to scale, and in actual implementations, the layers will have very different proportions. For example, in some examples, the ratio of semiconductor bulk layer to qubit layer may be 49:1.

[0047] Furthermore, despite Figure 11 and the remaining device diagrams in this disclosure show five qubits and five gates, but the number of qubits and gates in actual implementations may vary greatly from these numbers. In some cases, quantum processing device 100 may include tens, hundreds, or even thousands of qubits. In addition, quantum processing device 100 may be a node of a larger quantum processor that includes multiple such interconnected nodes 100.

[0048] like Figure 1 As shown, cosmic / gamma-ray events may generate electron-hole pair clusters 112 in the silicon substrate, which may cause correlated errors over time.

[0049] Typically, cosmic and gamma ray energies are in the range of about 1 MeV. When a cosmic / gamma ray event occurs in a semiconductor substrate 102 such as silicon, about 10% of the cosmic / gamma ray energy is used to generate electron-hole pairs in the silicon substrate. The generation of electron-hole pairs may require an energy of about 3.6 eV, so a cosmic ray event may generate a total of about 60,000 electron (negative charge)-hole (positive charge) pairs. These positive and negative charges are randomly distributed on the electron-hole cloud 112. If the volume of the cloud 112 is about 100 microns 3 , then the excitation density in the cloud will be about 1 excitation per 2 microns.

[0050] Therefore, the average distance between electrons and holes can be assumed to be about 1 micron. At these distances, electrons and holes can generate a voltage V given by,

[0051]

[0052] Since electrons and holes generate negative and positive voltages respectively, the sign and magnitude of the voltage increase randomly as the voltage moves further away. When the random positive and negative voltages are added, the average voltage is zero. However, the net square voltage is proportional to the number of voltages and the sum. In this example, the voltage decreases inversely proportional to the distance, and the average voltage fluctuation can be calculated as the integral of all particle voltages. In this example, the distance is approximated by a continuous distribution over a radius given by a dimensionless distance Rcloud / 2d, where Rcloud is the radius of the electron hole cloud 112.

[0053]

[0054] For the voltage, Rcloud and d values ​​discussed above, Thus, in some examples, the charge offset voltage due to a cosmic / gamma-ray event may be approximately 2.9 meV.

[0055] In general, a change in the potential of a donor atom (of a qubit) of about 50 MeV can change its charge state. The potential of the donor must be kept constant (e.g., voltage stability of 5 μeV) to maintain the charge state of the qubit. This stable value is 600 times smaller than the charge shift voltage of 2.9 MeV produced by the cosmic / gamma rate event calculated above. Therefore, this gamma or cosmic ray event will have a large effect on the qubit.

[0056] To mitigate the effects of such cosmic / gamma rays in the semiconductor substrate 102, the presently disclosed solid-state quantum device is designed such that the bulk layer 107 is shielded from the effects of cosmic / gamma rays.

[0057] By shielding the body layer 107, which is the thickest layer in the quantum processing device 100, a significant portion of the semiconductor 102 is protected. If the ratio of the body layer to the qubit layer is 49:1, approximately 98% of the semiconductor 102 can be protected from the mitigation effects of high-energy radiation. The depth of the qubit layer 103 is typically about 10 to 500 nanometers (and can be up to 1000 nanometers deep in some embodiments), and because this layer is not shielded, it may be affected by cosmic / gamma ray effects, that is, electron-hole pairs may form in this layer. However, given the thinness of this layer, the probability of a cosmic / gamma ray event occurring in the qubit layer 103 is very small. In addition, the accumulation of electron-hole pairs in this layer 103 will be limited and insufficient to generate charge offsets to cause perceptible correlated errors in the quantum processing device.

[0058] Figure 2 An example quantum processing device 200 is shown according to some embodiments of the present disclosure.

[0059] Similar to Figure 1 , the quantum processing device 200 includes a semiconductor substrate 102 and a dielectric 104. In this example, the semiconductor substrate is silicon, and the dielectric is silicon dioxide. The semiconductor substrate 102 forms an interface 105 with the dielectric 104, and the interface 105 is a Si / SiO2 interface in this example. In addition, the device 100 includes S53335233:AXD:glg formed in the semiconductor substrate 102 below the interface 105

[0060] Multiple qubits. In this example, device 100 includes five qubits, namely, 106A to 106E. It should be understood that this is merely an example, and in actual implementations, the quantum processing device may include hundreds or even thousands of qubits. In addition, any known solid-state technology may be used to form qubits. For example, qubit 106 may be a charge-based or spin-based qubit, that is, where the quantum information is encoded in the charge or spin of the qubit, respectively. Examples of such qubits include donor-based phosphorus atom qubits, silicon-MOS qubits, silicon spin qubits, ion traps, topological qubits, gate-patterned quantum dots, gate-controlled semiconductor quantum dots, and the like.

[0061] Gates 108A to 108E that control qubits 106A to 106E are fabricated on top of dielectric 104. Figure 1 , it should be understood that the layers of device 100 in this figure are not drawn to scale.

[0062] In addition, the quantum processing device 200 includes a ground plane layer 202. In some examples, the ground plane 202 can be an n-type semiconductor layer, such as an n-type silicon semiconductor doped with a group V element such as phosphorus, arsenic, or antimony. In a preferred embodiment, the ground plane 202 is formed of silicon doped with phosphorus, wherein the silicon doped with phosphorus is epitaxially fabricated on the bulk layer 107 of the silicon substrate 102.

[0063] Ground plane 202 can shield the top of silicon substrate 102 from cosmic / gamma rays from the environment / space. Generally speaking, even with ground plane 202, cosmic rays enter silicon substrate 102 from the bottom or sides of the quantum processing chip, thereby generating electron-hole pairs in the silicon substrate. However, since ground plane 202 is more conductive than the silicon substrate, it shields qubit layer 103 from any electric field generated by stationary or mobile trapped charges in bulk layer 107 and / or qubit layer 103.

[0064] In some examples, the thickness of the ground plane 202 is in the range of 10 to 50 nm.In addition, an electrical connection may be established between the ground plane 202 and an electrical ground for operating a measurement setup of the quantum processing device 200.

[0065] Figure 3 3 is a flow chart illustrating an example manufacturing process for manufacturing a quantum processing device 200. The method 300 describes a process for manufacturing a quantum processing device 200 having a qubit based on a donor atom. However, it should be understood that this is just an example and that the process can be implemented to manufacture a quantum processing device 200 having any other type of qubit 106 without departing from the scope of the present disclosure.

[0066] In step 302, the surface of the semiconductor substrate is prepared. If the substrate is silicon, this step includes forming a clean silicon substrate surface in ultra-high-vacuum (UHV) by heating to near the melting point. This surface has a 2×1 unit cell and consists of several rows of σ-bonded Si dimers, and the remaining dangling bonds on each Si atom form weak π-bonds with another Si atom of the dimer it includes.

[0067] Next, in step 304, a ground plane is formed on top of the prepared bulk layer 107. This can be done using different techniques. For example, in one example, the ground plane layer can be formed by ion implantation. In another example, the ground plane layer can be formed by diffusion. In any case, a ground plane is formed that includes a layer or blanket of metal atoms (e.g., phosphorus or aluminum). The depth of the ground plane can be anywhere between 1 atomic monolayer to 500 nanometers. In addition, the concentration of the dopant can be anywhere between 20% and 50%.

[0068] If the ground plane is silicon doped with phosphorus, phosphine (PH3) gas is introduced into the vacuum system via a controlled leak valve connected to a specially designed phosphine feed system. The phosphine molecules bind tightly to the exposed silicon 2×1 surface. Subsequently, heating of the surface causes the phosphine molecules to dissociate and causes the phosphorus atoms to be incorporated into the silicon. In some embodiments, a blanket layer of phosphorus atoms can be made in this way. Additional layers of phosphorus atoms can then be made, depending on the depth of the ground plane required. A similar process can be used to make ground planes doped with boron or aluminum.

[0069] Next, in step 306, the ground plane layer 202 is encapsulated by a silicon layer. The silicon layer can be tens of nanometers. In one example, state-of-the-art molecular beam epitaxy is used to encapsulate the ground plane 202. This step is called encapsulation.

[0070] At step 308, the surface of the packaged ground plane layer is prepared. This is similar to the process of step 302. However, this step and all subsequent surface preparation steps are performed at a lower temperature to avoid diffusion of dopants from the underlying pattern.

[0071] Thereafter, in step 310, qubits 106 are patterned into a silicon substrate. In particular, an STM tip is then used to selectively desorb H atoms from the passivated surface by applying an appropriate voltage and tunneling current, thereby forming a pattern in the H resist. In this way, areas of exposed reactive Si atoms are exposed, allowing the reactive species to be subsequently adsorbed directly onto the Si surface. Phosphine (PH3) gas is introduced into the vacuum system via a controlled leak valve connected to a specially designed phosphine microdosing system. Phosphine molecules are tightly bound to the exposed silicon 2×1 surface, passing through the holes in the hydrogen resist. Subsequently, heating of the STM patterned surface for crystal growth causes the phosphine molecules to dissociate and causes P to be incorporated into Si. Thus, the STM patterned H passivated surface is exposed to PH3, where PH3 is used to generate the desired array of donor atoms. Hydrogen can then be desorbed, followed by overgrowth with silicon at room temperature and rapid annealing of the surface. Silicon is then grown on the surface at elevated temperatures.

[0072] Thereafter, a dielectric layer may be formed on the qubit layer 103. The dielectric layer may be formed by exposing the device to ambient air or by growing the dielectric layer on top of the qubit layer. Finally, in some embodiments, a conductive gate 108 may be aligned on the surface.

[0073] In some cases, the gate may be aligned directly on the top layer of the silicon substrate of the quantum processing device 200. In this case, no dielectric layer exists between the silicon substrate and the gate.

[0074] Furthermore, it should be understood that the gate 108 need not be aligned on the surface of the device in all embodiments. In some embodiments, the gate 108 can be "in-plane" with the qubit layer 103. In this case, the gate can be patterned at step 310.

[0075] It should be understood that the thickness of the layers and the distance between the layers described in method 300 are merely exemplary. The actual thickness of the layers and the distance between the layers will depend on the qubit technology, the number of electrons, and the static magnetic field value selected for the quantum computer.

[0076] It is often difficult to create thick ground plane layers. This is because, at high concentrations of dopants, it is difficult for subsequent layers of dopant to "stick" to or bond with previous layers, since the previous layers were also doped. In addition, a highly concentrated thick ground plane may become electrically inactive if the dopant atoms are very close to each other. To address one or more of these issues, the ground plane can be segmented. Figure 4An alternative embodiment of a quantum processing system 400 is shown. In particular, in this embodiment, instead of a single ground plane 202, the shielding structure includes multiple ground plane layers 404 between the body layer 107 and the qubit layer 103. The ground plane layers (formed of n-type semiconductor) are separated by undoped semiconductor spacer layers 406.

[0077] Each ground plane can be any thickness between 10 and 500 nanometers, where 10 nanometers represents a single layer of doped silicon and 500 nanometers represents about 50 layers of doped silicon (if the dopant is phosphorus). Above each layer of ground plane, a spacer layer of undoped silicon is fabricated. The thickness of the spacer layer can also be any thickness between 10 and 500 nanometers.

[0078] exist Figure 4 In the example shown, the shield structure includes three ground plane layers 404 alternating with two spacer layers 406. However, in other examples, the number of ground plane layers and spacer layers may vary without departing from the scope of the present disclosure. For example, in one embodiment, each ground plane layer may be 10 nanometers, and the device may include 50 such ground plane layers alternating with the spacer layers. In addition, it should be understood that the thickness of each ground plane layer or the concentration of dopants in each layer need not be the same. There may be variations in the thickness of the ground plane layers and the concentration of dopants in the various ground plane layers.

[0079] Figure 5A and Figure 5B Two other variations of quantum processing systems according to embodiments of the present disclosure are shown in FIG. Figure 5A A quantum processing system 500 is shown, which includes a negatively charged electrode 502 positioned at the bottom of a bulk layer. A conductive ground plane (as a single layer (e.g. Figure 2 as shown) or as multiple layers (as Figure 3 ) shields the qubit layer from charges generated by stationary or moving charges in the bulk layer. In addition, the ground plane 202, 404 attracts electrons of electron-hole pairs from the substrate. In this example, the electrode 502 can attract holes. By including a negative electrode 502 in combination with the ground plane 202, 404, Figure 5A The device structure shown can be compared Figure 2 and Figure 4 The structure depicted in FIG. 4 absorbs / extracts electron-hole pairs faster.

[0080] exist Figure 5BIn the illustrated quantum processing system 510, the negatively charged electrode 502 is replaced by a metal plate 512 (e.g., copper, aluminum, or any other metal). In this case, since the metal plate is more conductive than the semiconductor ground plane 202, the holes are attracted toward the metal plate 512, and the background electrons of the electron-hole pairs are repelled away from the metal plate 512 and toward the ground plane 202, and are thus extracted from the substrate 202.

[0081] Although method 300 describes a method for manufacturing Figure 2 The process of the quantum processing device 200 is not disclosed, but it can be used to manufacture accordingly Figure 4 , Figure 5A and Figure 5B For example, in order to manufacture Figure 4 In the quantum processing device 400 , method step 304 is modified such that multi-layer ground planes 404 and undoped silicon layers 406 are grown alternately.

[0082] Similarly, to make Figure 5A In order to manufacture a quantum processing device 500, an additional method step may be performed at the end of method 300 to add a negatively charged electrode 502 at the bottom of the bulk layer 107. Alternatively, Figure 5B In the quantum processing device 510 , an additional method step may be performed to arrange a metal plate 512 at the bottom of the bulk layer 107 .

[0083] The above embodiments describe structures sufficient to direct the energy of muons away from the semiconductor bulk layer 107 and to shield the qubit layer from charge trapped in the bulk layer.

[0084] Mitigating the effects of charge noise on quantum computers

[0085] S53335233:AXD:glg

[0086] Charge noise is another type of noise that can cause errors in quantum computers. Charge noise is usually caused by defects at the interface 105 between the semiconductor substrate 102 and the dielectric 104. Defects at the Si / SiO2 interface 105 or in the dielectric layer 104 can be described as a bistable system called a two-level undulator (TLF). Each TLF has a unique Lorentzian spectrum. The random distribution of TLFs, all added together, leads to 1 / f noise.

[0087] Some aspects of the present disclosure attempt to solve this problem. Specifically, some embodiments of the present disclosure provide a new solid-state quantum processor chip architecture that helps reduce or eliminate the impact of charge noise on the qubit / gate of the solid-state quantum processor caused by the interface 105 between the silicon substrate 102 and the dielectric 104.

[0088] To mitigate the effects of charge in interface 105 or dielectric 104, some currently disclosed solid-state quantum devices are designed so that qubit layer 103 shields interface 105 and thus the effects of charge noise.

[0089] Figure 6 An example quantum processing device 600 is shown according to some embodiments of the present disclosure.

[0090] Similar to Figure 1 In the device 100 shown in , the quantum processing device 600 includes a semiconductor substrate 102 and a dielectric 104. In this example, the semiconductor substrate is silicon and the dielectric is silicon dioxide. The semiconductor substrate 102 and the dielectric 104 form an interface 105, which is a Si / SiO2 interface in this example. In addition, the device 600 includes a plurality of qubits formed in the semiconductor substrate 102 below the interface 105. In this example, the device 600 includes five qubits, namely, 106A to 106E. It should be understood that this is merely an example, and in actual implementations, the quantum processing device 600 may include hundreds or even thousands of qubits. In addition, any known solid-state technology may be used to form qubits. For example, the qubit 106 may be a charge-based or spin-based qubit, that is, where the quantum information is encoded in the charge or spin of the qubit, respectively. Examples of such qubits include donor-based phosphorus atom qubits, silicon-MOS qubits, silicon spin qubits, ion traps, topological qubits, gate-patterned quantum dots, gate-controlled semiconductor quantum dots, and the like.

[0091] Gates 108A to 108E that control qubits 106A to 106E are fabricated on top of dielectric 104. Figure 1 , it should be understood that the layers of device 100 in this figure are not drawn to scale.

[0092] In addition, quantum processing device 200 includes a ground plane layer 602 between qubit layer 103 and interface 105. In some examples, ground plane 602 can be an n-type semiconductor layer, such as an n-type silicon semiconductor doped with a group V element such as phosphorus, arsenic, or antimony. In a preferred embodiment, ground plane 602 is formed of phosphorus-doped silicon, wherein the phosphorus-doped silicon is epitaxially fabricated between qubit layer 103 and interface 105.

[0093] Ground plane 602 can shield qubit layer 103 from charge noise originating from interface 105 or dielectric 104. In some examples, the thickness of ground plane 602 is in the range of 10 to 50 nm. In addition, an electrical connection can be established between the ground plane and an electrical ground of a measurement setup for operating quantum processing device 600.

[0094] Figure 7 7 is a flow chart illustrating an example manufacturing process for manufacturing a quantum processing device 600. The method 700 describes a process for manufacturing a quantum processing device 600 having a qubit based on a donor atom. However, it should be understood that this is just an example and that the process can be implemented to manufacture a quantum processing device 600 having any other type of qubit 106 without departing from the scope of the present disclosure.

[0095] In step 702, the surface of the semiconductor substrate is prepared. If the substrate is silicon, this step includes forming a clean silicon substrate surface in an ultra-high-vacuum (UHV) by heating to near the melting point. This surface has a 2×1 unit cell and is composed of several rows of σ-bonded Si dimers, and the remaining dangling bonds on each Si atom form weak π-bonds with another Si atom of the dimer it includes.

[0096] Thereafter, in step 704, qubits 106 are patterned into the silicon substrate. In particular, an STM tip is then used to selectively desorb H atoms from the passivated surface by applying an appropriate voltage and tunneling current, thereby forming a pattern in the H resist. In this way, areas of exposed reactive Si atoms are exposed, allowing the active species to be subsequently adsorbed directly onto the Si surface. Phosphine (PH3) gas is introduced into the vacuum system via a controlled leak valve connected to a specially designed phosphine microdosing system. Phosphine molecules bind tightly to the exposed silicon 2×1 surface, passing through the holes in the hydrogen resist. Subsequently, heating of the STM patterned surface for crystal growth causes the phosphine molecules to dissociate and cause P to be incorporated into the Si. Thus, the STM patterned H passivated surface is exposed to PH3, where PH3 is used to generate the desired array of donor atoms. Hydrogen can then be desorbed and then overgrown with silicon at room temperature and the surface subjected to rapid S53335233:AXD:glg

[0097] Annealing. Then, silicon is grown on the surface at an elevated temperature. In some embodiments, 10 to 1000 nanometers of silicon may be grown on top of the qubit layer 103.

[0098] Next, at step 706, a ground plane 602 is formed on top of the grown silicon. This can be done using different techniques. For example, in one example, the ground plane layer 602 can be formed by ion implantation. In another example, the ground plane layer 602 can be formed by diffusion. In any case, a ground plane is formed that includes a layer or blanket of metal atoms (e.g., phosphorus or aluminum). The depth of the ground plane 602 can be anywhere between 1 atomic monolayer to 500 nanometers. In addition, the concentration of the dopant can be anywhere between 20% and 50%.

[0099] If the ground plane 602 is silicon doped with phosphorus, phosphine (PH3) gas is introduced into the vacuum system via a controlled leak valve connected to a specially designed phosphine feed system. The phosphine molecules bind tightly to the exposed silicon 2×1 surface. Subsequently, heating of the surface causes the phosphine molecules to dissociate and causes the phosphorus atoms to be incorporated into the silicon. In some embodiments, a blanket layer of phosphorus atoms can be made in this way. Additional layers of phosphorus atoms can then be made, depending on the depth of the ground plane 602 required. A similar process can be used to make ground planes doped with boron or aluminum.

[0100] Next, in step 708, the ground plane layer 202 is encapsulated by a silicon layer. The silicon layer can be tens of nanometers. In one example, state-of-the-art molecular beam epitaxy is used to encapsulate the ground plane 202. This step is called encapsulation.

[0101] At step 710, the surface of the packaged ground plane layer is prepared. This is similar to the process of step 702. However, this step and all subsequent surface preparation steps are performed at a lower temperature to avoid diffusion of dopants from the underlying pattern.

[0102] Thereafter, a dielectric layer may be formed on the qubit layer 103. The dielectric layer may be formed by exposing the device to ambient air or by growing the dielectric layer on top of the qubit layer. Finally, in some embodiments, a conductive gate 108 may be aligned on the surface.

[0103] In some cases, the gate may be aligned directly on the top layer of the silicon substrate of the quantum processing device 200. In this case, no dielectric layer exists between the silicon substrate and the gate.

[0104] Furthermore, it should be understood that gate 108 need not be aligned on the surface of the device in all embodiments. In some embodiments, gate 108 may be "in-plane" with qubit layer 103. In this case, the gate may be patterned at step 704 when qubit layer 103 is formed.

[0105] The thickness of the layers and the distance between the layers described in method 700 are merely exemplary. The actual thickness of the layers and the distance between the layers will depend on the qubit technology, the number of electrons, and the static magnetic field value selected for the quantum computer.

[0106] It is often difficult to create thick ground plane layers. This is because, at high concentrations of dopants, it is difficult for subsequent layers of dopant to "stick" to or bond with previous layers, since the previous layers were also doped. In addition, a highly concentrated thick ground plane may become electrically inactive if the dopant atoms are very close to each other. To address one or more of these issues, the ground plane can be segmented. Figure 8 An alternative embodiment of a quantum processing system 800 is shown. In particular, in this embodiment, instead of a single ground plane 602, the shielding structure includes multiple ground plane layers 804 between the qubit layer 103 and the interface 105. The ground plane layers (formed of n-type semiconductor) are separated by undoped semiconductor spacer layers 806.

[0107] Each ground plane can be any thickness between 10 and 500 nanometers, where 10 nanometers represents a single layer of doped silicon and 500 nanometers represents about 50 layers of doped silicon (if the dopant is phosphorus). Above each layer of ground plane, a spacer layer of undoped silicon is fabricated. The thickness of the spacer layer can also be any thickness between 10 and 500 nanometers.

[0108] exist Figure 8 In the example shown, the shield structure includes three ground plane layers 804 alternating with two spacer layers 806. However, in other examples, the number of ground plane layers and spacer layers may vary without departing from the scope of the present disclosure. For example, in one embodiment, each ground plane layer may be 10 nanometers, and the device may include 50 such ground plane layers alternating with the spacer layers. In addition, it should be understood that the thickness of each ground plane layer or the concentration of dopants in each layer need not be the same. There may be variations in the thickness of the ground plane layers and the concentration of dopants in the various ground plane layers.

[0109] Although method 700 describes a method for manufacturing Figure 6 The process of quantum processing device 600, but it can be used to manufacture Figure 8 For example, in order to manufacture Figure 8 In the quantum processing device 800 , method step 706 is modified such that multiple layers of ground plane 804 are grown alternately with undoped silicon layers 806 .

[0110] The above embodiments describe structures that shield the qubit layer 103 from the charge noise of the interface. This allows the qubit layer to be fabricated closer to the interface 105 and the qubit layer 103 no longer needs to be buried deep in the semiconductor substrate (e.g., hundreds of nanometers). S53335233:AXD:glg

[0111] Although this specification includes many specific details of implementation, these should not be construed to limit the scope of any invention or what may be claimed, but rather serve as descriptions of features specific to a particular embodiment. Certain features described in this specification in the context of a particular embodiment may also be implemented in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented in multiple embodiments, either individually or in any combination.

[0112] The foregoing description of the embodiments of the present invention is presented for illustrative purposes only and is not intended to be exhaustive or to limit the invention to the precise forms disclosed. It will be appreciated by those skilled in the art that many modifications and variations are possible in light of the above disclosure.

[0113] Finally, the language used in the specification has been selected primarily for readability and teaching purposes, and may not be selected to describe or limit the inventive subject matter. Therefore, it is intended that the scope of the present invention is not limited by this detailed description, but by any claims published based on the application herein. Therefore, the disclosure of the embodiments of the present invention is intended to illustrate rather than limit the scope of the present invention, and the scope of the present invention is set forth in the appended claims.

[0114] As used herein, unless the context requires otherwise, the term, "comprise" and variations such as "include", "contain" and "have", are not intended to exclude other additions, components, integers or steps.

Claims

1. A quantum processing device, comprising: a semiconductor substrate, including a bulk layer and a qubit layer; one or more qubits formed in the qubit layer; as well as A shielding structure is formed between the bulk layer and the qubit layer, the shielding structure being configured to shield the qubit layer from an electric field generated in the bulk layer due to high energy radiation.

2. The quantum processing device according to claim 1, wherein: The shielding structure is further configured to recombine, absorb or extract electron-hole pairs generated in the bulk layer due to high energy radiation.

3. The quantum processing device according to claim 1, wherein: The shielding structure includes a single layer of n-type semiconductor.

4. The quantum processing device according to claim 3, wherein: The n-type semiconductor is silicon doped with phosphorus.

5. The quantum processing device according to claim 4, wherein: The concentration of phosphorus in the n-type semiconductor is approximately between 30% and 50%.

6. The quantum processing device according to any one of claims 1 to 5, wherein: The shielding structure has a thickness in a range of 10 nanometers to 500 nanometers.

7. The quantum processing device according to any one of claims 1 to 2, wherein: The shielding structure includes multiple layers of n-type semiconductor material alternating with one or more spacer layers of intrinsic silicon material.

8. The quantum processing device according to claim 7, wherein: The shielding structure includes 2 to 50 layers of n-type semiconductor material.

9. The quantum processing device according to claim 8, wherein: The thickness of each shielding layer is about 10 to 500 nanometers.

10. A quantum processing device according to any one of the preceding claims, wherein: The shielding structure further includes an electrode disposed at the bottom of the bulk layer, the electrode being negatively charged to attract holes of the electron-hole pairs.

11. The quantum processing device according to any one of claims 1 to 9, wherein: The shielding structure further includes a metal plate disposed at the bottom of the bulk layer to attract holes of the electron-hole pairs.

12. A method for manufacturing a quantum processing device, comprising the steps of: preparing a bulk layer of a semiconductor substrate; preparing a clean crystalline surface of the bulk layer; exposing the clean crystalline surface of the bulk layer to dopant molecules to produce a layer of dopant molecules on the exposed surface; annealing the surface to incorporate at least some of the dopant atoms of the dopant molecules into the semiconductor and form a ground plane; and A qubit layer is prepared, the qubit layer being formed of isotopically inert silicon and comprising a plurality of qubits.

13. The method according to claim 12, wherein: Generating the ground plane further comprises: S53335233:AXD:glg A multi-layer ground plane is prepared alternating with one or more spacer layers of undoped semiconductor.

14. The method according to claim 12 or 13, wherein: The ground plane is between the bulk layer and the qubit layer.

15. The method according to any one of claims 12 to 14, wherein: The thickness of the ground plane is from 1 atomic monolayer to 500 nanometers.

16. The method according to any one of claims 12 to 15, wherein: The dopant is any one of phosphorus and aluminum.

17. The method according to any one of claims 12 to 16, wherein: The concentration of dopants in the ground plane is substantially between 20% and 50%.

18. The method according to any one of claims 12 to 17, further comprising the steps of: A negatively charged electrode is added at the bottom of the body layer.

19. The method according to any one of claims 12 to 17, further comprising the steps of: A metal plate is provided at the bottom of the bulk layer.

20. A quantum processor comprising: a semiconductor substrate including a qubit layer; a dielectric material forming an interface with the semiconductor substrate; one or more qubits formed in the qubit layer; as well as A shielding structure is formed between the interface and the qubit layer, the shielding structure being configured to shield the qubit layer from charge noise generated in the interface between the dielectric material and the semiconductor substrate.

21. A quantum processor according to claim 20, wherein: The shielding structure includes a single layer of n-type semiconductor.

22. A quantum processor according to claim 21, wherein: The n-type semiconductor is silicon doped with phosphorus.

23. A quantum processor according to claim 22, wherein: The concentration of phosphorus in the n-type semiconductor is approximately 30% to 50%.

24. A quantum processor according to any one of claims 20 to 23, wherein: The shielding structure has a thickness in a range of 10 nanometers to 500 nanometers.

25. The quantum processor of claim 20, wherein: The shielding structure includes multiple layers of n-type semiconductor material alternating with one or more spacer layers of intrinsic silicon material.

26. A quantum processor according to claim 25, wherein: The shielding structure includes two to fifty layers of n-type semiconductor material.

27. A quantum processor according to any one of claims 25 to 26, wherein: The thickness of each shielding layer is about 10 to 500 nanometers.

28. A method for manufacturing a quantum processing device, comprising the steps of: preparing a bulk layer of a semiconductor substrate; S53335233:AXD:glg preparing a clean crystalline surface of the bulk layer; preparing a qubit layer formed of isotopically inert silicon and comprising a plurality of qubits; growing a semiconductor layer over the qubit layer; exposing the semiconductor layer to dopant molecules to produce a layer of dopant molecules on the exposed surface; The exposed surface is annealed to incorporate at least some of the dopant atoms of the dopant molecules into the semiconductor and form a ground plane.

29. The method according to claim 28, wherein: Generating the ground plane further comprises: A multi-layer ground plane is prepared alternating with one or more spacer layers of undoped semiconductor.

30. The method according to claim 28 or 29, wherein: The ground plane is between the qubit layer and an interface formed between the semiconductor substrate and a dielectric.

31. The method according to any one of claims 28 to 30, wherein: The thickness of the ground plane is from 1 atomic monolayer to 500 nanometers.

32. The method according to any one of claims 28 to 31, wherein: The dopant is any one of phosphorus and aluminum.

33. The method according to any one of claims 28 to 32, wherein: The concentration of dopants in the ground plane is substantially between 20% and 50%.

Images