Dynamic random access memory with interleaved refresh

Abstract

A memory includes local control circuitry that manages refresh transactions using a set of sense amplifiers separate from the sense amplifiers used for access (read and write) transactions. The local control circuitry interrupts refresh transactions to prioritize access requests to provide improved memory performance. The local control circuitry also divides the refresh transaction into stages and periods based on whether the refresh transaction needs to access bit lines for read and write accesses. This partitioning allows local control circuitry to interleave and interrupt refresh transactions from access transactions in a manner that minimizes access disturbances.

Description

Background Art

[0001] Dynamic random access memory (DRAM) is a type of semiconductor memory in which an array of memory cells stores digital values ​​as voltage levels. The memory cell includes a capacitor that can be charged or discharged to represent a "bit", i.e., a logical 1 or 0. The capacitor can be selectively connected to a "bit line" so that a relatively high voltage across the capacitor when charged can be sensed to read the stored bit. The charge on the capacitor leaks and must therefore be refreshed periodically to prevent loss of stored data. A refresh transaction senses the voltage across the capacitor of the memory cell, interprets the bit value represented thereby, and writes that value back to the capacitor as the full refresh cell voltage. Refresh transactions interfere with access transactions and thereby limit the sustained bandwidth of the DRAM. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Figure 1 A memory system 100 is depicted in which a host controller 105 provides access to a DRAM 110 via a communication channel 115 that transmits access requests (eg, read and write requests) RQ and data DQ.

[0003] Figure 2 is a flow chart 200 illustrating a refresh transaction according to one embodiment.

[0004] Figure 3 Schematically showing a method according to an embodiment Figure 1 A portion of DRAM 110 .

[0005] Figure 4 is a waveform diagram 400 illustrating voltage levels for a read access transaction using access sense amplifier 135a, which uses the same Figure 3 The signal name corresponding to the node.

[0006] Figure 5 5 is a waveform diagram 500 illustrating voltage levels for a refresh transaction using refresh sense amplifier 135r.

[0007] Figure 6 A pair of waveform diagrams 600 and 605 are included, each waveform diagram illustrating how refresh phase 2 is interrupted to service an access transaction.

[0008] Figure 7 Flowcharts 700 and 705 are depicted, illustrating refresh phases 1 and 2, respectively.

[0009] Figure 8 Three timing diagrams 800, 805, and 810 are depicted, illustrating how refresh phase 1 schedules bit line usage to periods when read and write transactions do not require them.

[0010] Fig. 9 A sense amplifier pair 900 is depicted according to another embodiment. DETAILED DESCRIPTION

[0011] A memory system includes a host controller that issues access requests to a dynamic random access memory (DRAM) and a local controller that generates refresh requests. The access request from the host controller initiates an access transaction for data reading and writing. The access request includes a precharge request for a storage body that prepares a memory cell for access, an activation request for opening a memory cell row for access, a read request for initiating data reading from an opened memory cell row, and a write request for initiating data writing to an opened row. The local control circuit system initiates a refresh transaction asynchronously with the access request from the host. The local control circuit system divides the refresh transaction into phases and periods that are interleaved with the access transaction and interrupted by the access transaction to minimize access interference and thereby provide improved memory performance. The first phase of the refresh transaction senses and stores a bit value from a memory cell; the second phase restores the value to the cell. The first phase is divided into periods based on whether the refresh transaction requires a bit line access. The period of bit line use is time-shifted and interleaved with access transactions that require the same bit line to read or write data so as not to interfere with access. The access transaction interrupts the second phase so that the local control circuit system attempts cell recovery later when one or more access transactions are completed.

[0012] Figure 1 A memory system 100 is depicted in which a host controller 105 provides access to a DRAM 110 (i.e., a memory device) via a communication channel 115 that transmits access requests (e.g., precharge, activate, read, and write requests) RQ and data DQ. The DRAM 110 includes memory array tiles (MATs) 116t and 116c, each block being an array having rows and columns of memory cells 120. The local control circuitry 125 responds to the request RQ by issuing control signals RAt and RAc to respective row logic 130t and 130c that selectively assert signals on word lines WLt[N:0] and WLc[N:0] to "turn on" the row of memory cells 120 to make the memory cell voltages stored therein available on respective bit lines BLt[M:0] and BLc[M:0] to be sensed by the sense amplifier 135a and 135r stripes. The input / output (I / O) circuit 143a strip communicates data via complementary signals LDOt and LDOc on like-named signal paths with the local control circuitry 125. The local control circuitry 125 services access requests using access sense amplifiers 135a ("a" for "access") and services refresh requests using a separate set of refresh sense amplifiers 135r ("r" for "refresh").

[0013] The local control circuitry 125 includes a request interface 136 that receives and interprets requests from the host controller 105, a resource replacement register 137 that maps addresses of defective memory resources to redundant resources, a refresh open register 138 that maintains a list of incomplete (open) refresh transactions, a counter 139 that includes the addresses of rows to be refreshed, and a timer 140 that increments the counter to step through the rows. The functions of these elements are detailed below.

[0014] The host controller 105 and the memory device 110 are integrated circuit (IC) devices, commonly referred to as "chips". The host controller 105 can be a separate, independent chip or integrated into another chip. For example, the memory controller can be included on a single tube core with a microprocessor, or as part of a more complex system (such as a system on a chip (SOC)). The DRAM 110 includes storage banks / sub-storage banks of memory array slices (MATs) 116, but only two are shown for ease of illustration. Other elements that are not necessary for understanding the operation of the system 100 are also omitted. The upper and lower MATS are labeled 116t and 116c, respectively, with "t" and "c" representing "true" and "complementary", respectively. Cells or arrays are not permanently true or complementary; instead, a "true" cell or array refers to the cell or array read from or written to it, and the complement of the same element used as a reference.

[0015] Figure 2 2 is a flow chart 200 illustrating a refresh transaction according to one embodiment. The timer 140 is incremented periodically, causing the refresh counter 139 to initiate a refresh transaction. The local control circuit system 125 begins refresh phase 1 (Ph1) by evaluating the address of the refresh request. The establishment period P1r (standing for "period 1, refresh") does not require bit line access and therefore does not interfere with any ongoing access transactions. The request interface 136 checks the resource replacement register 137 to find the requested address and, if necessary, performs address replacement on redundant resources. The local control circuit system 125 then signals the master word line to fall MWF (not shown), which initiates the assertion of the word line signal WL0t to open the selected memory cell 120.

[0016] According to decision 210, if there is an ongoing access transaction using the bit lines required by the refresh request, local control circuitry 125 completes the activity of refresh period P1r and waits for completion of the ongoing access (215). If there is no ongoing access transaction, local control circuitry 125 enters refresh phase 1, period 2 (Ph1, P2r) and senses the memory cells identified during setup period P1r. Figure 13P3r, the refresh sense transistor 135r is allowed to amplify the sense difference between the voltages on the bit lines BL0t and BL0c.

[0017] The sensing action destroys the data from the memory cell and retains the sensed value in the refresh sense amplifier 135r, thereby completing the first phase Ph1 of the refresh transaction. According to decision 220, if the local control circuit system 125 receives an access request during the signal development period P3r, the local control circuit system 125 interrupts the refresh transaction to tend to the access request. The local control circuit system 125 evaluates the access request to determine whether the register 138 indicates that the target address is the subject of an open refresh transaction. Write accesses to the address listed in the register 138 proceed normally, and the target address is removed from the register 138. For read accesses to the memory cell undergoing a refresh transaction, the local control circuit system 125 reads the value stored in the refresh sense amplifier 135r, and the register 138 holds the open address. For another memory cell connected to the same bit line, the local control circuit system 125 begins an access setup period P1a (meaning "period 1, access"), during which the access request is evaluated and the bit line is equalized. In the second period P2a (access sensing period), the local control circuit system 125 asserts the word line signal (e.g., WL1t) and connects the access sense amplifier 135a to the bit lines BL0t and BL0c to allow the access sense transistor 135a to sense the bit voltage representing the stored value. In the amplification period P3a, the local control circuit system 125 disconnects the access sense amplifier 135a from the bit line and allows the sense signal to develop in the access sense transistor. Once the signal is amplified, the local control circuit system 125 enters a recovery period P4a, in which it reconnects the access sense amplifier 135a to the bit lines BL0t and BL0c and turns on the requested word line to restore the voltage in the accessed memory cell. The local control circuit system 125 also reads the accessed data using the corresponding I / O circuit 143a to make the data available to the requesting host. With the access complete, local control circuitry 125 issues control signal CNTRa which disconnects access sense amplifier 135a from the bit line and thereby allows refresh phase 2Ph2 value recovery to occur. The period of a write transaction differs from that of a read transaction because data does not need to be read from the target memory cell.

[0018] Returning to decision 220, if no access request is received during phase 1Ph1, the refresh transaction is allowed to continue normally (225). Interrupting phase 1Ph1 during sensing period P2r does not interfere with sensing because the refresh sensing operation has time to complete during setup phase P1a of the access transaction, during which the access sense amplifier 135a is decoupled from the bit line. Interrupting the refresh transaction during signal development P3r does not interfere with phase 1 of the refresh transaction because signal development does not require refresh sense amplifier 135r to couple to the bit line.

[0019] However, the process reaches refresh phase 2Ph2, where refresh sense amplifier 135r is reconnected to bit lines BL0t and BL0c, and word line WL0t is reasserted to turn on the memory cell and restore its contents (230). Bit lines BL0t and BL0c are again equalized (235), thereby ending the refresh transaction (240). The act of setting the bit line voltage to a common voltage between the high and low supply voltages is often referred to as "precharging," and prepares the bit lines for the next access.

[0020] Figure 3 Schematically showing a method according to an embodiment Figure 1 1. A portion of a DRAM 110 of the present invention, with like identified elements being the same or similar. In this example, the access sense amplifier 135a and the refresh sense amplifier 135r are identical, and both are selectively coupled between complementary bit lines BL0t and BL0c. Each sense amplifier detects and amplifies the voltage difference between the bit lines BL0t and BL0c when one of the word lines WL0t and WL0c is asserted to discharge the capacitor 300 onto the corresponding bit line through transistor 305, with the other line used as a reference. In this example, the bit line BL0t is used to read the contents of the leftmost memory cell 120 relative to the reference bit line BL0c. An optional I / O circuit 143r may be included to read the contents of the refresh sense amplifier 135r and thereby facilitate read access to the open word lines.

[0021] The access sense amplifier 135a includes a pair of cross-coupled inverters that are enabled by the evaluation control block 315. The cross-coupled inverters include an n-channel field effect transistor (NFET) on the left and a p-channel field effect transistor (PFET) on the right. The top NFET / PFET pair forms a first inverter that is cross-coupled to a second inverter formed using the bottom pair. When the local control circuit system 125 asserts the corresponding control signals NSETa and / PSETa, the negative supply voltage SANa and the positive supply voltage SAPa are selectively provided to the inverters, both of which are Figure 1135a. The signals NSETa and / PSETa are deasserted, and the signal EQL is asserted, to allow the bit line equalization block 320 to equalize the voltage levels on the bit lines BLt and BLc between sensing operations. The power equalization block 325a also equalizes the power lines SANa and SAPa to a common intermediate voltage VBLEQ between sensing operations. The I / O circuit 143a allows the local control circuit system 125 to shift the complementary data signals LDOt / LDOc into and out of the bit lines BLt / BLc during write and read accesses, respectively, by asserting the control signal CSLa. Each control node and signal that accesses the sense amplifier 135a is indicated by a tail "a" to indicate "access". Similarly, the control nodes and signals that refresh the sense amplifier 135r are indicated by a tail "r" to indicate "refresh". Signals with a leading " / " are active low, which means that they are asserted / deasserted to a relatively lower / higher voltage.

[0022] In the access sense amplifier 135a, the evaluation control block 315a receives the offset cancellation signal OCa and the isolation signal ISOa from the local control circuit system 125. The term "offset" refers to the characteristic differences between the components of the access sense amplifier 135a, which can cause the amplifier to be unbalanced and thus produce sensing errors. The assertion signal OCa connects the internal bit line nodes iBLt and iBLc to the external bit lines BL0c and BL0t, and the opposite connection is adopted when the isolation signal ISOa is asserted to sense the voltage difference between the bit lines BL0t and BL0c. The assertion signal OCa briefly senses the characteristic offset to apply a corresponding voltage offset between the bit lines BL0t and BL0c, thereby offsetting the effect of the characteristic offset when the signal ISOa is asserted. Deasserting both the OCa and ISOa signals disconnects the access sense amplifier 135a from the bit lines BL0t and BL0c. The refresh sense amplifier 135r is similarly controlled to sense and amplify the voltage difference between the bit lines BL0t and BL0c during refresh phase 1.

[0023] Refresh sense amplifier 135r can be read after refresh phase 1 to satisfy a read request to open the word line. In one embodiment, local control circuit system 125 instructs refresh I / O circuit 143r to read the contents of refresh sense amplifier 135r. In the case of access during refresh phase 2, an activation command opens the word line or keeps the word line open, and local control circuit system 125 uses refresh sense amplifier 135r and associated I / O circuit 143r instead of access sense amplifier 135a and I / O circuit 143a. A precharge command restores memory cell 120 from refresh sense amplifier 135r. Another embodiment omits I / O circuit 143r; instead, an activation command ACT opens the word line or keeps the word line open, and local control circuit system 125 copies data from refresh sense amplifier 135r to access sense amplifier 135a via bit lines BL0t and BL0c before reading from or writing to sense amplifier 135a. To replicate between the sense amplifiers, isolation signals ISOa and ISOr are both asserted simultaneously, while signals NSETa and / PSETa are deasserted. Refresh sense amplifier 135r drives bit lines BL0t and BLoc apart to create a voltage difference across internal bit lines iBLt and iBLc of access sense amplifier 135a. Signals NSETa and / PSETa are asserted after a short delay to drive internal bit lines iBLt and iBLc of access sense amplifier 135a to the value on the same node of refresh sense amplifier 135r. Thereafter, access begins from access sense amplifier 135a as previously described. Refresh phase 2 can be aborted and the address of the open word line removed from register 138 because the affected memory cells are written by access sense amplifier 135a as part of the ongoing access transaction.

[0024] If an access to a word line interrupts the setup period P1r of refresh phase 1 for the same word line, the setup period is aborted and the refresh transaction is replaced by the requested access transaction. The access transaction recovers or overwrites the affected memory cells and thereby avoids the refresh transaction. However, if the access interrupts the sensing period P2r of refresh phase 1, the refresh transaction ends refresh phase 1 early by omitting the word line closing and equalization steps.

[0025] Figure 4 is a waveform diagram 400 illustrating voltage levels for a read access transaction using access sense amplifier 135a, which uses the same Figure 3Signal Vc refers to the memory cell voltage across capacitor 300, which represents the stored binary value; signals iBLt and iBLc represent the voltage levels on the complementary input nodes of amplifier 135a, which can be isolated from bit lines BL0t and BL0c via control block 315, and signal WL0t represents the raised (asserted) word line voltage to make Figure 3 The transistor 305 in the memory cell 120 on the left is able to share the charge stored on the corresponding capacitor 300 with the bit line BL0t. The voltage Vc across the capacitor 300 is proportional to the stored charge. When the capacitor 300 is connected to the bit line BL0t, the resulting charge sharing has little effect on the bit line voltage compared to the initial stored voltage. The access sense amplifier 135a senses and amplifies the bit line voltage to recover the stored bit.

[0026] The labels along the timeline summarize the various periods of read access transactions. Figure 1 In the memory system 100, the host controller 105 initiates a transaction by issuing a read request or a read command to the local control circuit system 125. In response, the local control circuit system indicates that the control signal CNTRa is Figure 4 Manage transactions as shown.

[0027] Back to Figure 1 , the local control circuit system 125 decodes the command (CD=Command Decode) to determine the type and address of the access. This address allows the local control circuit system 125 to select the bank of memory cells (BS=Bank Select) and to perform a redundancy evaluation RE, by which the local control circuit system 125 can map the request from the defective memory resource to the redundant resource provided for this purpose. The local control circuit system 125 then signals the main word line fall MWF (not shown), which initiates the assertion of the word line signal WL0t to read the selected memory cell 120.

[0028] Before the word line signal WL0t is asserted, the sense amplifier 135a is powered on by the assertion of the signals / PSETa and NSETa, and the offset compensation signal OCa is asserted, thereby driving the voltage on the internal bit line nodes iBLt and iBLc to a degree determined by the inherent imbalance of the sense amplifier 135a. Then, / PSETa, NSETa and OCa are deasserted. Then, the word line signal WL0 is asserted to initiate charge sharing CS, in which the capacitor 300 is discharged to the bit line BL0t, causing the voltage Vc to drop and the voltage on the bit line BL0t to rise. Although not shown, the signal ISOa is also asserted, so the voltage on the bit lines BL0t and BL0c is transferred to the nodes iBLt and iBLc for sensing. Next, in the signal development SD, the isolation signal ISO is deasserted to isolate the amplifier 135a from the bit lines BL0t and BL0c. The amplifier 135a then amplifies the relatively small voltage difference between the nodes iBLt and iBLc. Although not shown, local control circuitry 125 may read data via I / O circuit 143a.

[0029] Charge recovery is performed using word line signal WL0t and asserted signal ISOa, so amplifier 135a charges capacitor 300 to the recovery level. Once recovered, the word line is closed (WLC), and equalization blocks 320 and 325a are used to equalize the power supply nodes of the bit line and amplifier 135a to prepare for the next access. As shown in the key in the lower left corner, during certain periods of the read transaction, amplifier 135a is disconnected from bit lines BL0t and BL0c. These periods can be used for refresh transactions that require access to the same bit line. If this is a write transaction, the sensing and amplification periods will be omitted, and a new bit will be presented across the bit line via I / O circuit 143a to store it in the target memory cell.

[0030] Figure 5 5 is a waveform diagram 500 illustrating the voltage levels of a refresh transaction using a refresh sense amplifier 135r. Diagram 500 divides the refresh transaction into two phases: in the first phase, amplifier 135r senses the value from the memory cell, and in the second phase, amplifier 135 restores the sensed value to the memory cell. The first phase is further divided into (multiple) time periods based on whether the operation performed requires access to bit lines BL0t and BL0c. Phase and time period division allows refresh transactions to be interleaved with access transactions and interrupted by access transactions. Access requests from the host controller 105 can and are likely to arrive asynchronously with respect to refresh transactions generated internally by the local control circuit system 125. In this case, "asynchronous" refers to the start of access and refresh transactions, not the timing of the signal relative to the clock signal.

[0031] refer to Figure 1, the local control circuit system 125 initiates a refresh transaction for a given word line, that is, the memory cell 120 under the control of the word line, and the refresh command RC specifies the address in the memory body that is specific to the word line. The local control circuit system 125 performs a redundancy evaluation RE and issues a signal master word line down MWF, as described above in conjunction with Figure 4 As described. During this setup period of refresh phase 1, the voltages depicted remain substantially constant and the internal nodes iBLt and iBLc within amplifier 135r are isolated from the bit lines BL0t and BL0c. During this period, bit line equalization following a previous access can be completed. The internal bit line nodes iBLt and iBLc for refreshing sense amplifier 135r are not shown, but they are substantially the same as those for accessing sense amplifier 135a.

[0032] Before the word line signal WL0t is asserted, the sense amplifier 135r is powered by the assertion of the signals / PSETr and NSETr, and the offset compensation signal OCr is asserted, thereby driving the voltages on the bit lines BLt and BLc to a degree determined by the inherent imbalance of the sense amplifier 135r. Then, / PSETa, NSETa, and OCa are deasserted. The word line signal WL0t is then asserted to initiate a charge sharing and word line closing period CS+WLC, during which the capacitor 300 is discharged onto the bit line BL0t, causing the voltage Vc to drop, and the voltage on the bit line BL0t to rise relative to the voltage on the bit line BL0c. Although not shown, during this bit line sensing period, the signal ISOr is also asserted, so the voltages on the bit lines BL0t and BL0c are transferred to the internal bit line nodes of the refresh sense amplifier 135r for sensing. In the last period of refresh phase 1, the amplification isolation signal ISOr is deasserted to isolate the amplifier 135r from the bit lines BL0t and BL0c. Amplifier 135r then amplifies the relatively small voltage difference and maintains the amplified value while local control circuitry 125 equalizes bit lines BL0t and BL0c in preparation for a subsequent refresh phase 2 or access transaction.

[0033] Refresh phase 2 is shown below on a word line close operation WLC from a previous read or write access, which causes the bit lines BL0t and BL0c to be high and low, respectively, which is opposite to the values ​​held in the refresh sense amplifier 135r obtained in refresh phase 1. The local control circuit system opens the word line (asserts signal WL0t) to provide access to the capacitor 300 of the target memory cell, and asserts signal ISOr to connect the internal bit line node of amplifier 135r to the bit lines BL0t and BL0c, thereby allowing amplifier 135r to restore the refresh voltage representing the stored value to the memory cell during the charge refresh CR period. The local control circuit system 125 then closes the word line and equalizes the bit line and power supply terminals in the refresh sense amplifier 135r to prepare for the next transaction.

[0034] During refresh phase 2, refresh sense amplifier 135r needs to access bit lines BL0t and BL0c. However, phase 2 can be interrupted without loss of data because the refreshed value is retained in refresh sense amplifier 135r until the end of phase 2. Local control circuitry 125 takes advantage of the interruptibility of refresh phase 2 to prioritize read and write access.

[0035] Figure 6 A pair of waveform diagrams 600 and 605 are included, each of which illustrates how refresh phase 2 is interrupted to service an access transaction. These phases are similar in operation to Figure 5 600, the local control circuitry 125 interrupts refreshing the sense amplifier 135r early in the charge recovery period CR, designated as / CR, before closing the word line (WLC) and equilibrating the bit lines in preparation for the requested access. This early closing of refresh phase 2 may be done during the setup period of the requested access. Diagram 605 is similar to diagram 600, but the refresh interrupt occurs later in the charge recovery period.

[0036] Figure 7 Flowcharts 700 and 705 are depicted, which illustrate refresh phases 1 and 2, respectively, according to another embodiment. The process shown is performed by the local control circuitry 125 in the manner described above to refresh the sense amplifiers 135r and Figure 3 The refresh transactions can be scheduled using a variety of strategies, a subset of which are detailed in this article.

[0037] The process begins, starting with refresh phase 1, when the local control circuitry 125 generates a refresh request (705) for a particular word line, which indicates that all memory cells 120 connected to the particular word line are to be read and their contents restored to the full voltage representing their stored values. The refresh request initiates a setup period 710. Based on decisions 715 and 720, if there are no read or write accesses in progress and the access request does not interrupt the setup period, phase 1 continues with the sensing and amplification period (725 and 730), thereby ending phase 1.

[0038] Returning to decision 715, if an access is ongoing when refresh setup begins, the local control circuit system 125 determines whether the access is being closed (decision 735). If so, the setup period does not have time to complete for the subsequent sensing period 725 to be inserted into the access setup period of the subsequent access transaction (during which the sensing period 725 does not interfere with the access transaction). Therefore, before transitioning to the sensing period 725, the local control circuit system 125 waits for the next closing period (step 740). According to decision 720, if the access request interrupts the refresh setup period started in 710, the local control circuit system 125 also waits for the next closing. During the sensing period 725, the bit lines BL0t and BL0c are connected to the internal nodes iBLt and iBLc of the refresh sense amplifier 135r. The amplification period 730 does not require the amplifier 135r to be connected to the bit lines BL0t and BL0c, and can overlap with the word line closing and equalization periods of the access transaction.

[0039] Flowchart 705 illustrates a process implemented by local control circuitry 125 for refresh phase 2, which recovers memory cells using the contents of refresh sense amplifiers 135r acquired during refresh phase 1. Local control circuitry 125 tracks incomplete refresh transactions and issues phase 2 commands to complete them. A protocol for ensuring that refresh commands are scheduled and completed in a timely manner to avoid data loss is discussed below.

[0040] According to decision 760, if there is no read or write access in progress, the local control circuit system 125 turns on the refresh word line RWL, asserts the signal ISOr, and waits for the charge recovery CR (765). The local control circuit system 125 can interrupt the refresh phase 2 to service the access request at any time before the charge recovery CR is completed (decision 770), because the refresh sense amplifier 135r retains the required bit and can be used for subsequent attempts in phase 2. The bit line associated with the interrupted refresh transaction is equalized (780). In this case, the word line is closed concurrently with the equalization operation (not shown in the figure) because the data in the cell does not need to be retained. According to decision 785, if the refresh was interrupted and therefore not completed, the refresh phase 2 returns to the beginning; otherwise, the refresh transaction is completed.

[0041] Refresh Phase 2 can be repeatedly interrupted without data loss because the data is retained in the refresh sense amplifiers from the start of Refresh Phase 1. However, Refresh Phase 2 must be completed at some point. Some embodiments implement a protocol in which the host controller allows each memory bank to have periodic windows of no access requests to allow the local control circuitry to complete Phase 2 of any open refresh transactions.

[0042] Figure 8 Three timing diagrams 800, 805, and 810 are depicted, illustrating how refresh phase 1 schedules bit line usage to periods when read and write transactions are not required. This timing allows refresh transactions to be hidden from the host controller 105. The protocol implemented by the host controller 105 may require periodic bank-specific pauses to ensure that all open refresh transactions have time to complete.

[0043] The access and refresh requests are designated RQa and RQr, respectively. The access request RQa is shown as occurring in four time periods divided into time periods that require interaction with the bit lines BL0t and BL0c and time periods that do not require such interaction. The refresh request RQr (first phase) is shown as occurring in three time periods that are also divided. These time periods will be combined with Figure 4 and Figure 5 Further details. In this example, the first period of the access request RQa (i.e., the setup period P1a in which the access command is decoded) is not as long as the sense period P2r of the refresh request RQr. The setup period P1a is extended by a small amount so that the local control circuit system 125 can time the refresh sense period P2r to access the bit lines BL0t and BL0c during the setup phase P1a of the access request (the period when the access transaction does not use the bit lines). The time expansion is labeled "tRCD expansion" because the data table parameter affected by the time expansion is the row column delay time, which is a function of the time between the access request and the access data available in the access sense amplifier.

[0044] Refresh phase 1 is completed at the latest after two consecutive regular accesses. The time required to equalize the bit lines before the regular access in phase 1 is very short because it occurs directly after charge sharing, during which the bit line voltages are relatively close. For access transactions, the fast decoding of the memory address and the fast generation of the memory select signal (here shown as the period P1a of the access request RQa) enable the refresh transaction to be interrupted quickly.

[0045] In diagram 800, any refresh request RQr initiated within interval 815 - during the access request but before the access request is closed - is aligned with the access request RQa, so that the sensing period P2r does not start before the bit line is available after the access request is closed. Diagram 805 is similar to diagram 800, but the refresh transaction is further delayed because the refresh request arrives too late in the access transaction to complete the setup period P1r before the access request abandons the bit line. In diagram 810, the refresh request RQr arrives before the access request RQa, but not in time for the refresh request RQr to completely overlap with the first part of the subsequent but overlapping access request RQa. Therefore, the sensing period P2r is time-shifted so that the second part P2r of the refresh request occurs after the access transaction is completed. The setup period P1r is shown as time-shifted in diagrams 800, 805 and 810, but can be completed in advance.

[0046] Interleaving refresh and access transactions (adding tRCD extensions if needed) can accommodate higher refresh rates with little or no impact on the host controller. This technique improves DRAM stability and can be used to combat row hammer, a security vulnerability in which certain access patterns cause charge to leak between cells and potentially change the contents of memory rows that were not addressed in the original memory access.

[0047] Fig. 9 A sense amplifier pair 900 according to another embodiment is depicted. Bit lines BL0t and BL0c are alternately connected to access sense amplifier 905 and refresh sense amplifier 910 via switch networks 915t and 915c. Sense amplifiers 905 and 910 may be similar to Figure 3 Sense amplifiers 135a and 135r are shown in Figure 1, but evaluation control block 315 is replaced by switch networks 915t and 915c. As previously described, signals OC and ISO control one or the other of sense amplifiers 905 and 910 depending on which of signals "normal" (for normal access) and "refresh" is asserted.

[0048] Back to Figure 1 , the memory system 100 can support a protocol in which the host controller 105 issues refresh commands to the memory 110 as needed to prevent data loss. Although this technique is common, the time required for a refresh transaction can be shortened because the time required for a refresh transaction is limited to the time required for phase 2, which is a significant time saving. The alternative refresh protocol requires that each memory bank have a window during which it will not be accessed (e.g., a 25 nanosecond refresh window every 1.9 microseconds). The protocol ensures that there are enough pauses in consecutive accesses to the memory bank so that the memory 100 can complete the open refresh transaction.

[0049] Another embodiment adds the worst-case time to complete a refresh transaction to the time required to precharge a row or memory cell, which is referred to in DRAM literature as tRP. This approach has slightly lower memory bus utilization for random off-page workloads than same-bank refresh, a protocol that allows refresh commands to be directed to one bank in a group of banks while the other banks remain open for normal operation. However, this approach is expected to improve as DRAM retention times decrease and capacities increase.

[0050] In some embodiments, a refresh command from the host controller signals to the DRAM that one or more banks will not be the target of an access request within a specified time window. The local control circuit system 125 maintains a list of open word lines in the refresh open register 138 - word lines for which refresh phase 2 has not yet completed - and can use this window to complete the open refresh transactions in these banks. Alternatively, the DRAM can attempt to complete the open refresh each time a word line for regular access is closed. The pause specified in the present protocol can ensure successful refresh completion within the refresh interval.

[0051] DRAM cell array architecture is expected to shift from today's single-layer cells with access transistors beneath the silicon surface to a 3D architecture with multiple layers of cells and access transistors in a metal stack. 3D DRAM architecture frees up silicon area that can be used to instantiate refresh sense amplifiers and related structures.

[0052] Hidden refresh transactions can be performed by requesting a refresh of one bank at a time, which is different from a full bank refresh protocol in which all banks are refreshed simultaneously, and also different from a same bank refresh protocol in which banks are organized in groups and each refresh request is for one bank in each subsequent group. Self-refresh as described herein supports a low power mode in which DRAM 110 can shut down all power except that required for self-refresh and receive a wake-up signal from host controller 105. Host controller 105 can then ignore DRAM 110 until needed, at which time DRAM 110 can wake up quickly without the need for simultaneous refresh and access transactions.

[0053] In the above description and accompanying drawings, specific terms and accompanying drawings are proposed to provide a thorough understanding of the present invention. In some cases, the terms and symbols may imply specific details that are not required for practicing the present invention. For example, the interconnection between circuit elements or circuit blocks may be shown or described as a multi-conductor or single-conductor signal line. Each of the multi-conductor signal lines may alternatively be a single-conductor signal line, and each of the single-conductor signal lines may alternatively be a multi-conductor signal line. The signals and signaling paths shown or described as single-ended may also be differential, and vice versa. Similarly, in alternative embodiments, the signals described or depicted as having a high-level effective or low-level effective logic level may have opposite logic levels. As another example, the circuit described or depicted as including a metal oxide semiconductor (MOS) transistor may alternatively be implemented using bipolar technology or any other technology that can implement signal control current. With regard to terminology, when a signal is driven to a low or high logic state (or charged to a high logic state or discharged to a low logic state) to indicate a specific condition, the signal is called "assertion". Conversely, a signal is referred to as "deasserted" to indicate that the signal is charged or discharged to a state other than the asserted state (including a high or low logic state, or a floating state that can occur when the signal driving circuit transitions to a high impedance state, such as a drain disconnect or collector disconnect condition).

[0054] The output of the integrated circuit design process may include a computer readable medium, such as, for example, a magnetic tape, encoded with a data structure defining a circuit system that can be physically instantiated as an integrated circuit. These data structures are typically written in the Caltech Intermediate Format (CIF) or GDSII (a proprietary binary format). One skilled in the art of mask preparation can develop such a data structure from a schematic diagram of the type described above.

[0055] Although the present invention has been described with reference to specific embodiments of the present invention, it is apparent that various modifications and changes may be made to the present invention without departing from the broader spirit and scope of the present invention. After reading this disclosure, variations of these embodiments will be apparent to those of ordinary skill in the art. In addition, some components are shown as being directly connected to each other, while other components are shown as being connected through intermediate components. In each case, the method of interconnection or "coupling" establishes some desired electrical communications between two or more circuit nodes or terminals. As will be appreciated by those skilled in the art, such coupling may generally be implemented using a variety of circuit configurations. Therefore, the spirit and scope of the appended claims should not be limited to the above description. Only those claims that specifically describe "means" or "steps" should be interpreted in accordance with the requirements of the sixth paragraph of Section 112 of Volume 35 of the United States Code.

Claims

1. A method for accessing and refreshing a memory cell in a dynamic random access memory (DRAM), the DRAM comprising a first memory cell selectively connected to a first bit line and a second memory cell selectively connected to the first bit line, the method comprising: receiving an access request to first data in the first memory unit; In response to the access request: sensing a first charge from the first memory cell on the first bit line relative to a second bit line during a first sensing period; restoring the first charge to the first memory cell via the first bit line within a first charge recovery period; as well as setting the first bit line and the second bit line to a common voltage during a first equalization period; generating a refresh request for second data in the second memory cell during one of the first sensing period and the first charge recovery period; as well as In response to the refresh request: Waiting for the end of the first balancing period; as well as After the completion, a second charge from the second memory cell is sensed on the first bit line relative to the second bit line during a second sensing period. 2 . The method of claim 1 , wherein sensing the first charge from the first memory cell comprises connecting an access sense amplifier to the first bit line and the second bit line. 3 . The method of claim 1 , wherein sensing the second charge from the second memory cell comprises connecting a refresh sense amplifier to the first bit line and the second bit line. 4 . The method of claim 3 , further comprising receiving a second access request during the second sensing period and decoding the second access request. The method of claim 4 , further comprising evaluating the refresh request during the charge recovery period.

6. The method according to claim 5, further comprising, in response to the second access request: sensing a third charge from a third memory cell on the first bit line relative to the second bit line during a third sensing period; and The third charge is restored to the third memory cell via the first bit line within a third charge restoration period. 7 . The method of claim 6 , further comprising starting restoring the second charge to the second memory cell after the second sensing period and interrupting the restoring of the second charge to the second memory cell before the second charge is restored in response to the second access request. 8 . The method of claim 7 , further comprising resuming the restoring of the second charge to the second memory cell after restoring the third charge to the third memory cell.

9. A memory device comprising: a memory cell array comprising columns of memory cells, each column of memory cells selectively coupled to a bit line; an access sense amplifier coupled to the bit line; a refresh sense amplifier coupled to the bit line; as well as control circuitry, coupled to the access sense amplifier and the refresh sense amplifier, the control circuitry: controlling the refresh sense amplifier to be connected to the bit line, sensing a voltage on the bit line, amplifying the sensed voltage into a bit voltage, storing the bit voltage, and disconnecting from the bit line; controlling the refresh sense amplifier to reconnect to the bit line to charge the bit line to a refresh voltage, thereby refreshing the memory cell; as well as before the bit line is charged to the refresh voltage; disconnecting the refresh sense amplifier from the bit line without refreshing the memory cell; as well as The access sense amplifier is controlled to be connected to the bit line.

10. The memory device of claim 9, the control circuitry receiving an access request and, in response to the access request, interrupting a refresh transaction by the disconnection of the refresh sense amplifier before the refresh sense amplifier refreshes the memory cell.

11. The memory device of claim 9, wherein the access sense amplifier is connected to the bit line during an access transaction, and the control circuit system further waits for completion of the access transaction to control the refresh sense amplifier to reconnect to the bit line to charge the bit line to the refresh voltage.

12. The memory device of claim 9, wherein the control circuitry is to generate a refresh request and to receive the access request asynchronously with respect to the refresh request.

13. The memory device of claim 12, wherein the control circuitry is to initiate the control of the refresh sense amplifier in response to the refresh request and to disconnect the refresh sense amplifier from the bit line in response to the access request.

14. The memory device of claim 9, wherein the control circuitry is to generate a refresh request that initiates the control of the refresh sense amplifier to connect to the bit line.

15. The memory device of claim 14, wherein the control circuitry is to receive an access request after generating the refresh request, initiate an access transaction in response to the access request, and delay connecting the refresh sense amplifier to the bit line until after the access transaction.

16. A method for accessing and refreshing a memory cell in a dynamic random access memory (DRAM), the memory cell being selectively connected to a bit line, the method comprising: receiving a first access request and a second access request consecutively for the bit line; performing consecutive first and second access transactions in response to respective first and second access requests, each access transaction including an access setup period and an access sense period; generating, during the first access transaction, a refresh request for the bit line that is asynchronous with respect to the first access request and the second access request, and in response to the refresh request: interpreting the refresh request during a refresh setup period during the first access transaction; as well as During a setup period of the second access transaction, a voltage on the bit line is sensed within a refresh sensing period.

17. The method according to claim 16, further comprising: A voltage representing a bit value is stored in response to the sensing of the bit line during the refresh period, an end of the second access transaction is awaited, and the voltage representing the bit value is written to a memory cell selectively connected to the bit line.

18. The method of claim 16, further comprising sensing a closing of the first access transaction and timing the refresh sense period to the closing.

19. The method according to claim 16, further comprising: receiving a third access request and a fourth access request consecutively for the bit line; performing consecutive third and fourth access transactions in response to respective third and fourth access requests; as well as generating a second refresh request for the bit line during the third access transaction, and in response to the second refresh request: sensing closing of the third access transaction; as well as A second refresh sensing period is timed after the fourth access transaction.

20. The method of claim 19, wherein sensing the shut down comprises sensing a word line signal.

21. The method of claim 16, further comprising: The voltage on the bit line is amplified to a bit voltage representing a bit, the voltage representing the bit is stored, a read access request for the bit line is received, and the bit voltage representing the bit is read in response to the read access request.

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