Multilayer ceramic capacitor

Abstract

Provided is an LW inversion type multilayer ceramic capacitor capable of suppressing deterioration of a self-alignment effect and performing stable mounting. The laminated ceramic capacitor (1) is at wgt, where l is the length in the longitudinal direction connecting a first end surface (LS1) and a second end surface (LS2) of a laminated body (10), w is the length in the width direction connecting a first side surface (WS1) and a second side surface (WS2), and t is the length in the height direction connecting a first main surface (TS1) and a second main surface (TS2); lgt; openings (H) that expose the surface of the laminated body (10) are present in a fourth surface portion (40A4) and a fifth surface portion (40A5) of the first external electrode (40A) and in a ninth surface portion (40B4) and a tenth surface portion (40B5) of the second external electrode (40B), and the fourth surface portion (40A4) and the ninth surface portion (40B4) and the fifth surface portion (40A5) and the tenth surface portion (40B5) have protruding portions (K) that protrude in the longitudinal direction from mutually opposed longitudinal center sides.

Description

Technical Field

[0001] The present invention relates to a laminated ceramic capacitor. Background Art

[0002] Conventionally, laminated ceramic capacitors are known. A typical laminated ceramic capacitor has a substantially rectangular parallelepiped laminate whose dimension in the length direction L is longer than that in the width direction W, and external electrodes are provided at both ends of the laminate in the length direction L. On the other hand, in order to reduce ESL, so-called LW inversion type laminated ceramic capacitors are also known in which the size relationship between the dimension in the length direction L and the dimension in the width direction W of the laminate is reversed (see Patent Documents 1 and 2).

[0003] Furthermore, in recent years, as the mounting density of substrates has increased, the mounting area of ​​multilayer ceramic capacitors has decreased. Therefore, the demand for multilayer ceramic capacitors mounted in the lower end of the substrate in the LSC (Land side Capacitor) type using the PoP (Package on Package) mounting method has increased. As such multilayer ceramic capacitors mounted in the LSC (Land side Capacitor) type, a multilayer ceramic capacitor with a reduced height and a thin thickness in the height direction is required.

[0004] Prior Art Literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Publication No. 2020-57753

[0007] Patent Document 2: Japanese Patent Application Publication No. 2020-61524 Summary of the invention

[0008] Problem that the invention aims to solve

[0009] Patent document 2 discloses an LW inversion type stacked ceramic electronic component, wherein a recessed portion is provided at at least one end edge of the fourth face portion and the fifth face portion of an external electrode, the recessed portion being recessed from the end edge toward the first face portion, and the two side portions of the recess in the third direction serve as a covering portion that covers the edges of the two faces of the component body in the second direction.

[0010] However, in the laminated ceramic electronic component disclosed in Patent Document 2, it is considered that the area and shape of the covering portion covering the edges of the two surfaces in the second direction of the component body are deviated due to the formation position and thickness deviation of the base conductor layer and the covering conductor layer arranged thereon. Here, when the LW inversion type laminated ceramic electronic component is mounted on the mounting substrate using solder, due to the left and right differences in the area and shape of the covering portion, the wetting method of the solder on the covering portion changes on each surface, and the tensile stress of the solder may be different. As a result, it is considered that the self-alignment effect is deteriorated. As a result, the laminated ceramic electronic component becomes easy to rotate or tilt, and the mounting performance may be reduced. In addition, the connection pads of the substrate on which the LW inversion type laminated ceramic electronic component is mounted are short in distance between the connection pads, so the self-alignment effect is deteriorated. When the laminated ceramic electronic component is rotated significantly, it will be installed as one external electrode across the connection pads with different polarities, which may cause a short circuit defect.

[0011] An object of the present invention is to provide an LW inversion type multilayer ceramic capacitor capable of suppressing deterioration of the self-alignment effect and performing stable mounting.

[0012] Technical solutions to solve problems

[0013] The multilayer ceramic capacitor of the present invention comprises: a multilayer body including a plurality of dielectric layers and a plurality of internal electrode layers alternately stacked in a height direction, and having a first main surface and a second main surface opposite to each other in the height direction, a first end surface and a second end surface opposite to each other in a length direction perpendicular to the height direction, and a first side surface and a second side surface opposite to each other in a width direction perpendicular to the height direction and the length direction; a first external electrode having at least any one of a first face portion located on the first end surface, a second face portion located on a portion of the first main surface, and a third face portion located on a portion of the second main surface, a fourth face portion located on a portion of the first side surface, and a fifth face portion located on a portion of the second side surface; and a second external electrode having a sixth face portion located on the second end surface, a seventh face portion located on a portion of the first main surface, and a seventh face portion located on a portion of the second side surface. At least any one of the 8th face portion and a portion of the 2nd main face, the 9th face portion located on a portion of the 1st side face, and the 10th face portion located on a portion of the 2nd side face, wherein, when the length of the stack connecting the first end face and the second end face in the longitudinal direction is set to l, the length of the stack connecting the first side face and the second side face in the width direction is set to w, and the length of the stack connecting the first main face and the second main face in the height direction is set to t, the size relationship is w>l>t, and there is an opening portion exposing the surface of the stack in the 4th face portion, the 5th face portion, the 9th face portion, and the 10th face portion, respectively, having a convex portion protruding from the center side of the longitudinal direction opposite to each other toward the longitudinal direction.

[0014] Effects of the Invention

[0015] According to the present invention, it is possible to provide an LW inversion type multilayer ceramic capacitor capable of suppressing deterioration of the self-alignment effect and performing stable mounting. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a perspective view of the appearance of a multilayer ceramic capacitor according to an embodiment.

[0017] Figure 2 Yes Figure 1 The illustrated multilayer ceramic capacitor is an arrow view when the first side surface is viewed along the direction of arrow II.

[0018] Figure 3 Yes Figure 1 The illustrated multilayer ceramic capacitor is an arrow view when the second side surface is viewed along the direction of arrow III.

[0019] Figure 4 Yes Figure 2The illustrated multilayer ceramic capacitor is an arrow view when the first main surface side is viewed along the direction of arrow IV.

[0020] Figure 5 Yes Figure 2 The illustrated multilayer ceramic capacitor is an arrow view when the second main surface side is viewed along the direction of arrow V.

[0021] Figure 6 It is along Figure 4 FIG. 1 is a cross-sectional view of the multilayer ceramic capacitor taken along line VI-VI shown in FIG.

[0022] Figure 7 It is along Figure 6 A cross-sectional view taken along line VII-VII of the multilayer ceramic capacitor shown.

[0023] Fig. 8A It is along Figure 6 The cross-sectional view taken along line VIIIA-VIIIA of the multilayer ceramic capacitor shown is a view showing the first internal electrode layer.

[0024] Figure 8B It is along Figure 6 The cross-sectional view taken along line VIIIB-VIIIB of the multilayer ceramic capacitor shown shows the second internal electrode layer.

[0025] Fig. 9A It is along Figure 4 The cross-sectional view taken along line IXA-IXA of the multilayer ceramic capacitor shown is a view showing a first side surface of the multilayer body.

[0026] Fig. 9B It is along Figure 4 The cross-sectional view taken along line IXB-IXB of the multilayer ceramic capacitor shown is a view showing the second side surface of the multilayer body.

[0027] Fig. 10A yes Figure 6 The enlarged view of the XA portion in is a view showing the cross section of the first external electrode.

[0028] Fig. 10B yes Figure 6 The enlarged view of the XB portion in is a view showing the cross section of the second external electrode.

[0029] Fig.11A is a cross-sectional view showing a modified example of the layer structure of the external electrode of the multilayer ceramic capacitor of the above-mentioned embodiment, Fig. 10A The corresponding figure.

[0030] Fig. 11B is a cross-sectional view showing a modified example of the layer structure of the external electrode of the multilayer ceramic capacitor of the above-mentioned embodiment, Fig. 10B The corresponding figure.

[0031] Fig.12 It is a diagram showing a state in the middle of the manufacturing process of the multilayer ceramic capacitor according to the above-mentioned embodiment.

[0032] Fig.13 It is a diagram showing a state in the middle of the manufacturing process of the multilayer ceramic capacitor according to the above-mentioned embodiment.

[0033] Fig.14 It is a diagram showing a state in the middle of the manufacturing process of the multilayer ceramic capacitor according to the above-mentioned embodiment.

[0034] Fig.15 is a cross-sectional view showing a modified example of the arrangement position of the external electrodes of the multilayer ceramic capacitor according to the above embodiment, Figure 1 The corresponding figure.

[0035] Fig.16A is a perspective view of the appearance of the multilayer ceramic capacitor of Comparative Example 1, which is similar to Figure 1 The corresponding figure.

[0036] Fig. 16B is a diagram showing the first internal electrode layer of the multilayer ceramic capacitor of the comparative example, Fig. 8A The corresponding figure.

[0037] Fig. 16C is a diagram showing the second internal electrode layer of the multilayer ceramic capacitor of the comparative example, Figure 8B The corresponding figure.

[0038] Fig.17A is a perspective view of the appearance of the multilayer ceramic capacitor of Comparative Example 2. Figure 1 The corresponding figure.

[0039] Fig. 17B is a diagram showing the first internal electrode layer of the multilayer ceramic capacitor of the comparative example, Fig. 8A The corresponding figure.

[0040] Fig. 17C is a diagram showing the second internal electrode layer of the multilayer ceramic capacitor of the comparative example, Figure 8B The corresponding figure.

[0041] Fig.18A It is a figure for demonstrating the evaluation method of the mountability in the experimental example.

[0042] Fig.18B It is a figure for demonstrating the evaluation method of the mountability in the experimental example.

[0043] Fig. 18C It is a figure for demonstrating the evaluation method of the mountability in the experimental example.

[0044] Fig.18D It is a figure for demonstrating the evaluation method of the mountability in the experimental example. DETAILED DESCRIPTION

[0045] Hereinafter, a multilayer ceramic capacitor 1 according to an embodiment of the present disclosure will be described. Figure 1 It is a perspective view of the appearance of the multilayer ceramic capacitor 1 according to the present embodiment. Figure 2 Yes Figure 1 The illustrated multilayer ceramic capacitor 1 is an arrow view when the first side surface WS1 is viewed along the direction of arrow II. Figure 3 Yes Figure 1 The illustrated multilayer ceramic capacitor 1 is an arrow view when the second side surface WS2 is viewed along the direction of arrow III. Figure 4 Yes Figure 2 The illustrated multilayer ceramic capacitor 1 is a view when the first main surface TS1 side is viewed along the direction of arrow IV. Figure 5 Yes Figure 2 The illustrated multilayer ceramic capacitor 1 is a view when the second main surface TS2 side is viewed along the direction of arrow V. Figure 6 It is along Figure 4 1 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line VI-VI. Figure 7 It is along Figure 6 1 is a cross-sectional view taken along line VII-VII of the multilayer ceramic capacitor 1 shown. Fig. 8A It is along Figure 6 FIG. 1 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line VIIIA-VIIIA. Figure 8B It is along Figure 6 VIIIB-VIIIB line cross-sectional view of the multilayer ceramic capacitor 1 shown. Fig. 9A It is along Figure 4 The cross-sectional view taken along line IXA-IXA of the multilayer ceramic capacitor 1 shown is a view showing the first side surface WS1 of the multilayer body 10 . Fig. 9B It is along Figure 4 The cross-sectional view taken along line IXB-IXB of the multilayer ceramic capacitor 1 shown is a view showing the second side surface WS2 of the multilayer body 10 . Fig. 10A yes Figure 6 The enlarged view of the XA portion in FIG. 1 is a view showing a cross section of the first external electrode 40A. Fig. 10B yes Figure 6 The enlarged view of the XB portion in FIG. 1 is a view showing a cross section of the second external electrode 40B.

[0046] The multilayer ceramic capacitor 1 includes a multilayer body 10 and external electrodes 40 .

[0047] exist Figures 1 to 9B, an XYZ orthogonal coordinate system is shown. The length direction L of the laminated ceramic capacitor 1 and the laminated body 10 corresponds to the Y direction. The width direction W of the laminated ceramic capacitor 1 and the laminated body 10 corresponds to the X direction. The height direction T of the laminated ceramic capacitor 1 and the laminated body 10 corresponds to the Z direction. Here, Figure 6 The section shown is also referred to as the LT section. Figure 7 The section shown is also referred to as the WT section. Fig. 8A as well as Figure 8B The section shown is also referred to as the LW section.

[0048] like Figure 1 to Figure 5 As shown, the stack 10 includes a first main surface TS1 and a second main surface TS2 opposite to each other in a height direction T, a first end surface LS1 and a second end surface LS2 opposite to each other in a length direction L perpendicular to the height direction T, and a first side surface WS1 and a second side surface WS2 opposite to each other in a width direction W perpendicular to the height direction T and the length direction L.

[0049] The laminate 10 has a substantially rectangular parallelepiped shape. Preferably, the corners and ridges of the laminate 10 are rounded. The corners are the portions where three faces of the laminate intersect, and the ridges are the portions where two faces of the laminate intersect. In addition, a portion or all of the surface constituting the laminate 10 may be formed with concavities and convexities.

[0050] like Figure 6 as well as Figure 7 As shown, the laminate 10 includes an inner layer portion 11 , and a first main surface side outer layer portion 12 and a second main surface side outer layer portion 13 arranged in the height direction T so as to sandwich the inner layer portion 11 .

[0051] The inner layer portion 11 includes a plurality of dielectric layers 20 and a plurality of internal electrode layers 30. The inner layer portion 11 includes, in the height direction T, the internal electrode layer 30 located closest to the first main surface TS1 to the internal electrode layer 30 located closest to the second main surface TS2. In the inner layer portion 11, the plurality of internal electrode layers 30 are arranged opposite to each other with the dielectric layer 20 interposed therebetween. The inner layer portion 11 is a portion that generates electrostatic capacitance and substantially functions as a capacitor. In addition, the inner layer portion 11 is also referred to as an effective layer portion.

[0052] The plurality of dielectric layers 20 are composed of a dielectric material. The dielectric material is, for example, a ceramic material. The dielectric material may also be, for example, a dielectric ceramic containing BaTiO3, CaTiO3, SrTiO3, or CaZrO3. When these components are the main components, it is also possible to add, according to the desired characteristics of the laminate, a secondary component such as a Mn compound, an Fe compound, a Cr compound, a Co compound, or a Ni compound, whose content is less than that of the main component.

[0053] The thickness of the dielectric layer 20 is preferably 0.5 μm or more and 10 μm or less. The number of laminated dielectric layers 20 is preferably 15 or more and 700 or less. The number of dielectric layers 20 is the sum of the number of dielectric layers of the inner layer portion 11 and the number of dielectric layers of the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13.

[0054] The plurality of internal electrode layers 30 include a plurality of first internal electrode layers 31 and a plurality of second internal electrode layers 32. The first internal electrode layers 31 are arranged on the plurality of dielectric layers 20 and are led out to the first end surface LS1. The second internal electrode layers 32 are arranged on the plurality of dielectric layers 20 and are led out to the second end surface LS2. The plurality of first internal electrode layers 31 and the plurality of second internal electrode layers 32 are alternately arranged in the height direction T of the laminate 10 with the dielectric layers 20 interposed therebetween. The first internal electrode layers 31 and the second internal electrode layers 32 are arranged so as to sandwich the dielectric layers 20.

[0055] like Fig. 8A As shown, the first internal electrode layer 31 has: a first opposing electrode portion 31A, opposing the second internal electrode layer 32; a first lead portion 31B, led from the first opposing electrode portion 31A to the first end surface LS1, a portion of the first side surface WS1, and a portion of the second side surface WS2; a second lead portion 31C, led from the first opposing electrode portion 31A to a portion of the first side surface WS1; and a third lead portion 31D, led from the first opposing electrode portion 31A to a portion of the second side surface WS2.

[0056] The first opposing electrode portion 31A is located inside the stacked body 10. The first lead portion 31B is connected to the first opposing electrode portion 31A and is exposed at the first end surface LS1, a portion of the first side surface WS1, and a portion of the second side surface WS2. The second lead portion 31C is connected to the first opposing electrode portion 31A and is exposed at a portion of the first side surface WS1. The third lead portion 31D is connected to the first opposing electrode portion 31A and is exposed at a portion of the second side surface WS2.

[0057] The second lead portion 31C is disposed at a distance from the portion of the first lead portion 31B led to the first side surface WS1 in the longitudinal direction L. The third lead portion 31D is disposed at a distance from the portion of the first lead portion 31B led to the second side surface WS2 in the longitudinal direction L.

[0058] like Figure 8BAs shown, the second internal electrode layer 32 has: a second opposing electrode portion 32A, opposite to the first internal electrode layer 31; a fourth lead portion 32B, led from the second opposing electrode portion 32A to the second end surface LS2, a portion of the first side surface WS1, and a portion of the second side surface WS2; a fifth lead portion 32C, led from the second opposing electrode portion 32A to a portion of the first side surface WS1; and a sixth lead portion 32D, led from the second opposing electrode portion 32A to a portion of the second side surface WS2.

[0059] The second opposing electrode portion 32A is located inside the stacked body 10. The fourth lead portion 32B is connected to the second opposing electrode portion 32A and is exposed at the second end surface LS2, a portion of the first side surface WS1, and a portion of the second side surface WS2. The fifth lead portion 32C is connected to the second opposing electrode portion 32A and is exposed at a portion of the first side surface WS1. The sixth lead portion 32D is connected to the second opposing electrode portion 32A and is exposed at a portion of the second side surface WS2.

[0060] The fifth lead portion 32C is arranged at a distance from the portion of the fourth lead portion 32B led to the first side surface WS1 in the longitudinal direction L. The sixth lead portion 32D is arranged at a distance from the portion of the fourth lead portion 32B led to the second side surface WS2 in the longitudinal direction L.

[0061] Fig. 9A It is along Figure 4 The cross-sectional view taken along line IXA-IXA of the multilayer ceramic capacitor 1 shown is a view showing the first side surface WS1 of the multilayer body 10 . Fig. 9B It is along Figure 4 The cross-sectional view of the multilayer ceramic capacitor 1 taken along the line IXB-IXB shown in FIG. 1 is a view showing the second side surface WS2 of the multilayer body 10. Fig. 8A as well as Figure 8B It is also shown that Fig. 9A The cross-sectional view is located on the IXA-IXA line and shows the Fig. 9B The cross-sectional view is located on the IXB-IXB line.

[0062] like Fig. 9A As shown, on the first side surface WS1 of the stacked body 10, the first lead portions 31B and the second lead portions 31C of each of the plurality of first internal electrode layers 31, and the fourth lead portions 32B and the fifth lead portions 32C of each of the plurality of second internal electrode layers 32 are exposed. The plurality of first lead portions 31B and the plurality of second lead portions 31C are exposed on the surface of the stacked body 10 in a separated state. The plurality of fourth lead portions 32B and the plurality of fifth lead portions 32C are exposed on the surface of the stacked body 10 in a separated state.

[0063] like Fig. 9AAs shown, in the first side surface WS1, among the plurality of second lead portions 31C arranged in the height direction T of the stacked body 10, the dimension in the length direction L of the plurality of second lead portions 31C located in the center of the height direction T is longer than the dimension in the length direction L of the second lead portions 31C located outside the center of the height direction T, that is, located on the first main surface TS1 side and the second main surface TS2 side of the center of the height direction T. The positions of the outer ends in the length direction L of all the second lead portions 31C, that is, the ends on the first end surface LS1 side, are aligned in the length direction L. Therefore, the center side in the length direction L of the plurality of second lead portions 31C located in the center of the height direction T protrudes toward the center side in the length direction L compared with the plurality of second lead portions 31C located outside the center of the height direction T. In other words, each of the plurality of second lead portions 31C located in the center in the height direction T has a protrusion 31C1 protruding from the ends of the plurality of second lead portions 31C located in the center in the length direction other than the center in the height direction T toward the center in the length direction.

[0064] The front end of the longitudinal center side of the protruding portion 31C1 is located closer to the longitudinal center side than the end 40A9 on the longitudinal center side of the second surface 40A2 and the third surface 40A3. That is, the longitudinal center side of the plurality of second lead-out portions 31C located in the center portion in the height direction T protrudes toward the longitudinal center side than the end 40A9 on the longitudinal center side of the second surface 40A2 and the third surface 40A3.

[0065] Furthermore, among the plurality of fifth lead portions 32C arranged in the height direction T of the stacked body 10, the dimension in the length direction L of the plurality of fifth lead portions 32C located in the center of the height direction T is longer than the dimension in the length direction L of the fifth lead portions 32C located outside the center of the height direction T, that is, located on the first principal surface TS1 side and the second principal surface TS2 side of the center of the height direction T. The positions of the outer ends in the length direction L of all the fifth lead portions 32C, that is, the ends on the second end surface LS2 side, are aligned in the length direction L. Therefore, the center side in the length direction L of the plurality of fifth lead portions 32C located in the center of the height direction T protrudes toward the center side in the length direction L compared with the plurality of fifth lead portions 32C located outside the center of the height direction T. In other words, the plurality of fifth lead portions 32C located in the center of the height direction T each have a protrusion 32C1 protruding toward the center side in the length direction from the end portion on the center side in the length direction of the plurality of fifth lead portions 32C located outside the center of the height direction T.

[0066] The front end of the longitudinal center side of the protruding portion 32C1 is located closer to the longitudinal center side than the end 40B9 on the longitudinal center side of the seventh surface portion 40B2 and the eighth surface portion 40B3. That is, the longitudinal center side of the plurality of fifth lead portions 32C located in the center portion in the height direction T protrudes toward the longitudinal center side than the end 40B9 on the longitudinal center side of the seventh surface portion 40B2 and the eighth surface portion 40B3.

[0067] like Fig. 9B As shown, on the second side surface WS2 side, among the plurality of third lead portions 31D arranged in the height direction T of the stacked body 10, the dimension in the length direction L of the plurality of third lead portions 31D located in the center of the height direction T is longer than the dimension in the length direction L of the third lead portions 31D located outside the center of the height direction T, that is, located on the first main surface TS1 side and the second main surface TS2 side of the center of the height direction T. The positions of the outer ends in the length direction L of all the third lead portions 31D, that is, the ends on the first end surface LS1 side, are aligned in the length direction L. Therefore, the center side in the length direction L of the plurality of third lead portions 31D located in the center of the height direction T protrudes toward the center side in the length direction L compared with the plurality of third lead portions 31D located outside the center of the height direction T. In other words, each of the third lead portions 31D located in the center in the height direction T has a protrusion 31D1 protruding from the end portion on the longitudinal center side of the third lead portions 31D other than the center in the height direction T toward the longitudinal center side.

[0068] The front end of the longitudinal center side of the protruding portion 31D1 is located closer to the longitudinal center side than the end 40A9 on the longitudinal center side of the second surface 40A2 and the third surface 40A3. That is, the longitudinal center side of the plurality of third lead-out portions 31D located in the center portion in the height direction T protrudes toward the longitudinal center side than the end 40A9 on the longitudinal center side of the second surface 40A2 and the third surface 40A3.

[0069] Furthermore, among the plurality of sixth lead portions 32D arranged in the height direction T of the stacked body 10, the dimension in the length direction L of the plurality of sixth lead portions 32D located in the center of the height direction T is longer than the dimension in the length direction L of the sixth lead portions 32D located outside the center of the height direction T, that is, located on the first main surface TS1 side and the second main surface TS2 side of the center of the height direction T. The positions of the outer ends in the length direction L of all the sixth lead portions 32D, that is, the ends on the second end surface LS2 side, are aligned in the length direction T. Therefore, the center side in the length direction L of the plurality of sixth lead portions 32D located in the center of the height direction T protrudes toward the center side in the length direction L compared with the plurality of sixth lead portions 32D located outside the center of the height direction T. In other words, the plurality of sixth lead portions 32D located in the center of the height direction T each have a protrusion 32D1 protruding toward the center side in the length direction from the end portion on the center side in the length direction of the plurality of sixth lead portions 32D located outside the center of the height direction T.

[0070] The front end of the longitudinal center side of the protruding portion 32D1 is located closer to the longitudinal center side than the end 40B9 on the longitudinal center side of the seventh surface portion 40B2 and the eighth surface portion 40B3. That is, the longitudinal center side of the plurality of sixth lead portions 32D located in the center portion in the height direction T protrudes toward the longitudinal center side than the end 40B9 on the longitudinal center side of the seventh surface portion 40B2 and the eighth surface portion 40B3.

[0071] The dimensions of the length direction L of the portion of the first lead portion 31B and the fourth lead portion 32B exposed at a portion of the first side surface WS1 are preferably 30 μm or more and 230 μm or less. The dimensions of the length direction L of the portion of the first lead portion 31B and the fourth lead portion 32B exposed at a portion of the second side surface WS2 are preferably 30 μm or more and 230 μm or less. The dimensions of the length direction L of the portion of the second lead portion 31C and the fifth lead portion 32C exposed at a portion of the first side surface WS1 are preferably 30 μm or more and 230 μm or less. The dimensions of the length direction L of the portion of the third lead portion 31D and the sixth lead portion 32D exposed at a portion of the second side surface WS2 are preferably 30 μm or more and 230 μm or less.

[0072] The size of each lead portion exposed on the side of the laminate 10 is not particularly limited. However, the size of the portion of the second lead portion 31C and the fifth lead portion 32C exposed on a portion of the first side WS1 in the length direction L may be longer than the size of the portion of the first lead portion 31B and the fourth lead portion 32B exposed on a portion of the first side WS1 in the length direction L. The size of the portion of the third lead portion 31D and the sixth lead portion 32D exposed on a portion of the second side WS2 in the length direction L may be longer than the size of the portion of the first lead portion 31B and the fourth lead portion 32B exposed on a portion of the second side WS2 in the length direction L.

[0073] Thus, the shape of the external electrode 40 of the present embodiment having the opening H and the convex portion K described later can be realized. Furthermore, since the distance between the second lead portion 31C of the first internal electrode layer 31 and the fifth lead portion 32C of the second internal electrode layer 32 can be shortened, and since the distance between the third lead portion 31D of the first internal electrode layer 31 and the sixth lead portion 32D of the second internal electrode layer 32 can be shortened, the path through which the current flows can be shortened. Therefore, ESL can be reduced.

[0074] In the present embodiment, the first counter electrode portion 31A and the second counter electrode portion 32A face each other via the dielectric layer 20 , thereby forming capacitance and exhibiting capacitor characteristics.

[0075] The shapes of the first counter electrode portion 31A and the second counter electrode portion 32A are not particularly limited, but are preferably rectangular shapes. However, the corners of the rectangular shape may be rounded or the corners of the rectangular shape may be formed to be inclined.

[0076] The shapes of the first lead-out portion 31B and the fourth lead-out portion 32B are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded, or the corners of the rectangular shape may be formed obliquely. In the present embodiment, the shapes of the first lead-out portion 31B and the fourth lead-out portion 32B are substantially T-shaped with a portion of the corners of the rectangular shape removed.

[0077] The shapes of the second lead portion 31C, the third lead portion 31D, the fifth lead portion 32C, and the sixth lead portion 32D are not particularly limited, but are preferably rectangular shapes. However, the corners of the rectangular shapes may be rounded or may be formed to be inclined.

[0078] The portion of the first lead portion 31B exposed at the first end surface LS1 has a larger dimension in the width direction W than the first opposing electrode portion 31A. The portion of the fourth lead portion 32B exposed at the second end surface LS2 has a larger dimension in the width direction W than the second opposing electrode portion 32A.

[0079] The first internal electrode layer 31 and the second internal electrode layer 32 are made of a suitable conductive material such as a metal such as Ni, Cu, Ag, Pd, Au, or an alloy containing at least one of these metals. When an alloy is used, the first internal electrode layer 31 and the second internal electrode layer 32 may be made of, for example, an Ag-Pd alloy.

[0080] The thickness of each of the first internal electrode layer 31 and the second internal electrode layer 32 is preferably about 0.2 μm or more and 2.0 μm or less, for example. The total number of the first internal electrode layers 31 and the second internal electrode layers 32 is preferably 15 or more and 200 or less.

[0081] The first main surface side outer layer portion 12 is located on the first main surface TS1 side of the stacked body 10. The first main surface side outer layer portion 12 is a collection of a plurality of dielectric layers 20 located between the first main surface TS1 and the internal electrode layer 30 closest to the first main surface TS1. That is, the first main surface side outer layer portion 12 is formed by a plurality of dielectric layers 20 located between the first main surface TS1 and the internal electrode layer 30 located closest to the first main surface TS1 among the plurality of internal electrode layers 30. The dielectric layer 20 used in the first main surface side outer layer portion 12 may be the same as the dielectric layer 20 used in the internal layer portion 11.

[0082] The second main surface side outer layer portion 13 is located on the second main surface TS2 side of the stacked body 10. The second main surface side outer layer portion 13 is a collection of a plurality of dielectric layers 20 located between the second main surface TS2 and the internal electrode layer 30 closest to the second main surface TS2. That is, the second main surface side outer layer portion 13 is formed by a plurality of dielectric layers 20 located between the second main surface TS2 and the internal electrode layer 30 located closest to the second main surface TS2 side among the plurality of internal electrode layers 30. The dielectric layer 20 used in the second main surface side outer layer portion 13 may be the same as the dielectric layer 20 used in the internal layer portion 11.

[0083] As described above, the laminated body 10 includes the plurality of laminated dielectric layers 20 and the plurality of internal electrode layers 30 laminated on the dielectric layers 20. That is, the laminated ceramic capacitor 1 includes the laminated body 10 in which the dielectric layers 20 and the internal electrode layers 30 are alternately laminated.

[0084] The laminate 10 also includes an opposing electrode portion 11E. The opposing electrode portion 11E is a portion where the first opposing electrode portion 31A of the first internal electrode layer 31 and the second opposing electrode portion 32A of the second internal electrode layer 32 face each other. The opposing electrode portion 11E is configured as a part of the inner layer portion 11. Fig. 8A as well as Figure 8B, the range of the opposing electrode portion 11E in the width direction W and the length direction L is shown. In addition, the opposing electrode portion 11E is also referred to as a capacitor effective portion.

[0085] In addition, the stacked body 10 has an end face side outer layer portion. The end face side outer layer portion has a first end face side outer layer portion LG1 located on the first end face LS1 side, and a second end face side outer layer portion LG2 located on the second end face LS2 side. The first end face side outer layer portion LG1 is a portion including the dielectric layer 20 and the first lead portion 31B located between the opposing electrode portion 11E and the first end face LS1. That is, the first end face side outer layer portion LG1 is a collection of a plurality of pieces of portions on the first end face LS1 side of the dielectric layer 20 and a plurality of pieces of first lead portions 31B. The second end face side outer layer portion LG2 is a portion including the dielectric layer 20 and the fourth lead portion 32B located between the opposing electrode portion 11E and the second end face LS2. That is, the second end face side outer layer portion LG2 is a collection of a plurality of pieces of portions on the second end face LS2 side of the dielectric layer 20 and a plurality of pieces of fourth lead portions 32B. Figure 6 , Fig. 8A as well as Figure 8B , the range of the first end surface side outer layer portion LG1 and the second end surface side outer layer portion LG2 in the length direction L is shown. In addition, the first end surface side outer layer portion LG1 and the second end surface side outer layer portion LG2 are also referred to as L gaps or end gaps.

[0086] In addition, the stacked body 10 has a side outer layer portion. The side outer layer portion has a first side outer layer portion WG1 located on the first side WS1 side, and a second side outer layer portion WG2 located on the second side WS2 side. The first side outer layer portion WG1 is a portion including the dielectric layer 20 located between the opposing electrode portion 11E and the first side WS1. That is, the first side outer layer portion WG1 is a collection of portions of the dielectric layer 20 on the first side WS1 side of a plurality of sheets. The second side outer layer portion WG2 is a portion including the dielectric layer 20 located between the opposing electrode portion 11E and the second side WS2. That is, the second side outer layer portion WG2 is a collection of portions of the dielectric layer 20 on the second side WS2 side of a plurality of sheets. Figure 7 , Fig. 8A as well as Figure 8B , the range of the first side outer layer portion WG1 and the second side outer layer portion WG2 in the width direction W is shown. In addition, the first side outer layer portion WG1 and the second side outer layer portion WG2 are also referred to as W gaps or side gaps.

[0087] like Figures 6 to 8BAs shown in FIG. 1 , when the length of the length direction L connecting the first end face LS1 and the second end face LS2 of the stacked body 10 is set to l, the length of the width direction W connecting the first side face WS1 and the second side face WS2 is set to w, and the length of the height direction T connecting the first main face TS1 and the second main face TS2 is set to t, the relationship between these dimensions is w>l>t. As a result, the width of the lead portion in the end face of the internal electrode layer 30 can be widened. In addition, the distance between the first external electrode 40A and the second external electrode 40B can be shortened, so that the ESL of the stacked ceramic capacitor 1 can be reduced.

[0088] The length l of the length direction L connecting the first end face LS1 and the second end face LS2 of the stack 10 is preferably greater than 0.05mm and less than 0.7mm. In addition, the length w of the width direction W connecting the first side surface WS1 and the second side surface WS2 of the stack 10 is preferably greater than 0.15mm and less than 1.5mm. In addition, the length t of the height direction T connecting the first main surface TS1 and the second main surface TS2 of the stack 10 is preferably less than 150μm. Thus, high-density mounting can be achieved. In addition, the length t of the height direction T connecting the first main surface TS1 and the second main surface TS2 of the stack 10 is preferably less than 100μm, more preferably less than 50μm. Thus, higher-density mounting can be achieved.

[0089] In addition, each dimension of l, w, and t of the laminated body 10 was measured by the following method.

[0090] First, the w dimension of the laminated body 10 is measured. Specifically, the w dimension of the laminated body 10 is measured at the exact center of the laminated ceramic capacitor 1 in the longitudinal direction L, that is, at the position L / 2 of the laminated ceramic capacitor 1 using a micrometer.

[0091] Next, the l dimension and t dimension of the laminated body 10 are measured. First, the laminated ceramic capacitor 1 which is the same as the laminated ceramic capacitor 1 whose w dimension is measured is ground to the exact center position in the width direction W of the laminated ceramic capacitor 1, that is, it is ground to the W / 2 position of the laminated ceramic capacitor 1 so as to be parallel to the LT plane. Then, the LT cross section exposed by grinding is observed under a microscope. The l dimension of the laminated body 10 is measured under a microscope at the exact center position in the height direction T of the laminated body 10 in the LT cross section, that is, at the t / 2 position of the laminated body 10. The t dimension of the laminated body 10 is measured under a microscope at the exact center position in the length direction L of the laminated body 10 in the LT cross section, that is, at the l / 2 position of the laminated body 10.

[0092] The external electrode 40 includes a first external electrode 40A disposed on the first end surface LS1 side and a second external electrode 40B disposed on the second end surface LS2 side.

[0093] The first external electrode 40A is connected to the first internal electrode layer 31. The first external electrode 40A of the present embodiment includes a first face portion 40A1 located on the first end surface LS1, a second face portion 40A2 located on a portion of the first main surface TS1, a third face portion 40A3 located on a portion of the second main surface TS2, a fourth face portion 40A4 located on a portion of the first side surface WS1, and a fifth face portion 40A5 located on a portion of the second side surface WS2. In addition, the first external electrode 40A preferably includes at least one of the second face portion 40A2 located on a portion of the first main surface TS1 and the third face portion 40A3 located on a portion of the second main surface TS2, the first face portion 40A1 located on the first end surface LS1, the fourth face portion 40A4 located on a portion of the first side surface WS1, and the fifth face portion 40A5 located on a portion of the second side surface WS2.

[0094] The first surface portion 40A1 is a portion that covers the entire first end surface LS1 and is connected to the first internal electrode layer 31. Any of the second surface portion 40A2 and the third surface portion 40A3 is a portion that is connected to a land of a mounting substrate.

[0095] The fourth surface portion 40A4 is a portion connected to the first lead portion 31B and the second lead portion 31C exposed on the first side surface WS1. The fifth surface portion 40A5 is a portion connected to the first lead portion 31B and the third lead portion 31D exposed on the second side surface WS2. In this way, the first lead portion 31B, the second lead portion 31C, and the third lead portion 31D are all connected to the same external electrode, that is, the first external electrode 40A.

[0096] The fourth surface portion 40A4 and the fifth surface portion 40A5 have an opening H that exposes the laminate 10. The opening H is surrounded by a material constituting the external electrode 40. The opening H is a recessed portion recessed from the surface of the fourth surface portion 40A4 and the fifth surface portion 40A5, and the surface of the laminate 10 is exposed at the bottom.

[0097] By forming such an opening portion H, a connecting surface that connects the second surface 40A2 and the third surface 40A3 in the height direction is formed on both sides of the opening portion H in the length direction L of the stack 10, serving as a wetting and climbing portion for solder.

[0098] like Figure 2As shown, the fourth face portion 40A4 has a first connecting surface F1 connecting the second face portion 40A2 and the third face portion 40A3 in the height direction on the center side of the opening H in the longitudinal direction L of the stacked body 10. In addition, the fourth face portion 40A4 has a second connecting surface F2 connecting the second face portion 40A2 and the third face portion 40A3 in the height direction on the first end surface LS1 side of the opening H. The second connecting surface F2 is connected to the first face portion 40A1.

[0099] like Figure 3 As shown, the fifth face portion 40A5 has a third connecting surface F3 connecting the second face portion 40A2 and the third face portion 40A3 in the height direction on the center side of the opening H in the longitudinal direction L of the stacked body 10. In addition, the fifth face portion 40A5 has a fourth connecting surface F4 connecting the second face portion 40A2 and the third face portion 40A3 in the height direction on the first end surface LS1 side of the opening H. The fourth connecting surface F4 is connected to the first face portion 40A1.

[0100] The second external electrode 40B is connected to the second internal electrode layer 32. The second external electrode 40B of the present embodiment has a sixth face portion 40B1 located on the second end surface LS2, a seventh face portion 40B2 located on a portion of the first main surface TS1, an eighth face portion 40B3 located on a portion of the second main surface TS2, a ninth face portion 40B4 located on a portion of the first side surface WS1, and a tenth face portion 40B5 located on a portion of the second side surface WS2. In addition, the second external electrode 40B preferably has at least any one of the seventh face portion 40B2 located on a portion of the first main surface TS1 and the eighth face portion 40B3 located on a portion of the second main surface TS2, the first external electrode 40A, the sixth face portion 40B1 located on the second end surface LS2, the ninth face portion 40B4 located on a portion of the first side surface WS1, and the tenth face portion 40B5 located on a portion of the second side surface WS2.

[0101] The sixth surface portion 40B1 is a portion that covers the entire second end surface LS2 and is connected to the second internal electrode layer 32. Either the seventh surface portion 40B2 or the eighth surface portion 40B3 is a portion that is connected to a land of the mounting substrate.

[0102] The ninth surface portion 40B4 is a portion connected to the fourth lead portion 32B and the fifth lead portion 32C exposed on the first side surface WS1. The tenth surface portion 40B5 is a portion connected to the fourth lead portion 32B and the sixth lead portion 32D exposed on the second side surface WS2. In this way, the fourth lead portion 32B, the fifth lead portion 32C, and the sixth lead portion 32D are all connected to the same external electrode, that is, the second external electrode 40B.

[0103] The ninth surface portion 40B4 and the tenth surface portion 40B5 have an opening H that exposes the laminate 10. The opening H is surrounded by a material constituting the external electrode 40. The opening H is a recessed portion recessed from the surface of the ninth surface portion 40B4 and the tenth surface portion 40B5, and the surface of the laminate 10 is exposed at the bottom.

[0104] By forming such an opening portion H, a connecting surface that connects the 7th face 40B2 and the 8th face 40B3 in the height direction is formed on both sides of the opening portion H in the length direction L of the stack 10, serving as a wetting and climbing portion for solder.

[0105] like Figure 2 As shown, the ninth face portion 40B4 has a fifth connecting surface F5 connecting the seventh face portion 40B2 and the eighth face portion 40B3 in the height direction on the center side of the opening H in the longitudinal direction L of the stacked body 10. In addition, the ninth face portion 40B4 has a sixth connecting surface F6 connecting the seventh face portion 40B2 and the eighth face portion 40B3 in the height direction on the second end surface LS2 side of the opening H. The sixth connecting surface F6 is connected to the sixth face portion 40B1.

[0106] like Figure 3 As shown, the tenth face portion 40B5 has a seventh connecting surface F7 connecting the seventh face portion 40B2 and the eighth face portion 40B3 in the height direction on the center side of the opening H in the longitudinal direction L of the stacked body 10. In addition, the tenth face portion 40B5 has an eighth connecting surface F8 connecting the seventh face portion 40B2 and the eighth face portion 40B3 in the height direction on the second end surface LS2 side of the opening H. The eighth connecting surface F8 is connected to the sixth face portion 40B1.

[0107] As a result, the wetting climb amount of the solder on the first side WS1 and the second side WS2 of the stack 10 can be made appropriate. In addition, since the solder wetting climb surrounds the opening H, the solder can be divided into two parts with the opening H as a boundary for wetting climb. Therefore, on the mounting surface side of the stacked ceramic capacitor 1, the points where stress is applied by the solder can be dispersed to two points. Therefore, the self-alignment effect is improved and the mountability of the stacked ceramic capacitor 1 is stabilized. As a result, the stacked ceramic capacitor 1 can be prevented from tilting. In addition, the stacked ceramic capacitor 1 can be prevented from rotating and causing a short circuit defect.

[0108] The openings H provided in the fourth surface 40A4, the fifth surface 40A5, the ninth surface 40B4, and the tenth surface 40B5 are preferably formed in substantially the same size. The shape of the opening H is not particularly limited, and is preferably rectangular, polygonal, circular, or elliptical.

[0109] The opening H formed in the fourth face portion 40A4 and the fifth face portion 40A5 is preferably arranged at the center of the fourth face portion 40A4 and the fifth face portion 40A5 in the height direction T. The opening H formed in the fourth face portion 40A4 and the fifth face portion 40A5 is preferably arranged at the center of the length direction L of the fourth face portion 40A4 and the fifth face portion 40A5, or is arranged closer to the first end face LS1 than the center of the length direction L of the fourth face portion 40A4 and the fifth face portion 40A5. By arranging the opening H formed in the fourth face portion 40A4 and the fifth face portion 40A5 closer to the first end face LS1, the area of ​​the first connection face F1 and the third connection face F3 as the solder wetting and climbing portion can be ensured.

[0110] The opening H formed in the ninth face portion 40B4 and the tenth face portion 40B5 is preferably arranged at the center of the ninth face portion 40B4 and the tenth face portion 40B5 in the height direction T. The opening H formed in the ninth face portion 40B4 and the tenth face portion 40B5 is preferably arranged at the center of the length direction L of the ninth face portion 40B4 and the tenth face portion 40B5, or is arranged closer to the second end face LS2 than the center of the length direction L of the ninth face portion 40B4 and the tenth face portion 40B5. By arranging the opening H formed in the ninth face portion 40B4 and the tenth face portion 40B5 closer to the second end face LS2, the area of ​​the fifth connecting face F5 and the seventh connecting face F7, which are the solder wetting and climbing portions, can be ensured.

[0111] As a result, it becomes easy to divide the solder into two parts with the opening H as the boundary to perform wetting and climbing. Therefore, on the mounting surface side of the multilayer ceramic capacitor 1, the points where stress is applied by the solder can be dispersed to two points. Therefore, the self-alignment effect is improved, and the mounting performance of the multilayer ceramic capacitor 1 is stable. As a result, the multilayer ceramic capacitor can be prevented from tilting. In addition, the multilayer ceramic capacitor 1 can be prevented from rotating and causing a short circuit defect.

[0112] The area of ​​the opening H formed in the fourth face portion 40A4, the fifth face portion 40A5, the ninth face portion 40B4, and the tenth face portion 40B5 is preferably 1% or more and 50% or less relative to the area of ​​each of the fourth face portion 40A4, the fifth face portion 40A5, the ninth face portion 40B4, and the tenth face portion 40B5. More preferably, the area ratio of the opening H is 3% or more and 20% or less. Thus, the self-alignment effect can be exerted, and the effect of suppressing the short circuit failure caused by the tilt and rotation of the multilayer ceramic capacitor 1 can be made more significant.

[0113] The area ratio of the opening H is measured using an optical microscope. Figure 2, a method for measuring the area ratio of the opening H in the fourth surface portion 40A4 will be described. In addition, a method for measuring the area ratio when the fourth surface portion 40A4 and the opening H are both substantially rectangular will be described below.

[0114] First, the field of view is set to a magnification at which the first external electrode 40A located on the first side surface WS1 of the multilayer ceramic capacitor 1 enters the field of view of the microscope. Next, the contour of the opening H is identified, and the dimension d1 in the length direction L and the dimension d2 in the height direction T of the opening H are measured. Then, the area A1 of the opening H is calculated by the calculation formula A1=d1×d2. Next, the contour of the first external electrode 40A is identified, and the dimension D1 in the length direction L and the dimension D2 in the height direction T of the fourth surface 40A4 are measured. Then, the area A2 of the fourth surface 40A4 is calculated by the calculation formula A2=D1×D2. Then, the area ratio of the opening H located on the fourth surface 40A4 to the area of ​​the fourth surface 40A4 is calculated by the calculation formula A1÷A2.

[0115] In the above, the method for measuring the area ratio of the opening H located at the fourth surface portion 40A4 is described as a representative method for measuring the area ratio of the opening H, but the area ratios of the opening H located at the fifth surface portion 40A5, the ninth surface portion 40B4, and the tenth surface portion 40B5 are also calculated by the same measuring method. The area ratios of the opening H located at the fourth surface portion 40A4, the fifth surface portion 40A5, the ninth surface portion 40B4, and the tenth surface portion 40B5 are calculated respectively, and then the average value of the area ratios of the four openings H is calculated as the area ratio of the opening H in the multilayer ceramic capacitor 1.

[0116] In the multilayer ceramic capacitor 1 of the present embodiment, the fourth surface 40A4 of the first external electrode 40A and the ninth surface 40B4 of the second external electrode 40B arranged in the length direction L and the fifth surface 40A5 of the first external electrode 40A and the tenth surface 40B5 of the second external electrode 40B arranged in the length direction L respectively have a protrusion K protruding from the center side of the length direction L opposite to each other toward the length direction L.

[0117] like Figure 2 As shown, the fourth face 40A4 and the ninth face 40B4 disposed on the first side surface WS1 of the stacked body 10 have a rectangular convex portion K. The convex portion K of the fourth face 40A4 protrudes in the length direction L from the edge K4 on the longitudinal center side opposite to the ninth face 40B4 toward the ninth face 40B4. The convex portion K of the ninth face 40B4 protrudes in the length direction L from the edge K9 on the longitudinal center side opposite to the fourth face 40A4 toward the fourth face 40A4.

[0118] like Fig. 9A As shown, the convex portion K of the fourth face portion 40A4 covers each protrusion 31C1 of the plurality of second lead portions 31C exposed on the first side surface WS1 of the stacked body 10 and located in the center of the height direction T. Moreover, the convex portion K of the fourth face portion 40A4 is connected to the plurality of protrusions 31C1. In addition, the convex portion K of the ninth face portion 40B4 covers each protrusion 32C1 of the plurality of fifth lead portions 32C exposed on the first side surface WS1 of the stacked body 10 and located in the center of the height direction T. Moreover, the convex portion K of the ninth face portion 40B4 is connected to the plurality of protrusions 32C1.

[0119] like Figure 3 As shown, the fifth face portion 40A5 and the tenth face portion 40B5 disposed on the second side surface WS2 of the stacked body 10 have a rectangular convex portion K. The convex portion K of the fifth face portion 40A5 protrudes in the length direction L from the edge K5 on the longitudinal center side opposite to the tenth face portion 40B5 toward the tenth face portion 40B5. The convex portion K of the tenth face portion 40B5 protrudes in the length direction L from the edge K10 on the longitudinal center side opposite to the fifth face portion 40A5 toward the fifth face portion 40A5.

[0120] like Fig. 9B As shown, the convex portion K of the fifth face portion 40A5 covers each protrusion 31D1 of the plurality of second lead portions 31D located in the center of the height direction T among the plurality of third lead portions 31D exposed on the second side surface WS2 of the stacked body 10. Moreover, the convex portion K of the fifth face portion 40A5 is connected to the plurality of protrusions 31D1. In addition, the convex portion K of the tenth face portion 40B5 covers each protrusion 32D1 of the plurality of sixth lead portions 32D located in the center of the height direction T among the plurality of sixth lead portions 32D exposed on the second side surface WS2 of the stacked body 10. Moreover, the convex portion K of the tenth face portion 40B5 is connected to the plurality of protrusions 32D1.

[0121] As described above, in the multilayer ceramic capacitor 1 of the present embodiment, the fourth face 40A4 and the ninth face 40B4 arranged on the first side surface WS1 and the fifth face 40A5 and the tenth face 40B5 arranged on the second side surface WS2 of each external electrode each have a convex portion K. Thus, when the amount of solder becomes more than necessary when the external electrodes are soldered to the substrate and mounted, the excess amount of solder can flow to the convex portion K, so that the amount of solder between the external electrode and the substrate can be made into an amount suitable for mounting. That is, the convex portion K becomes a so-called escape path for the solder, and the excess solder is captured by the convex portion K. As a result, an effect that the mountability of the multilayer ceramic capacitor 1 can be stabilized can be obtained.

[0122] The convex portion K of the fourth face portion 40A4 is preferably arranged at the center of the fourth face portion 40A4 in the height direction T. The convex portion K of the fifth face portion 40A5 is preferably arranged at the center of the fifth face portion 40A5 in the height direction T. The convex portion K of the ninth face portion 40B4 is preferably arranged at the center of the ninth face portion 40B4 in the height direction T. The convex portion K of the tenth face portion 40B5 is preferably arranged at the center of the tenth face portion 40B5 in the height direction T. Thus, the above-mentioned effects can be made more significant.

[0123] The dimension of each convex portion K in the height direction T is preferably not less than 10% and not more than 90% of the dimension in the height direction T. Thereby, the above-mentioned effect can be made more remarkable.

[0124] The dimension of each convex portion K in the longitudinal direction L is preferably not less than 2% and not more than 18% of the dimension in the longitudinal direction L. Thereby, the above-mentioned effect can be made more remarkable.

[0125] The dimension of the height direction T of each convex portion K arranged on the fourth face portion 40A4 and the fifth face portion 40A5 is measured by a microscope at a position 1 / 2 of the length direction L of each convex portion K arranged on the fourth face portion 40A4 and the fifth face portion 40A5 when observed from the first side surface WS1 of the stacked body 10. Similarly, the dimension of the height direction T of each convex portion K arranged on the ninth face portion 40B4 and the tenth face portion 40B5 is measured by a microscope at a position 1 / 2 of the length direction L of each convex portion K arranged on the ninth face portion 40B4 and the tenth face portion 40B5 when observed from the second side surface WS2 of the stacked body 10.

[0126] The dimension of the length direction L of each convex portion K arranged on the fourth face portion 40A4 and the fifth face portion 40A5 is measured by a microscope at a position 1 / 2 of the height direction T of each convex portion K arranged on the fourth face portion 40A4 and the fifth face portion 40A5 when observed from the first side surface WS1 of the stacked body 10. Similarly, the dimension of the length direction L of each convex portion K arranged on the ninth face portion 40B4 and the tenth face portion 40B5 is measured by a microscope at a position 1 / 2 of the height direction T of each convex portion K arranged on the ninth face portion 40B4 and the tenth face portion 40B5 when observed from the second side surface WS2 of the stacked body 10.

[0127] In addition, the shape of each convex portion K is not limited to a rectangular shape, and may be, for example, a polygonal shape, a semicircular arc shape, a semi-elliptical shape, or the like.

[0128] like Fig. 10AAs shown, the first external electrode 40A includes a first foundation electrode layer 50A and a first plating layer 60A disposed on the first foundation electrode layer 50A. The first foundation electrode layer 50A is disposed on the surface of the laminate 10. The first plating layer 60A is disposed to cover the first foundation electrode layer 50A.

[0129] like Fig. 10B As shown, the second external electrode 40B includes a second foundation electrode layer 50B and a second plating layer 60B disposed on the second foundation electrode layer 50B. The second foundation electrode layer 50B is disposed on the surface of the laminate 10. The second plating layer 60B is disposed to cover the second foundation electrode layer 50B.

[0130] The first foundation electrode layer 50A and the second foundation electrode layer 50B include at least one selected from a baked layer, a thin film layer, and the like.

[0131] In the present embodiment, the first foundation electrode layer 50A and the second foundation electrode layer 50B are thin film layers. The thin film layer is a layer where metal particles are deposited.

[0132] When the first foundation electrode layer 50A and the second foundation electrode layer 50B are formed by thin film layers, they are preferably formed by a thin film forming method such as sputtering or vapor deposition. Here, a sputtering electrode formed by sputtering will be described.

[0133] The first base electrode layer 50A of the present embodiment is composed of a first thin film layer 51A formed by a sputtering electrode. The second base electrode layer 50B is composed of a second thin film layer 51B formed by a sputtering electrode. When the base electrode layer is formed by a sputtering electrode, it is preferable to directly form the sputtering electrode on the first main surface TS1 and the second main surface TS2 of the stacked body 10.

[0134] like Figure 6 , Fig. 10A As shown in FIG. 1 , the first thin film layer 51A formed by the sputtered electrode is arranged on a portion of the first end face LS1 side on the first main surface TS1 and a portion of the first end face LS1 side on the second main surface TS2. Specifically, the first thin film layer 51A is preferably arranged on the first main surface TS1. Figure 4 The first thin film layer 51A is preferably arranged on the second main surface TS2 and is covered by the first external electrode 40A. Figure 5 The portion covered by the first external electrode 40A is shown.

[0135] Furthermore, if Fig. 9AAs shown, the first thin film layer 51A is preferably configured on a portion of the first main surface TS1 and is configured to be slightly surrounded from a portion of the first main surface TS1 to a portion of the first side surface WS1. The first thin film layer 51A is preferably configured on a portion of the second main surface TS2 and is configured to be slightly surrounded from a portion of the second main surface TS2 to a portion of the first side surface WS1.

[0136] In addition, if Fig. 9B As shown, similarly to the first side surface WS1 side, on the second side surface WS2 side, the first thin film layer 51A is also preferably configured on a portion of the first main surface TS1 and is configured to be slightly surrounded from a portion on the first main surface TS1 to a portion of the second side surface WS2 continuously. In addition, the first thin film layer 51A is also preferably configured on a portion of the second main surface TS2 and is configured to be slightly surrounded from a portion on the second main surface TS2 to a portion of the second side surface WS2 continuously.

[0137] For example, when a chamfered portion such as a rounded corner is formed on the ridgeline portion of the stacked body 10, the first thin film layer 51A is preferably arranged on a portion of the first end face LS1 side of the first main surface TS1, and the chamfered portion of the first side face WS1 side continuous with the portion, and the chamfered portion of the second side face WS2 side. The first thin film layer 51A is preferably arranged on a portion of the first end face LS1 side of the second main surface TS2, and the chamfered portion of the first side face WS1 side continuous with the portion, and the chamfered portion of the second side face WS2 side. In this case, it is easy to form the thin film layer by sputtering or the like.

[0138] By the above method, when forming the plating layer, the distance between the first thin film layer 51A disposed on a portion of the first side surface WS1 and a portion of the second side surface WS2 and the internal electrode layer 30 exposed on the first side surface WS1 and the second side surface WS2 can be controlled. Therefore, the plating layer can also be easily deposited on the surface of the stacked body 10 between the first thin film layer 51A disposed on a portion of the first side surface WS1 and a portion of the second side surface WS2 and the internal electrode layer 30 exposed on the first side surface WS1 and the second side surface WS2.

[0139] like Figure 6 , Fig. 10B As shown in FIG. 1 , the second thin film layer 51B formed by the sputtered electrode is arranged on a portion of the first main surface TS1 on the second end surface LS2 side and a portion of the second main surface TS2 on the second end surface LS2 side. Specifically, the second thin film layer 51B is preferably arranged on the first main surface TS1 and on the second end surface LS2 side. Figure 4 The second thin film layer 51B is preferably arranged on the second main surface TS2 and is covered by the second external electrode 40B. Figure 5 The portion covered by the second external electrode 40B is shown.

[0140] Furthermore, if Fig. 9A As shown, the second thin film layer 51B is preferably configured on a portion of the first main surface TS1 and is configured to be slightly surrounded from a portion on the first main surface TS1 to a portion of the first side surface WS1. The second thin film layer 51B is preferably configured on a portion of the second main surface TS2 and is configured to be slightly surrounded from a portion on the second main surface TS2 to a portion of the first side surface WS1.

[0141] In addition, if Fig. 9B As shown, similarly to the first side surface WS1 side, on the second side surface WS2 side, the second thin film layer 51B is also preferably configured on a portion of the first main surface TS1 and is configured to be slightly surrounded from a portion on the first main surface TS1 to a portion of the second side surface WS2 continuously. In addition, the second thin film layer 51B is also preferably configured on a portion of the second main surface TS2 and is configured to be slightly surrounded from a portion on the second main surface TS2 to a portion of the second side surface WS2 continuously.

[0142] For example, when a chamfered portion such as a rounded corner is formed on the ridgeline portion of the stacked body 10, the second thin film layer 51B is preferably arranged on a portion of the first main surface TS1 on the second end surface LS2 side, and the chamfered portion of the first side surface WS1 side and the chamfered portion of the second side surface WS2 side continuous with the portion. The second thin film layer 51B is preferably arranged on a portion of the second main surface TS2 on the second end surface LS2 side, and the chamfered portion of the first side surface WS1 side and the chamfered portion of the second side surface WS2 side continuous with the portion. In this case, it is easy to form the thin film layer by sputtering or the like.

[0143] The longitudinal center sides of the second lead portion 31C and the third lead portion 31D located in the center portion in the height direction T protrude toward the longitudinal center side compared to the end portions on the longitudinal center side of the first thin film layer 51A arranged on the first main surface TS1 and the end portions on the longitudinal center side of the first thin film layer 51A arranged on the second main surface TS2. Similarly, the longitudinal center sides of the fifth lead portion 32C and the sixth lead portion 32D located in the center portion in the height direction T protrude toward the longitudinal center side compared to the end portions on the longitudinal center side of the second thin film layer 51B arranged on the first main surface TS1 and the end portions on the longitudinal center side of the second thin film layer 51B arranged on the second main surface TS2.

[0144] By the above method, when forming the plating layer, the distance between the second thin film layer 51B arranged on a portion of the first side surface WS1 and a portion of the second side surface WS2 and the internal electrode layer 30 exposed on the first side surface WS1 and the second side surface WS2 can be controlled. Therefore, it is also easy to deposit the plating layer on the surface of the stacked body 10 between the second thin film layer 51B arranged on a portion of the first side surface WS1 and a portion of the second side surface WS2 and the internal electrode layer 30 exposed on the first side surface WS1 and the second side surface WS2.

[0145] The thin film layer formed by the sputtering electrode preferably contains at least one metal selected from the group consisting of Mg, Al, Ti, W, Cr, Cu, Ni, Ag, Co, Mo and V. This can improve the fixing force of the external electrode 40 to the stacked body 10. The thin film layer may be a single layer or may be formed of multiple layers. For example, it may be formed of a two-layer structure of a Ni-Cr alloy layer and a Ni-Cu alloy layer.

[0146] The thickness of the sputtering electrode in the lamination direction connecting the first main surface TS1 and the second main surface TS2 is preferably 50 nm to 400 nm, and more preferably 50 nm to 130 nm.

[0147] In the case where a sputtering electrode is directly formed on the first main surface TS1 and the second main surface TS2 of the stacked body 10 to configure a base electrode layer, it is preferred to form a base electrode layer of a sintered layer on the first end surface LS1 and the second end surface LS2, or to directly form a plating layer described later without forming a base electrode layer. In the present embodiment, a plating layer described later is directly formed on the first end surface LS1 and the second end surface LS2 without forming a base electrode layer.

[0148] In addition, as described later in the modification, the first base electrode layer 50A and the second base electrode layer 50B may also be sintered layers. The sintered layer preferably contains a metal component and either a glass component or a ceramic component, or contains both of them. The metal component, for example, contains at least one selected from Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. The glass component, for example, contains at least one selected from B, Si, Ba, Mg, Al, Li, etc. The ceramic component may use the same type of ceramic material as the dielectric layer 20, or a ceramic material of a different type from the dielectric layer 20. The ceramic component, for example, contains at least one selected from BaTiO3, CaTiO3, (Ba, Ca)TiO3, SrTiO3, CaZrO3, etc.

[0149] The sintered layer is, for example, a sintered layer obtained by applying a conductive paste containing glass and metal to the stacked body 10 and sintering it. The sintered layer may be a sintered layer obtained by simultaneously sintering a stacked chip having an internal electrode layer and a dielectric layer and a conductive paste applied to the stacked chip, or a sintered layer obtained by sintering a stacked chip having an internal electrode layer and a dielectric layer, and then applying a conductive paste to the stacked body 10 and sintering it. In addition, when the stacked chip having an internal electrode layer and a dielectric layer and the conductive paste applied to the stacked chip are sintered simultaneously, the sintered layer is preferably formed by sintering a paste to which a ceramic material is added instead of a glass component. In this case, as the added ceramic material, it is particularly preferred to use a ceramic material of the same type as the dielectric layer 20. The sintered layer may also be a multilayer.

[0150] Alternatively, a configuration may be adopted in which the first and second base electrode layers 50A and 50B are not provided, and the first and second plated layers 60A and 60B described below are directly disposed on the laminate 10 .

[0151] The first plating layer 60A is arranged to cover the first base electrode layer 50A.

[0152] The second plating layer 60B is arranged to cover the second base electrode layer 50B.

[0153] The first plating layer 60A and the second plating layer 60B may include at least one selected from, for example, Cu, Ni, Sn, Ag, Pd, Ag-Pd alloy, Au, etc. The first plating layer 60A and the second plating layer 60B may each be formed of a plurality of layers.

[0154] When the base electrode layer is formed by a thin film layer, the plating layer is preferably formed by a three-layer structure of a Cu plating layer as a lower plating layer, a Ni plating layer as a middle plating layer, and a Sn plating layer as an upper plating layer. That is, the first plating layer 60A preferably has a first Cu plating layer 61A, a first Ni plating layer 62A, and a first Sn plating layer 63A. The second plating layer 60B preferably has a second Cu plating layer 61B, a second Ni plating layer 62B, and a second Sn plating layer 63B. However, the first plating layer 60A and the second plating layer 60B are not limited to a three-layer structure, and may also be other layer structures.

[0155] The first Cu plating layer 61A is configured to cover the first end surface LS1 of the stack 10 and the first thin film layer 51A as the first base electrode layer 50A arranged on the first main surface TS1 and the second main surface TS2 of the stack 10. In the present embodiment, the first Cu plating layer 61A is configured to also cover the exposed portion of the internal electrode layer 30 in the first side surface WS1 and the second side surface WS2 of the stack 10. At this time, the gap between the first thin film layer 51A and the internal electrode layer 30 exposed on the surface of the stack 10 and the gaps between the plurality of internal electrode layers 30 exposed on the surface of the stack 10 are formed narrow, so the plating layer is also deposited in the region of these gaps. Therefore, the above-mentioned opening H is formed on the fourth face 40A4 and the fifth face 40A5 of the first external electrode 40A.

[0156] The first Ni plating layer 62A is arranged to cover the first Cu plating layer 61A. The first Sn plating layer 63A is arranged to cover the first Ni plating layer 62A. In the present embodiment, the first plating layer 60A is directly electrically connected to the first internal electrode layer 31 .

[0157] The second Cu plating layer 61B is configured to cover the second end surface LS2 of the stack 10 and the second thin film layer 51B as the second base electrode layer 50B configured on the first main surface TS1 and the second main surface TS2 of the stack 10. In the present embodiment, the second Cu plating layer 61B is configured to also cover the exposed portion of the internal electrode layer 30 in the first side surface WS1 and the second side surface WS2 of the stack 10. At this time, the gap between the second thin film layer 51B and the internal electrode layer 30 exposed on the surface of the stack 10 and the gaps between the plurality of internal electrode layers 30 exposed on the surface of the stack 10 are formed narrow, so the plating layer is also deposited in the region of these gaps. Therefore, the above-mentioned opening H is formed on the 9th face portion 40B4 and the 10th face portion 40B5 of the second external electrode 40B.

[0158] The second Ni plating layer 62B is arranged so as to cover the second Cu plating layer 61B. The second Sn plating layer 63B is arranged so as to cover the second Ni plating layer 62B. In the present embodiment, the second plating layer 60B is directly electrically connected to the second internal electrode layer 32 .

[0159] By providing the plated layer including the Cu plated layer and the Ni plated layer to cover the base electrode layer, the base electrode layer is prevented from being corroded by the solder when mounting the multilayer ceramic capacitor 1. In addition, by further providing the Sn plated layer on the surface of the Ni plated layer, the wettability of the solder when mounting the multilayer ceramic capacitor 1 is improved. Thus, the multilayer ceramic capacitor 1 can be easily mounted.

[0160] The thickness of each layer of the plating layer is preferably 2 μm or more and 15 μm or less. That is, the average thickness of each of the first Cu plating layer 61A, the first Ni plating layer 62A, the first Sn plating layer 63A, the second Cu plating layer 61B, the second Ni plating layer 62B, and the second Sn plating layer 63B is preferably 2 μm or more and 15 μm or less. More specifically, the average thickness of each of the first Cu plating layer 61A and the second Cu plating layer 61B is more preferably 5 μm or more and 8 μm or less. In addition, the average thickness of each of the first Ni plating layer 62A, the first Sn plating layer 63A, the second Ni plating layer 62B, and the second Sn plating layer 63B is more preferably 2 μm or more and 4 μm or less.

[0161] In addition, if the dimension in the length direction of the first end surface LS1 and the second end surface LS2 of the multilayer ceramic capacitor 1 including the stack 10 and the external electrode 40 is set to L dimension, the L dimension is preferably 0.1 mm or more and 0.8 mm or less. In addition, if the dimension in the width direction of the first side surface WS1 and the second side surface WS2 of the multilayer ceramic capacitor 1 is set to W dimension, the W dimension is preferably 0.2 mm or more and 1.6 mm or less. In addition, if the dimension in the height direction of the first main surface TS1 and the second main surface TS2 of the multilayer ceramic capacitor 1 is set to T dimension, the T dimension is preferably 0.05 mm or more and 0.2 mm or less. The L dimension in the length direction of the multilayer ceramic capacitor 1 of the present embodiment is smaller than the W dimension in the width direction of the multilayer ceramic capacitor 1. In addition, in the present embodiment, the height direction of the first main surface TS1 and the second main surface TS2 of the multilayer ceramic capacitor 1 is the stacking direction of the dielectric layer 20 and the internal electrode layer 30.

[0162] As described above, regarding the multilayer ceramic capacitor 1 of the present embodiment, in the LW inversion type multilayer ceramic capacitor, the opening H exposing the surface of the stacked body 10 is formed on the fourth face 40A4 and the fifth face 40A5 of the first external electrode 40A and the ninth face 40B4 and the tenth face 40B5 of the second external electrode 40B. Thus, it is possible to suppress the deterioration of the self-alignment effect and perform stable mounting. The so-called self-alignment effect is an effect that the electronic component to be mounted supported by the molten solder moves and is positioned due to the force that reduces the surface area, i.e., surface tension, acting on the molten solder during soldering. Since this self-alignment effect can be obtained, it is possible to prevent positional deviation during mounting.

[0163] In addition, regarding the multilayer ceramic capacitor 1 of the present embodiment, in the LW reverse type multilayer ceramic capacitor, the fourth surface 40A4 and the fifth surface 40A5 of the first external electrode 40A and the ninth surface 40B4 and the tenth surface 40B5 of the second external electrode 40B have a convex portion K protruding toward the center side in the length direction L. Thus, when the amount of solder becomes more than necessary when soldering to the lands of the substrate to mount each external electrode, the excess amount of solder flows to the convex portion K, thereby making it possible to make the amount of solder between the first external electrode 40A and the second external electrode 40B and the lands an amount suitable for mounting. As a result, the mountability of the multilayer ceramic capacitor 1 can be stabilized.

[0164] Hereinafter, a modification of the layer structure of the external electrode 40 of the multilayer ceramic capacitor 1 of the present embodiment will be described. In the following description, the same reference numerals are used for the same structures as those in the above embodiment, and detailed description thereof will be omitted. Fig.11A as well as Fig. 11B is a cross-sectional view showing a modified example of the layer structure of the external electrode 40 of the multilayer ceramic capacitor 1 according to the present embodiment, and is similar to Fig. 10A as well as Fig. 10B The corresponding figure.

[0165] In this modification, the structure of the external electrode 40 is different from that of the above-described embodiment.

[0166] The first external electrode 40A includes a first base electrode layer 50A and a first plated layer 60A. The first base electrode layer 50A of this modification example is composed of a first sintered layer 52A. The first plated layer 60A of this modification example includes a first Ni plated layer 62A and a first Sn plated layer 63A.

[0167] The second external electrode 40B includes a second base electrode layer 50B and a second plated layer 60B. The second base electrode layer 50B of this modification example is composed of a second sintered layer 52B. The second plated layer 60B of this modification example includes a second Ni plated layer 62B and a second Sn plated layer 63B.

[0168] In this modification, the first base electrode layer 50A has, for example, a first face portion located on the first end surface LS1, a second face portion located on a portion of the first main surface TS1, a third face portion located on a portion of the second main surface TS2, a fourth face portion located on a portion of the first side surface WS1, and a fifth face portion located on a portion of the second side surface WS2, similarly to the first external electrode 40A described above. In addition, openings corresponding to the aforementioned openings H are formed in the fourth and fifth face portions of the first base electrode layer 50A. In addition, in this modification, the first base electrode layer 50A is connected to the first internal electrode layer 31.

[0169] The first Ni plating layer 62A is arranged to cover the first base electrode layer 50A. The first Sn plating layer 63A is arranged to cover the first Ni plating layer 62A.

[0170] In this modification, the second base electrode layer 50B has, for example, a sixth face portion located on the second end surface LS2, a seventh face portion located on a portion of the first main surface TS1, an eighth face portion located on a portion of the second main surface TS2, a ninth face portion located on a portion of the first side surface WS1, and a tenth face portion located on a portion of the second side surface WS2, similarly to the second external electrode 40B described above. In addition, openings corresponding to the aforementioned openings H are formed in the ninth and tenth face portions of the second base electrode layer 50B. In this modification, the second base electrode layer 50B is connected to the second internal electrode layer 32.

[0171] The second Ni plating layer 62B is arranged to cover the second base electrode layer 50B. The second Sn plating layer 63B is arranged to cover the second Ni plating layer 62B.

[0172] The first sintered layer 52A constituting the first base electrode layer 50A and the second sintered layer 52B constituting the second base electrode layer 50B may be, for example, sintered layers obtained by applying a conductive paste containing glass and metal to the laminate and sintering it. In addition, when the laminated small pieces before sintering and the conductive paste applied to the laminated small pieces are sintered at the same time, the sintered layers are preferably formed by sintering a paste to which a ceramic material is added instead of a glass component. At this time, as the added ceramic material, it is particularly preferred to use a ceramic material of the same type as the dielectric layer 20.

[0173] When the base electrode layer is formed of a sintered layer, the first plating layer 60A and the second plating layer 60B are preferably a two-layer structure in which a Sn plating layer is formed on a Ni plating layer. In this case, the Ni plating layer prevents the base electrode layer from being corroded by the solder when mounting the multilayer ceramic capacitor 1. In addition, the Sn plating layer improves the wettability of the solder when mounting the multilayer ceramic capacitor 1. As a result, it becomes easy to mount the multilayer ceramic capacitor 1.

[0174] In addition, the first plating layer 60A and the second plating layer 60B are not limited to a two-layer structure, and may be formed of a three-layer structure including Cu plating as in the above-described embodiment, or may have other layer structures.

[0175] The thickness of each plating layer is preferably 2 μm or more and 15 μm or less. That is, the average thickness of each of the first Ni plating layer 62A, the first Sn plating layer 63A, the second Ni plating layer 62B, and the second Sn plating layer 63B is preferably 2 μm or more and 15 μm or less. More specifically, the average thickness of each of the first Ni plating layer 62A, the first Sn plating layer 63A, the second Ni plating layer 62B, and the second Sn plating layer 63B is more preferably 2 μm or more and 4 μm or less.

[0176] Next, a method for manufacturing the multilayer ceramic capacitor 1 according to the present embodiment will be described.

[0177] A dielectric sheet for the dielectric layer 20 and a conductive paste for the internal electrode layer 30 are prepared. The conductive paste for the dielectric sheet and the internal electrode contains a binder and a solvent. The binder and the solvent may be known binders and solvents. The paste containing the conductive material is, for example, a paste in which an organic binder and an organic solvent are added to metal powder.

[0178] On the dielectric sheet, for example, a conductive paste for the internal electrode layer 30 is printed by screen printing, gravure printing, etc., using a printing plate whose pattern is designed to form the shape of the internal electrode layer 30 of the present embodiment. Thus, a dielectric sheet having a pattern of the first internal electrode layer 31 and a dielectric sheet having a pattern of the second internal electrode layer 32 are prepared. Here, the size of the opening H can be adjusted by controlling the interval between the first lead portion 31B and the second lead portion 31C and the third lead portion 31D, and the interval between the fourth lead portion 32B and the fifth lead portion 32C and the sixth lead portion 32D.

[0179] The conductive paste for the first internal electrode layer 31 is printed so that the length L of the plurality of second lead portions 31C and the third lead portion 31D located in the center of the height direction T becomes longer than the length L of the plurality of second lead portions 31C and the third lead portion 31D located outside the center of the height direction T, thereby forming the protrusion 31C1 and the protrusion 31D1. Thus, when the first external electrode 40A is formed, the protrusion K can be formed. Furthermore, the conductive paste for the second internal electrode layer 32 is printed so that the length L of the plurality of fifth lead portions 32C and the sixth lead portion 32D located in the center of the height direction T becomes longer than the length L of the plurality of second lead portions 32C and the sixth lead portion 32D located outside the center of the height direction T, thereby forming the protrusion 32C1 and the protrusion 32D1. Thus, when the second external electrode 40B is formed, the protrusion K can be formed.

[0180] In addition, by adjusting the dimensions in the length direction L and the position in the height direction T of the parts corresponding to the convex portion K at this time, namely the protrusion 31C1, protrusion 31D1, protrusion 32C1 and protrusion 32D1, the dimension in the length direction L and the position in the height direction T of the convex portion K can be controlled.

[0181] By stacking a predetermined number of dielectric sheets on which the pattern of the internal electrode layer is not printed, a portion of the first main surface side outer layer portion 12 on the first main surface TS1 side is formed. By alternately stacking dielectric sheets on which the pattern of the first internal electrode layer 31 is printed and dielectric sheets on which the pattern of the second internal electrode layer 32 is printed, a portion of the inner layer portion 11 is formed. By stacking a predetermined number of dielectric sheets on which the pattern of the internal electrode layer is not printed on the portion that is to become the inner layer portion 11, a portion of the second main surface side outer layer portion 13 on the second main surface TS2 side is formed. In this way, a laminated sheet is produced.

[0182] The laminated sheets are pressed in the lamination direction by isostatic pressing or the like, thereby producing a laminated block.

[0183] The stacked blocks are cut into predetermined sizes to produce stacked small pieces. At this time, the corners and ridges of the stacked small pieces may be rounded by barrel grinding or the like.

[0184] The stacked small pieces are fired to produce the stacked body 10. The firing temperature depends on the materials of the dielectric layer 20 and the internal electrode layer 30, but is preferably 900°C or higher and 1400°C or lower.

[0185] In this embodiment, the base electrode layer is formed by a thin film layer. When the base electrode layer is formed by a thin film layer, the thin film layer is formed on a portion of the laminate 10 where an external electrode is to be formed by masking or the like. The thin film layer is formed by a thin film forming method such as sputtering or evaporation. In this embodiment, a sputtering electrode as a thin film layer is formed by sputtering.

[0186] Figure 12 to Figure 14 1 is a diagram showing a state in the middle of the manufacturing process of the multilayer ceramic capacitor of the present embodiment, and is a diagram showing a state after the thin film layer is arranged on the multilayer body 10 and before the plating layer is arranged. Fig.12 1 is a diagram showing a state in which a first thin film layer 51A and a second thin film layer 51B as thin film layers are arranged in a laminate 10, and is similar to Figure 6 The LT section corresponds to the figure. Fig.13 1 is a diagram showing a state in which a first thin film layer 51A as a thin film layer is arranged in the laminate 10, and is similar to Figure 7 The WT cross section corresponds to Fig. Fig.141 is a diagram showing a state where the first thin film layer 51A and the second thin film layer 51B are arranged in the laminate 10, and Fig. 9A The corresponding figure is a view of the surface of the first side surface WS1 of the stacked body 10 .

[0187] The first thin film layer 51A formed by the sputtering electrode is arranged on a portion of the first end face LS1 side on the first main surface TS1 and a portion of the first end face LS1 side on the second main surface TS2. The second thin film layer 51B formed by the sputtering electrode is arranged on a portion of the second end face LS2 side on the first main surface TS1 and a portion of the second end face LS2 side on the second main surface TS2.

[0188] In the present embodiment, the thin film layer formed by the sputtering electrode is arranged on a portion of the first main surface TS1 and a portion of the second main surface TS2 and is arranged to slightly surround a portion of the first side surface WS1 and a portion of the second side surface WS2 continuously from a portion of the first main surface TS1 and a portion of the second main surface TS2. Thus, the distance between the thin film layer arranged on a portion of the first side surface WS1 and a portion of the second side surface WS2 and the internal electrode film exposed on the first side surface WS1 and the second side surface WS2 can be controlled. Therefore, a plating layer can also be deposited on the surface of the stacked body 10 between the thin film layer arranged on a portion of the first side surface WS1 and a portion of the second side surface WS2 and the internal electrode layer exposed on the first side surface WS1 and the second side surface WS2.

[0189] Then, a plating layer is formed on the surface of the base electrode layer including the thin film layer and the laminate. In this embodiment, a three-layer plating layer of a Cu plating layer, a Ni plating layer, and a Sn plating layer is formed as the plating layer.

[0190] When forming the plated layer, it is formed by electrolytic plating. As the plating method, barrel plating is preferably used.

[0191] Here, when the thin film layer is formed to also wrap around a portion on the first side WS1 and a portion on the second side WS2, it is possible to control the distance between the thin film layer and the internal electrode layer exposed on the first side WS1 and the second side WS2 of the stacked body 10. Therefore, it is also easy to deposit a plating layer on the surface of the stacked body 10 between the thin film layer arranged on a portion on the first side WS1 and a portion on the second side WS2 and the internal electrode layer exposed on the first side WS1 and the second side WS2.

[0192] In addition, the plating layer is configured to cover the exposed portion of the internal electrode layer in the first side surface WS1 and the second side surface WS2 of the stack 10. At this time, the gap between the thin film layer and the internal electrode layer exposed on the surface of the stack 10, and the gaps between the multiple internal electrode layers exposed on the surface of the stack 10 are formed narrow, so the plating layer is also deposited in the region of these gaps. Thus, the plating layer is formed in the portion other than the opening H in this embodiment.

[0193] In addition, for example, when the area of ​​the opening H is small and it is difficult to control the formation of the plating layer, the plating layer may be formed by performing masking at the location where the opening is provided. This makes it easier to form the opening H.

[0194] In addition, when the base electrode layer is formed by a sintered layer, a conductive paste that becomes the first base electrode layer is applied to the first face portion located on the first end face LS1 of the stack 10, the second face portion located on a portion of the first main surface TS1, the third face portion located on a portion of the second main surface TS2, the fourth face portion located on a portion of the first side surface WS1, and the fifth face portion located on a portion of the second side surface WS2. In addition, a conductive paste that becomes the second base electrode layer is applied to the sixth face portion located on the second end face LS2 of the stack 10, the seventh face portion located on a portion of the first main surface TS1, the eighth face portion located on a portion of the second main surface TS2, the ninth face portion located on a portion of the first side surface WS1, and the tenth face portion located on a portion of the second side surface WS2 on the second end face LS2 of the stack 10.

[0195] In addition, masking is performed in advance on the portion where the base electrode layer is not to be formed, such as the portion to be the opening H. After masking, a conductive paste containing a glass component and a metal is applied to the laminate 10 by a method such as dipping or screen printing. Then, a sintering treatment is performed to form the base electrode layer. The temperature of the sintering treatment at this time is preferably 700° C. or more and 900° C. or less.

[0196] In addition, when the stacked small pieces before firing and the conductive paste applied to the stacked small pieces are fired at the same time, the sintered layer is preferably formed by firing a paste to which a ceramic material is added instead of a glass component. In this case, as the added ceramic material, it is particularly preferred to use a ceramic material of the same type as the dielectric layer 20. In this case, the conductive paste is applied to the stacked small pieces before firing, and the stacked small pieces and the conductive paste applied to the stacked small pieces are fired at the same time, thereby forming a stacked body 10 formed with a sintered layer.

[0197] Then, a plating layer is formed on the surface of the base electrode layer including the sintered layer and the laminate 10. When the base electrode layer is formed by the sintered layer, a two-layer plating layer of, for example, a Ni plating layer and a Sn plating layer is formed as the plating layer. When forming the plating layer, it is formed by an electrolytic plating method. As the plating method, preferably, drum plating is used.

[0198] Furthermore, for example, when the area of ​​the opening H is small and it is difficult to control the formation of the plating layer, the plating layer may be formed by performing masking at the location where the opening H is provided. This makes it easier to form the opening H.

[0199] Through such manufacturing steps, the multilayer ceramic capacitor 1 can be manufactured.

[0200] In addition, the structure of the external electrode 40 is not limited to the above-mentioned structure. Hereinafter, a modification of the arrangement position of the external electrode 40 of the multilayer ceramic capacitor 1 of this embodiment will be described. In addition, in the following description, the same reference numerals are used for the same structure as the above-mentioned embodiment, and detailed description thereof will be omitted. Fig.15 is a cross-sectional view showing a modified example of the arrangement position of the external electrode 40 of the multilayer ceramic capacitor 1 according to the present embodiment, and is similar to Figure 1 The corresponding figure.

[0201] In this modification, the arrangement position of the external electrode 40 is different from that of the above-mentioned embodiment. In this modification, the first external electrode 40A and the second external electrode 40B are arranged only on either the first main surface TS1 or the second main surface TS2.

[0202] For example, the first external electrode 40A of the present modification example includes a first face portion 40A1 located on the first end surface LS1, a third face portion 40A3 located as a portion on the second main surface TS2, a fourth face portion 40A4 located as a portion on the first side surface WS1, and a fifth face portion 40A5 located as a portion on the second side surface WS2. That is, the first external electrode 40A of the present modification example is not formed on the first main surface TS1.

[0203] For example, the second external electrode 40B of this modification example has a sixth face 40B1 located on the second end face LS2, an eighth face 40B3 located on a portion of the second main surface TS2, a ninth face 40B4 located on a portion of the first side surface WS1, and a tenth face 40B5 located on a portion of the second side surface WS2. That is, the second external electrode 40B of this modification example is not formed on the first main surface TS1.

[0204] Further, similarly to the above-described embodiment, the fourth surface portion 40A4 and the fifth surface portion 40A5 of the first external electrode 40A and the ninth surface portion 40B4 and the tenth surface portion 40B5 of the second external electrode 40B in this modification have openings H that expose the surface of the stacked body 10 .

[0205] With such a structure, it is also possible to suppress the deterioration of the self-alignment effect and perform stable mounting. Furthermore, by not configuring the first external electrode 40A and the second external electrode 40B on either the first main surface TS1 or the second main surface TS2, the dimension of the height direction T of the multilayer ceramic capacitor 1 can be reduced, and the height of the multilayer ceramic capacitor 1 can be further reduced. In addition, by not configuring the first external electrode 40A and the second external electrode 40B on either the first main surface TS1 or the second main surface TS2, the height dimension of the multilayer body 10 can be ensured according to the thickness of the external electrode 40. Therefore, the volume of the effective layer portion of the multilayer body 10 can be increased, and the capacity of the multilayer ceramic capacitor 1 can be increased.

[0206] According to the multilayer ceramic capacitor 1 of the present embodiment, the following effects are achieved.

[0207] (1) The multilayer ceramic capacitor 1 of the present embodiment comprises: a multilayer body 10 having a plurality of laminated dielectric layers 20 and a plurality of internal electrode layers 30 laminated on the dielectric layers 20, and having a first main surface TS1 and a second main surface TS2 opposite to each other in the height direction, a first end surface LS1 and a second end surface LS2 opposite to each other in the length direction perpendicular to the height direction, and a first side surface WS1 and a second side surface WS2 opposite to each other in the width direction perpendicular to the height direction and the length direction; and a first external electrode 40A , having at least any one of a first face portion 40A1 located on the first end face LS1, a second face portion 40A2 located on a portion of the first main surface TS1, and a third face portion 40A3 located on a portion of the second main surface TS2, a fourth face portion 40A4 located on a portion of the first side surface WS1, and a fifth face portion 40A5 located on a portion of the second side surface WS2; and a second external electrode 40B, having a sixth face portion 40B1 located on the second end face LS2, a fourth face portion 40A4 located on a portion of the first side surface WS1, and a fifth face portion 40A5 located on a portion of the second side surface WS2 At least one of the 7th face 40B2 and the 8th face 40B3 located on the second main surface TS2, the 9th face 40B4 located on the first side surface WS1, and the 10th face 40B5 located on the second side surface WS2, wherein the length of the stacked body 10 in the longitudinal direction connecting the first end surface LS1 and the second end surface LS2 is set to l, the length in the width direction connecting the first side surface WS1 and the second side surface WS2 is set to w, and the length in the width direction connecting the first main surface TS1 and the second main surface TS2 is set to When the length of the height direction of the surface TS2 is t, the dimensional relationship is w>l>t, and the fourth surface 40A4 and the fifth surface 40A5 and the ninth surface 40B4 and the tenth surface 40B5 have an opening H that exposes the surface of the stacked body 10, and the fourth surface 40A4 and the ninth surface 40B4 arranged in the length direction L and the fifth surface 40A5 and the tenth surface 40B5 arranged in the length direction L each have a convex portion K protruding from the longitudinal center side facing each other toward the longitudinal direction L. Thus, it is possible to provide an LW inversion type laminated ceramic capacitor that can suppress the deterioration of the self-alignment effect and perform stable mounting.

[0208] (2) In the multilayer ceramic capacitor 1 of the present embodiment, the projection K is disposed at the center of the fourth and fifth surface portions 40A4 and 40A5 and the ninth and tenth surface portions 40B4 and 40B5 in the height direction T. This makes the above-described effects more significant.

[0209] (3) In the multilayer ceramic capacitor 1 of the present embodiment, the dimension of the protrusion K in the height direction T is not less than 10% and not more than 90% of the dimension in the height direction T. This makes the above-mentioned effect more remarkable.

[0210] (4) In the multilayer ceramic capacitor 1 of the present embodiment, the dimension of the protrusion K in the longitudinal direction L is 2% to 18% of the dimension in the longitudinal direction L. This makes the above-mentioned effect more remarkable.

[0211] (5) In the multilayer ceramic capacitor 1 of the present embodiment, the internal electrode layer 30 includes a first internal electrode layer 31 and a second internal electrode layer 32, and the first internal electrode layer 31 includes a first opposing electrode portion 31A located inside the multilayer body 10, a first lead portion 31B connected to the first opposing electrode portion 31A and exposed at the first end surface LS1, a portion of the first side surface WS1, and a portion of the second side surface WS2, and a gap is formed between the first lead portion 31B and the portion of the first lead portion 31B led to the first side surface WS1. The second internal electrode layer 32 includes a second lead portion 31C connected to the first opposing electrode portion 31A and exposed at a portion of the first side surface WS1, and a third lead portion 31D spaced apart from the portion of the first lead portion 31B led to the second side surface WS2 and connected to the first opposing electrode portion 31A and exposed at a portion of the second side surface WS2. The second internal electrode layer 32 includes a second opposing electrode portion 32A located inside the stack 10, and a third lead portion 31C connected to the first opposing electrode portion 31A and exposed at a portion of the first side surface WS1. 1 and a portion of the second side WS2, the fourth lead portion 32B is exposed, the fifth lead portion 32C is spaced apart from the portion of the fourth lead portion 32B led to the first side WS1 and connected to the second opposing electrode portion 32A and exposed on a portion of the first side WS1, and the sixth lead portion 32D is spaced apart from the portion of the fourth lead portion 32B led to the second side WS2 and connected to the second opposing electrode portion 32A and exposed on a portion of the second side WS2, and is located at a height of The second lead portion 31C and the third lead portion 31D at the center of the direction T have a longer dimension in the length direction L than the second lead portion 31C and the third lead portion 31D located outside the center of the height direction T, and the fifth lead portion 32C and the sixth lead portion 32D located at the center of the height direction T have a longer dimension in the length direction L than the fifth lead portion 32C and the sixth lead portion 32D located outside the center of the height direction T. Thus, the convex portion K protruding from the center of the length direction of the fourth surface portion 40A4 and the ninth surface portion 40B4 facing each other in the length direction L and the convex portion K protruding from the center of the length direction of the fifth surface portion 40A5 and the tenth surface portion 40B5 facing each other in the length direction L can be easily formed. Furthermore, the distance between the second lead portion 31C of the first internal electrode layer 31 and the fifth lead portion 32C of the second external electrode 40B, and the distance between the third lead portion 31D of the first internal electrode layer 31 and the sixth lead portion 32D of the second external electrode 40B can be shortened, thereby shortening the path of the current flow. Therefore, ESL can be reduced.

[0212] (6) In the multilayer ceramic capacitor 1 of the present embodiment, the longitudinal center side of the second lead portion 31C and the third lead portion 31D located in the center of the height direction T protrudes toward the longitudinal center side relative to the end portion 40A9 located in the longitudinal center side of the second face portion 40A2 and the third face portion 40A3, and the longitudinal center side of the fifth lead portion 32C and the sixth lead portion 32D located in the center of the height direction T protrudes toward the longitudinal center side relative to the end portion 40B9 located in the longitudinal center side of the seventh face portion 40B2 and the eighth face portion 40B3. As a result, the distance between the second lead portion 31C of the first internal electrode layer 31 and the fifth lead portion 32C of the second external electrode 40B and the distance between the third lead portion 31D of the first internal electrode layer 31 and the sixth lead portion 32D of the second external electrode 40B can be shortened, thereby shortening the path through which current flows. As a result, ESL can be reduced.

[0213] (7) The opening H of the multilayer ceramic capacitor 1 of the present embodiment is disposed at the center of the fourth and fifth surface portions 40A4 and 40A5 and the ninth and tenth surface portions 40B4 and 40B5 in the height direction. Thus, the solder wets and climbs appropriately to surround the opening H.

[0214] (8) The opening H formed in the fourth surface portion 40A4 and the fifth surface portion 40A5 of the multilayer ceramic capacitor 1 of the present embodiment is arranged to be offset toward the first end surface LS1 relative to the center portion in the longitudinal direction of the fourth surface portion 40A4 and the fifth surface portion 40A5, and the opening H formed in the ninth surface portion 40B4 and the tenth surface portion 40B5 is arranged to be offset toward the second end surface LS2 relative to the center portion in the longitudinal direction of the ninth surface portion 40B4 and the tenth surface portion 40B5. Thus, the area for solder wetting and climbing can be appropriately ensured on both sides of the opening H.

[0215] (9) The area of ​​the opening H of the multilayer ceramic capacitor 1 of the present embodiment is 3% or more and 20% or less of the area of ​​each of the fourth surface portion 40A4 and the fifth surface portion 40A5 and the ninth surface portion 40B4 and the tenth surface portion 40B5 where the opening H is arranged. This can produce a self-alignment effect, and can make the effect of suppressing short-circuit failure caused by tilting and rotating the multilayer ceramic capacitor 1 more significant.

[0216] (10) The length t of the laminated body 10 connecting the first main surface TS1 and the second main surface TS2 in the height direction T of the laminated ceramic capacitor 1 of the present embodiment is 150 μm or less. In such a laminated ceramic capacitor with a reduced height, the effects of the present embodiment can be appropriately obtained.

[0217] (11) The length t in the height direction T connecting the first main surface TS1 and the second main surface TS2 of the laminated body 10 of the laminated ceramic capacitor 1 of the present embodiment is 100 μm or less. In such a laminated ceramic capacitor with a reduced height, the effects of the present embodiment can be appropriately obtained.

[0218] (12) The length t of the laminated body 10 in the height direction T connecting the first main surface TS1 and the second main surface TS2 of the laminated ceramic capacitor 1 of the present embodiment is 50 μm or less. In such a laminated ceramic capacitor with a reduced height, the effects of the present embodiment can be appropriately obtained.

[0219] (13) In the multilayer ceramic capacitor 1 of the present embodiment, the first lead portion 31B, the second lead portion 31C, and the third lead portion 31C are all connected to the first external electrode 40A, and the fourth lead portion 32B, the fifth lead portion 32C, and the sixth lead portion 32D are all connected to the second external electrode. Thus, the opening H exposing the surface of the multilayer body 10 can be formed in the fourth surface portion 40A4 and the fifth surface portion 40A5 and the ninth surface portion 40B4 and the tenth surface portion 40B5, and the ESL can be reduced.

[0220] (14) The first external electrode 40A of the multilayer ceramic capacitor 1 of the present embodiment includes a first base electrode layer 50A and a first plated layer 60A disposed on the first base electrode layer 50A, and the second external electrode 40B includes a second base electrode layer 50B and a second plated layer 60B disposed on the second base electrode layer 50B, and the first base electrode layer 50A and the second base electrode layer 50B are sputtered electrodes. Thus, the thickness of the external electrodes can be formed thin, and the thickness of the multilayer body 10 can be easily ensured, so that the capacitance and the strength of the multilayer body 10 can be ensured.

[0221] <Experimental example>

[0222] As samples of experimental examples, multilayer ceramic capacitors were produced and their mountability was evaluated.

[0223] First, as a sample of the embodiment, according to the above-mentioned manufacturing method, a Figure 1 to Figure 10B A multilayer ceramic capacitor 1 having the following specifications is shown. In addition, as a sample of Comparative Example 1, Fig.16A The multilayer ceramic capacitor 101 shown in FIG. 1 does not have an opening H and a protrusion K in the external electrodes 140 (the first external electrode 140A and the second external electrode 140B). Fig.17AThe illustrated multilayer ceramic capacitor 201 has no openings H and convex portions K in the external electrodes 240 (first external electrode 240A and second external electrode 240B) but has recesses R recessed from the edges of the external electrodes toward the end surface of the stack 10 .

[0224] Fig.16A is a perspective view of the appearance of a multilayer ceramic capacitor 101 of Comparative Example 1. Figure 1 The corresponding figure. Fig. 16B is a diagram showing the first internal electrode layer 131 of the multilayer ceramic capacitor 101 of Comparative Example 1, and is similar to Fig. 8A The corresponding figure. Fig. 16C is a diagram showing the second internal electrode layer 132 of the multilayer ceramic capacitor 101 of Comparative Example 1, and is similar to Figure 8B The corresponding figure. Fig.17A is a perspective view of the appearance of a multilayer ceramic capacitor 201 of Comparative Example 2. Figure 1 The corresponding figure. Fig. 17B is a diagram showing the first internal electrode layer 231 of the multilayer ceramic capacitor 201 of Comparative Example 2, and is similar to Fig. 8A The corresponding figure. Fig. 17C is a diagram showing the second internal electrode layer 232 of the multilayer ceramic capacitor 201 of Comparative Example 2, and is similar to Figure 8B In addition, Fig. 16B , Fig. 16C , Fig. 17B , Fig. 17C In the example, the external electrodes are omitted.

[0225] (Structure of Embodiment)

[0226] · Dimensions of multilayer ceramic capacitors: L×W×T=0.520mm×1.000mm×0.100mm

[0227] Ceramic material of dielectric layer: BaTiO3

[0228] Capacitance: 0.47μF

[0229] Rated voltage: 4V

[0230] Internal electrode material: Ni

[0231] Pattern of internal electrode layer: Fig. 8A , Figure 8B The pattern shown

[0232] ·Construction of external electrodes:

[0233] Base electrode layer: thin film layer (sputtered electrode)

[0234] Material of base electrode layer: 2-layer structure of NiCr layer and NiCu layer

[0235] Thickness of the underlying electrode layer: main surface thickness 0.2 μm (thickness of the underlying electrode layer disposed on the first main surface TS1 and the second main surface TS2 )

[0236] Plating layer: 3-layer structure of Cu plating, Ni plating, and Sn plating

[0237] Cu plating thickness: 5.5μm

[0238] Ni plating thickness: 2.5μm

[0239] Sn plating thickness: 3.2μm

[0240] Area ratio of the opening H of the 4th, 5th, 9th, and 10th surfaces where the laminate is exposed: 13%

[0241] Height dimension of the convex portion of the fourth surface and the convex portion of the fifth surface: 50% of the height dimension of the laminate

[0242] Height dimension of the convex portion of the 9th face portion and the convex portion of the 10th face portion: 50% of the height dimension of the laminate

[0243] The lengthwise dimension of the convex portion of the fourth face portion and the convex portion of the fifth face portion: 10% of the lengthwise dimension of the laminate

[0244] The lengthwise dimension of the convex portion of the 9th face portion and the convex portion of the 10th face portion: 10% of the lengthwise dimension of the laminate

[0245] (Structure of Comparative Example 1)

[0246] · Dimensions of multilayer ceramic capacitors: L×W×T=0.520mm×1.000mm×0.100mm

[0247] Ceramic material of dielectric layer: BaTiO3

[0248] Capacitance: 0.47μF

[0249] Rated voltage: 4V

[0250] Internal electrode material: Ni

[0251] Pattern of internal electrode layer: Fig. 16B , Fig. 16C The pattern shown

[0252] ·Construction of external electrodes:

[0253] Base electrode layer: A sintered layer on which a conductive paste is applied and sintered

[0254] Material of base electrode layer: Ni

[0255] Thickness of the underlying electrode layer: end surface thickness 10 μm, side surface thickness 5 μm, main surface thickness 5 μm (the thickness of the underlying electrode layer disposed on the first main surface TS1 and the second main surface TS2, respectively)

[0256] Plating layer: 3-layer structure of Cu plating, Ni plating, and Sn plating

[0257] Cu plating thickness: 5.5μm

[0258] Ni plating thickness: 2.5μm

[0259] Sn plating thickness: 3.2μm

[0260] (Structure of Comparative Example 2)

[0261] · Dimensions of multilayer ceramic capacitors: L×W×T=0.520mm×1.000mm×0.100mm

[0262] Ceramic material of dielectric layer: BaTiO3

[0263] Capacitance: 0.47μF

[0264] Rated voltage: 4V

[0265] Internal electrode material: Ni

[0266] Pattern of internal electrode layer: Fig. 17B , Fig. 17C The pattern shown

[0267] ·Construction of external electrodes:

[0268] Base electrode layer: thin film layer (sputtered electrode)

[0269] Material of base electrode layer: 2 layers of NiCr and NiCu

[0270] Thickness of the underlying electrode layer: main surface thickness 0.2 μm (thickness of the underlying electrode layer disposed on the first main surface TS1 and the second main surface TS2 )

[0271] Plating layer: 3-layer structure of Cu plating, Ni plating, and Sn plating

[0272] Cu plating thickness: 5.5μm

[0273] Ni plating thickness: 2.5μm

[0274] Sn plating thickness: 3.2μm

[0275] Next, the mountability was evaluated using the produced samples.

[0276] (Installation evaluation)

[0277] The mountability was evaluated using the samples of the example in which the area ratio of the opening H was 13% and the samples of Comparative Examples 1 and 2. The evaluation was performed using 100 samples respectively. Table 1 shows the results of the mountability evaluation.

[0278] [Table 1]

[0279]

[0280] In Comparative Example 1, eight samples suffered from rotation failure. By increasing the amount of solder for evaluation, it is presumed that the rotation failure occurred due to a difference in the way the solder wetting and climbing to the first external electrode and the second external electrode.

[0281] In Comparative Example 2, 15 samples were found to have poor rotation. Two of them had large rotation amounts and were installed with one external electrode crossing over connection pads with different polarities, resulting in a short circuit. In the samples of Comparative Example 2, due to the deviation in the formation position and thickness of the base electrode layer and the plating layer disposed thereon, the area and shape of the external electrode covering the ridgeline of the first side and second side of the laminated body were deviated, and the wetting mode of the external electrode on the first side and second side of the laminated body was easily changed by the solder, and it is believed that the wetting climb amount of the solder sometimes has a large difference. As a result, it is speculated that the poor rotation occurred due to the difference in the way the solder applied the tensile stress to the laminated ceramic capacitor.

[0282] The evaluation method in this experimental example is shown below.

[0283] (Evaluation method for installability)

[0284] FIG. 18A to FIG. 18D This is a diagram for explaining the evaluation method of installability. Fig.18A Solder (solder composition Sn-3.0Ag-0.5Cu) is printed on two connection pads 310A and 310B arranged on the glass epoxy substrate 300. In order to set the conditions more stringent than those in the usual test, the amount of solder at this time is set to 1.5 times the amount of the usual test. Specifically, a solder with a thickness of 150um is printed on each connection pad. In addition, as shown in FIG. Fig.18A As shown, the length of the connection pad in the width direction is set to 1.0 mm, the length of the connection pad in the length direction is set to 0.3 mm, and the distance between the two connection pads is set to 0.2 mm.

[0285] Next, the multilayer ceramic capacitor is placed on the lands coated with solder. Fig.18BAs shown in FIG. 1 , a reference line perpendicular to the width direction of the connection pad is selected at the center of the width direction of the connection pad, and the multilayer ceramic capacitor is placed so that the center of the width direction W of the multilayer ceramic capacitor is located at a position deviated by 0.1 mm from the reference line along the width direction of the connection pad. Fig. 18C The angle θ formed between the connecting pad shown and the stacked ceramic capacitor is within 5°, that is, the angle θ on the acute angle side formed by either of the opposing inner edges of the two connecting pads and the surface on the first end face LS1 side or the surface on the second end face LS2 side of the external electrode of the stacked ceramic capacitor is within 5°.

[0286] Then, by reflow soldering, the external electrodes of the multilayer ceramic capacitor are soldered to the connection pads, and the multilayer ceramic capacitor is mounted on the substrate. After mounting, the mounting state of the multilayer ceramic capacitor is observed, and the case where the angle θ between the connection pad and the multilayer ceramic capacitor is 5° or more is considered to be a rotational failure. Fig.18D As shown in FIG. 1 , a case where the multilayer ceramic capacitor is greatly rotated and mounted so that the first external electrode or the second external electrode straddles two lands is regarded as a short-circuit failure.

[0287] (Calculation method of area ratio of opening H)

[0288] The area ratio of the opening H is measured using an optical microscope. First, the field of view is set so that the first external electrode 40A located on the first side surface WS1 of the multilayer ceramic capacitor 1 enters the field of view of the microscope. Next, the contour of the opening H is identified, and the dimension d1 of the opening H in the length direction L and the dimension d2 in the height direction T are measured (refer to Figure 2 ). Then, the area A1 of the opening H is calculated by the formula A1=d1×d2. Next, the contour of the first external electrode 40A is identified, and the dimension D1 in the length direction L and the dimension D2 in the height direction T of the fourth surface 40A4 are measured (refer to Figure 2 ). Then, the area A2 of the fourth face 40A4 is calculated by the calculation formula A2=D1×D2. Then, the area ratio of the opening H located on the fourth face 40A4 relative to the area of ​​the fourth face 40A4 is calculated by the calculation formula A1÷A2. Similarly, the area ratios of the openings H located on the fifth face 40A5, the ninth face 40B4, and the tenth face 40B5 are also calculated. Thereafter, the average value of the area ratios of the four openings H, that is, the average value of the area ratios of the openings H located on the fourth face 40A4, the fifth face 40A5, the ninth face 40B4, and the tenth face 40B5 is calculated as the area ratio of the openings H in the multilayer ceramic capacitor 1.

[0289] (Method for measuring the height dimension of the projection K)

[0290] The dimension of the height direction T of each convex portion K arranged on the fourth face portion 40A4 and the fifth face portion 40A5 is measured by a microscope at a position 1 / 2 of the length direction L of each convex portion K arranged on the fourth face portion 40A4 and the fifth face portion 40A5 when observed from the first side surface WS1 of the stacked body 10. Similarly, the dimension of the height direction T of each convex portion K arranged on the ninth face portion 40B4 and the tenth face portion 40B5 is measured by a microscope at a position 1 / 2 of the length direction L of each convex portion K arranged on the ninth face portion 40B4 and the tenth face portion 40B5 when observed from the second side surface WS2 of the stacked body 10.

[0291] (Method for measuring the lengthwise dimension of the projection K)

[0292] The dimension of the length direction L of each convex portion K arranged on the fourth face portion 40A4 and the fifth face portion 40A5 is measured by a microscope at a position 1 / 2 of the height direction T of each convex portion K arranged on the fourth face portion 40A4 and the fifth face portion 40A5 when observed from the first side surface WS1 of the stacked body 10. Similarly, the dimension of the length direction L of each convex portion K arranged on the ninth face portion 40B4 and the tenth face portion 40B5 is measured by a microscope at a position 1 / 2 of the height direction T of each convex portion K arranged on the ninth face portion 40B4 and the tenth face portion 40B5 when observed from the second side surface WS2 of the stacked body 10.

[0293] The present invention is not limited to the configuration of the above-described embodiment, and can be appropriately modified and applied within the scope of the gist of the present invention. In addition, a combination of two or more of the preferred configurations described in the above-described embodiment also constitutes the present invention.

[0294] (1) A multilayer ceramic capacitor comprising:

[0295] A laminate comprising a plurality of dielectric layers and a plurality of internal electrode layers alternately laminated in a height direction, and having a first main surface and a second main surface opposite to each other in the height direction, a first end surface and a second end surface opposite to each other in a length direction perpendicular to the height direction, and a first side surface and a second side surface opposite to each other in a width direction perpendicular to the height direction and the length direction;

[0296] a first external electrode having at least any one of a first face portion located on the first end surface, a second face portion located on a portion of the first main surface, and a third face portion located on a portion of the second main surface, a fourth face portion located on a portion of the first side surface, and a fifth face portion located on a portion of the second side surface; and

[0297] The second external electrode has at least one of a sixth face portion located on the second end surface, a seventh face portion located on a portion of the first main surface, and an eighth face portion located on a portion of the second main surface, a ninth face portion located on a portion of the first side surface, and a tenth face portion located on a portion of the second side surface.

[0298] in,

[0299] When the length of the stack connecting the first end face and the second end face in the longitudinal direction is set to l, the length of the stack connecting the first side face and the second side face in the width direction is set to w, and the length of the stack connecting the first main face and the second main face in the height direction is set to t, the stack is in a dimensional relationship of w>l>t.

[0300] The fourth face portion, the fifth face portion, the ninth face portion, and the tenth face portion have openings that expose the surface of the laminate.

[0301] The fourth surface portion, the ninth surface portion, the fifth surface portion, and the tenth surface portion each have a convex portion protruding in the longitudinal direction from the longitudinal center sides facing each other.

[0302] (2) In the multilayer ceramic capacitor described in (1),

[0303] The convex portion is disposed at a central portion in the height direction of the fourth surface portion, the fifth surface portion, the ninth surface portion, and the tenth surface portion.

[0304] (3) In the multilayer ceramic capacitor described in (1) or (2),

[0305] The dimension of the convex portion in the height direction is not less than 10% and not more than 90% of the dimension in the height direction.

[0306] (4) In the multilayer ceramic capacitor according to any one of (1) to (3),

[0307] The dimension of the convex portion in the longitudinal direction is not less than 2% and not more than 18% of the dimension in the longitudinal direction.

[0308] (5) In the multilayer ceramic capacitor according to any one of (1) to (4),

[0309] The internal electrode layer includes a first internal electrode layer and a second internal electrode layer,

[0310] The first internal electrode layer comprises: a first opposing electrode portion located inside the stack; a first lead portion connected to the first opposing electrode portion and exposed at the first end surface, a portion of the first side surface and a portion of the second side surface; a second lead portion spaced apart from a portion of the first lead portion that is led out to the first side surface, connected to the first opposing electrode portion and exposed at a portion of the first side surface; and a third lead portion spaced apart from a portion of the first lead portion that is led out to the second side surface, connected to the first opposing electrode portion and exposed at a portion of the second side surface.

[0311] The second internal electrode layer comprises: a second opposing electrode portion located inside the stack; a fourth lead portion connected to the second opposing electrode portion and exposed at the second end surface, a portion of the first side surface and a portion of the second side surface; a fifth lead portion spaced apart from a portion of the fourth lead portion that is led out to the first side surface, connected to the second opposing electrode portion and exposed at a portion of the first side surface; and a sixth lead portion spaced apart from a portion of the fourth lead portion that is led out to the second side surface, connected to the second opposing electrode portion and exposed at a portion of the second side surface,

[0312] The second lead-out portion and the third lead-out portion located in the center of the height direction have respective lengthwise dimensions longer than the lengthwise dimensions of the second lead-out portion and the third lead-out portion located outside the center of the height direction.

[0313] The fifth lead portion and the sixth lead portion located in the center in the height direction have respective lengthwise dimensions longer than the lengthwise dimensions of the fifth lead portion and the sixth lead portion located outside the center in the height direction.

[0314] (6) In the multilayer ceramic capacitor described in (5),

[0315] The second lead-out portion and the third lead-out portion located in the center portion in the height direction protrude toward the center in the length direction more than the end portions of the second face portion and the third face portion located in the center in the length direction.

[0316] The fifth lead portion and the sixth lead portion located in the center portion in the height direction protrude toward the longitudinal center side more than the ends of the seventh face portion and the eighth face portion located at the longitudinal center side.

[0317] (7) In the multilayer ceramic capacitor described in any one of (1) to (6),

[0318] The opening is arranged at a central portion in the height direction of the fourth surface portion, the fifth surface portion, the ninth surface portion, and the tenth surface portion.

[0319] (8) In the multilayer ceramic capacitor described in any one of (1) to (7),

[0320] The openings formed in the fourth face portion and the fifth face portion are arranged closer to the first end surface than the central portions in the longitudinal direction of the fourth face portion and the fifth face portion.

[0321] The openings formed in the ninth surface portion and the tenth surface portion are arranged to be offset toward the second end surface side relative to the middle portions in the longitudinal direction of the ninth surface portion and the tenth surface portion.

[0322] (9) In the multilayer ceramic capacitor described in any one of (1) to (8),

[0323] The area of ​​the opening is greater than or equal to 3% and less than or equal to 20% of the area of ​​each of the fourth surface portion and the fifth surface portion and the ninth surface portion and the tenth surface portion on which the opening is arranged.

[0324] (10) In the multilayer ceramic capacitor described in any one of (1) to (9),

[0325] The length of the stacked body in a height direction connecting the first main surface and the second main surface is 150 μm or less.

[0326] (11) In the multilayer ceramic capacitor according to any one of (1) to (10),

[0327] The length of the stacked body in a height direction connecting the first main surface and the second main surface is 100 μm or less.

[0328] (12) In the multilayer ceramic capacitor described in any one of (1) to (11),

[0329] The length of the stacked body in a height direction connecting the first main surface and the second main surface is 50 μm or less.

[0330] (13) In the multilayer ceramic capacitor described in (5),

[0331] The first lead portion, the second lead portion, and the third lead portion are all connected to the first external electrode.

[0332] The fourth lead portion, the fifth lead portion, and the sixth lead portion are all connected to the second external electrode.

[0333] (14) In the multilayer ceramic capacitor described in any one of (1) to (13),

[0334] The first external electrode includes a first base electrode layer and a first plating layer disposed on the first base electrode layer.

[0335] The second external electrode includes a second base electrode layer and a second plating layer disposed on the second base electrode layer.

[0336] The first foundation electrode layer and the second foundation electrode layer are sputtered electrodes.

[0337] Description of Reference Numerals

[0338] 1: Multilayer ceramic capacitor;

[0339] 10: laminate;

[0340] 11: inner layer;

[0341] 12: first main surface side outer layer portion;

[0342] 13: outer layer portion on the second main surface side;

[0343] 20: dielectric layer;

[0344] 30: internal electrode layer;

[0345] 31: first internal electrode layer;

[0346] 31A: first opposing electrode portion;

[0347] 31B: 1st lead-out portion;

[0348] 31C: 2nd lead-out portion;

[0349] 31D: 3rd lead-out section;

[0350] 32: second internal electrode layer;

[0351] 32A: second opposing electrode portion;

[0352] 32B: 4th lead-out portion;

[0353] 32C: 5th lead;

[0354] 32D: 6th lead-out section;

[0355] 40: external electrode;

[0356] 40A: 1st external electrode;

[0357] 40A1: face 1;

[0358] 40A2: second face;

[0359] 40A3: face 3;

[0360] 40A4: face 4;

[0361] 40A5: face 5;

[0362] 40B: second external electrode;

[0363] 40B1: face 6;

[0364] 40B2: face 7;

[0365] 40B3: face 8;

[0366] 40B4: 9th face;

[0367] 40B5: 10th face;

[0368] 50A: 1st base electrode layer;

[0369] 50B: second base electrode layer;

[0370] 51A: 1st film layer;

[0371] 51B: second film layer;

[0372] 60A: 1st plating layer;

[0373] 60B: second plating layer;

[0374] H: opening;

[0375] K: convex part;

[0376] L: length direction;

[0377] W: width direction;

[0378] T: stacking direction;

[0379] LS1: 1st end face;

[0380] LS2: 2nd end face;

[0381] WS1: side 1;

[0382] WS2: side 2;

[0383] TS1: 1st main surface;

[0384] TS2: 2nd main surface;

[0385] l: length in the longitudinal direction;

[0386] w: length in width direction;

[0387] t: length in height direction.

Claims

1. A laminated ceramic capacitor comprising: A laminate comprising a plurality of dielectric layers and a plurality of internal electrode layers alternately laminated in a height direction, and having a first main surface and a second main surface opposite to each other in the height direction, a first end surface and a second end surface opposite to each other in a length direction perpendicular to the height direction, and a first side surface and a second side surface opposite to each other in a width direction perpendicular to the height direction and the length direction; a first external electrode having at least any one of a first face portion located on the first end surface, a second face portion located on a portion of the first main surface, and a third face portion located on a portion of the second main surface, a fourth face portion located on a portion of the first side surface, and a fifth face portion located on a portion of the second side surface; and The second external electrode has at least one of a sixth face portion located on the second end surface, a seventh face portion located on a portion of the first main surface, and an eighth face portion located on a portion of the second main surface, a ninth face portion located on a portion of the first side surface, and a tenth face portion located on a portion of the second side surface. in, When the length of the stack connecting the first end face and the second end face in the longitudinal direction is set to l, the length of the stack connecting the first side face and the second side face in the width direction is set to w, and the length of the stack connecting the first main face and the second main face in the height direction is set to t, the stack is in a dimensional relationship of w>l>t. The fourth face portion, the fifth face portion, the ninth face portion, and the tenth face portion have openings that expose the surface of the laminate. The fourth surface portion, the ninth surface portion, the fifth surface portion, and the tenth surface portion each have a convex portion protruding in the longitudinal direction from the longitudinal center sides facing each other.

2. The multilayer ceramic capacitor according to claim 1, wherein The convex portion is disposed at a central portion in the height direction of the fourth surface portion, the fifth surface portion, the ninth surface portion, and the tenth surface portion.

3. The multilayer ceramic capacitor according to claim 1 or 2, wherein: The dimension of the convex portion in the height direction is not less than 10% and not more than 90% of the dimension in the height direction.

4. The multilayer ceramic capacitor according to any one of claims 1 to 3, wherein The dimension of the convex portion in the longitudinal direction is not less than 2% and not more than 18% of the dimension in the longitudinal direction.

5. The multilayer ceramic capacitor according to any one of claims 1 to 4, wherein The internal electrode layer includes a first internal electrode layer and a second internal electrode layer, The first internal electrode layer comprises: a first opposing electrode portion located inside the stack; a first lead portion connected to the first opposing electrode portion and exposed at the first end surface, a portion of the first side surface, and a portion of the second side surface; a second lead portion spaced apart from a portion of the first lead portion led to the first side surface, connected to the first opposing electrode portion, and exposed at a portion of the first side surface; and a third lead portion which is spaced apart from the portion of the first lead portion led out to the second side surface, is connected to the first opposing electrode portion, and is exposed at a portion of the second side surface, The second internal electrode layer comprises: a second opposing electrode portion located inside the stack; a fourth lead portion connected to the second opposing electrode portion and exposed at the second end surface, a portion of the first side surface and a portion of the second side surface; a fifth lead portion spaced apart from a portion of the fourth lead portion that is led out to the first side surface, connected to the second opposing electrode portion and exposed at a portion of the first side surface; and a sixth lead portion spaced apart from a portion of the fourth lead portion that is led out to the second side surface, connected to the second opposing electrode portion and exposed at a portion of the second side surface, The second lead-out portion and the third lead-out portion located in the center of the height direction have respective lengthwise dimensions longer than the lengthwise dimensions of the second lead-out portion and the third lead-out portion located outside the center of the height direction. The fifth lead portion and the sixth lead portion located in the center in the height direction have respective lengthwise dimensions longer than the lengthwise dimensions of the fifth lead portion and the sixth lead portion located outside the center in the height direction.

6. The multilayer ceramic capacitor according to claim 5, wherein: The second lead-out portion and the third lead-out portion located in the center portion in the height direction protrude toward the center in the length direction more than the end portions of the second face portion and the third face portion located in the center in the length direction. The fifth lead portion and the sixth lead portion located in the center portion in the height direction protrude toward the longitudinal center side more than the ends of the seventh face portion and the eighth face portion located at the longitudinal center side.

7. The multilayer ceramic capacitor according to any one of claims 1 to 6, wherein The opening is arranged at a central portion in the height direction of the fourth surface portion, the fifth surface portion, the ninth surface portion, and the tenth surface portion.

8. The multilayer ceramic capacitor according to any one of claims 1 to 7, wherein The opening formed in the fourth face portion and the fifth face portion is arranged closer to the first end face than the center portion in the longitudinal direction of the fourth face portion and the fifth face portion. The opening formed in the ninth surface portion and the tenth surface portion is arranged to be offset toward the second end surface side relative to a center portion in a longitudinal direction of the ninth surface portion and the tenth surface portion.

9. The multilayer ceramic capacitor according to any one of claims 1 to 8, wherein The area of ​​the opening is greater than or equal to 3% and less than or equal to 20% of the area of ​​each of the fourth surface portion and the fifth surface portion and the ninth surface portion and the tenth surface portion on which the opening is arranged.

10. The multilayer ceramic capacitor according to any one of claims 1 to 9, wherein The length of the stacked body in a height direction connecting the first main surface and the second main surface is 150 μm or less.

11. The multilayer ceramic capacitor according to any one of claims 1 to 10, wherein The length of the stacked body in a height direction connecting the first main surface and the second main surface is 100 μm or less.

12. The multilayer ceramic capacitor according to any one of claims 1 to 11, wherein The length of the stacked body in a height direction connecting the first main surface and the second main surface is 50 μm or less.

13. The multilayer ceramic capacitor according to claim 5, wherein The first lead portion, the second lead portion, and the third lead portion are all connected to the first external electrode. The fourth lead portion, the fifth lead portion, and the sixth lead portion are all connected to the second external electrode.

14. The multilayer ceramic capacitor according to any one of claims 1 to 13, wherein The first external electrode includes a first base electrode layer and a first plating layer disposed on the first base electrode layer. The second external electrode includes a second base electrode layer and a second plating layer disposed on the second base electrode layer. The first foundation electrode layer and the second foundation electrode layer are sputtered electrodes.

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