Control Method of Test Equipment and Chip Test System

Abstract

The present application relates to a control method for a test device and a chip test system. The method is applied to a second controller in a test resource board. The test resource board further includes a first controller and a third controller. The second controller and the third controller are connected to the test device. The method includes: receiving instruction data sent by the first controller; based on the instruction data, obtaining a corresponding operation type and a control mode, where the control mode includes any one of a direct control mode, a preloading mode, and a micro-instruction mode; based on the control mode, obtaining control information corresponding to the instruction data; sending the control information to a corresponding test device, or sending the control information to a corresponding test device through the third controller. The test device performs corresponding control actions based on the control information, solving the problem that the test device control method cannot meet the requirements of different test scenarios for IC testing.

Description

Technical Field

[0001] This application relates to the field of integrated circuit testing, and particularly to a control method for a testing device and a chip testing system. Background Art

[0002] Integrated circuit (IC) testing determines whether the functions, performance, and structure of a chip meet the requirements by applying known test vectors (patterns) to the IC under test, observing its output results, and comparing them with the known correct output results. During the testing process, an arbitrary waveform generator can be used to convert the test vectors into corresponding test signals and input them into the IC under test, and a waveform collector can be used to collect the output results of the IC under test. In addition, test equipment such as oscilloscopes and multimeters can be used to collect and measure the input or output test signals. These test equipment need to be triggered and controlled based on the running process of the pattern to cooperate with the chip testing process, and have high requirements for the time synchronization of control.

[0003] In the existing test equipment control methods, control instructions can be directly sent by a host computer. This method has low efficiency and cannot achieve synchronization of multiple test channels, but it can be used for problem troubleshooting and positioning; or through a preloading mode, control instructions are stored in the DDR in advance, and the control instructions in the DDR are read out and sent to the test equipment according to the preloading start instruction. This method is suitable for batch testing of ICs, but has low synchronization accuracy. The above methods cannot meet the requirements of different test scenarios for IC testing. Summary of the Invention

[0004] In this embodiment, a control method for a testing device and a chip testing system are provided to solve the problem that the test equipment control method in the related technology cannot meet the requirements of different test scenarios for IC testing.

[0005] In a first aspect, in this embodiment, a control method for a testing device is provided. The method is applied to a second controller in a test resource board. The test resource board further includes a first controller and a third controller connected to the second controller. The second controller and the third controller are connected to multiple test devices. The method includes:

[0006] Receiving instruction data sent by the first controller;

[0007] Based on the instruction data, obtaining the corresponding operation type and control mode, where the control mode includes any one of a direct control mode, a preloading mode, and a micro-instruction mode;

[0008] Based on the control mode, obtaining control information corresponding to the instruction data;

[0009] Send the control information to the corresponding test device, or send it to the corresponding test device through the third controller, and the test device performs corresponding control actions based on the control information.

[0010] In some embodiments, the instruction data includes an operation code and register information. Based on the instruction data, obtaining the corresponding operation type and control mode includes:

[0011] Based on the operation code and the register information, determine the operation type corresponding to the instruction data, and the operation type includes any one of a read operation, a write operation, and test device control;

[0012] When the operation type corresponding to the instruction data is test device control, based on the register information, determine the control mode corresponding to the instruction data.

[0013] In some embodiments, based on the control mode, obtaining the control information corresponding to the instruction data includes:

[0014] When the control mode is a direct control mode, obtain the control information in the instruction data and write the control information into the register corresponding to the register information;

[0015] When the control mode is a preloading mode, read the corresponding control information based on the storage address in the instruction data.

[0016] In some embodiments, based on the control mode, obtaining the control information corresponding to the instruction data includes:

[0017] When the control mode is a micro-instruction mode, expand the pre-stored test vector into corresponding micro-instructions, and the micro-instructions include an event type and event parameters;

[0018] When the event type of the micro-instruction is instruction loading, based on the loading address in the event parameters, read the corresponding control information from the memory;

[0019] When the event type of the micro-instruction is not instruction loading, write the control information in the micro-instruction into the register corresponding to the register information.

[0020] In some embodiments, after determining the operation type corresponding to the instruction data based on the operation code, the method further includes:

[0021] When the operation type corresponding to the instruction data is a write operation, write the data to be written in the instruction data into the memory based on the storage address in the instruction data, where the data to be written is the control information in the preloading mode or the test vector in the micro-instruction mode;

[0022] When the operation type corresponding to the instruction data is a read operation, read the register corresponding to the register information, or read the memory based on the storage address to obtain the return data.

[0023] In a second aspect, a chip testing system is provided in this embodiment. The system includes a host computer, a test resource board, and multiple test devices connected in sequence. The test resource board includes a first controller, a second controller, and a third controller connected in sequence; the second controller and the third controller are connected to the multiple test devices, and the first controller is communicatively connected to the host computer;

[0024] The first controller is configured to receive the instruction data sent by the host computer, obtain the corresponding return data based on the instruction data, or send the instruction data to the second controller;

[0025] The second controller is configured to control the multiple test devices based on the control method of the test device in the first aspect, or send the instruction data to the third controller;

[0026] The third controller is configured to control the multiple test devices based on the instruction data or control information sent by the second controller.

[0027] In some embodiments, the first controller and the second controller are connected through a first high-speed communication interface and a serial interface, and the second controller and the third controller are connected through the first high-speed communication interface, the serial interface, and a second high-speed communication interface.

[0028] The first high-speed communication interface is used for the downlink transmission of the instruction data and the uplink transmission of the return data;

[0029] The second high-speed communication interface is used for the downlink transmission of the preloading data;

[0030] The serial interface is used for the uplink transmission of the self-check status data.

[0031] In some embodiments, the first controller, the second controller, and the third controller all include a main control decoding module, a service decoding module, a service return module, and a status readback module.

[0032] Based on the register information in the instruction data, the main control decoding module sends the instruction data to the corresponding functional module in the controller where it is located for processing, or transmits the instruction data downward to the next controller;

[0033] The service decoding module decodes the instruction data to obtain the corresponding control information;

[0034] The service return module reads the status information of the external device corresponding to the instruction data to obtain the return data;

[0035] The status readback module reads the register corresponding to the instruction data to obtain the return data.

[0036] In some embodiments, the second controller further includes a micro-instruction control module, a cache module, a preloading control module, and a service parameter selection module,

[0037] The micro-instruction control module expands the test vector stored in the cache module into corresponding micro-instructions; in the case where the micro-instruction is a load micro-instruction, the load micro-instruction is sent to the preloading control module; in the case where the micro-instruction is not a load micro-instruction, the control information in the micro-instruction is sent to the service parameter selection module;

[0038] The preloading control module reads the preloading data stored in the cache module and sends it to the service parameter selection module;

[0039] The service parameter selection module is used to send the preloading data or the control information to the third controller or the corresponding test device.

[0040] In some embodiments, the third controller further includes a preloading parameter decoding module and a service parameter selection module,

[0041] The preloading parameter decoding module receives the preloading data sent by the second controller, decodes the corresponding control information and sends it to the service parameter selection module;

[0042] The service parameter selection module sends the control information to the corresponding test device.

[0043] In some embodiments, the main control decoding module of the third controller receives the instruction data sent by the second controller, and based on the register information in the instruction data, sends the instruction data to the corresponding functional module in the third controller;

[0044] The service decoding module of the third controller decodes the instruction data to obtain corresponding control information, and directly sends the control information to the corresponding test device, or sends it to the service parameter selection module.

[0045] In some embodiments, the first controller, the second controller, and the third controller all include an upstream arbitration module.

[0046] The upstream arbitration module of the third controller arbitrates multiple upstream requests corresponding to multiple pieces of return data, and sequentially sends the multiple pieces of return data to the second controller based on the arbitration result.

[0047] The upstream arbitration module of the second controller arbitrates multiple upstream requests corresponding to the return data sent by the third controller and the return data read by the second controller, and sequentially sends the return data to the first controller based on the arbitration result.

[0048] The upstream arbitration module of the first controller arbitrates multiple upstream requests corresponding to the return data sent by the second controller and the return data read by the first controller, and sequentially sends the return data to the host computer based on the arbitration result.

[0049] In some embodiments, the first controller determines whether the instruction data is valid based on the board card domain in the instruction data; in the case of validity, the instruction data is transparently transmitted to the second controller based on the register information in the instruction data.

[0050] The second controller determines whether the instruction data is valid based on the daughter board card domain in the instruction data; in the case of validity, the instruction data is transparently transmitted to the third controller based on the register information in the instruction data; the third controller sends the instruction data to the corresponding functional module for processing based on the register information in the instruction data.

[0051] In some embodiments, the number of the second controllers and the third controllers is multiple.

[0052] The first controller is used to broadcast the instruction data to multiple second controllers, so that the multiple second controllers synchronously execute the control of the test device.

[0053] Compared with the related art, in the control method of the test device provided in this embodiment, the control instruction of the host computer is obtained by receiving the instruction data sent by the first controller; the corresponding operation type and control mode are obtained based on the instruction data, and the test device is controlled through the control mode specified by the host computer. The control modes include direct control mode, preloading mode, and micro-instruction mode; the control information corresponding to the instruction data is obtained based on the control mode, including control parameters, control signals, etc.; the control information is sent to the corresponding test device, or sent to the corresponding test device through the third controller, and the test device performs corresponding control actions based on the control information, and controls the test device through the specified control mode, solving the problem that the test device control method cannot meet the requirements of different test scenarios.

[0054] Details of one or more embodiments of the present application are set forth in the following drawings and description to make other features, objects, and advantages of the present application more concise and understandable. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] The drawings described herein are used to provide a further understanding of the present application and form a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation of the present application. In the drawings:

[0056] Figure 1 is the hardware structure block diagram of the chip test system of some embodiments of the present application;

[0057] Figure 2 is the flowchart of the control method of the test device of some embodiments of the present application;

[0058] Figure 3 is the flowchart of obtaining the operation type and control mode of some embodiments of the present application;

[0059] Figure 4 is the flowchart of obtaining the control information corresponding to the instruction data of some embodiments of the present application;

[0060] Figure 5 is the flowchart of obtaining the control information corresponding to the instruction data of other embodiments of the present application;

[0061] Figure 6 is the flowchart of the control method of the test device of some preferred embodiments of the present application;

[0062] Figure 7 is the structure block diagram of the test resource board of some embodiments of the present application;

[0063] Figure 8 is the structure block diagram of the first controller of some embodiments of the present application;

[0064] Figure 9 It is a structural block diagram of a second controller according to some embodiments of the present application;

[0065] Figure 10 It is a structural block diagram of a third controller according to some embodiments of the present application. Detailed implementation manners

[0066] To understand the purpose, technical solution and advantages of the present application more clearly, the present application will be described and illustrated below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0067] Unless otherwise defined, the technical terms or scientific terms involved in the present application shall have the general meanings understood by those with ordinary skills in the technical field to which the present application belongs. In the present application, words such as "a", "one", "a kind of", "the", "these" and the like do not indicate a limitation in quantity, and they can be singular or plural. The terms "including", "comprising", "having" and any variants thereof involved in the present application are intended to cover non-exclusive inclusion; for example, a process, method, system, product or device including a series of steps or modules (units) is not limited to the listed steps or modules (units), but may include unlisted steps or modules (units), or may include other steps or modules (units) inherent in these processes, methods, products or devices. The terms "connected", "coupled" and the like involved in the present application are not limited to physical or mechanical connections, but may include electrical connections, whether directly or indirectly connected. The term "plurality" involved in the present application refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" may mean: A exists alone, A and B exist simultaneously, and B exists alone. Usually, the character " / " indicates that the associated objects before and after are in an "or" relationship. The terms "first", "second", "third" and the like involved in the present application are only used to distinguish similar objects and do not represent a specific order for the objects.

[0068] The control method of the test device provided by the embodiments of the present application can be executed in the second controller of the test resource board in the chip test system. Figure 1 It is a structural block diagram of a chip test system according to some embodiments of the present application. As Figure 1 shown, the chip test system includes a host computer 10, a test resource board 20 (1 is shown in the figure) and a plurality of test devices 30 connected in sequence. The test resource board includes a first controller 21, a second controller 22 and a third controller 23 connected in sequence, and the second controller 22 and the third controller 23 are connected to a plurality of test devices 30 (2 are shown in the figure). Those of ordinary skill in the art can understand thatFigure 1 The structure shown is only schematic and does not limit the structure of the above chip testing system. For example, the chip testing system may further include more or fewer components than those shown in Figure 1 , or have a different configuration from that shown in Figure 1 . The testing device can be used to provide test resources for the chip under test.

[0069] In this embodiment, a control method for a testing device is provided. Figure 2 is a flowchart of the control method for the testing device according to some embodiments of the present application. As shown in Figure 2 , the process includes the following steps:

[0070] Step S201, receiving instruction data sent by the first controller.

[0071] In this embodiment, the first controller, the second controller, and the third controller may be FPGAs (Field Programmable Gate Arrays). Among them, the first controller is the first FPGA, the second controller is the second FPGA, and the third controller is the third FPGA.

[0072] The main function of the first controller is to communicate and interact with the host computer and the second controller, identify and distribute the instruction data sent by the host computer, and the distribution objects are each functional module in the first controller and the second controller; each functional module obtains the return data corresponding to the instruction data, or receives the return data sent from the second controller and returns it to the host computer; and controls the program loading of the second controller and the third controller, the in-line program upgrade of the board, etc. The main function of the second controller is to process the received instruction data and send the processed control information to the corresponding testing device or the third controller; the third controller controls the external DAC / ADC of the testing device according to the control information. In this embodiment, the testing device includes an arbitrary waveform generator AWG and a waveform collector DGT. The control information includes control signals and configuration parameters sent to the testing device, etc.

[0073] Step S202, based on the instruction data, obtaining the corresponding operation type and control mode, and the control mode includes any one of a direct control mode, a preloading mode, and a micro-instruction mode.

[0074] In this embodiment, the second controller receives the instruction data sent by the first controller, and obtains the corresponding operation type and control mode according to the instruction data. The operation type may include read operation, write operation, and test device control. The read operation includes reading the register content or DDR content of the second controller and the third controller, and reading the status information of the test device; the write operation includes writing content to the registers or DDR of the second controller, and writing content to the registers of the test device; the test device control includes sending control information to the test device through the second controller or the third controller to control the test device to perform corresponding operations.

[0075] The control mode may include any one of the direct control mode, the preloading mode, and the micro-instruction mode. The direct control mode means that the host computer directly issues the control information for the test device through the instruction data, and then the second controller forwards it to the third controller or the test device.

[0076] The preloading mode means that the control information to be issued is pre-stored in the DDR. After the host computer issues a preloading instruction to the second controller, the second controller reads out the control information and then issues it to the third controller or the test device in sequence. The preloading mode can store different control instructions and configuration parameters of multiple test items in the DDR in advance, and select the control information of the corresponding test item for reading according to the preloading instruction, which improves the test efficiency compared with the direct control mode.

[0077] The micro-instruction mode means that the test instructions (patterns) are pre-stored in the DDR. After the second controller receives the start instruction sent by the host computer, it reads the corresponding pattern and expands it into micro-instructions, and realizes the control function of the test device through the operation of the micro-instructions. Specifically, the micro-instructions may include channel connection, channel disconnection, preloading, start, and stop of the test device, etc. The preloading micro-instruction is used to realize the reading of preloaded data, which is pre-stored in the DDR and can be control information. The channel connection, channel disconnection, start, and stop micro-instructions are used to control the test device to perform corresponding operations. Since the execution cycle of each micro-instruction is strictly corresponding to the clock cycle, the micro-instruction mode can realize the synchronous control of multiple or various types of test resource boards, and has a higher synchronous accuracy compared with the preloading mode.

[0078] Step S203: Based on the control mode, obtain the control information corresponding to the instruction data.

[0079] In different control modes, the second controller obtains the control information corresponding to the instruction data in different ways. The control information includes control signals and configuration parameters sent to the test device, etc.

[0080] Step S204: Send the control information to the corresponding test device, or send it to the corresponding test device through the third controller. The test device performs corresponding control actions based on this control information.

[0081] According to the content of the control information, directly send the control information to the corresponding test device, or send it to the corresponding test device through the third controller. The test device performs corresponding control actions according to the control information.

[0082] Through steps S201 to S204, obtain the control instructions of the host computer by receiving the instruction data sent by the first controller; obtain the corresponding operation type and control mode based on the instruction data, and control the test device through the control mode specified by the host computer. The control modes include direct control mode, preloading mode, and micro-instruction mode; obtain the control information corresponding to the instruction data based on the control mode, including control parameters, control signals, etc.; send the control information to the corresponding test device, or send it to the corresponding test device through the third controller. The test device performs corresponding control actions based on this control information, and controls the test device through the specified control mode, solving the problem that the test device control method cannot meet the requirements of different test scenarios.

[0083] In some embodiments, the instruction data includes an operation code and register information. Figure 3 It is a flowchart of obtaining the operation type and control mode in some embodiments of the present application. As Figure 3 shown, this process includes the following steps:

[0084] Step S301: Based on the operation code and register information, determine the operation type corresponding to the instruction data. The operation type includes any one of read operation, write operation, and test device control.

[0085] The instruction data received by the second controller complies with a preset format, which includes an operation code and register information. The operation code is used to describe the specific operation type, and the register information is the register domain corresponding to this operation. Further, it may also include information such as board domain, sub-board domain, channel domain, data length, parity bit, etc. According to whether the sub-board domain field is consistent with the sub-board where the second controller is located, it can be determined whether the instruction data is valid for the second controller. In the case of invalidity, ignore the instruction data. In the case of validity, determine the operation type corresponding to the instruction data according to the operation code and register information.

[0086] Specifically, according to the operation code and register information, the instruction data can be classified into service decoding instructions, micro-instruction decoding instructions, service return instructions, status readback instructions, micro-instruction return instructions, third controller instructions, etc. Among them, the status readback instructions, service return instructions, and micro-instruction return instructions can be classified as read operations for reading data in the corresponding registers.

[0087] According to the register information corresponding to the service decoding instructions, the service decoding instructions are further divided into DDR write instructions, service control instructions, and preloading instructions. Among them, the DDR write instructions can be classified as write operations for writing the content in the instruction data into the DDR. The service control instructions and preloading instructions can be classified as test device control. The micro-instruction decoding instructions can also be classified as test device control.

[0088] Step S302, when the operation type corresponding to the instruction data is test device control, based on the register information, determine the control mode corresponding to the instruction data.

[0089] The three types of instructions for test device control include service control instructions, preloading instructions, and micro-instruction decoding instructions. Among them, the service control instructions correspond to the direct control mode, the preloading instructions correspond to the preloading mode, and the micro-instruction decoding instructions correspond to the micro-instruction mode. It should be noted that the micro-instructions in the micro-instruction mode can also be issued by the preloading method or the direct issuing method. Therefore, the three control modes have certain associations or overlaps in some operation steps.

[0090] Through steps S301 to S302, by determining the operation type corresponding to the instruction data based on the operation code and register information to perform the corresponding operation; when the operation type corresponding to the instruction data is test device control, based on the register information, determine the control mode corresponding to the instruction data, and obtain the control information corresponding to the instruction data through the corresponding method based on different control modes, so as to realize the control of the test device and meet the requirements of different test scenarios for IC testing.

[0091] In some embodiments, Figure 4 is a flowchart of obtaining the control information corresponding to the instruction data in some embodiments of the present application, as Figure 4 shown, this process includes the following steps:

[0092] Step S401, when the control mode is the direct control mode, obtain the control information in the instruction data and write the control information into the register corresponding to the register information.

[0093] In the direct control mode, the instruction data contains control information. The second controller can directly obtain the control information by parsing the instruction data and send it to the service parameter selection module in the second controller. The service parameter selection module updates and writes the control information into the corresponding register and sends it to the corresponding test device or the third controller.

[0094] Step S402: When the control mode is the preloading mode, read the corresponding control information based on the storage address in the instruction data.

[0095] In the preloading mode, the control information is pre-stored in the DDR. After receiving the preloading instruction, the second controller starts the preloading function, reads the DDR according to the storage address in the preloading instruction, obtains the corresponding control information, and sends it to the service parameter selection module. The service parameter selection module updates and writes the control information into the corresponding register and sends it to the corresponding test device or the third controller.

[0096] Through steps S401 to S402, in the direct control mode, the control information in the instruction data is obtained, the control information is written into the register corresponding to the register information, and the control parameters are directly sent to the corresponding test device, completing the direct control of the test device, and improving the flexibility of the test device control in the problem troubleshooting and positioning scenario; in the preloading mode, the corresponding control information is read based on the storage address in the instruction data, improving the test efficiency.

[0097] In some embodiments, Figure 5 is a flowchart of obtaining the control information corresponding to the instruction data in other embodiments of the present application. As Figure 5 shown, the process includes the following steps:

[0098] Step S501: When the control mode is the micro-instruction mode, expand the pre-stored test vector into the corresponding micro-instructions, and the micro-instructions include event types and event parameters.

[0099] In the micro-instruction mode, the second controller expands and generates the corresponding micro-instructions according to the pattern pre-stored in the DDR. The micro-instructions include event types and event parameters. Specifically, the format of the event type can be control object_operation type. Among them, the control object can be any arbitrary waveform generator AWG and waveform collector DGT, and the operation type can be connection, disconnection, start, stop, instruction loading. The event parameters can be the configuration parameters required in the process of controlling the AWG and DGT. Further, the micro-instructions also include the execution cycle serial number, which is used to control the execution time of the micro-instructions and ensure the execution time accuracy.

[0100] Step S502, when the event type of the micro-instruction is instruction loading, read the corresponding control information from the memory based on the loading address in the event parameters.

[0101] Specifically, when the event type of the micro-instruction is instruction loading, the preloading function is enabled, and the corresponding control information in the DDR is read according to the storage address and event parameters in the micro-instruction. The control information may include control signals, waveform files, FIR (finite impulse response) coefficients, etc. The control information is sent to the service parameter selection module, and the service parameter selection module updates and writes the control information into the corresponding register and sends it to the corresponding test device or the third controller.

[0102] Step S503, when the event type of the micro-instruction is not instruction loading, write the control information in the micro-instruction into the register corresponding to the register information.

[0103] When the event type of the micro-instruction is not instruction loading, the event type of the micro-instruction may include connection, disconnection, start, and stop. According to the event type and event parameters, the corresponding control information can be sent to the service parameter selection module, and the service parameter selection module updates and writes the control information into the corresponding register and sends it to the corresponding test device or the third controller.

[0104] The service parameter selection module determines the corresponding sending object according to the control information. The sending objects include AWG, DGT, and the third controller. The third controller is also connected to AWG and DGT and can further process the received instruction information and send it to AWG and DGT. Therefore, it should be noted that the sending object is not exactly the same as the control object in the micro-instruction. In this embodiment, the control objects are AWG and DGT, while the sending objects also include the third controller.

[0105] Through steps S501 to S503, when the control mode is the micro-instruction mode, the pre-stored test vectors are expanded into corresponding micro-instructions. When the event type of the micro-instruction is instruction loading, the corresponding control information is read from the memory based on the loading address in the event parameters; when the event type of the micro-instruction is not instruction loading, the control information in the micro-instruction is written into the register corresponding to the register information, realizing the control of multiple test devices through multiple control methods and improving the automatic control level of the test devices.

[0106] In some embodiments, it also involves specific control methods for read or write operations. The method includes:

[0107] When the operation type corresponding to the instruction data is a write operation, based on the storage address in the instruction data, write the data to be written in the instruction data into the memory, where the data to be written is the control information in the preloading mode or the test vector in the micro-instruction mode.

[0108] When the operation type corresponding to the instruction data is a read operation, read the register corresponding to the register information, or read the memory based on the storage address to obtain the return data.

[0109] When the operation type is a write operation, the instruction data includes the storage address of the DDR and the data to be written, and the data to be written can be a test vector or control information. The second controller writes the data to be written into the corresponding storage address of the DDR in advance, and in the subsequent preloading mode or micro-instruction mode, reads based on the preloading instruction. If the data to be written is a test vector, the test vector is expanded into micro-instructions in the micro-instruction mode, which improves the time synchronization and control efficiency of controlling the test device through micro-instructions; if the data to be written is control information, the distribution efficiency of the control information is improved through the preloading mode, thereby improving the test efficiency.

[0110] The control method of the test device in the preferred embodiment is described and illustrated below through a preferred embodiment. The control method of the test device in this preferred embodiment is applied to the second FPGA in the test resource board. The test resource board further includes a first FPGA and a third FPGA connected to the second FPGA, where the second FPGA and the third FPGA are both connected to the AWG and the DGT. Figure 6 It is a flowchart of the control method of the test device in some preferred embodiments of the present application, as Figure 6 shown, and the process includes the following steps:

[0111] Step S601, receive a frame of instruction data from the first FPGA;

[0112] Step S602, decode the instruction data, and divide the instruction data into service decoding instructions, micro-instruction decoding instructions, service return instructions, status readback instructions, micro-instruction return instructions, and third FPGA instructions according to the operation code and register information;

[0113] Step S603, when the instruction data is a status readback instruction or a micro-instruction return instruction, read the corresponding register content to obtain the return data, pack the return data and initiate an uplink request;

[0114] Step S604, when the instruction data is a service return instruction, determine whether it is a read DDR instruction;

[0115] Step S605, if it is a DDR read instruction, perform a read operation on the DDR according to the storage address to obtain the return data, pack the return data and initiate an uplink request;

[0116] Step S606, if it is not a DDR read instruction, read the content of the corresponding register to obtain the return data, pack the return data and initiate an uplink request;

[0117] Step S607, after the uplink arbitration, each uplink request returns to the first FPGA in turn;

[0118] Step S608, when the instruction data is a third FPGA instruction, send the instruction to the third FPGA;

[0119] Step S609, when the instruction data is a service decoding instruction, divide the service decoding instruction into a DDR write instruction, a preloading instruction, and a service control instruction according to the register information;

[0120] Step S610, for the DDR write instruction, write the data to be written in the instruction data into the DDR according to the storage address in the instruction data;

[0121] Step S611, for the preloading instruction, start the preloading function, read the control information in the DDR according to the storage address in the instruction data, and send it to the service parameter selection module;

[0122] Step S612, for the service control instruction, send the control information in the service control instruction to the service parameter selection module;

[0123] Step S613, when the instruction data is a micro-instruction decoding instruction, control the start of pattern operation;

[0124] Step S614, expand the pattern pre-stored in the DDR into the corresponding micro-instructions;

[0125] Step S615, determine whether the micro-instruction is an instruction loading micro-instruction;

[0126] Step S616, if so, start the preloading function, read the control information in the DDR according to the storage address in the micro-instruction, and send it to the service parameter selection module;

[0127] Step S617, if not, send the control information in the micro-instruction to the service parameter selection module;

[0128] Step S618, the service parameter selection module updates and writes the received control information into the corresponding register and sends it to the corresponding test device or the third FPGA.

[0129] Through steps S601 to S618, the instruction data is decoded, and the operation type of the instruction data is obtained according to the operation code and register information. For read and write operations, the corresponding operations can be directly executed according to the operation code and register information, and the corresponding data is uploaded through the upstream arbitration to realize the reading of the status information of the resource board and the pre-storage of the pre-loaded data. For the control of the test equipment, the corresponding control mode is determined by identifying the instruction data, including the direct control mode, the pre-loading mode, and the micro-instruction mode, which are respectively applicable to different application scenarios. The direct control mode improves the flexibility of control and is applicable to the problem location scenario. The pre-loading mode improves the control efficiency and is applicable to the batch test scenario. The micro-instruction mode improves the time synchronization accuracy and operation efficiency of control through micro-instruction control.

[0130] Some embodiments of the present application also provide a chip test system, as Figure 1 shown. The system includes a host computer 10, a test resource board 20 (1 is shown in the figure), and multiple test devices 30 connected in sequence. The test resource board 20 includes a first controller 21, a second controller 22, and a third controller 23 connected in sequence. The second controller 22 and the third controller 23 are connected to multiple test devices 30 (2 are shown in the figure), and the first controller 21 is communicatively connected to the host computer 10.

[0131] The first controller 21 is configured to receive the instruction data sent by the host computer 10, obtain the corresponding return data based on the instruction data, or send the instruction data to the second controller 22;

[0132] The second controller 22 is configured to control the multiple test devices 30 based on the control method of the test device in the above embodiment, or send the instruction data to the third controller 23;

[0133] The third controller 23 is configured to control the multiple test devices 30 based on the instruction data or control information sent by the second controller 22.

[0134] In this embodiment, the first controller 21, the second controller 22, and the third controller 23 may be FPGAs (Field Programmable Gate Arrays). Among them, the first controller 21 is the first FPGA, the second controller 22 is the second FPGA, and the third controller 23 is the third FPGA.

[0135] In some embodiments, Figure 7 is the structural block diagram of the test resource board in some embodiments of the present application, as Figure 7 shown. The first controller 21 and the second controller 22 are connected through a first high-speed communication interface T1 and a serial interface T3, and the second controller 22 and the third controller 23 are connected through a first high-speed communication interface T1, a serial interface T3, and a second high-speed communication interface T2.

[0136] The first high-speed communication interface T1 is used for the downlink transmission of command data and the uplink transmission of return data; the second high-speed communication interface T2 is used for the downlink transmission of preloaded data; the serial interface T3 is used for the uplink transmission of self-check status data.

[0137] Specifically, the first high-speed communication interface T1 and the second high-speed communication interface T2 can be GTX high-speed communication interfaces. The serial interface T3 can be a HUART serial interface.

[0138] Among them, the first high-speed communication interface T1 is the main communication link between the three controllers, used for the downlink transmission of command data and the uplink transmission of return data. The communication protocol of the first high-speed communication interface T1 is the up-down communication protocol format for the host computer to communicate with the three controllers. The protocol format includes information such as operation code, board domain, daughter board domain, channel domain, data length, register, check bit, etc., and can be applied to any board in the system.

[0139] A second high-speed communication interface T2 is provided between the second controller and the third controller. This communication interface is unidirectional downlink, and transmits the preloaded data from the second controller to the third controller. The second high-speed communication interface T2 is the interface for the second controller to directly transmit preloaded parameters to the third controller. The communication content only involves data, and a custom protocol can be used, including the channel domain and register, which is applicable to data transmission with high real-time requirements inside the board.

[0140] The main function of the serial interface T3 is to transmit the initialization self-check status of the second controller and the third controller to the first controller, and the first controller groups and uploads it to the host computer uniformly. The communication protocol can be the UART protocol, including the frame header, frame tail, register, and is applicable to data transmission with low real-time requirements inside the board.

[0141] The chip test system of this embodiment realizes the downlink transmission of command data and the uplink transmission of return data through the first high-speed communication interface, realizes the unidirectional downlink transmission of preloaded data through the second high-speed communication interface, and meets the real-time requirements for data transmission during the IC test process; realizes the upload of the self-check status of the controller through the serial interface, and transmits the data with low real-time requirements through a dedicated serial interface, avoiding affecting the data transmission with high real-time requirements, and improving the data transmission efficiency.

[0142] In some embodiments, the first controller, the second controller, and the third controller all include a main control decoding module, a service decoding module, a service return module, and a status readback module. Taking the first controller as an example, Figure 8 is the structural block diagram of the first controller 21 in some embodiments of the present application, as Figure 8As shown, the first controller 21 includes a main control decoding module 212, a service decoding module 213, a service return module 214, and a status readback module 215. In a further embodiment, the first controller 21 may also include a communication module (not shown in the figure), a peripheral control module 216, and an uplink arbitration module 211.

[0143] The main control decoding module 212 sends the instruction data to the corresponding functional module in the controller 21 for processing based on the register information in the instruction data, or transmits the instruction data downstream to the next controller. For the first controller 21, the next controller is the second controller 22.

[0144] The service decoding module 213 decodes the instruction data to obtain corresponding control information, and further sends the control information to the peripheral control module 216 for controlling the corresponding external device.

[0145] The service return module 214 reads the status information of the external device corresponding to the instruction data through the peripheral control module 216 to obtain the return data.

[0146] The status read-back module 215 reads the register corresponding to the instruction data to obtain the return data.

[0147] The main function of the communication module is to communicate with the host computer and the second controller for data transmission. In a specific embodiment, the communication module communicates with the host computer using a standard communication interface, and the data format is a custom communication protocol format. After receiving the communication data through the interface, the communication module extracts valid information, removes the frame header and frame tail information, and sends it to the main control decoding module 212 for logical function control; and according to the arbitration result of the uplink arbitration module 211, the return data is sent to the host computer after adding the frame header and frame tail information according to the interface protocol. The communication module also adds the frame header and frame tail information to the valid information that the main control decoding module 212 needs to send to the second controller according to the interface protocol and sends it to the second controller.

[0148] Specifically, the service decoding module 213 decodes the instruction data into the corresponding register according to the register information, and then controls the corresponding peripheral to perform the corresponding operation through the peripheral control module 216 .

[0149] The service return module 214 packages the read return data according to the communication protocol format based on the operation code and register information of the instruction data, and initiates a request to the uplink arbitration module 211. When receiving the response from the uplink arbitration module 211, the packaged return data is sent to the uplink arbitration module 211.

[0150] The status readback module 215 reads data through blocking read instructions. According to the operation code of the instruction data, the timeout period and the expected data information are obtained. When the status readback module 215 receives the instruction data, it does not immediately perform the data return operation. Instead, when the internal state of the register is consistent with the issued expected data information, it will return the data. Or if it has not been consistent with the expected data information for a long time but reaches the timeout period, it will also return the data. This operation form reduces the polling read operations of the host computer and greatly improves both the logic control and communication efficiency.

[0151] Similarly, the second controller and the third controller also include a main control decoding module, a service decoding module, a service return module, and a status readback module. And the functions of each module are basically the same as those in the above embodiments. The main control decoding modules of the first controller, the second controller, and the third controller will be described below through an embodiment.

[0152] The first controller determines whether the instruction data is valid based on the board domain in the instruction data; in the case of validity, based on the register information in the instruction data, the instruction data is transparently transmitted to the second controller.

[0153] The second controller determines whether the instruction data is valid based on the daughter board domain in the instruction data; in the case of validity, based on the register information in the instruction data, the instruction data is transparently transmitted to the third controller.

[0154] The third controller sends the instruction data to the corresponding function module for processing based on the register information in the instruction data.

[0155] Specifically, the main control decoding module of the first controller determines whether the instruction data is valid for the test resource board based on the board domain in the instruction data; in the case of validity, based on the register information in the instruction data, the instruction data is transparently transmitted to the second controller; or the instruction data is decoded by the service decoding module to obtain the corresponding control information, and the corresponding external device is controlled based on the control information; or the status information of the register or external device corresponding to the instruction data is read to obtain the return data.

[0156] Specifically, the instruction data may include information such as operation code, board domain, sub-board domain, channel domain, data length, register information, check bit, etc. The main control decoding module of the first controller determines whether the instruction data is valid for the test resource board according to the board domain in the instruction data. Specifically, the instruction data can be divided into broadcast instructions and unicast instructions. For unicast instructions, the board domain field can be compared with the slot number where the test resource board is located. If the comparison result is consistent, it is determined that the instruction data is valid for the test board, otherwise it is invalid; for broadcast instructions, the card domain field can be compared with the pre-defined board type information. If the comparison result is consistent, it is determined that the instruction data is valid for the test board, otherwise it is invalid.

[0157] If it is valid, the data of the test resource board is distributed to different modules or the second controller according to the operation code and register information. If it is invalid, the whole packet of data can be discarded.

[0158] Specifically, if the instruction data is a service return instruction, the main control decoding module forwards the instruction data to the service return module, the service return module reads the corresponding register data or status information of the external device, and packages the response information and initiates a request to the uplink arbitration module.

[0159] If the instruction data is a status readback instruction, the instruction data is forwarded to the status readback module, the status readback module reads the register corresponding to the instruction data, obtains the return data and initiates a request to the uplink arbitration module; after receiving the response of the uplink arbitration, the service return module or the status readback module sends the packaged return data to the uplink arbitration module and then to the host computer.

[0160] If the instruction data is a second controller instruction or a third controller instruction, the main control decoding module of the first controller will transmit the instruction data to the second controller; if the instruction data is a business decoding instruction, the instruction data will be forwarded to the business decoding module, the business decoding module will decode the instruction data to obtain corresponding control information, and send the control information to the peripheral control module, and the peripheral control module will control the corresponding external device based on the control information.

[0161] Similarly, the main control decoding module of the second controller determines whether the instruction data is valid for the sub-board card based on the sub-board card field in the instruction data. It should be noted that each test resource board may include multiple sub-board cards, and each sub-board card may include a second controller. In the case of validity, based on the register information in the instruction data, the instruction data is transparently transmitted to the third controller, or the instruction data is sent to the corresponding functional module in the second controller.

[0162] The main control decoding module of the third controller sends the instruction data to the corresponding functional module for processing based on the register information in the instruction data.

[0163] The chip test system of this embodiment identifies the validity of instruction data through the main control decoding modules of the first controller and the second controller, and filters out the instruction data that is invalid for the test resource board or daughter board; the main control decoding module distributes the instruction data according to the operation code and register information in the instruction data; through the communication method of instruction pass-through between the three controllers, the instruction data is processed in a division of labor manner, realizing the effective allocation of instruction processing resources; cooperating with other functional modules of the first controller, the second controller, and the third controller, it realizes the reading and writing of data and the multi-mode control of test equipment, improves the IC test efficiency, and expands the application scenarios of test equipment control.

[0164] In a further embodiment, Figure 9 is the structural block diagram of the second controller in some embodiments of the present application, as Figure 9 shown, the second controller further includes a micro-instruction control module 226, a cache module 227, a preloading control module 228, and a service parameter selection module 229.

[0165] The micro-instruction control module 226 expands the test vector stored in the cache module 227 into corresponding micro-instructions; in the case where the micro-instruction is a load micro-instruction, the load micro-instruction is sent to the preloading control module 228; in the case where the micro-instruction is not a load micro-instruction, the control information in the micro-instruction is sent to the service parameter selection module 229.

[0166] The preloading control module 228 reads the preloading data stored in the cache module 227 and sends it to the service parameter selection module 229.

[0167] The service parameter selection module 229 is used to send the preloading data or control information to the third controller or the corresponding test equipment.

[0168] Specifically, the micro-instruction control module 226 may include a test vector control sub-module, a micro-instruction decoding sub-module, and a micro-instruction return sub-module. The test vector control sub-module reads the test vector stored in the cache module 227, and the micro-instruction decoding sub-module decodes the test vector to obtain the corresponding micro-instructions.

[0169] If the micro-instruction is a load micro-instruction, the test vector control sub-module sends the load micro-instruction to the preloading control module 228, and the preloading control module 228 reads the corresponding preloading data according to the storage address in the load micro-instruction, and the preloading data may be control information. The preloading data is sent to the service parameter selection module 229.

[0170] If the micro-instruction is not a load micro-instruction, the test vector control sub-module sends the control information in the micro-instruction to the service parameter selection module 229. After receiving the control information sent by the micro-instruction control module 226 or the preloading control module 228, the service parameter selection module 229 determines that the sending object of the control information is the third controller or the test devices AWG and DGT according to the data format of the control information, and sends the control information to the corresponding sending object.

[0171] In some embodiments, the main control decoding module 222 of the second controller sends the instruction data to the service decoding module 223 for processing according to the register information in the instruction data. The service decoding module 223 then performs corresponding processing according to the operation code and register information of the instruction data. Specifically, if the instruction data is a write operation instruction, the written content in the instruction data is written into the corresponding address of the cache module 227.

[0172] If the instruction data is a test device control instruction, the control information in the instruction data is sent to the service parameter selection module 229. The service parameter selection module 229 sends the control information to the corresponding sending object.

[0173] If the instruction data is a preloading instruction, the instruction data is sent to the preloading control module 228, and the preloading function is controlled to be enabled. The preloading control module 228 reads the preloading data stored in the cache module 227 according to the storage address in the instruction data, and the preloading data can be control information. The preloading data is sent to the service parameter selection module 229. The service parameter selection module 229 sends the preloading data to the corresponding sending object.

[0174] The chip test system of this embodiment obtains control information in different ways in the micro-instruction mode, controls various test devices, improves the test efficiency, and enriches the control methods of the test devices.

[0175] In some embodiments, Figure 10 is the structural block diagram of the third controller in some embodiments of the present application, as Figure 10 shown, the third controller 23 further includes a preloading parameter decoding module 237 and a service parameter selection module 236.

[0176] The preloading parameter decoding module 237 receives the preloading data sent by the second controller, decodes to obtain the corresponding control information and sends it to the service parameter selection module 236; the service parameter selection module 236 sends the control information to the corresponding test device.

[0177] Specifically, the preloaded data refers to the control information sent by the second controller in the preloading mode, or the control information read by the second controller based on the loading micro-instruction in the micro-instruction mode. The service parameter selection module 236 determines the sending object of the control information as the test equipment AWG, DGT or other external equipment according to the data format of the control information, and sends the control information to the corresponding sending object. Specifically, the control information can be a read or write operation on the external equipment. Specifically, the module structures of the service parameter selection module 236 of the third controller and the service parameter selection module 229 of the second controller can be the same or different.

[0178] In some embodiments, the main control decoding module of the third controller receives the instruction data sent by the second controller, and based on the register information in the instruction data, sends the instruction data to the corresponding functional module in the third controller. The service decoding module of the third controller decodes the instruction data to obtain the corresponding control information, and directly sends the control information to the corresponding test equipment, or sends it to the service parameter selection module.

[0179] Similar to the first controller and the second controller, the third controller also includes a service decoding module, a service return module and a status readback module.

[0180] When the service decoding module receives the instruction data, it decodes the instruction data and determines whether the instruction data is a pin precision measurement unit (PMU) instruction. If so, it directly sends the corresponding control information to the PMU to implement the corresponding control function. If not, it sends the decoded control information to the service parameter selection module. The service parameter selection module updates the register and sends the control information to the corresponding test equipment or external equipment to implement the corresponding control function.

[0181] For the specific functions and specific examples of the service return module and the status readback module in this embodiment, reference can be made to the examples described in the above embodiments and alternative embodiments, and will not be elaborated in this embodiment.

[0182] In the chip test system of this embodiment, the third controller receives the preloaded data and instruction data sent by the second controller, the preloading parameter decoding module decodes the preloaded data to obtain the corresponding control information, the main control decoding module decodes the instruction data to obtain the corresponding control information, and the service parameter selection module sends the control information to the corresponding test equipment to realize the control of the test equipment. On the basis of the second controller controlling the test equipment, the control function is further enriched, and the automation degree of the test equipment control is improved.

[0183] In some embodiments, the first controller, the second controller and the third controller all include an upstream arbitration module.

[0184] The upstream arbitration module of the third controller arbitrates multiple upstream requests corresponding to multiple pieces of returned data, and sequentially sends the multiple pieces of returned data to the second controller based on the arbitration result;

[0185] The upstream arbitration module of the second controller arbitrates multiple upstream requests corresponding to the returned data sent by the third controller and the returned data read by the second controller, and sequentially sends the returned data to the first controller based on the arbitration result;

[0186] The upstream arbitration module of the first controller arbitrates multiple upstream requests corresponding to the returned data sent by the second controller and the returned data read by the first controller, and sequentially sends the returned data to the host computer based on the arbitration result.

[0187] In the chip test system of this embodiment, the upstream arbitration module arbitrates the returned data corresponding to multiple functional modules of the present controller and the returned data of the downstream controller, and sequentially uploads the multiple pieces of returned data according to the arbitration result, ensuring that the returned data is uploaded according to the priority, improving the data upload efficiency, and avoiding data conflicts.

[0188] In some embodiments, the number of the second controllers and the third controllers is multiple, and the first controller is used to broadcast instruction data to the multiple second controllers, so that the multiple second controllers synchronously execute the control of the test equipment.

[0189] In a specific embodiment, the first controller can be connected to 4 second controllers and 4 third controllers. During the program loading process, the first controller can use broadcast instructions to load programs for 4 second controllers or 4 third controllers simultaneously, effectively improving the loading rate.

[0190] It should be noted that the specific examples in this embodiment can refer to the examples described in the above embodiments and optional implementation manners, and will not be elaborated in this embodiment.

[0191] It should be understood that the specific embodiments described here are only used to explain this application, rather than to limit it. According to the embodiments provided in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the protection scope of this application.

[0192] Obviously, the accompanying drawings are only some examples or embodiments of the present application. For those of ordinary skill in the art, the present application can also be applied to other similar situations based on these drawings without creative efforts. Additionally, it can be understood that although the work done during this development process may be complex and time-consuming, for those of ordinary skill in the art, certain design, manufacturing, or production changes based on the technical content disclosed in the present application are only routine technical means and should not be regarded as insufficient disclosure of the present application.

[0193] The term "embodiment" in the present application means that the specific features, structures, or characteristics described in connection with the embodiment can be included in at least one embodiment of the present application. The phrase appears in various positions in the specification and does not necessarily mean the same embodiment, nor does it mean being independent or alternative to other embodiments and mutually exclusive. Those of ordinary skill in the art can clearly or implicitly understand that the embodiments described in the present application can be combined with other embodiments without conflict.

[0194] The above-described embodiments only represent several implementation manners of the present application, and their descriptions are relatively specific and detailed. However, they should not be construed as limiting the scope of patent protection. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all fall within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the appended claims.

Claims

1. A control method for a testing device, characterized in that, The method is applied to a second controller in a test resource board. The test resource board further includes a first controller and a third controller connected to the second controller. The second controller and the third controller are connected to multiple test devices. The method includes: Receiving instruction data sent by the first controller; Based on the instruction data, obtaining a corresponding operation type and a control mode, where the control mode includes any one of a direct control mode, a preloading mode, and a micro-instruction mode; Based on the control mode, obtaining control information corresponding to the instruction data; in different control modes, obtaining control information corresponding to the instruction data in different ways; Sending the control information to a corresponding test device, or sending it to a corresponding test device through the third controller, and the test device performs corresponding control actions based on the control information; The instruction data includes an operation code and register information. Based on the instruction data, obtaining a corresponding operation type and a control mode includes: Based on the operation code and the register information, determining the operation type corresponding to the instruction data, where the operation type includes any one of a read operation, a write operation, and test device control; When the operation type corresponding to the instruction data is test device control, based on the register information, determining the control mode corresponding to the instruction data.

2. The method according to claim 1, characterized in that, Based on the control mode, obtaining control information corresponding to the instruction data includes: When the control mode is the direct control mode, obtaining the control information in the instruction data and writing the control information into the register corresponding to the register information; When the control mode is the preloading mode, reading the corresponding control information based on the storage address in the instruction data.

3. The method according to claim 1, wherein Based on the control mode, obtaining control information corresponding to the instruction data includes: When the control mode is the micro-instruction mode, expanding a pre-stored test vector into corresponding micro-instructions, where the micro-instructions include an event type and event parameters; When the event type of the micro-instruction is instruction loading, reading the corresponding control information from the memory based on the loading address in the event parameters; When the event type of the micro-instruction is not instruction loading, writing the control information in the micro-instruction into the register corresponding to the register information.

4. The method according to claim 1, characterized in that, After determining the operation type corresponding to the instruction data based on the operation code, the method further includes: When the operation type corresponding to the instruction data is a write operation, writing the data to be written in the instruction data into the memory based on the storage address in the instruction data, where the data to be written is the control information in the preloading mode or the test vector in the micro-instruction mode; When the operation type corresponding to the instruction data is a read operation, reading the register corresponding to the register information, or reading the memory based on the storage address to obtain return data.

5. A chip testing system, characterized in that, The system includes a host computer, a test resource board, and multiple test devices connected in sequence. The test resource board includes a first controller, a second controller, and a third controller connected in sequence; the second controller and the third controller are connected to the multiple test devices, and the first controller is communicatively connected to the host computer; The first controller is configured to receive instruction data sent by the host computer, obtain corresponding return data based on the instruction data, or send the instruction data to the second controller; The second controller is configured to control the multiple test devices based on the control method of any one of the test devices according to claims 1 to 4, or send the instruction data to the third controller; The third controller is configured to control the multiple test devices based on the instruction data or control information sent by the second controller.

6. The system according to claim 5, wherein The first controller and the second controller are connected through a first high-speed communication interface and a serial interface, and the second controller and the third controller are connected through the first high-speed communication interface, the serial interface, and a second high-speed communication interface. The first high-speed communication interface is used for the downlink transmission of the instruction data and the uplink transmission of the return data; The second high-speed communication interface is used for the downlink transmission of preloaded data; The serial interface is used for the uplink transmission of self-check status data.

7. The system according to claim 5, wherein The first controller, the second controller, and the third controller all include a main control decoding module, a service decoding module, a service return module, and a status reading module. The main control decoding module sends the instruction data to the corresponding function module in the controller for processing based on the register information in the instruction data, or downlinks the instruction data to the next controller; The service decoding module decodes the instruction data to obtain corresponding control information; The service return module reads the status information of the external device corresponding to the instruction data to obtain the return data; The status reading module reads the register corresponding to the instruction data to obtain the return data.

8. The system according to claim 7, wherein The second controller further includes a micro-instruction control module, a cache module, a preloading control module, and a service parameter selection module. The micro-instruction control module expands the test vector stored in the cache module into corresponding micro-instructions; in the case where the micro-instruction is a loading micro-instruction, the loading micro-instruction is sent to the preloading control module; In the case where the micro-instruction is not a loading micro-instruction, the control information in the micro-instruction is sent to the service parameter selection module; The preloading control module reads the preloaded data stored in the cache module and sends it to the service parameter selection module; The service parameter selection module is configured to send the preloaded data or the control information to the third controller or the corresponding test device.

9. The system according to claim 7, wherein The third controller further includes a preloading parameter decoding module and a service parameter selection module. The preloading parameter decoding module receives the preloaded data sent by the second controller, decodes it to obtain corresponding control information and sends it to the service parameter selection module; The service parameter selection module sends the control information to the corresponding test device.

10. The system according to claim 9, characterized in that, The main control decoding module of the third controller receives the instruction data sent by the second controller, and based on the register information in the instruction data, sends the instruction data to the corresponding functional module in the third controller; The service decoding module of the third controller decodes the instruction data to obtain the corresponding control information, and directly sends the control information to the corresponding test device, or sends it to the service parameter selection module.

11. The system according to claim 5, wherein The first controller, the second controller, and the third controller all include an upstream arbitration module. The upstream arbitration module of the third controller arbitrates multiple upstream requests corresponding to multiple pieces of return data, and based on the arbitration result, sequentially sends the multiple pieces of return data to the second controller; The upstream arbitration module of the second controller arbitrates multiple upstream requests corresponding to the return data sent by the third controller and the return data read by the second controller, and based on the arbitration result, sequentially sends the return data to the first controller; The upstream arbitration module of the first controller arbitrates multiple upstream requests corresponding to the return data sent by the second controller and the return data read by the first controller, and based on the arbitration result, sequentially sends the return data to the host computer.

12. The system according to claim 5, wherein The first controller determines whether the instruction data is valid based on the board card domain in the instruction data; in the case of validity, based on the register information in the instruction data, transparently transmits the instruction data to the second controller; The second controller determines whether the instruction data is valid based on the daughter board card domain in the instruction data; in the case of validity, based on the register information in the instruction data, transparently transmits the instruction data to the third controller; the third controller sends the instruction data to the corresponding functional module for processing based on the register information in the instruction data.

13. The system according to claim 5, wherein, The number of the second controllers and the third controllers is multiple. The first controller is used to broadcast the instruction data to multiple second controllers, so that the multiple second controllers synchronously execute the control of the test device.

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