Power supply output capability test circuit, method and equipment

Abstract

The invention discloses a power supply output capability test circuit and method and test equipment. The circuit comprises a control module which comprises a signal output end, a current acquisition end, a control voltage acquisition end and a plurality of to-be-measured voltage acquisition ends; the current control sub-circuit comprises a signal access end, a sampling current output end and a plurality of control voltage output ends, the signal access end is connected with the signal output end, the sampling current output end is connected with the current acquisition end, and one of the plurality of control voltage output ends is connected with the control voltage acquisition end; and the current extraction sub-circuit comprises a plurality of power supply ports, a control voltage access end is arranged corresponding to each power supply port, each power supply port is connected with a preset power supply to be tested and a voltage acquisition end to be tested, and each control voltage access end is connected with a control voltage output end. According to the embodiment of the invention, the control module can obtain the current of each to-be-tested power supply through calculation by only collecting the current of the sampling current output end.

Description

Technical Field

[0001] The present application belongs to the technical field of circuit testing, and in particular relates to a power supply output capability testing circuit, method, and testing equipment. Background Art

[0002] When performing performance testing on a chip's power supply, if there are multiple power supplies to be tested, it is often necessary to use test equipment to test them one by one. That is, it is necessary to use the test equipment to test one power supply to be tested, and after the test is completed, test the other power supplies to be tested.

[0003] Thus, when multiple power supplies to be tested need to be tested, repeated work is required, that is, current data of the circuits where each power supply to be tested is located needs to be collected separately, and multiple current collection operations are required to complete the testing of multiple power supplies to be tested, resulting in low test efficiency. Summary of the Invention

[0004] The embodiments of the present application provide a power supply output capacity testing circuit, method, and testing equipment, which can collect current only once during each test and complete the test of multiple power supplies to be tested.

[0005] In a first aspect, an embodiment of the present application provides a power supply output capability test circuit, the circuit comprising:

[0006] A control module, comprising a signal output terminal, a current acquisition terminal, a control voltage acquisition terminal and a plurality of voltage acquisition terminals to be measured;

[0007] The current control subcircuit includes a signal access terminal, a sampling current output terminal, and multiple control voltage output terminals, wherein the signal access terminal is connected to the signal output terminal, the sampling current output terminal is connected to the current collection terminal, and one of the multiple control voltage output terminals is connected to the control voltage collection terminal;

[0008] The current extraction subcircuit includes a plurality of power ports, a control voltage access terminal is provided for each power port, each power port is connected to a preset power supply to be tested and a voltage acquisition terminal to be tested, and each control voltage access terminal is connected to a control voltage output terminal;

[0009] The control module is used to generate a control signal, and the control signal is used to adjust the sampling current flowing through the current control subcircuit and the control voltage output by each control voltage output terminal;

[0010] Collect the voltage to be measured outputted by the corresponding power supply to be measured from each power port, collect the sampling current from the sampling current output terminal, and collect the corresponding control voltage from one of the multiple control voltage output terminals;

[0011] The sampled current and the collected control voltage are input into a preset voltage function to calculate the control voltages connected to the remaining control voltage access terminals, and each control voltage is used to determine the target current predetermined by the corresponding control voltage access terminal, and the target current is determined as the current to be tested output by the corresponding power supply to be tested when the corresponding power supply to be tested outputs the voltage to be tested.

[0012] The signal output terminal includes a first signal output terminal and a second signal output terminal, and the control signal includes a first control signal output by the first signal output terminal and a second control signal output by the second signal output terminal;

[0013] Furthermore, the current control subcircuit includes:

[0014] A first control unit includes a first unit access port, a first signal access port, a first control voltage output port, and a second control voltage output port, wherein the first signal access port is connected to the first signal output port, and the first control unit is configured to receive a preset power supply voltage through the first unit access port;

[0015] The second control unit comprises a second unit access port, a second signal access port and a third control voltage output port, wherein the second unit access port is connected to the second control voltage output port, and the second signal access port is connected to the second signal output port;

[0016] The third control unit includes a third unit access port and a third unit output port, and the third unit access port is connected to the third control voltage output terminal.

[0017] Furthermore, the signal output terminal also includes a switch signal output terminal for outputting a switch signal;

[0018] Furthermore, the current extraction subcircuit includes a plurality of current extraction units, each current extraction unit including:

[0019] A switching transistor, wherein the source is connected to a power supply port and the gate is connected to a switching signal output terminal;

[0020] The regulating transistor has a source connected to the drain of the switching transistor and a gate as a control voltage access terminal.

[0021] Furthermore, the current control subcircuit further includes:

[0022] The acquisition unit comprises a fourth unit access port, a fourth unit output port and a sampling current output terminal, wherein the fourth unit access port is connected to the third unit output port.

[0023] Furthermore, the first control unit includes:

[0024] A first transistor, wherein the source is the first unit access port, the gate is the first signal access terminal, the drain is the first control voltage output terminal, and the drain is connected to the gate of the regulating transistor of the first current extraction unit;

[0025] The first resistor has a first end connected to the drain of the first transistor, a second end serving as a second control voltage output end, and a second end connected to the gate of the regulating transistor of the second current extraction unit.

[0026] Furthermore, the second control unit includes:

[0027] The second transistor has a source connected to the second end of the first resistor, a gate as a second signal access terminal, a drain as a third control voltage output terminal, and a drain connected to the gate of the regulating transistor of the third current extraction unit.

[0028] Furthermore, the third control unit includes:

[0029] The third transistor has a gate connected to a source, the source is connected to the drain of the second transistor, and the drain is the output port of the third unit.

[0030] Furthermore, the acquisition unit includes:

[0031] A second resistor, the first end of which is the fourth unit access port and the second end of which is the fourth unit output port, is used to receive the sampling current and output it from the second end;

[0032] The acquisition amplifier includes a positive electrode, a negative electrode and a sampling current output terminal, wherein the negative electrode is connected to the first terminal of the second resistor, the positive electrode is connected to the second terminal of the second resistor, and the output terminal is connected to the control module.

[0033] In a second aspect, an embodiment of the present application provides a method for testing the output capability of a power supply, the method comprising:

[0034] Generate a control signal, the control signal is used to adjust the sampling current flowing through the current control subcircuit and the control voltage output by each control voltage output terminal;

[0035] Collect the voltage to be measured outputted by the corresponding power supply to be measured from each power port, collect the sampling current from the sampling current output terminal, and collect the control voltage from one of the multiple control voltage output terminals;

[0036] The sampled current and the collected control voltage are input into a preset voltage function to calculate the control voltage output by each other control voltage output terminal, and each control voltage is used to determine the target current of the corresponding control voltage access terminal, and the target current is determined as the measured current output by the corresponding power supply under test when the corresponding power supply under test outputs the measured voltage.

[0037] In a third aspect, an embodiment of the present application provides a testing device, which includes: a power output capability testing circuit as described in any of the above items.

[0038] The power supply output capacity testing circuit, method and device of the embodiments of the present application are based on a control module, a current control subcircuit and a current extraction subcircuit that are interconnected. When the current extraction subcircuit is connected to multiple power supplies to be tested, the control module can collect the test voltage output by each power supply to be tested connected to the current extraction subcircuit by controlling the voltage collection end. Based on the current collection end, the control module can collect the sampled current flowing through the current control subcircuit from the sampling current output end of the current control subcircuit. When testing multiple power supplies to be tested, only one sampling current needs to be collected to deduce the test current output by each power supply to be tested, thereby determining the test voltage of each power supply to be tested under different test currents, thereby improving test efficiency.

[0039] Among them, based on the signal output terminal set by the control module and the signal access terminal set in the current control subcircuit, the control module can interact with the current control subcircuit to control the control signal, thereby realizing the control of the sampling current and output control voltage of the current control subcircuit.

[0040] Furthermore, based on the multiple control voltage output terminals set in the current control subcircuit and the multiple control voltage access terminals set in the current extraction subcircuit, the control voltage controlled by the control module can be input into the current extraction subcircuit, thereby controlling the measured current output by each power supply to be measured.

[0041] Among them, the control module can also calculate the various control voltages output by the current control subcircuit based on the sampled current collected by the set current collection terminal, and then, while using the control module to control the current to be measured, the current to be measured output by each power supply to be measured is calculated through the control voltage, so that the current to be measured of each power supply to be measured can be known by collecting the sampled current only once. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0043] Figure 1 This is the intention of the current power supply output capability test;

[0044] Figure 2 This is a first circuit diagram of a power supply output capability test circuit provided by an embodiment of the present application;

[0045] Figure 3 is a circuit diagram of a current control subcircuit provided in an embodiment of the present application;

[0046] Figure 4This is a second circuit diagram of a power supply output capability test circuit provided in an embodiment of the present application;

[0047] Figure 5 This is a flow chart of a method for testing power supply output capability provided in an embodiment of the present application. DETAILED DESCRIPTION

[0048] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is merely to provide a better understanding of the present application by illustrating the examples of the present application.

[0049] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, the elements defined by the phrase "comprising..." do not exclude the presence of other identical elements in the process, method, article, or device comprising the elements.

[0050] As described in the background technology section, the related power supply output capacity testing technology has low testing efficiency and is difficult to meet the needs of actual work.

[0051] Most current chips integrate power management units. When testing the power performance of a power management unit (PMU), it is necessary to test the output capability of the power supply. When testing the output capability of multiple PMUs, or when testing the output capability of a single PMU with multiple power supplies, the current commonly used test method is to use a DC analyzer or other equipment to connect each power supply to be tested in turn, and extract the load current value of each power supply to be tested as the test current, while observing the voltage drop of the power supply to be tested when it outputs different test current values.

[0052] In the process of implementing this application, it was found that in the relevant power supply output capacity testing technology, when testing multiple power supplies to be tested at the same time, it is necessary to use multiple DC analyzers with the same number of power supplies to be tested to collect data from each power supply to be tested separately.

[0053] Specifically, if Figure 1 As shown, Figure 1 A schematic diagram showing the current capability of testing multiple power supply outputs.

[0054] The PMU of the IC (Integrated Circuit, IC, chip) has three power supplies to be tested, namely power supply to be tested 1, power supply to be tested 2 and power supply to be tested 3.

[0055] According to the current testing method, the test port needs to be manually connected to one power supply under test at a time during testing. When testing three power supplies under test simultaneously, a corresponding DC analyzer needs to be set for each power supply under test, that is, three DC analyzers are required, and the test current of the DC analyzer is set at the same time. The voltage value of each power supply under test is observed. When the increase in the test current causes the output voltage of the power supply under test to decrease by, for example, 5%, the current test current value is the output capacity of the corresponding power supply under test.

[0056] That is, in the current testing method, if multiple power supplies need to be tested simultaneously, multiple DC analyzers, the same number as the power supplies to be tested, need to be used to test each power supply to be tested separately. It is impossible to use one device to complete the testing of multiple power supplies to be tested simultaneously.

[0057] Furthermore, when testing multiple power supplies to be tested simultaneously, it is necessary to collect the output current to be tested of each power supply to be tested, that is, multiple current collection operations need to be performed, resulting in low test efficiency.

[0058] In order to solve the problems of the prior art, the embodiments of the present application provide a plurality of power supply output capability testing circuits, methods and testing equipment.

[0059] The power output capability test circuit provided in the embodiment of the present application is described in detail below with reference to the accompanying drawings.

[0060] Figure 2 A circuit diagram of a power supply output capability test circuit provided by an embodiment of the present application is shown.

[0061] like Figure 2 As shown, the power output capability test circuit 1 includes:

[0062] The control module 101 includes a signal output terminal, a current acquisition terminal A4I, a control voltage acquisition terminal A5I and a plurality of voltage acquisition terminals to be measured;

[0063] The current control subcircuit 102 includes a signal access terminal, a sampling current output terminal A4O, and multiple control voltage output terminals. The signal access terminal is connected to the signal output terminal, the sampling current output terminal is connected to the current collection terminal A4I, and one of the multiple control voltage output terminals is connected to the control voltage collection terminal A5I.

[0064] The current extraction subcircuit 103 includes multiple power ports, each of which is provided with a control voltage access terminal. Each power port is connected to a preset power supply to be tested and a voltage acquisition terminal to be tested, and each control voltage access terminal is connected to a control voltage output terminal.

[0065] In this embodiment, the control module 101 is provided with a signal output terminal, and the current control sub-circuit 102 is correspondingly provided with a signal input terminal, and the signal output terminal is connected to the signal input terminal.

[0066] Furthermore, the control module 101 is further provided with a current acquisition terminal A4I, and the current control sub-circuit 102 is correspondingly provided with a sampling current output terminal A4O. Figure 2 As shown, the current collection terminal A4I is connected to the sampling current output terminal A4O.

[0067] Furthermore, if Figure 2 As shown, the current extraction sub-circuit 103 is provided with multiple power ports for connecting to the same number of power supplies to be tested, for example, connecting to a first power port S1I, a second power port S2I and a third power port S3I, wherein each power port is connected to a preset power supply to be tested.

[0068] Furthermore, in the control module 101, a voltage acquisition port to be measured is set corresponding to each power port, such as Figure 2 As shown, a first voltage acquisition terminal A1I to be measured is correspondingly set for the first power port S1I, a second voltage acquisition terminal A2I to be measured is correspondingly set for the second power port S2I, and a third voltage acquisition terminal A3I to be measured is correspondingly set for the third power port S3I. Each voltage acquisition terminal to be measured is connected to the corresponding power port.

[0069] Furthermore, a control voltage access terminal is provided for each power port, such as Figure 2As shown, a first control voltage Vgs1 access terminal V1I is correspondingly set for the first power port S1I, a second control voltage access terminal V2I is correspondingly set for the second power port S2I, and a third control voltage access terminal V3I is correspondingly set for the third power port S3I. Correspondingly, in the current control sub-circuit 102, a control voltage output terminal is correspondingly set for each control voltage access terminal, a first control voltage Vgs1 output terminal V1O is correspondingly set for the first control voltage Vgs1 access terminal V1I, a second control voltage output terminal V2O is correspondingly set for the second control voltage access terminal V2I, and a third control voltage output terminal V3O is correspondingly set for the third control voltage access terminal V3I, wherein each control voltage output terminal is connected to the corresponding control voltage access terminal.

[0070] Furthermore, the control module 101 is further provided with a control voltage acquisition terminal A5I, which is connected to one of the multiple control voltage output terminals. Figure 2 In the example, the control voltage acquisition terminal A5I is connected to the second control voltage output terminal V2O.

[0071] Based on this, the control module 101 can be used to generate a control signal and send the control signal to the signal access terminal through the signal output terminal.

[0072] Furthermore, the current control subcircuit 102 is also connected to a power supply voltage VDD. When the power supply voltage VDD is connected, the current formed by the power supply voltage VDD is also connected and serves as the sampling current I flowing through the current control subcircuit 102. The sampling current I is output to the current acquisition terminal A4I through the sampling current output terminal A4O, so that the control module 101 obtains the sampling current I.

[0073] Furthermore, the signal access terminal can adjust the total resistance of the current control subcircuit 102 using the access control signal. By changing the total resistance, the sampling current flowing through the current control subcircuit 102 can be adjusted.

[0074] Furthermore, after receiving the power supply voltage VDD, the current control sub-circuit 102 can generate the same number of control voltages as the control voltage output terminals, and output the control voltages through each control voltage output terminal, such as Figure 2 As shown, the first control voltage Vgs1 is generated at the output terminal V1O corresponding to the first control voltage Vgs1, the second control voltage Vgs2 is generated at the output terminal V2O corresponding to the second control voltage, and the third control voltage Vgs3 is generated at the output terminal V3O corresponding to the third control voltage, and the corresponding control voltages are output through each control voltage output terminal.

[0075] When the total resistance changes, each control voltage will also change. By adjusting the total resistance, each control voltage can be adjusted while adjusting the sampling current.

[0076] Furthermore, based on the control voltage acquisition terminal A5I connected to the second control voltage output terminal V2O, the control module 101 can acquire the second control voltage Vgs2 through the control voltage acquisition terminal A5I.

[0077] Based on this, the control module 101 can obtain the sampling current I and the second control voltage Vgs2.

[0078] Furthermore, the control module 101 can input the sampling current I and the second control voltage Vgs2 into a preset voltage function, thereby calculating the control voltages connected to the remaining control voltage access terminals, that is, the first control voltage Vgs1 and the second control voltage Vgs2. Using the known control voltages, the predetermined target current of the corresponding control voltage access terminal can be determined.

[0079] Specifically, based on the device characteristics of each control voltage access terminal, when it is connected to the control voltage, the control voltage access terminal has a constant target current corresponding to the control voltage, and uses the target current as the measured current output by the corresponding power supply under test.

[0080] Furthermore, the control module 101 can obtain the measured voltage output by each power supply under test through each measured voltage acquisition terminal while obtaining the measured current of each power supply under test. That is to say, the obtained measured current is the output of the corresponding power supply under the current measured voltage condition.

[0081] Based on this, the control module 101 can determine whether the voltage to be measured has dropped below a preset voltage threshold based on the obtained voltage to be measured. When the voltage to be measured drops below the voltage threshold, it is considered that the output capacity of the corresponding power supply to be measured has reached its limit, and the corresponding current to be measured at this time is used as the output capacity of the power supply to be measured.

[0082] The voltage threshold may be, for example, 95% of the voltage to be measured output by the power supply to be measured before the voltage to be measured drops.

[0083] It can be seen that in this embodiment, based on the interconnected control module 101, current control subcircuit 102 and current extraction subcircuit 103, when the current extraction subcircuit 103 is connected to multiple power supplies to be tested, the control module 101 can collect the measured voltage output by each power supply to be tested connected to the current extraction subcircuit 103 by controlling the voltage collection terminal A5I, and based on the current collection terminal A4I, the control module 101 can collect the sampled current flowing through the current control subcircuit 102 from the sampling current output terminal of the current control subcircuit 102, and achieve that when testing multiple power supplies to be tested, only one sampling current needs to be collected to deduce the measured current output by each power supply to be tested, thereby determining the measured voltage of each power supply to be tested under different measured currents.

[0084] Among them, based on the signal output terminal set by the control module 101 and the signal access terminal set in the current control subcircuit 102, the control module 101 can interact with the current control subcircuit 102 to control the signal, thereby realizing the control of the sampling current and output control voltage of the current control subcircuit 102.

[0085] Furthermore, based on the multiple control voltage output terminals set in the current control subcircuit 102 and the multiple control voltage access terminals set in the current extraction subcircuit 103, the control voltage controlled by the control module 101 can be input into the current extraction subcircuit 103, thereby controlling the measured current output by each power supply to be tested.

[0086] Among them, the control module 101 can also calculate the various control voltages output by the current control subcircuit 102 based on the sampled current collected by the set current collection terminal A4I, and then, while using the control module 101 to control the current to be measured, the current to be measured output by each power supply to be measured is calculated through the control voltage, so that the current to be measured of each power supply to be measured can be known by collecting the sampled current only once.

[0087] In another embodiment of the present application, the signal output terminal includes a first signal output terminal D10 and a second signal output terminal, and the control signal includes a first control signal DAC1 output by the first signal output terminal D10 and a second control signal DAC2 output by the second signal output terminal;

[0088] The current control subcircuit 102 includes:

[0089] The first control unit 1021 includes a first unit access port, a first signal access terminal D1I, a first control voltage output terminal V1O, and a second control voltage output terminal V2O. The first signal access terminal D1I is connected to the first signal output terminal D1O. The first control unit 1021 is configured to receive a preset power supply voltage VDD through the first unit access port.

[0090] The second control unit 1022 includes a second unit access port, a second signal access terminal D2I, and a third control voltage output terminal V3O, wherein the second unit access port is connected to the second control voltage output terminal V2O, and the second signal access terminal D2I is connected to the second signal output terminal;

[0091] The third control unit 1023 includes a third unit access port and a third unit output port, and the third unit access port is connected to the third control voltage output terminal V3O.

[0092] In this embodiment, if Figure 2 As shown, the control module 101 may have multiple signal output terminals, which may specifically include a first signal output terminal D10 and a second signal output terminal D20.

[0093] Furthermore, if Figure 2 As shown, the control module 101 can generate a plurality of control signals, including a first control signal DAC1 and a second control signal DAC2.

[0094] The control module 101 may output a first control signal DAC1 through a first signal output terminal D10, and output a second control signal DAC2 through a second signal output terminal D20.

[0095] Correspondingly, when there are multiple signal output terminals in the control module 101 , there are also multiple signal input terminals in the current control sub-circuit 102 .

[0096] Specifically, if Figure 2 As shown, when the control module 101 is provided with a first signal output terminal D1O and a second signal output terminal D2O, a first signal access terminal D1I is provided in the current control subunit corresponding to the first signal output terminal D1O, and is used to access the first control signal DAC1 from the first signal output terminal D1O, and a second signal access terminal D2I is provided corresponding to the second signal output terminal D2O, and is used to access the second control signal DAC2 from the second signal output terminal D2O.

[0097] Furthermore, if Figure 3 As shown, the current control subcircuit 102 includes a first control unit 1021 , a second control unit 1022 , a third control unit 1023 and a collection unit 1024 .

[0098] The first control unit 1021 is provided with a first unit access port 1021I, a first signal access terminal D1I, a first control voltage output terminal V1O and a second control voltage output terminal V2O.

[0099] Furthermore, the first unit access port 1021I can be connected to the power supply voltage VDD.

[0100] Based on this, the first control unit 1021 can access the power supply voltage VDD and the sampling current formed by the power supply voltage VDD through the first unit access port, and access the first control signal DAC1 through the first signal access terminal D1I.

[0101] Furthermore, the first control unit 1021 may utilize the first control signal DAC1 to control a first resistance value within the first control unit 1021 . By changing the first resistance value, the sampling current flowing through the first control unit 1021 may be adjusted.

[0102] Furthermore, after the first control unit 1021 is connected to the power supply voltage VDD, it can generate first control voltages Vgs1 and Vgs2 by dividing the power supply voltage VDD using a first resistance, and output the first control voltage Vgs1 through the first control voltage output terminal V1O, and output the second control voltage Vgs2 through the second control voltage output terminal V2O.

[0103] The sampling current flowing through the first control unit 1021 may also be outputted through the second control voltage output terminal V20.

[0104] Furthermore, the second control unit 1022 includes a second unit access port 1022I, a second signal access terminal D2I, and a third control voltage output terminal V3O.

[0105] Among them, Figure 3 As shown, the second unit access port 1022I is connected to the second control voltage output terminal V2O in the first control unit 1021. Accordingly, the second unit access port 1022I can receive the second control voltage Vgs2 and the sampling current output by the second control voltage output terminal V2O.

[0106] Based on this, the second control unit 1022 can access the second control signal DAC2 through the second signal access terminal D2I.

[0107] Furthermore, the second control unit can use the second control signal DAC2 to control the second resistance value in the second control unit 1022 . By changing the second resistance value, the sampling current flowing through the second control unit 1022 can be adjusted.

[0108] Furthermore, after the second control voltage Vgs2 is connected, the second control unit 1022 can generate a third control voltage Vgs3 by dividing the second control voltage Vgs2 using the second resistance value, and output the third control voltage Vgs3 through the third control voltage output terminal V3O. At the same time, the sampling current flowing through the second control unit 1022 is output through the third control voltage output terminal V3O.

[0109] Furthermore, the third control unit 1023 includes a third unit inlet 1023I and a third unit outlet 1023O.

[0110] The third unit access port 1023I is connected to the third control voltage output terminal V3O.

[0111] Based on this, the third control unit 1023 can access the third control voltage Vgs3 and the sampling current output by the third control voltage output terminal V3O through the third unit access port 1023I.

[0112] Furthermore, based on the device characteristics of the third control unit 1023, the third control unit 1023 can keep the sampling current constant. Similarly, based on the device characteristics of the third control unit 1023, the voltage dividing effect of the third control unit 1023 on the third control voltage Vgs3 can be ignored. Accordingly, the third control voltage Vgs3 and the sampling current can be output through the third unit output port 1023O.

[0113] Furthermore, the current control subcircuit 102 further includes:

[0114] The acquisition unit 1024 includes a fourth unit access port, a fourth unit output port and a sampling current output port. The fourth unit access port is connected to the third unit output port for receiving the sampling current, and the sampling current is outputted from the sampling current output port and the third unit output port respectively.

[0115] In this embodiment, if Figure 3 As shown, the current control sub-circuit 102 includes a fourth unit input port 1024I, a fourth unit output port 1024O and a sampling current output terminal A4O.

[0116] The fourth unit inlet 1024I is connected to the third unit output 1023O.

[0117] Based on this, the fourth control unit can access the third control voltage Vgs3 and the sampling current from the third unit output port 1023O, and use the resistance of the fourth control unit itself to divide the third control voltage Vgs3 and output the divided voltage and the sampling current.

[0118] Furthermore, the fourth unit output port 1024O is grounded, thereby outputting the divided voltage and the sampled current.

[0119] Furthermore, the sampling current output terminal A40 is connected to the current collection terminal A4I of the control module 101. When the fourth control unit outputs the sampling current flowing through the sampling current output terminal A40, the control module 101 can collect the sampling current through the current collection terminal A4I.

[0120] It can be seen that in this embodiment, by setting up the first control unit 1021 and the second control unit 1022, their respective resistance values ​​can be adjusted respectively according to the first control signal DAC1 and the second control signal DAC2 output by the control module 101, so that the total resistance value of the current control subcircuit 102 changes, thereby realizing the adjustment of the first control voltage Vgs1, the second control voltage Vgs2 and the third control voltage Vgs3.

[0121] At the same time, based on the third control unit 1023, the sampling current flowing through the current control subcircuit 102 is kept constant, so that it can be determined that the sampling current of the third control voltage output terminal V3O is consistent with the sampling current flowing through the third control unit 1023, so that the sampling current collected by the control module 101 from the collection unit 1024 is consistent with the sampling current flowing through the first control unit 1021, the second control unit 1022 and the third control unit 1023.

[0122] In another embodiment of the present application, the signal output terminal further includes a switch signal output terminal CTLO, each switch signal output terminal CTLO is used to output a switch signal;

[0123] The current extraction sub-circuit 103 includes a plurality of current extraction units, each of which includes:

[0124] A switching transistor, wherein the source is connected to a power supply port and the gate is connected to a switch signal output terminal CTLO, for receiving a switch signal and receiving a voltage and a current to be measured. When the gate is turned on by the switch signal, the voltage and current to be measured connected to the source are output through the drain;

[0125] The regulating transistor has a source connected to the drain of the switching transistor and a gate as a control voltage access terminal, which is used to access the voltage and current to be measured and access a control voltage to control the current to be measured under the condition of the voltage to be measured.

[0126] In this embodiment, the signal output terminal of the control module 101 may further include a switch signal output terminal CTLO.

[0127] Specifically, if Figure 2 In the example, in the current extraction subunit, multiple switch signal access terminals are provided, and all of them are connected to the switch signal output terminal CTLO.

[0128] Specifically, based on the first power port S1I, the second power port S2I and the third power port S3I respectively connected to the three power supplies to be tested, a corresponding first switch signal access terminal CTL1I is set for the first power port S1I, a corresponding second switch signal access terminal CTL2I is set for the second power port S2I, and a corresponding third switch signal access terminal CTL3I is set for the third power port S3I.

[0129] Furthermore, the switch signal output terminal CTLO is simultaneously connected to the first switch signal access terminal CTL1I, the second switch signal access terminal CTL2I, and the third switch signal access terminal CTL3I.

[0130] Based on this, when the control module 101 outputs the switching signal CTL through the switching signal output terminal CTLO, each switching signal input terminal in the power extraction sub-circuit can simultaneously receive the switching signal and execute the switching signal.

[0131] In a specific example, the current extraction sub-circuit 103 includes a plurality of current extraction units. Figure 4 In the example, the current extraction sub-circuit 103 includes a first current extraction unit 1031 , a second current extraction unit 1032 and a third current extraction unit 1033 .

[0132] Among them, the circuit structure of each current extraction unit is the same, each current extraction unit corresponds to a control voltage output terminal, and is connected to a power supply to be tested, used to access the test voltage and test current output by the power supply to be tested, and access the corresponding control voltage from the corresponding control voltage output terminal.

[0133] Each current extraction unit includes a power supply port, a switching transistor and a regulating transistor.

[0134] like Figure 4 As shown, the first current extraction unit 1031 includes a first power supply port S1I, a first switching transistor Q1 and a first regulating transistor Q2; the second current extraction unit 1032 includes a second power supply port S2I, a second switching transistor Q3 and a second regulating transistor Q4; the third current extraction unit 1033 includes a third power supply port S3I, a third switching transistor Q5 and a third regulating transistor Q6.

[0135] Specifically, Figure 4 Taking the third current extraction unit 1033 in the embodiment as a specific example, the third power supply port S3I in the third current extraction unit 1033 is connected to the third voltage acquisition terminal A3I to be measured, so that the control module 101 can obtain the voltage to be measured of the power supply to be measured connected to the third current extraction unit 1033.

[0136] Furthermore, the source of the third switching transistor Q5 in the third current extraction unit 1033 is connected to the third power supply port S3I to receive the voltage and current to be measured from the corresponding third power supply port S3I, and its gate serves as the third switching signal access terminal CTL3I, connected to the switching signal output terminal CTLO to receive the switching signal CTL from the switching signal output terminal CTLO.

[0137] Furthermore, the source of the third regulating transistor Q6 in the third current extraction unit 1033 is connected to the drain of the third switching transistor Q5, and its gate serves as the third control voltage input terminal V3I and is connected to the third control voltage output terminal V3O to input the third control voltage Vgs3 from the third control voltage output terminal V3O, and its drain is grounded.

[0138] Based on this, the third switching transistor Q5 is turned on when the gate receives the switching signal, so that the third voltage to be measured and the third current to be measured connected to the source can be output through the drain and connected to the gate of the third regulating transistor Q6.

[0139] Furthermore, when the gate of the third regulating transistor Q6 is connected to the third control voltage Vgs3, the third control voltage Vgs3 can cause the third regulating transistor Q6 to operate in a saturated constant current region. Accordingly, the characteristics of the saturated constant current region are such that the greater the third control voltage Vgs3 connected to the gate, the greater the current to be measured flowing through the third regulating transistor Q6. Moreover, when the third control voltage Vgs3 connected to the gate is fixed, the current to be measured flowing through the third regulating transistor Q6 is also fixed.

[0140] Furthermore, based on the device characteristics of the third regulating transistor Q6, when the third regulating transistor Q6 operates in the saturated constant current region, the magnitude of the current to be measured flowing through the third regulating transistor Q6 can be determined according to the magnitude of the third control voltage Vgs3 connected to the gate.

[0141] The relationship between the corresponding currents flowing through different gate voltages can be obtained by looking up a table or pre-testing the third regulating transistor Q6. Accordingly, when the third control voltage Vgs3 is determined, the current to be measured flowing through the third transistor Q13 can be directly determined.

[0142] It can be seen that this embodiment is based on the device characteristics of the transistor. When a control voltage is applied thereto, the size of the current to be measured output by the power supply to be measured can be determined according to the size of the control voltage, thereby achieving the ability to determine each voltage to be measured without collecting the voltage to be measured output by each power supply to be measured.

[0143] In another embodiment of the present application, the first control unit 1021 includes:

[0144] A first transistor Q11, having a source serving as a first unit access port, a gate serving as a first signal access terminal D1I, and a drain serving as a first control voltage output terminal V1O. The drain is connected to the gate of the regulating transistor of the first current extraction unit and is used to receive a supply voltage VDD and a sampled current. The drain is also connected to a first control signal DAC1, and the resistance of the first transistor Q11 is controlled by the first control signal DAC1. The supply voltage VDD is divided by the resistance of the first transistor Q11 to obtain a first control voltage Vgs1. The drain outputs the first control voltage Vgs1 and the sampled current.

[0145] The first resistor R1 has a first end connected to the drain of the first transistor Q11, a second end being the second control voltage output end V2O, and a second end connected to the gate of the regulating transistor of the second current extraction unit. The first resistor R1 is used to receive the first control voltage Vgs1 and the sampling current, divide the first control voltage Vgs1 to obtain the second control voltage Vgs2, and output the second control voltage Vgs2 and the sampling current from the second end.

[0146] Furthermore, the second control unit 1022 includes:

[0147] The second transistor Q12 has a source connected to the second end of the first resistor R1, a gate as the second signal access terminal D2I, a drain as the third control voltage output terminal V3O, and a drain connected to the gate of the regulating transistor of the third current extraction unit. It is used to receive the second control voltage Vgs2 and the sampling current, and receive the second control signal DAC2. The second control signal DAC2 is used to control the resistance of the second transistor Q12, and the resistance of the second transistor Q12 is used to divide the second control voltage Vgs2 to obtain a third control voltage Vgs3. The third control voltage Vgs3 and the sampling current are output from the drain.

[0148] Furthermore, the third control unit 1023 includes:

[0149] The third transistor Q13 has a gate connected to a source, the source of which is connected to the drain of the second transistor Q12. The drain is the output port of the third unit and is used to receive the third control voltage Vgs3 and the sampling current. The gate uses the third control voltage Vgs3 to control the third transistor Q13 to operate in a saturated constant current region to keep the sampling current constant, and the sampling current is output from the drain.

[0150] Furthermore, the collection unit 1024 includes:

[0151] The second resistor R2 has a first end as the fourth unit input port and a second end as the fourth unit output port, and is used to receive the sampling current and output it from the second end;

[0152] The acquisition amplifier OPA includes a positive electrode, a negative electrode and a sampling current output end, the negative electrode is connected to the first end of the second resistor R2, the positive electrode is connected to the second end of the second resistor R2, and the output end is connected to the control module 101, and is used to collect the sampling current flowing through the second resistor R2 and output it through the sampling current output end.

[0153] In this embodiment, if Figure 4 As shown, the first control unit 1021 includes a first transistor Q11 and a first resistor R1.

[0154] The source of the first transistor Q11 is connected to the power supply voltage VDD and is also connected to the sampling current formed by the power supply voltage VDD.

[0155] Furthermore, the gate of the first transistor Q11 serves as a first signal input terminal D1I, connected to the first signal output terminal D1O, so as to receive the first control signal DAC1 outputted from the first signal output terminal D1O.

[0156] Accordingly, after the gate of the first transistor Q11 is turned on by the first control signal DAC1 , the first transistor Q11 outputs the supply voltage VDD connected to the source and the sampling current through the drain.

[0157] Among them, based on the component characteristics of the first transistor Q11, the first control signal DAC1 connected to the gate of the first transistor Q11 can enable the first transistor Q11 to operate in the variable resistance area. The first transistor Q11 operating in the variable resistance area can adjust its own resistance Rds11 according to the voltage connected to the gate, that is, the first control signal DAC1, so that the first transistor Q11 can divide the power supply voltage VDD to different degrees based on different first control signals DAC1, thereby obtaining different first control voltages Vgs1, thereby realizing the adjustment of the first control voltage Vgs1 based on the first control signal DAC1 of the control module 101.

[0158] Furthermore, the drain of the first transistor Q11 serves as the first control voltage output terminal V10, and is connected to the gate of the first regulating transistor Q2 in the first current extraction unit 1031. When the drain outputs the first control voltage Vgs1 obtained by dividing the supply voltage VDD and the sampling current, the first control voltage Vgs1 can be output to the gate of the first regulating transistor Q2.

[0159] Furthermore, a first end of the first resistor R1 is connected to the drain of the first transistor Q11 so as to receive the first control voltage Vgs1 and the sampling current from the drain of the first transistor Q11 .

[0160] Furthermore, the second end of the second resistor R2 serves as a second control voltage output end V2O, which is connected to the gate of the second regulating transistor Q4 in the second current extraction unit 1032. After the second resistor R2 divides the first control voltage Vgs1, a second control voltage is obtained, and the second control voltage Vgs2 and the sampling current are output to the gate of the second regulating transistor Q4 through the second end.

[0161] It can be seen that in this embodiment, the first control signal DAC1 controls the first transistor Q11, and at the same time, since the resistance value of the second resistor R2 is fixed, the first control voltage Vgs1 of different sizes will also obtain the second control voltage Vgs2 of different sizes after fixed voltage division, thereby realizing the adjustment of the second control voltage Vgs2.

[0162] Furthermore, if Figure 4 As shown, the second control unit 1022 includes a second transistor Q12.

[0163] The source of the second transistor Q12 is connected to the second end of the first resistor R1 so as to receive the second control voltage Vgs2 and the sampling current from the second end of the first resistor R1 .

[0164] Furthermore, the gate of the second transistor Q12 serves as a second signal input terminal D2I, connected to the second signal output terminal D2O, so as to receive the second control signal DAC2 outputted from the second signal output terminal D2O.

[0165] Accordingly, after the gate of the second transistor Q12 is turned on by the second control signal DAC2 , the second transistor Q12 outputs the second control voltage Vgs2 connected to the source and the sampling current through the drain.

[0166] Among them, based on the component characteristics of the second transistor Q12, the second control signal DAC2 connected to the gate of the second transistor Q12 can enable the second transistor Q12 to operate in the variable resistance area. The second transistor Q12 operating in the variable resistance area can adjust its own resistance Rds12 according to the voltage connected to the gate, that is, the second control signal DAC2, so that the second transistor Q12 can divide the second control voltage Vgs2 to different degrees based on different second control signals DAC2, thereby obtaining different third control voltages Vgs3, thereby realizing the adjustment of the third control voltage Vgs3 based on the second control signal DAC2 of the control module 101.

[0167] Furthermore, the drain of the second transistor Q12 serves as the third control voltage output terminal V3O and is connected to the gate of the third regulating transistor Q6 in the third current extraction unit 1033. When the drain outputs the third control voltage Vgs3 obtained after voltage division and the sampling current, the third control voltage Vgs3 can be output to the gate of the third regulating transistor Q6.

[0168] It can be seen that in this embodiment, the second control signal DAC2 controls the second transistor Q12, so as to adjust the third control voltage Vgs3 by controlling the resistance of the second transistor Q12.

[0169] Furthermore, if Figure 4 As shown, the third control unit 1023 includes a third transistor Q13.

[0170] The source of the third transistor Q13 is connected to the drain of the second transistor Q12 so as to access the third control voltage Vgs3 and the sampling current from the drain of the second transistor Q12.

[0171] Furthermore, the source of the third transistor Q13 and the gate of the third transistor Q13 are connected to each other, so that the gate of the third transistor Q13 is also connected to the third control voltage Vgs3. Based on the component characteristics of the third transistor Q13, the third control voltage Vgs3 can cause the third transistor Q13 to operate in a saturated constant current region. Accordingly, the sampling current connected to the third transistor Q13 can remain constant when flowing through the third transistor Q13. When the third control voltage Vgs3 connected to the gate of the third transistor Q13 remains unchanged, the sampling current flowing through the third transistor Q13 is also constant.

[0172] Furthermore, the relationship between the magnitudes of the currents flowing through the third transistor Q13 under different gate voltages can be obtained by looking up a table or pre-testing the third transistor Q13. Accordingly, when the third transistor Q13 operates in the saturated constant current region, when determining the sampled current, the magnitude of the third control voltage Vgs3 connected to the gate of the third transistor Q13 is directly determined based on the sampled current flowing through the third transistor Q13. Simultaneously, because the gate of the third regulating transistor Q6 in the third current extraction unit 1033 is also connected to the same third control voltage Vgs3 and the third regulating transistor Q6 also operates in the saturated constant current region, when the gates of the third transistor Q13 and the gates of the third regulating transistor Q6 have the same third control voltage Vgs3, the sampled current flowing through the third transistor Q13 is the same as the current to be measured flowing through the third regulating transistor Q6.

[0173] In this embodiment, the shunting effect of the third control voltage Vgs3 on the sampling current output by the second transistor Q12 can be ignored, so that the current output by the drain of the third transistor Q13 can be equal to the sampling current.

[0174] It can be seen that based on the third transistor Q13 being in the saturated constant current region and based on the control of the third transistor Q13 by the third control voltage Vgs3, the same current flows through the third transistor Q13 and the third regulating transistor Q6, so that the measured current of the power supply to be measured connected to the third power port S3I can be directly determined according to the sampled current.

[0175] Furthermore, if Figure 4 As shown, the acquisition unit 1024 includes a second resistor R2 and an acquisition amplifier OPA.

[0176] The first end of the second resistor R2 is connected to the drain of the third transistor Q13 and the sampling current is connected to the drain of the third transistor Q13. The second end of the second resistor R2 is grounded and can be used to output the sampling current.

[0177] Furthermore, the acquisition amplifier OPA has a positive electrode, a negative electrode and a sampling current output terminal.

[0178] Among them, the positive electrode is connected to the second end of the second resistor R2, and the negative electrode is connected to the first end of the second resistor R2. Accordingly, the acquisition amplifier OPA can obtain the sampling current flowing through the second resistor R2 and output it to the current acquisition terminal A4I of the control module 101 through the sampling current output terminal.

[0179] Based on this, the control module 101 can obtain the sampled current. Since the sampled current is the same as the current to be measured of the power supply to be measured connected to the third current extraction unit 1033 , the magnitude of the current to be measured can be known.

[0180] Furthermore, the control module 101 can determine the current to be measured when the voltage to be measured drops below the voltage threshold based on the measured voltage of the power supply to be measured collected by the third current extraction unit 1033, and determine the measured current to be measured as the output capacity of the power supply to be measured.

[0181] Furthermore, with respect to the current to be measured in the second current extraction unit 1032 and the current to be measured in the first current extraction unit 1031, as described above, since the second regulating transistor Q4 and the third regulating transistor Q6 are both in the saturated constant current region, when the second control voltage Vgs2 connected to the second regulating transistor Q4 is determined, the current to be measured flowing through the second regulating transistor Q4, i.e., the current to be measured of the power supply to be measured connected to the second power port S2I, can be directly determined. When the third control voltage Vgs3 connected to the third regulating transistor Q6 is determined, the current to be measured flowing through the third regulating transistor Q6, i.e., the current to be measured of the power supply to be measured connected to the third power port S3I, can be directly determined. The control module 101 can collect the voltage to be measured output by each power supply to be measured through the corresponding voltage to be measured collection terminal. Therefore, when any voltage to be measured drops below the voltage threshold, the corresponding current to be measured can be determined at that time, and the current to be measured can be determined as the output capacity of the corresponding power supply to be measured.

[0182] In this embodiment, the control module 101 may collect the second control voltage Vgs2 through the control voltage collection terminal A5I, and may input the second control voltage Vgs2 and the sampling current into a preset voltage function to calculate the third control voltage Vgs3.

[0183] Specifically, the voltage function specifically indicates that the supply voltage VDD is equal to the sum of the voltage differences across the components that have a voltage divider effect, and can be specifically expressed as the following formula (1):

[0184] VDD=U DS11 +U1+U DS12 +U DS13 +U2 (1)

[0185] Among them, U DS11 represents the voltage difference between the source and drain of the first transistor Q11, U1 represents the voltage difference between the first end and the second end of the first resistor R1, and U DS12 represents the voltage difference between the source and drain of the second transistor Q12, U DS13 represents the voltage difference between the source and the drain of the third transistor Q13, and U2 represents the voltage difference between the first end and the second end of the second resistor R2.

[0186] Since the third transistor Q13 works in the saturated constant current region, U DS13 The third control voltage Vgs3 connected to the gate of the third transistor Q13 is the same, so that U DS13 .

[0187] Furthermore, according to the acquired sampling current and the known resistance value of the second resistor R2 , the product of the sampling current and the resistance value of the second resistor R2 can be used as U2 .

[0188] Furthermore, if Figure 4 As shown, U DS12 +U DS13 The voltage of +U2 is equal to the second control voltage Vgs2 connected to the second transistor Q12. DS13 When U and U2 are generated and the second control voltage Vgs2 is collected, U can be directly determined. DS12 .

[0189] Furthermore, according to the acquired sampling current and the known resistance value of the first resistor R1 , the product of the sampling current and the resistance value of the first resistor R1 can be used as U1 .

[0190] Furthermore, in formula (1), based on the known supply voltage VDD, U DS11 , and as Figure 4 As shown, the supply voltage VDD and U DS11 The difference between them is the first control voltage Vgs1.

[0191] It can be seen that in this embodiment, by only collecting the sampled current, each control voltage can be calculated based on the component characteristics in the saturated constant current region and combined with the calculation of the voltage function. Moreover, based on the fact that the first regulating transistor Q2, the second regulating transistor Q4 and the third regulating transistor Q6 connected to each control voltage are all in the saturated constant current region, it is possible to determine the current to be measured flowing through each regulating transistor according to the corresponding control voltage.

[0192] At the same time, the control module 101 can control the first control voltage Vgs1, the second control voltage Vgs2 and the third control voltage Vgs3 through the first control signal DAC1 and the second control signal DAC2, so that when testing multiple power supplies to be tested at the same time, the test current output by each power supply to be tested can be adjusted at the same time.

[0193] It should be noted that, since the first control voltage Vgs1 is greater than the second control voltage Vgs2, and the second control voltage Vgs2 is greater than the third control voltage Vgs3, based on the characteristics of the saturated constant current region, the measured current flowing through the third regulating transistor Q6 is the largest, the measured current flowing through the second regulating transistor Q4 is greater than the measured current flowing through the first regulating transistor Q2, and the measured current flowing through the first regulating transistor Q2 is the smallest.

[0194] That is to say, the extreme value of the voltage output capability to be measured connected to the first current extraction unit 1031 must be smaller than the extreme value of the voltage output capability to be measured connected to the second current extraction unit 1032, and the extreme value of the voltage output capability to be measured connected to the second current extraction unit 1032 must be smaller than the extreme value of the voltage output capability to be measured connected to the third current extraction unit 1033.

[0195] Based on the same inventive concept, corresponding to any of the above-mentioned embodiments and methods, an embodiment of the present application further provides a method for testing the output capacity of a power supply.

[0196] refer to Figure 5 The power output capability test method is applied to the power output capability test circuit of any of the aforementioned embodiments, and specifically comprises the following steps:

[0197] Step S501: Generate multiple control signals, output one control signal through each signal output terminal, and use each control signal to control the total resistance of the current control subcircuit, so as to adjust the sampling current flowing through the current control subcircuit and the control voltage output by each control voltage output terminal through the total resistance.

[0198] Step S502: collect the voltage under test output from the corresponding power port through each voltage under test collection terminal, collect the sampled current from the sampled current output terminal through the current collection terminal, and collect the control voltage from the corresponding control voltage output terminal through the control voltage collection terminal.

[0199] Step S503: Calculate the control voltage output by each other control voltage output terminal using the sampled current and the collected control voltage, determine the target current of the corresponding control voltage input terminal using each control voltage, and determine the target current as the current to be measured that the corresponding power port receives from the power supply to be measured under the condition of the voltage to be measured.

[0200] The power output capability testing method of the above embodiment is used to implement the corresponding power output capability testing circuit in any of the above embodiments, and has the beneficial effects of the corresponding method embodiment, which will not be described in detail here.

[0201] Based on the same inventive concept, corresponding to any of the above-mentioned embodiments and methods, an embodiment of the present application further provides a power supply output capacity testing device.

[0202] The power output capability testing device includes the power output capability testing circuit of any one of the aforementioned embodiments and is controlled according to the aforementioned power output capability testing method.

[0203] The test device of the above embodiment is used to implement the corresponding power output capability test circuit in any of the above embodiments, and has the beneficial effects of the corresponding method embodiment, which will not be described in detail here.

[0204] It should also be noted that the exemplary embodiments mentioned in this application describe some methods or systems based on a series of steps or devices. However, this application is not limited to the order of the above steps. In other words, the steps can be performed in the order mentioned in the embodiments, or in a different order, or several steps can be performed simultaneously.

[0205] Aspects of the present disclosure have been described above with reference to the flowcharts and / or block diagrams of the methods, devices (systems) and computer program products according to the embodiments of the present disclosure. It should be understood that each box in the flowchart and / or block diagram and the combination of each box in the flowchart and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer or other programmable data processing device to produce a machine so that these instructions executed by the processor of the computer or other programmable data processing device enable the implementation of the function / action specified in one or more boxes of the flowchart and / or block diagram. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor or a field programmable logic circuit. It is also understood that each box in the block diagram and / or flowchart and the combination of the boxes in the block diagram and / or flowchart can also be implemented by dedicated hardware that performs the specified function or action, or can be implemented by a combination of dedicated hardware and computer instructions.

[0206] The above description is only a specific embodiment of the present application. Those skilled in the art will clearly understand that for the convenience and brevity of description, the specific working processes of the systems, modules and units described above can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here. It should be understood that the scope of protection of the present application is not limited thereto. Any person skilled in the art can easily think of various equivalent modifications or replacements within the technical scope disclosed in the present application, and these modifications or replacements should be included in the scope of protection of the present application.

Claims

1. A power supply output capability test circuit, characterized in that: include: A control module, comprising a signal output terminal, a current collection terminal, a control voltage collection terminal and a plurality of voltage collection terminals to be measured; A current control subcircuit, comprising a signal access terminal, a sampling current output terminal and a plurality of control voltage output terminals, wherein the signal access terminal is connected to the signal output terminal, the sampling current output terminal is connected to the current collection terminal, and one of the plurality of control voltage output terminals is connected to the control voltage collection terminal; The current extraction subcircuit includes a plurality of power ports, a control voltage access terminal is provided corresponding to each power port, each power port is connected to a preset power supply to be tested and a voltage collection terminal to be tested, and each control voltage access terminal is connected to a control voltage output terminal; The control module is used to generate a control signal, and the control signal is used to adjust the sampling current flowing through the current control subcircuit and the control voltage output by each control voltage output terminal; Collecting the voltage to be tested outputted by the corresponding power supply to be tested from each power supply port, collecting the sampled current from the sampled current output terminal, and collecting the corresponding control voltage from one of the plurality of control voltage output terminals; The sampled current and the collected control voltage are input into a preset voltage function to calculate the control voltages connected to the remaining control voltage access terminals, and each control voltage is used to determine a predetermined target current of the corresponding control voltage access terminal, and the target current is determined as the current to be tested output by the corresponding power supply to be tested when the corresponding power supply to be tested outputs the voltage to be tested.

2. The power output capability test circuit according to claim 1, characterized in that: The signal output terminal includes a first signal output terminal and a second signal output terminal, and the control signal includes a first control signal output by the first signal output terminal and a second control signal output by the second signal output terminal; The current control subcircuit comprises: A first control unit comprises a first unit access port, a first signal access terminal gate, a first control voltage output terminal drain and a second control voltage output terminal, wherein the first signal access terminal is connected to the first signal output terminal, and the first control unit is used to access a preset power supply voltage through the first unit access port; A second control unit comprises a second unit access port, a second signal access port and a third control voltage output port, wherein the second unit access port is connected to the second control voltage output port, and the second signal access port is connected to the second signal output port; The third control unit comprises a third unit access port and a third unit output port, wherein the third unit access port is connected to the third control voltage output terminal.

3. The power output capability test circuit according to claim 1, characterized in that: The signal output end also includes a switch signal output end, which is used to output a switch signal; The current extraction subcircuit comprises a plurality of current extraction units, each current extraction unit comprising: A switching transistor, wherein a source is connected to a power supply port and a gate is connected to a switching signal output terminal; The regulating transistor has a source connected to the drain of the switching transistor and a gate as a control voltage access terminal.

4. The power output capability test circuit according to claim 1, characterized in that: The current control subcircuit also includes: The collection unit comprises a fourth unit access port, a fourth unit output port and the sampling current output end, wherein the fourth unit access port is connected to the third unit output port.

5. The power output capability test circuit according to claim 2, characterized in that: The first control unit comprises: A first transistor, whose source is the first unit access port, whose gate is the first signal access terminal, whose drain is the first control voltage output terminal, and whose drain is connected to the gate of the regulating transistor of the first current extraction unit; A first resistor has a first end connected to the drain of the first transistor, a second end being the second control voltage output end, and a second end connected to the gate of the regulating transistor of the second current extraction unit.

6. The power output capability test circuit according to claim 5, characterized in that: The second control unit comprises: The second transistor has a source connected to the second end of the first resistor, a gate as the second signal access terminal, a drain as the third control voltage output terminal, and a drain connected to the gate of the regulating transistor of the third current extraction unit.

7. The power output capability test circuit according to claim 6, characterized in that: The third control unit comprises: The third transistor has a gate connected to a source, the source is connected to the drain of the second transistor, and the drain is the output port of the third unit.

8. The power output capability test circuit according to claim 7, characterized in that: The acquisition unit comprises: A second resistor, a first end of which is the fourth unit access port, a second end of which is the fourth unit output port, and is used to receive the sampling current and output the sampling current from the second end; The acquisition amplifier comprises a positive electrode, a negative electrode and a sampling current output terminal, wherein the negative electrode is connected to the first terminal of the second resistor, the positive electrode is connected to the second terminal of the second resistor, and the output terminal is connected to the control module.

9. A method for testing power output capability, characterized in that: Applicable to a power supply output capability test circuit as claimed in any one of claims 1 to 8; the method comprising: Generate a control signal, wherein the control signal is used to adjust the sampling current flowing through the current control subcircuit and the control voltage output by each control voltage output terminal; Collecting the voltage to be tested output by the corresponding power supply to be tested from each power supply port, collecting the sampled current from the sampled current output terminal, and collecting the control voltage from one of the plurality of control voltage output terminals; The sampled current and the collected control voltage are input into a preset voltage function to calculate the control voltage output by each other control voltage output terminal, and each control voltage is used to determine the target current of the corresponding control voltage access terminal, and the target current is determined as the current to be measured output by the corresponding power supply to be measured when the corresponding power supply to be measured outputs the voltage to be measured.

10. A testing device, characterized in that: The testing device comprises a power supply output capability testing circuit as claimed in any one of claims 1 to 8.

Images