Display device

Abstract

The invention relates to a display device. The display device includes: at least one spatial light modulator that displays an augmented reality content image; a surface light source device which supplies the image display light to the at least one spatial light modulator as background light from a rear direction of the at least one spatial light modulator; and at least one image transmission member forming a display path of the augmented reality content image. The surface light source device includes an organic light emitting display unit including a plurality of light emitting pixels performing surface emission. The surface light source device includes an emission driving circuit that supplies each of an emission control voltage and a scan timing control signal to a plurality of light emitting pixels to control a light emitting operation of the plurality of light emitting pixels.

Description

Technical Field

[0001] The present disclosure relates to a display device. Background Art

[0002] With the development of electronic devices and display devices capable of realizing virtual reality (VR), technologies capable of realizing extended reality content images (such as, for example, augmented reality (AR), mixed reality (MR), and extended holographic images) have been studied as the next step of virtual reality.

[0003] Unlike virtual reality, which is based on a completely virtual world, augmented reality is a display technology that can further increase the effect of reality by superimposing virtual objects or image information on the real world environment. In some cases, stereoscopic imaging technology using a hologram method or the like can fundamentally avoid the weakness of the traditional stereoscopic method of viewing stereoscopic images using binocular parallax. Therefore, stereoscopic imaging technology using a hologram method has attracted attention as the next generation of stereoscopic imaging technology that is finally achieved.

[0004] In the case of an extended reality content image such as a holographic image, since the actual image formed is directly seen by the eyes without using an optical illusion, the user may experience a 3D effect in which the user feels no different from seeing a corresponding real object or environment. Therefore, the holographic image can provide an advantage that viewing the holographic image for a long time does not cause fatigue.

[0005] Some methods of displaying extended reality content images (such as, for example, holograms) may use spatial light modulators, and in some cases, the performance of the spatial light modulator may be used as a factor in determining performance and 3D effects. Recently, liquid crystal display panels have been used as spatial light modulators. Therefore, the light-emitting structure of a light-emitting panel used as a background light source (such as, for example, a backlight) may be used as a factor in determining the display quality and viewing angle of the extended reality content image. Summary of the invention

[0006] Aspects of the present disclosure provide a display device capable of improving a light emitting pixel arrangement structure and a surface light emission driving method of a surface light source device used as a backlight of a spatial light modulator. In some aspects, the display device can display an extended reality content image, such as a hologram, using an ultra-low resolution surface light source.

[0007] Aspects of the present disclosure also provide a display device capable of controlling light emitting operations of light emitting pixels for each emission area to correspond to a displayed image.

[0008] However, aspects of the present disclosure are not limited to the examples set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0009] According to an embodiment of the present disclosure, a display device includes: at least one spatial light modulator, which displays an extended reality content image; a surface light source device, which provides image display light from the rear direction of at least one spatial light modulator to at least one spatial light modulator as background light; and at least one image transmission member, which forms a display path for the extended reality content image, wherein the surface light source device includes: an organic light-emitting display unit, which includes a plurality of light-emitting pixels that perform surface emission; and an emission drive circuit, which provides an emission control voltage and a scanning timing control signal to each of the plurality of light-emitting pixels to control the light-emitting operation of the plurality of light-emitting pixels.

[0010] In an embodiment, a plurality of light-emitting pixels include: a plurality of pixel drivers, which receive scan timing control signals according to the same timing; and light-emitting elements, which emit light based on one or more driving currents through at least one pixel driver among the plurality of pixel drivers, wherein the plurality of pixel drivers receive scan timing control signals and emission control voltages according to the same timing so that the light-emitting elements emit light simultaneously.

[0011] In an embodiment, the light emitting element is formed on the organic light emitting display surface in one or more of a sector shape, a triangle shape, a quadrangular shape, a circular shape, a semicircular shape, and an elliptical shape.

[0012] In an embodiment, a display device includes: at least one spatial light modulator that displays an extended reality content image; a surface light source device that provides image display light to the spatial light modulator from a rear direction of the at least one spatial light modulator as background light; and at least one image transmission member that forms a display path for the extended reality content image. The surface light source device includes an organic light emitting display unit, which includes a plurality of light emitting pixels that perform surface light emission. The surface light source device includes an emission driving circuit that controls the light emitting operation of the plurality of light emitting pixels by providing each of an emission control voltage and a scanning timing control signal to the plurality of light emitting pixels, wherein the emission driving circuit provides the scanning timing control signal and the emission control voltage to the plurality of light emitting pixels according to the same timing, so that the plurality of light emitting pixels are driven according to the same timing in at least one frame unit.

[0013] According to an embodiment supported by aspects of the present disclosure, a display device can improve the light-emitting pixel arrangement structure and the surface light emission driving method of a surface light source device to provide ultra-low resolution background light to a spatial light modulator, thereby improving the driving efficiency and manufacturing efficiency of the display device displaying extended reality content images (such as, for example, holograms).

[0014] According to an embodiment supported by aspects of the present disclosure, a display device may control the light-emitting operation of light-emitting pixels for each emission area of ​​a surface light source device to increase the three-dimensional effect of an extended reality content image (such as, for example, a hologram) and reduce power consumption.

[0015] However, the effects of the present disclosure are not limited to the above effects, and various other effects are included in the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above and other aspects and features of the present disclosure will become more apparent by describing embodiments thereof in detail with reference to the accompanying drawings, in which:

[0017] Figure 1 An application example of a projector-type extended reality content image display device according to an embodiment supported by aspects of the present disclosure is shown;

[0018] Figure 2 An application example of a glasses-type extended reality content image display device according to an embodiment supported by aspects of the present disclosure is shown;

[0019] Figure 3 is an exploded perspective view schematically showing the configuration of an augmented reality content image display device according to the first embodiment;

[0020] Figure 4 is an exploded perspective view schematically showing a configuration of an augmented reality content image display device according to a second embodiment;

[0021] Figure 5 It specifically shows Figure 3 A plan view of a first embodiment of a surface light source device shown;

[0022] Figure 6 It specifically shows Figure 4 A plan view of a first embodiment of a surface light source device shown;

[0023] Figure 7 It is shown Figure 5 A side cross-sectional view of the cross-sectional structure of the surface light source device shown in;

[0024] Figure 8 It is schematically shown Figure 6A plan view of the structure of an organic light emitting display surface of a surface light source device shown;

[0025] Fig. 9 is a circuit diagram showing a circuit structure of a light-emitting pixel according to a first embodiment supported by aspects of the present disclosure;

[0026] Fig.10 is provided to Fig. 9 The waveform diagram of the scanning timing control signal of the multiple light emitting elements shown;

[0027] Fig.11 is a circuit diagram showing a circuit structure of a light-emitting pixel according to a second embodiment supported by aspects of the present disclosure;

[0028] Fig.12 is provided to Fig.11 The waveform diagram of the scanning timing control signal of the multiple light emitting elements shown;

[0029] Fig.13 It specifically shows Figure 3 A plan view of a second embodiment of the surface light source device shown;

[0030] Fig.14 It specifically shows Figure 4 A plan view of a second embodiment of the surface light source device shown;

[0031] Fig.15 It is schematically shown Fig.14 A plan view of the structure of an organic light emitting display surface of a surface light source device shown;

[0032] Fig.16 It is specifically shown that the arrangement is Fig.15 A circuit diagram of a first embodiment of a circuit structure of a light-emitting pixel on an organic light-emitting display surface;

[0033] Fig.17 is a diagram showing a display image displayed on a spatial light modulator;

[0034] Fig.18 It shows that Fig.16 A circuit diagram of a method for controlling light-emitting driving of each emission region of a light-emitting pixel shown in FIG.

[0035] Fig.19 It is specifically shown that the arrangement is Fig.15 A circuit diagram of a second embodiment of a circuit structure of a light-emitting pixel on an organic light-emitting display surface; and

[0036] Fig. 20 It is shown Fig.19 FIG. 1 is a circuit diagram of a first embodiment of a circuit structure of a light-emitting pixel. DETAILED DESCRIPTION

[0037] The present disclosure will now be described more fully below with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. However, the present disclosure may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete and will fully convey the scope of the present disclosure to those skilled in the art.

[0038] It will also be understood that when a layer is referred to as being 'on' another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Throughout the specification, the same reference numerals refer to the same components.

[0039] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. For example, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element. Similarly, the second element may also be referred to as the first element. Unless otherwise stated, terms in the singular may include plural forms.

[0040] Each of the features of the various embodiments of the present disclosure can be combined with each other in part or in whole, and various interlocks and drives are technically possible. Each embodiment can be implemented independently of each other, or can be implemented together in association.

[0041] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

[0042] Figure 1 An application example of a projector-type extended reality content image display device according to an embodiment supported by aspects of the present disclosure is shown. Figure 2 An application example of a glasses-type extended reality content image display device according to an embodiment supported by aspects of the present disclosure is shown.

[0043] refer to Figure 1 and Figure 2 According to an embodiment, the display device 200 for displaying an extended reality content image (such as, for example, a hologram) can be formed as a projector type, which can be easily carried by a user and can be installed or assembled into a structure on a ceiling or wall or in a specific space.

[0044] In some aspects, the display device 200 according to the embodiment may be integrally formed with a glasses-type frame that can be easily carried and worn or removed by a user, or may be mounted or assembled in a glasses-type frame.

[0045] In the present disclosure, the display device 200 displays and provides an extended reality content image FH in a specific space through a 3D lens or sheet, so that the extended reality content image FH (such as, for example, a hologram) can be recognized in the real space visible to the user's eyes. The extended reality content image FH may include 2D or 3D extended reality image content and sound content, wherein the 2D or 3D extended reality image content is a combination of a graphic image, an image captured by a camera, and a text image.

[0046] Figure 3 is an exploded perspective view schematically showing the configuration of the augmented reality content image display device according to the first embodiment. Figure 4 is an exploded perspective view schematically showing the configuration of an augmented reality content image display device according to the second embodiment.

[0047] refer to Figure 3 and Figure 4 The display device 200 for displaying an extended reality content image (such as, for example, a hologram) according to the first embodiment may have a shape similar to a polygonal plane (such as, for example, a square or rectangular plane) or a quadrilateral plate. In some examples, the display device 200 according to the second embodiment may have a shape similar to a disk or a circular plate with a curved edge (such as, for example, a circular or elliptical edge).

[0048] The display device 200 having a shape similar to a quadrilateral plate or a circular plate includes at least one spatial light modulator 210, at least one surface light source device 110, and at least one image transmission member 310. Here, each of the spatial light modulator 210 and the surface light source device 110 may be a quadrilateral plate or a circular plate shaped according to the planar structure or shape of the display device 200.

[0049] At least one surface light source device 110 is disposed behind the spatial light modulator 210 to provide background light to a rear surface of the spatial light modulator 210 as backlight.

[0050] The surface light source device 110 may include an organic light emitting display device (OLED), an inorganic electroluminescent (EL) display device, a quantum dot light emitting display device (QED), a cathode ray tube (CRT) display device, a micron light emitting diode (LED) display device, or a nano LED display device.

[0051] The following will describe the case where an organic light emitting display panel is applied as the surface light source device 110 as an example. However, the surface light source device 110 according to the embodiment is not limited to the organic light emitting display panel or device, and other display panels or devices listed herein or known in the art may also be applied within the scope of the shared technical spirit.

[0052] The surface light source device 110 applied as an organic light emitting display panel may be formed to have a different resolution than the at least one spatial light modulator 210. Specifically, the surface light source device 110 may be formed to have a lower resolution than the at least one spatial light modulator 210.

[0053] The surface light source device 110 receives the extended reality content image data from the outside, arranges the extended reality content image data according to a preset first resolution, and then converts the extended reality content image data of the first resolution into a digital analog image signal and displays it on the emission area of ​​the organic light emitting display surface.

[0054] The organic light emitting display surface may include an emission area of ​​the surface light source device 110. The first resolution of the extended reality content image display light displayed on the organic light emitting display surface of the surface light source device 110 (i.e., displayed on the emission area of ​​the surface light source device 110) is provided to the rear surface of the spatial light modulator 210 as backlight (i.e., background light). The terms "extended reality content image display light", "image display light", and "surface light of the surface light source device 110" may be used interchangeably herein.

[0055] The spatial light modulator 210 generates an extended reality content image based on the extended reality content image data from the outside, and provides the extended reality content image to the image transmission component 310 in front of the spatial light modulator 210 so that the extended reality content image is displayed in the image display direction and space of the image transmission component 310.

[0056] The spatial light modulator 210 may include a liquid crystal display device (LCD) that displays an augmented reality content image of a second resolution on a front surface by using background light of a first resolution provided from a surface light source device 110 positioned behind the spatial light modulator 210 .

[0057] The following describes the case where a liquid crystal display panel is used as the spatial light modulator 210 as an example. However, the embodiments are not limited to liquid crystal display panels or devices, and other display panels listed herein or display devices known in the art may also be applied within the scope of the shared technical spirit.

[0058] The spatial light modulator 210 applied as a liquid crystal display panel may be formed to have the same resolution or a different resolution than the at least one surface light source device 110. However, in an embodiment, the spatial light modulator 210 may be formed to have a higher resolution than the at least one surface light source device 110.

[0059] The spatial light modulator 210 receives the extended reality content image data input from the outside, and arranges the extended reality content image data according to a preset second resolution. The spatial light modulator 210 converts the extended reality content image data of the second resolution into an analog image signal, and displays the extended reality content image data on an image display surface on which a plurality of pixels are arranged. The second resolution of the spatial light modulator 210 is set to be higher than the first resolution of the surface light source device 110. Therefore, the spatial light modulator 210 generates an extended reality content image of a second resolution higher than the first resolution by using the background light of the first resolution provided from at least one surface light source device 110 behind the spatial light modulator 210, and displays the generated extended reality content image on its front surface.

[0060] At least one image transmission component 310 transmits the augmented reality content image FH according to the third resolution (in which the background light of the first resolution is mixed with the augmented reality content image of the second resolution) through a preset optical path to guide and provide the augmented reality content image FH in a preset image display direction. Specifically, for example, the image transmission component 310 forms a display path (or optical path) of the augmented reality content image FH so that the augmented reality content image FH of the third resolution can be displayed in a preset space or display surface.

[0061] The image transmission member 310 may include at least one optical member among an optical waveguide (e.g., a prism), a diverging lens, and a focusing lens. Therefore, the extended reality content image FH displayed by the at least one spatial light modulator 210 is guided to a specific space through the optical waveguide, the diverging lens, and the at least one focusing lens, and is recognized as an extended reality content image FH of a third resolution in the real space. The extended reality content image FH displayed as a hologram type by the image transmission member 310 may include 2D or 3D extended reality image content. In some examples, the 2D or 3D extended reality image content may include a combination of graphic images, images captured by a camera, and text images, as well as sound content.

[0062] Figure 5 It specifically shows Figure 3 FIG. 1 is a plan view of a first embodiment of a surface light source device shown in FIG. Figure 6 It specifically shows Figure 4 FIG. 1 is a plan view of a first embodiment of a surface light source device shown in FIG.

[0063] refer to Figure 5 and Figure 6 At least one surface light source device 110 is formed to serve as a light source for providing background light to the rear surface of at least one spatial light modulator 210.

[0064] The surface light source device 110 may have a rectangular shape, a square shape, a circular shape, an elliptical shape, or other quadrilateral shapes in a plan view. For example, the spatial light modulator 210 may be formed in a circular shape in a plan view, and the surface light source device 110 may have a circular shape corresponding to the circular shape of the spatial light modulator 210 in a plan view. However, the embodiment is not limited thereto, and the surface light source device 110 and the spatial light modulator 210 may be formed in a rectangular shape having a long side extending in a first direction (e.g., in a horizontal direction) and a short side extending in a second direction (e.g., in a vertical direction).

[0065] refer to Figure 5 , at least one surface light source device 110 includes: a surface light-emitting unit DU1, which presents background light as a surface light source; an emission driving circuit 120, which drives the light-emitting pixels of the surface light-emitting unit DU1; and a first data processor 140, which provides extended reality content image data of a first resolution to the emission driving circuit 120.

[0066] Specifically, for example, at least one surface light source device 110 includes a surface light emitting unit DU1 that presents background light as a surface light source. Here, the surface light emitting unit DU1 may include a plurality of light emitting pixels, and the background light (which is a surface light source) may be emitted through the light emitting pixels. The light emitting pixels in the surface light emitting unit DU1 are formed and arranged to correspond to a preset first resolution.

[0067] The first data processor 140 extracts the extended reality content image data of the first resolution from the extended reality content image data input from the outside. Additionally or alternatively, the first data processor 140 may convert the extended reality content image data input from the outside into extended reality content image data of the preset first resolution. The first data processor 140 transmits the extended reality content image data of the first resolution to the emission driving circuit 120 of the surface light source device 110.

[0068] The emission driving circuit 120 may output a data signal and a voltage for driving the light-emitting pixels of the surface light-emitting unit DU1. Specifically, for example, the emission driving circuit 120 receives the extended reality content image data from the first data processor 140 (such as, for example, a graphics card), and arranges the extended reality content image data according to a preset first resolution. Then, the emission driving circuit 120 may convert the extended reality content image data of the first resolution into an analog emission signal (or an analog emission control signal), and provide the analog emission signal to the light-emitting pixels arranged on the organic light-emitting display surface DA1 of the surface light-emitting unit DU1.

[0069] Figure 7 It is shown Figure 5A side sectional view of the sectional structure of the surface light source device shown in FIG.

[0070] refer to Figure 5 and Figure 7 , the surface light emitting unit DU1 may be divided into a first main area MA1 and a first sub-area SBA1. The first main area MA1 may include an organic light emitting display surface DA1 on which a plurality of light emitting pixels performing surface emission are arranged and a first non-display area NDA1 disposed around the organic light emitting display surface DA1. The term “performing surface emission” may include emitting light at the first main area MA1 of the organic light emitting display surface DA1.

[0071] Light emitted from the corresponding emission area or opening area of ​​the light-emitting pixel can be displayed as background light on the organic light-emitting display surface DA1. The light-emitting pixel of the organic light-emitting display surface DA1 may include a pixel driver including a switching element, a pixel defining layer defining the emission area or opening area, and a self-luminous element.

[0072] The first non-display area NDA1 may be an area at the periphery of the organic light emitting display surface DA1. The first non-display area NDA1 may be defined as an edge area of ​​the first main area MA1. The first non-display area NDA1 may include a first gate driver 111 that provides a gate signal to a gate line (not shown) and a fan-out line (not shown) connecting the emission driving circuit 120 and the organic light emitting display surface DA1.

[0073] The first sub-area SBA1 may extend from one side of the first main area MA1. The first sub-area SBA1 may include a flexible material that may be bent, folded, or curled. For example, when the first sub-area SBA1 is bent, it may overlap with the first main area MA1 in the thickness direction (Z-axis direction). The first sub-area SBA1 may include an emission drive circuit 120 and a pad unit connected to the first circuit board 130. Alternatively, the first sub-area SBA1 may be omitted, and the emission drive circuit 120 and the pad unit may be disposed in the first non-display area NDA1.

[0074] At least one emission driving circuit 120 may be formed as an integrated circuit and mounted in the first non-display area NDA1 by a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic bonding method. For example, the emission driving circuit 120 may be disposed in the first sub-area SBA1 and may overlap with the first main area MA1 in the thickness direction (Z-axis direction) by bending of the first sub-area SBA1. In another example, the emission driving circuit 120 may be mounted on the first circuit board 130.

[0075] The first circuit board 130 may be attached to the pad unit in the first non-display area NDA1 using an anisotropic conductive film (ACF). The leads of the first circuit board 130 may be electrically connected to the pad unit in the first non-display area NDA1. The first circuit board 130 may be a flexible printed circuit board, a printed circuit board, or a flexible film (such as, for example, a chip on film).

[0076] Figure 7 The first substrate SUB1 of the surface light-emitting unit DU1 shown may be a base substrate or a base member. The first substrate SUB1 may be a flexible substrate that can be bent, folded, or curled. For example, the first substrate SUB1 may include a glass material or a metal material. However, the embodiment is not limited thereto. In another example, the first substrate SUB1 may include a polymer resin, such as polyimide (PI) as an example.

[0077] The first thin film transistor layer TFTL1 may be disposed on the first substrate SUB1. The first thin film transistor layer TFTL1 may include a plurality of thin film transistors constituting a pixel driver of a light emitting pixel. The first thin film transistor layer TFTL1 may also include a gate line, a data line, a power line, a gate control line, a fan-out line connecting the emission driving circuit 120 and the data line, and a lead connecting the emission driving circuit 120 and the pad unit. When the first gate driver 111 is formed on one side of the first non-display area NDA1 of the surface light emitting unit DU1, the first gate driver 111 may also include a thin film transistor.

[0078] The first thin film transistor layer TFTL1 may be disposed on the organic light emitting display surface DA1, the first non-display area NDA1, and the first sub-area SBA1. The thin film transistors, gate lines, data lines, and power lines of the pixels of the first thin film transistor layer TFTL1 may be disposed on the organic light emitting display surface DA1. The gate control lines and fan-out lines of the first thin film transistor layer TFTL1 may be disposed in the first non-display area NDA1. The lead lines of the first thin film transistor layer TFTL1 may be disposed in the first sub-area SBA1.

[0079] The first light emitting element layer EML1 may be disposed on the first thin film transistor layer TFTL1. The first light emitting element layer EML1 may include a plurality of light emitting elements and a pixel defining layer defining pixels, each light emitting element including a first electrode, a light emitting layer, and a second electrode sequentially stacked to emit light. The light emitting elements of the first light emitting element layer EML1 may be disposed on the organic light emitting display surface DA1. The light emitting elements may be formed on the organic light emitting display surface DA1 in one or more of a fan shape, a triangular shape, a quadrilateral shape, a circular shape, a semicircular shape, and an elliptical shape. As an example, the light emitting element may have a rhombus shape.

[0080] The first encapsulation layer TFEL1 may cover the upper surface and the side surface of the first light emitting element layer EML1 and may protect the first light emitting element layer EML1. The first encapsulation layer TFEL1 may include at least one inorganic layer and at least one organic layer to encapsulate the first light emitting element layer EML1.

[0081] Figure 8 It is schematically shown Figure 6 The surface light source device shown is a plan view of the structure of the organic light emitting display surface.

[0082] refer to Figure 8 , the organic light emitting display surface DA1 of the surface light emitting unit DU1 is an area that presents background light through surface light emission, and can be defined as the central area of ​​the surface light emitting unit DU1. The organic light emitting display surface DA1 may include a plurality of light emitting pixels OSP, a plurality of gate lines GL, a plurality of data lines DL, and a plurality of power lines PL. Each of the light emitting pixels OSP may be defined as a minimum unit that emits light. The plurality of gate lines GL may include at least one of a display initialization line, a display scan line, and a display control line.

[0083] The plurality of gate lines GL may provide the light-emitting pixels OSP with a plurality of scan timing control signals received from the first gate driver 111. Each of the gate lines GL (scanning lines) may extend in the X-axis direction and the Y-axis direction based on the arrangement direction and the planar shape of the light-emitting pixels OSP, and may be disposed in the X-axis direction or the Y-axis direction around the light-emitting pixels OSP.

[0084] The data line DL may provide the emission pixel OSP with an emission control voltage received from the emission driving circuit 120. The data line DL may extend in the X-axis direction and the Y-axis direction based on the arrangement direction and the planar shape of the emission pixel OSP, and may be disposed in the X-axis direction or the Y-axis direction around the emission pixel OSP.

[0085] The power line PL may provide each power supply voltage received from the emission driving circuit 120 or a separate power supply unit to the light-emitting pixel OSP. Here, the power supply voltage may be at least one of a high potential driving voltage, a low potential ground voltage, and a reference voltage. The power line PL may extend in the X-axis direction and the Y-axis direction based on the arrangement direction and the plane shape of the light-emitting pixel OSP, and may be arranged around the light-emitting pixel OSP in the X-axis direction or the Y-axis direction. The description of the elements (e.g., gate lines GL, data lines DL, power lines PL) arranged around the light-emitting pixel OSP in the X-axis direction or the Y-axis direction may be applied to elements arranged above or below the light-emitting pixel OSP (in the Y-axis direction) and / or arranged to the side of the light-emitting pixel OSP (the side in the X-axis direction).

[0086] The first non-display area NDA1 may include a first gate driver 111, a fan-out line (not shown), and a gate control line (not shown). The first gate driver 111 may generate a gate signal in units of at least one frame period based on a gate control signal, and may simultaneously provide the gate signal to a plurality of gate lines GL (scanning lines) in units of at least one frame period.

[0087] The fan-out line may extend from the emission driving circuit 120 to the organic light emitting display surface DA1. The fan-out line may simultaneously receive an emission control voltage from the emission driving circuit 120 and provide the emission control voltage to the data line DL in units of at least one frame period.

[0088] The first gate control line may extend from the emission driving circuit 120 to the first gate driver 111. The first gate control line may provide a gate control signal received from the emission driving circuit 120 to the first gate driver 111.

[0089] The emission driving circuit 120 provides a gate control signal to the first gate driver 111 through a gate control line. Therefore, for example, the first gate driver 111 provides a plurality of scan timing control signals for simultaneously driving the light-emitting pixels OSP to the light-emitting pixels OSP (for example, providing the plurality of scan timing control signals to the light-emitting pixels OSP based on the gate control signal). Here, the emission driving circuit 120 may output an analog emission control voltage for simultaneously driving the light-emitting pixels OSP to the fan-out line. The analog emission control voltage may be provided to the light-emitting pixels OSP, and the brightness of the light-emitting pixels OSP may be based on the analog emission control voltage.

[0090] Fig. 9 is a circuit diagram showing a circuit structure of a light-emitting pixel according to a first embodiment supported by aspects of the present disclosure.

[0091] refer to Fig. 9 as well as Figure 8 , each of the light emitting pixels OSP arranged on the organic light emitting display surface DA1 includes a light emitting element LEL and at least one of the pixel drivers DP1 to DPn.

[0092] Each of the light emitting elements LEL may be connected in series to at least one of the pixel drivers DP1 to DPn. Each of the light emitting elements LEL may emit light in response to a driving current simultaneously input from the pixel drivers DP1 to DPn. For example, each light emitting element LEL may emit light in response to a driving current simultaneously input from a corresponding pixel driver (e.g., pixel driver DP1 to pixel driver DPn) electrically connected to the light emitting element LEL. The term "connected to" as stated herein may represent an electrical and / or physical connection between elements.

[0093] The pixel drivers DP1 to DPn receive the same scan timing control signal and the analog emission control voltage through the emission driving circuit 120 and the first gate driver 111, and the pixel drivers DP1 to DPn can drive the light emitting elements LEL connected in series therewith according to the same driving timing in units of at least one frame. The scan timing control signal may include a display initialization signal, a display scan signal, an emission control signal, and a display control signal.

[0094] Specifically, for example, the light-emitting pixel OSP is set at an ultra-low resolution. For example, the light-emitting pixel OSP can be formed in units of at least three and arranged on the organic light-emitting display surface DA1. In other words, the light-emitting pixel OSP can be formed in units of at least three and arranged on the organic light-emitting display surface DA1, and the number of the light-emitting pixels OSP arranged on the organic light-emitting display surface DA1 can be a multiple of 3 (for example, 3, 6, 9, 12, 15, ...).

[0095] The planar area of ​​the light-emitting element LEL of each light-emitting pixel OSP is inversely proportional to the number of resolutions (or the number of light-emitting elements). That is, the planar area of ​​each light-emitting element LEL may be inversely proportional to the resolution at which the light-emitting element LEL is set, so that the lower the resolution, the wider the planar area of ​​each light-emitting element LEL can be formed. In some aspects, the resolution of a given light-emitting element LEL decreases as the width of the planar area of ​​the light-emitting element LEL increases. Here, since the resistance-capacitance (RC) value of each light-emitting element LEL increases as the planar area of ​​each light-emitting element LEL increases, the systems and techniques described herein may include connecting a plurality of pixel drivers DP1 to DPn to each light-emitting element LEL to prevent a reduction in the amount of light emitted from each light-emitting element LEL. Therefore, for example, the pixel drivers DP1 to DPn of each light-emitting pixel OSP may receive a scan timing control signal and an analog emission control voltage according to the same timing, and drive the light-emitting element LEL according to the same drive timing. In other words, the pixel drivers DP1 to DPn of each light emitting pixel OSP may receive the scan timing control signal and the analog emission control voltage according to the same timing, and drive the light emitting element LEL based on the scan timing control signal and the analog emission control voltage.

[0096] refer to Fig. 9 , each of the pixel drivers DP1 to DPn of each light emitting pixel OSP may be connected to the display initialization line GIL, the display scan line GSL, the display control line GCL, and the emission control line VL.

[0097] In some aspects, each of the pixel drivers DP1 to DPn may be connected to a first driving voltage line VDL to which the display device 200 may provide a first driving voltage of a high potential, a second driving voltage line VSL to which the display device 200 may provide a second driving voltage of a low potential, and a third driving voltage line VIL to which the display device 200 may provide a third driving voltage of a high potential. The letter marks k and n (or i, j, n) used herein will be hereinafter defined as positive integers not including zero.

[0098] Each of the pixel drivers DP1 to DPn of each light emitting pixel OSP may include a driving transistor DT, a switching element, and a capacitor CST1. In some embodiments, the switching element includes first to sixth transistors ST1 to ST6.

[0099] The driving transistor DT of each of the pixel drivers DP1 to DPn may include a gate electrode, a first electrode, and a second electrode. The driving transistor DT controls a drain-source current Ids (hereinafter referred to as a "driving current") flowing between the first electrode and the second electrode based on an analog emission control voltage applied to the gate electrode. The driving current Ids flowing through the channel of the driving transistor DT is proportional to the square of the difference between the voltage Vsg between the first electrode and the gate electrode of the driving transistor DT and the threshold voltage Vth, as shown in Formula 1.

[0100] Ids = k' × (Vsg - Vth)

[0101] Referring to Formula 1, k′ is a proportionality coefficient determined by the structure and physical characteristics of a driving transistor (eg, driving transistor DT), Vsg is a voltage between a first electrode and a gate electrode of the driving transistor, and Vth is a threshold voltage of the driving transistor.

[0102] The light emitting element LEL emits light based on the driving current Ids provided simultaneously by at least one of the pixel drivers DP1 to DPn. For example, in the case where the display device 200 simultaneously provides the driving current Ids to the pixel drivers DP1 to DPn connected to the light emitting element LEL, the light emitting element LEL emits light based on the driving current Ids. As the driving current Ids provided in parallel from the pixel drivers DP1 to DPn increases, the amount of light emitted from the light emitting element LEL can increase.

[0103] The light emitting element LEL may be an organic light emitting diode including an organic light emitting layer disposed between an anode and a cathode. Additionally or alternatively, the light emitting element LEL may be an inorganic light emitting element including an inorganic semiconductor disposed between an anode and a cathode. Additionally or alternatively, the light emitting element LEL may be a quantum dot light emitting element including a quantum dot light emitting layer disposed between an anode and a cathode. Additionally or alternatively, the light emitting element LEL may be a micro light emitting element including a micro light emitting diode disposed between an anode and a cathode.

[0104] The anode of each light emitting element LEL may be connected to the first electrode of the fourth transistor ST4 and the second electrode of the sixth transistor ST6 of each of the pixel drivers DP1 to DPn, and the cathode of the light emitting element LEL may be connected to the second driving voltage line VSL. In some embodiments, a parasitic capacitor Cel may be formed between the anode and the cathode of the light emitting element LEL.

[0105] The first transistor ST1 is turned on by a scan timing control signal (e.g., an initialization scan signal at the display initialization line GIL) to connect the gate electrode of the drive transistor DT to the third drive voltage line VIL. For example, in the on state, the first transistor ST1 connects the gate electrode of the drive transistor DT to the third drive voltage line VIL. Therefore, for example, the third drive voltage at the third drive voltage line VIL can be applied to the gate electrode of the drive transistor DT. The first transistor ST1 may have a gate electrode connected to the display initialization line GIL, a first electrode connected to the gate electrode of the drive transistor DT, and a second electrode connected to the third drive voltage line VIL.

[0106] The second transistor ST2 is turned on by a scan timing control signal (e.g., a display scan signal at the display scan line GSL) to connect the first electrode of the drive transistor DT to the data line DL. For example, in a turned-on state, the second transistor ST2 connects the first electrode of the drive transistor DT to the data line DL. Therefore, for example, an emission control voltage (or an analog emission control voltage) at the data line DL can be applied to the first electrode of the drive transistor DT. The second transistor ST2 may have a gate electrode connected to the display scan line GSL, a first electrode connected to the first electrode of the drive transistor DT, and a second electrode connected to the data line DL.

[0107] The third transistor ST3 is turned on by the display scan signal of the display scan line GSL to connect the gate electrode and the second electrode of the driving transistor DT. For example, in the on state, the third transistor ST3 connects the gate electrode and the second electrode of the driving transistor DT. Therefore, when the gate electrode and the second electrode of the driving transistor DT are connected, the driving transistor DT works as a diode. The third transistor ST3 may have a gate electrode connected to the display scan line GSL, a first electrode connected to the second electrode of the driving transistor DT, and a second electrode connected to the gate electrode of the driving transistor DT.

[0108] The fourth transistor ST4 is turned on by the scan timing control signal (e.g., the display control signal at the display control line GCL) to connect the anode of the light emitting element LEL to the third driving voltage line VIL. For example, in the on state, the fourth transistor ST4 connects the anode of the light emitting element LEL to the third driving voltage line VIL. Therefore, for example, the third driving voltage at the third driving voltage line VIL can be applied to the anode of the light emitting element LEL. The fourth transistor ST4 may have a gate electrode connected to the display control line GCL, a first electrode connected to the anode of the light emitting element LEL, and a second electrode connected to the third driving voltage line VIL.

[0109] The fifth transistor ST5 is turned on by a scan timing control signal (e.g., an emission control signal at the emission control line VL) to connect the first electrode of the drive transistor DT to the first drive voltage line VDL. For example, in a turned-on state, the fifth transistor ST5 connects the first electrode of the drive transistor DT to the first drive voltage line VDL. The fifth transistor ST5 may have a gate electrode connected to the emission control line VL, a first electrode connected to the first drive voltage line VDL, and a second electrode connected to the first electrode of the drive transistor DT.

[0110] The sixth transistor ST6 is disposed between the second electrode of the driving transistor DT and the anode of the light emitting element LEL. The sixth transistor ST6 is turned on by the emission control signal at the emission control line VL to connect the second electrode of the driving transistor DT to the anode of the light emitting element LEL. For example, in the on state, the sixth transistor ST6 connects the second electrode of the driving transistor DT to the anode of the light emitting element LEL. The sixth transistor ST6 may have a gate electrode connected to the emission control line VL, a first electrode connected to the second electrode of the driving transistor DT, and a second electrode connected to the anode of the light emitting element LEL.

[0111] When both the fifth transistor ST5 and the sixth transistor ST6 are turned on, a driving current Ids of the driving transistor DT corresponding to the analog emission control voltage applied to the gate electrode of the driving transistor DT may flow to the light emitting element LEL.

[0112] The capacitor CST1 is formed between the gate electrode of the driving transistor DT and the first driving voltage line VDL. A first capacitor electrode of the capacitor CST1 may be connected to the gate electrode of the driving transistor DT, and a second capacitor electrode of the capacitor CST1 may be connected to the first driving voltage line VDL.

[0113] In an example, the corresponding first electrode of each of the first to sixth transistors ST1 to ST6 and the driving transistor DT may be a source electrode, and the corresponding second electrode may be a drain electrode. Additionally or alternatively, when the first electrode of each of the first to sixth transistors ST1 to ST6 and the driving transistor DT is a drain electrode, the second electrode may be a source electrode.

[0114] The active layer of each of the first to sixth transistors ST1 to ST6 and the driving transistor DT may be formed of any one of polysilicon, amorphous silicon, and an oxide semiconductor. Fig. 9 1 and 2 mainly describe the case where the first transistor ST1 to the sixth transistor ST6 and the driving transistor DT are formed as P-type metal oxide semiconductor field effect transistors (MOSFETs), but the embodiment is not limited thereto. For example, the first transistor ST1 to the sixth transistor ST6 and the driving transistor DT may also be formed as N-type MOSFETs. Additionally or alternatively, at least one of the first transistor ST1 to the sixth transistor ST6 may be formed as an N-type MOSFET.

[0115] Fig.10 is provided to Figure 8 and Fig. 9 The waveform diagram of the scanning timing control signal of multiple light-emitting elements shown.

[0116] Fig.10 An example of a scan timing control signal according to an exemplary aspect of the present disclosure is shown. In the example, the scan timing control signal may include an emission control signal EMn sent to the emission control line VL during the N-1th frame period FN-1 and the Nth frame period FN, a display initialization signal GIn sent to the display initialization line GIL, a display control signal ELn sent to the display control line GCL, and a display scan signal GWn sent to the display scan line GSL.

[0117] Among the scan timing control signals, the display initialization signal GIn is a signal for controlling the on / off of the first transistor ST1 of the pixel drivers DP1 to DPn. The display control signal ELn is a signal for controlling the on / off of the fourth transistor ST4 of the pixel drivers DP1 to DPn. Among the scan timing control signals, the display scan signal GWn is a signal for controlling the on / off of the second transistor ST2 and the third transistor ST3 of each of the pixel drivers DP1 to DPn. The emission control signal EMn is a signal for controlling the on / off of the fifth transistor ST5 and the sixth transistor ST6.

[0118] Each of the N-1th frame period FN-1 and the Nth frame period FN may include a first period t1, a second period t2, and a third period t3.

[0119] The first period t1 is a period in which the display device 200 initializes the gate electrode of the driving transistor DT to a third driving voltage, the second period t2 is a period in which the display device 200 provides an analog emission control voltage to the gate electrode of the driving transistor DT and samples the threshold voltage of the driving transistor DT, and the third period t3 is a period in which the light emitting element LEL emits light based on the gate voltage of the driving transistor DT.

[0120] The emission control signal EMn has a first level voltage V1 during the third period t3, and has a second level voltage V2 during the first period t1 and the second period t2. The display scan signal GWn has a first level voltage V1 during the second period t2, and has a second level voltage V2 during the first period t1 and the third period t3.

[0121] The display initialization signal GIn and the display control signal ELn have a first level voltage V1 during the first period t1, and have a second level voltage V2 during the second period t2 and the third period t3. That is, the display initialization signal GIn and the display control signal ELn may be substantially the same.

[0122] The first level voltage V1 may be a turn-on voltage that can turn on the first to sixth transistors ST1 to ST6. The second level voltage V2 may be a turn-off voltage that can turn off the first to sixth transistors ST1 to ST6. The second level voltage V2 may be higher than the first level voltage V1.

[0123] Now refer to Fig. 9 and Fig.10 An example of the operation of the light emitting pixel OSP during the first period t1 , the second period t2 , and the third period t3 is described.

[0124] First, in the first period t1 , the display device 200 may provide the display initialization signal GIn of the first level voltage V1 to the display initialization line GIL, and the display device 200 may provide the display control signal ELn of the first level voltage V1 to the display control line GCL.

[0125] During the first period t1, the first transistor ST1 is turned on by the display initialization signal GIn of the first level voltage V1. Due to the turning on of the first transistor ST1, the third driving voltage of the third driving voltage line VIL is applied to the gate electrode of the driving transistor DT. When the third driving voltage is applied to the gate electrode of the driving transistor DT during the first period t1, the voltage Vsg between the first electrode and the gate electrode of the driving transistor DT is greater than the threshold voltage Vth of the driving transistor DT. Therefore, for example, the driving transistor DT can be turned on based on the voltage Vsg. That is, the display device 200 is able to apply a turn-on bias to the driving transistor DT, which can improve the hysteresis characteristic of the driving transistor DT.

[0126] In some aspects, during the first period t1, the fourth transistor ST4 is turned on by the display control signal ELn of the first level voltage V1. Due to the turning on of the fourth transistor ST4 during the first period t1, the anode of the light emitting element LEL may be initialized to the third driving voltage of the third driving voltage line VIL.

[0127] Second, the display device 200 may provide the display scan signal GWn of the first level voltage V1 to the display scan line GSL during the second period t2. During the second period t2, each of the second transistor ST2 and the third transistor ST3 is turned on by the display scan signal GWn of the first level voltage V1.

[0128] During the second period t2, due to the conduction of the third transistor ST3, the gate electrode and the second electrode of the driving transistor DT are connected to each other, and the driving transistor DT operates as a diode. In some aspects, due to the conduction of the second transistor ST2 during the second period t2, the emission control voltage (e.g., the analog emission control voltage) is provided to the first electrode of the driving transistor DT. In this case, since the voltage between the first electrode and the gate electrode of the driving transistor DT (Vsg=Vdata-VINT) is less than the threshold voltage Vth, the driving transistor DT forms a current path until the voltage Vsg between the first electrode and the gate electrode reaches the threshold voltage Vth, wherein Vdata represents the emission control voltage and VINT represents the third driving voltage. Therefore, for example, during the second period t2, the differential voltage between the gate electrode and the second electrode of the driving transistor DT rises to the differential voltage (Vdata-Vth) between the data voltage Vdata and the threshold voltage Vth of the driving transistor DT.

[0129] Third, the display device 200 may provide the emission control signal EMn having the first level voltage V1 to the emission control line VL during the third period t3. During the third period t3, each of the fifth transistor ST5 and the sixth transistor ST6 is turned on by the emission control signal EMn having the first level voltage V1.

[0130] Due to the conduction of the fifth transistor ST5, the first electrode of the driving transistor DT is connected to the first driving voltage line VDL. Due to the conduction of the sixth transistor ST6, the second electrode of the driving transistor DT is connected to the anode of the light emitting element LEL.

[0131] When the fifth transistor ST5 and the sixth transistor ST6 are turned on, a driving current Ids flowing based on the voltage of the gate electrode of the driving transistor DT may be provided to the light emitting element LEL. The driving current Ids may be defined as in Equation 2.

[0132] Ids=k'×{VDD-(Vdata-Vth)-Vth 2 (2)

[0133] In Formula 2, k' is a proportionality coefficient determined by the structure and physical characteristics of the driving transistor DT, Vth is the threshold voltage of the driving transistor DT, VDD is the first driving voltage of the first driving voltage line VDL, and Vdata is the emission control voltage. The voltage of the gate electrode of the driving transistor DT is "Vdata-Vth", and the voltage of the first electrode is VDD. Formula 2 is integrated into Formula 3.

[0134] Ids=k'×(VDD-Vdata)(3)

[0135] Finally, the driving current Ids may be independent of the threshold voltage Vth of the driving transistor DT as shown in Equation 3. That is, the display device 200 supports compensating the threshold voltage Vth of the driving transistor DT.

[0136] Fig.11 is a circuit diagram showing a circuit structure of a light-emitting pixel according to a second embodiment supported by aspects of the present disclosure.

[0137] refer to Fig.11 as well as Fig.10 , each of the light emitting pixels OSP arranged on the organic light emitting display surface DA1 includes a light emitting element LEL and at least one of the pixel drivers DP1 to DPn.

[0138] Each of the light emitting elements LEL may be connected in series to at least one of the pixel drivers DP1 to DPn. Each of the light emitting elements LEL may emit light in response to a driving current simultaneously input from the pixel drivers DP1 to DPn. For example, each light emitting element LEL may emit light in response to a driving current simultaneously input from a corresponding pixel driver (e.g., pixel driver DP1 to pixel driver DPn) electrically coupled to the light emitting element LEL.

[0139] The pixel drivers DP1 to DPn receive the same gate control signal and analog emission control voltage through the emission driving circuit 120 and the first gate driver 111, and drive the light emitting elements LEL connected in series therewith in units of at least one frame according to the same driving timing.

[0140] Each of the pixel drivers DP1 to DPn for each light emitting pixel OSP may include a driving transistor DT, an i-th transistor STi, a j-th transistor STj, and a capacitor voltage supply terminal Cp.

[0141] The driving transistor DT of each of the pixel drivers DP1 to DPn may include a gate electrode, a first electrode, and a second electrode. The driving transistor DT controls a drain-source current Ids (hereinafter, referred to as a "driving current") flowing between the first electrode and the second electrode based on a capacitor voltage applied to the gate electrode. The driving current Ids flowing through the channel of the driving transistor DT is proportional to the square of the difference between the voltage Vsg between the first electrode and the gate electrode of the driving transistor DT and the threshold voltage Vth.

[0142] The capacitor voltage is an analog emission control voltage input through the capacitor voltage supply terminal Cp, and the size of the capacitor voltage can be preset according to the amplitude of the analog emission control voltage and the capacitor amplitude of the capacitor voltage supply terminal Cp.

[0143] The i-th transistor STi is turned on by the display scan signal at the display scan line GSL to connect the gate electrode and the second electrode of the driving transistor DT. For example, in the on state, the i-th transistor STi connects the gate electrode and the second electrode of the driving transistor DT. When the gate electrode and the second electrode of the driving transistor DT are connected, the driving transistor DT is driven as a diode. The gate electrode of the i-th transistor STi can be connected to the display scan line GSL, the first electrode can be connected to the second electrode of the driving transistor DT, and the second electrode can be connected to the gate electrode of the driving transistor DT.

[0144] The jth transistor STj is disposed between the second electrode of the driving transistor DT and the anode electrode of the light emitting element LEL. The jth transistor STj is turned on by the emission control signal of the emission control line VL to connect the second electrode of the driving transistor DT to the anode electrode of the light emitting element LEL. For example, in the on state, the jth transistor STj connects the second electrode of the driving transistor DT to the anode electrode of the light emitting element LEL. The jth transistor STj may have a gate electrode connected to the emission control line VL, a first electrode connected to the second electrode of the driving transistor DT, and a second electrode connected to the anode electrode of the light emitting element LEL.

[0145] The light emitting element LEL emits light based on the driving current Ids provided simultaneously by at least one of the pixel drivers DP1 to DPn. For example, in the case where the display device 200 simultaneously provides the driving current Ids to the pixel drivers DP1 to DPn connected to the light emitting element LEL, the light emitting element LEL emits light based on the driving current Ids. As the driving current Ids provided in parallel from the pixel drivers DP1 to DPn increases, the amount of light emitted from the light emitting element LEL can increase.

[0146] Fig.12 is provided to Figure 8 and Fig.11 The waveform diagram of the scanning timing control signal of multiple light-emitting elements shown.

[0147] Fig.12 An example of a scan timing control signal according to an exemplary aspect of the present disclosure is shown. In the example, the scan timing control signal may include an emission control signal EMn sent to the emission control line VL during the N-1th frame period FN-1 and the Nth frame period FN and a display scan signal GWn sent to the display scan line GSL.

[0148] The display scan signal GWn is a signal for controlling on / off of the i-th transistor STi of each of the pixel drivers DP1 to DPn. The emission control signal EMn is a signal for controlling on / off of the j-th transistor STj of each of the pixel drivers DP1 to DPn.

[0149] Each of the N-1th frame period FN-1 and the Nth frame period FN may include a first period t1, a second period t2, and a third period t3.

[0150] The first period t1 and the second period t2 are periods in which the display device 200 provides the capacitor voltage CapV to the capacitor voltage supply terminal Cp and thus provides the capacitor voltage CapV to the gate electrode of the driving transistor DT and samples the threshold voltage of the driving transistor DT, and the third period t3 is a period in which the light emitting element LEL emits light based on the gate voltage of the driving transistor DT.

[0151] The display scan signal GWn has a first level voltage V1 during the first and second periods t1 and t2 , and has a second level voltage V2 during the third period t3 .

[0152] The emission control signal EMn has the second level voltage V2 during the first period t1 and the second period t2, and has the first level voltage V1 during the third period t3.

[0153] The first level voltage V1 may be a turn-on voltage that can turn on the i-th transistor STi and the j-th transistor STj. The second level voltage V2 may be a turn-off voltage that can turn off the i-th transistor STi and the j-th transistor STj. The second level voltage V2 may be higher than the first level voltage V1.

[0154] During the first period t1 and the second period t2, the display device 200 may provide the display scan signal GWn of the first level voltage V1 to the display scan line GSL. Therefore, during the first period t1 and the second period t2, the i-th transistor STi is turned on by the display scan signal GWn of the first level voltage V1.

[0155] During the third period t3, the display device 200 may provide the emission control signal EMn of the first level voltage V1 to the emission control line VL. During the third period t3, the jth transistor STj is turned on by the emission control signal EMn of the first level voltage V1. When the jth transistor STj is turned on, the driving current Ids flowing based on the voltage of the gate electrode of the driving transistor DT may be provided to the light emitting element LEL.

[0156] Fig.13 It specifically shows Figure 3 A plan view of a second embodiment of a surface light source device is shown. In some aspects, Fig.14 It specifically shows Figure 4 FIG. 1 is a plan view of a second embodiment of a surface light source device shown in FIG.

[0157] refer to Fig.13 and Fig.14, the first gate driver 111 may not be separately formed in the first non-display area NDA1, and the first gate driver 111 may be formed integrally with the emission driving circuit 120. That is, for example, the first gate driver 111 may be formed in the form of a single chip with the emission driving circuit 120. Therefore, for example, at least one emission driving circuit 120 may simultaneously provide a plurality of scanning timing control signals for simultaneously driving the light-emitting pixels OSP to the entire light-emitting pixels OSP. In some aspects, the emission driving circuit 120 may output an analog emission control voltage for simultaneously driving the light-emitting pixels OSP to each of the data lines DL through a fan-out line. For example, referring to Fig.13 Each of the emission driving circuits 120 can output an analog emission control voltage for simultaneously driving one or more light-emitting pixels OSP to each of the data lines DL through a fan-out line. Fig.14 The emission driving circuit 120 may output an analog emission control voltage for simultaneously driving the light-emitting pixel OSP to each of the data lines DL through a fan-out line. (Multiple) analog emission control voltages may be provided to the light-emitting pixel OSP, and the brightness of the light-emitting pixel OSP may be based on the analog emission control voltage.

[0158] Fig.15 It is schematically shown Fig.14 A plan view of the structure of the organic light emitting display surface of the surface light source device shown. In some aspects, Fig.16 It is specifically shown that the arrangement is Fig.15 A circuit diagram of a first embodiment of a circuit structure of a light-emitting pixel on an organic light-emitting display surface.

[0159] refer to Fig.14 and Fig.15 , the light-emitting pixels OSP can be arranged in a matrix form on the organic light-emitting display surface DA1 in the vertical stripe direction and the horizontal stripe direction. That is, for example, the light-emitting pixels OSP can be arranged in a matrix form including rows and columns of light-emitting pixels OSP. Each of the light-emitting pixels OSP includes at least one light-emitting element LEL. For each light-emitting element LEL, the first electrode of the light-emitting element LEL is connected to each data line DL, and the second electrode of the light-emitting element LEL is connected to each display scan line GSL. In other words, each light-emitting element LEL constitutes a light-emitting pixel OSP, and the first electrode which is the input electrode of each light-emitting element LEL is connected to each data line DL. The second electrode which is the output electrode of each light-emitting element LEL can be connected to each display scan line GSL.

[0160] The emission driving circuit 120 may selectively supply the high potential emission control voltage HV or the low potential emission control voltage LV to at least one data line DL arranged parallel to each other in a vertical direction or a horizontal direction among the plurality of data lines DL.

[0161] The emission driving circuit 120 may selectively supply the high potential scan control voltage HGV or the low potential scan control voltage LGV to at least one display scan line GSL arranged parallel to each other in a vertical direction or a horizontal direction among a plurality of display scan lines GSL.

[0162] The high potential emission control voltage HV and the high potential scanning control voltage HGV may be driving voltages of the light emitting element LEL that cause the light emitting element LEL to emit light. In some embodiments, the high potential emission control voltage HV and the high potential scanning control voltage HGV may be positive polarity voltages of about 5V or more. In some embodiments, the low potential emission control voltage LV and the low potential scanning control voltage LGV may be ground voltages, and may be voltages of about 0V. In some embodiments, the low potential emission control voltage LV and the low potential scanning control voltage LGV may be negative polarity voltages of about negative 5V or more (e.g., negative 5.1V, etc.).

[0163] The emission driving circuit 120 selectively provides a high potential emission control voltage HV or a low potential emission control voltage LV to the plurality of data lines DL to provide the high potential emission control voltage HV or the low potential emission control voltage LV to the first electrode of the light emitting element LEL. In addition, for example, the emission driving circuit 120 selectively provides a high potential scanning control voltage HGV or a low potential scanning control voltage LGV to the plurality of display scanning lines GSL to provide the high potential scanning control voltage HGV or the low potential scanning control voltage LGV to the second electrode of the light emitting element LEL.

[0164] The emission driving circuit 120 can selectively provide a high potential emission control voltage HV or a low potential emission control voltage LV to a plurality of data lines DL by using an internal switch circuit structure. In some aspects, the emission driving circuit 120 can selectively provide a high potential scan control voltage HGV or a low potential scan control voltage LGV to a plurality of display scan lines GSL by using an internal switch circuit structure.

[0165] The light emitting elements LEL may selectively emit light based on a high potential emission control voltage HV input to corresponding first electrodes through a plurality of data lines DL and a low potential scan control voltage LGV input to corresponding second electrodes through a plurality of display scan lines GSL.

[0166] The light emitting elements LEL may be connected in a diode structure. For example, each light emitting element LEL may be a light emitting diode (LED) that emits light when current flows through the light emitting element LEL. Therefore, for example, a light emitting element LEL to which a low potential emission control voltage LV is applied to its corresponding first electrode through a plurality of data lines DL may not emit light. In some aspects, a light emitting element LEL to which a high potential scanning control voltage HGV is applied to its corresponding second electrode through a plurality of display scanning lines GSL may not emit light. According to an exemplary aspect of the present disclosure, a light emitting element LEL to which a high potential emission control voltage HV is input to its corresponding first electrode through a plurality of data lines DL and a low potential scanning control voltage LGV is input to its corresponding second electrode through a plurality of display scanning lines GSL may selectively emit light.

[0167] Fig.17 is a diagram showing a display image displayed on the spatial light modulator described herein. Fig.18 It shows that Fig.16 A circuit diagram of a method for controlling light-emitting driving of each emission area of ​​a light-emitting pixel shown in FIG.

[0168] refer to Fig.17 , the emission driving circuit 120 divides the image data input from the outside into at least one frame unit, and analyzes the grayscale value or brightness value of each pixel data for at least one frame of the image data. The term "each pixel data" may refer to the corresponding pixel data of each light-emitting pixel OSP. The emission driving circuit 120 may analyze the grayscale value or brightness value of the corresponding pixel data for each light-emitting pixel OSP for at least one frame of the image data.

[0169] The emission driving circuit 120 analyzes and sets at least one emission area HLD for rear surface emission (e.g., an emission area HLD required for rear surface emission or rear surface emission) according to the arrangement position of the grayscale value or brightness value of each pixel data of the image data. The emission driving circuit 120 can set the remaining area (e.g., an area different from the at least one emission area HLD set for rear surface emission) as a blackened area of ​​a low gray level.

[0170] The emission driving circuit 120 distinguishes and sets the position of the organic light emitting display surface DA1 of the surface light source device 110 corresponding to the position of the emission region HLD (ie, the emission region HLD of the organic light emitting display surface DA1 ).

[0171] The emission driving circuit 120 selectively provides the high potential emission control voltage HV to a plurality of data lines DL disposed at a position or region corresponding to the emission region HLD of the organic light emitting display surface DA1. The emission driving circuit 120 provides the low potential scan control voltage LGV to a plurality of display scan lines GSL disposed to correspond to or overlap the emission region HLD of the organic light emitting display surface DA1. Therefore, the light emitting element LEL to which the high potential emission control voltage HV is input to its corresponding first electrode through the plurality of data lines DL and to which the low potential scan control voltage LGV is input to its corresponding second electrode through the plurality of display scan lines GSL selectively emits light. That is, the emission driving circuit 120 can selectively emit light from the light emitting element LEL disposed at a position or region corresponding to the emission region HLD of the organic light emitting display surface DA1.

[0172] The emission drive circuit 120 may selectively provide the low potential emission control voltage LV to a plurality of data lines DL corresponding to or overlapping the remaining area (i.e., the blackened area of ​​the low gray level) that does not correspond to or overlap the emission area HLD of the organic light emitting display surface DA1 or overlaps the remaining area. In some aspects, the high potential scan control voltage HGV may be provided to a plurality of display scan lines GSL that correspond to or overlap the blackened area of ​​the low gray level. Therefore, for example, the light emitting element LEL disposed in the blackened area of ​​the low gray level may not emit light.

[0173] Fig.19 It is specifically shown that the arrangement is Fig.15 A circuit diagram of a second embodiment of a circuit structure of a light-emitting pixel on an organic light-emitting display surface. Fig. 20 It is shown Fig.19 FIG. 1 is a circuit diagram of a first embodiment of a circuit structure of a light-emitting pixel.

[0174] refer to Fig.19 and Fig. 20 , each of the light emitting pixels OSP arranged on the organic light emitting display surface DA1 includes a light emitting element LEL and at least one of the pixel drivers DP1 to DPn.

[0175] Each of the light emitting elements LEL may be connected in series to at least one of the pixel drivers DP1 to DPn. Each of the light emitting elements LEL may emit light in response to a driving current simultaneously input from the pixel drivers DP1 to DPn. For example, each light emitting element LEL may emit light in response to a driving current simultaneously input from a corresponding pixel driver (e.g., pixel driver DP1 to pixel driver DPn) electrically coupled to the light emitting element LEL.

[0176] Each of the pixel drivers DP1 to DPn for each light emitting pixel OSP may include a capacitor voltage supply terminal Cp, a driving transistor DT, an i-th transistor STi, a j-th transistor STj, and an emission control transistor STv.

[0177] The driving transistor DT controls a drain-source current Ids (hereinafter referred to as a "driving current") flowing between the first electrode and the second electrode based on the capacitor voltage applied to the gate electrode. The driving current Ids flowing through the channel of the driving transistor DT is proportional to the square of the difference between the voltage Vsg between the first electrode and the gate electrode of the driving transistor DT and the threshold voltage Vth.

[0178] The capacitor voltage is an analog emission control voltage input through the capacitor voltage supply terminal Cp, and the size of the capacitor voltage may be preset based on the magnitude of the analog emission control voltage and the capacitor magnitude of the capacitor voltage supply terminal Cp.

[0179] The i-th transistor STi is turned on by the display scan signal at the display scan line GSL to connect the gate electrode and the second electrode of the driving transistor DT. For example, in the on state, the i-th transistor STi connects the gate electrode and the second electrode of the driving transistor DT. When the gate electrode and the second electrode of the driving transistor DT are connected, the driving transistor DT is driven as a diode.

[0180] The jth transistor STj is disposed between the second electrode of the driving transistor DT and the anode electrode of the light emitting element LEL. The jth transistor STj is turned on by the emission control signal VC input through the emission control transistor STv to connect the second electrode of the driving transistor DT to the anode electrode of the light emitting element LEL. For example, in the on state, the jth transistor STj connects the second electrode of the driving transistor DT to the anode electrode of the light emitting element LEL. The jth transistor STj may have a gate electrode connected to the emission control transistor STv, a first electrode connected to the second electrode of the driving transistor DT, and a second electrode connected to the anode electrode of the light emitting element LEL.

[0181] The emission control transistor STv provides an emission control signal VC to the gate electrode of the jth transistor STj in response to a high potential emission control voltage HV input through any one of a first emission control line among a plurality of first emission control lines VL1-1 to VL1-n and a high potential scanning control voltage HGV input through any one of a second emission control line among a plurality of second emission control lines VL2-1 to VL2-n.

[0182] A first electrode of the emission control transistor STv is connected to any one of the second emission control lines among the plurality of second emission control lines VL2-1 to VL2-n, and a gate electrode of the emission control transistor STv is connected to any one of the first emission control lines among the plurality of first emission control lines VL1-1 to VL1-n. A second electrode of the emission control transistor STv is connected to the gate electrode of the j-th transistor STj.

[0183] An emission control signal input terminal including an emission control capacitor VCp in a parallel structure with the gate electrode of the j-th transistor STj may be additionally provided at the second electrode of the emission control transistor STv.

[0184] The emission driving circuit 120 selectively provides the high potential emission control voltage HV or the low potential emission control voltage LV to the plurality of first emission control lines VL1-1 to VL1-n to provide the high potential emission control voltage HV or the low potential emission control voltage LV to the gate electrode of the emission control transistor STv. For example, the emission driving circuit 120 selectively provides the high potential emission control voltage HV or the low potential emission control voltage LV to the gate electrode of the emission control transistor STv through the plurality of first emission control lines VL1-1 to VL1-n. In addition, for example, the emission driving circuit 120 selectively provides the high potential scanning control voltage HGV or the low potential scanning control voltage LGV to the plurality of second emission control lines VL2-1 to VL2-n to provide the high potential scanning control voltage HGV or the low potential scanning control voltage LGV to the first electrode of the emission control transistor STv. For example, the emission driving circuit 120 selectively supplies the high potential scan control voltage HGV or the low potential scan control voltage LGV to the first electrode of the emission control transistor STv via the plurality of second emission control lines VL2 - 1 to VL2 - n.

[0185] The emission driving circuit 120 selectively provides a high potential emission control voltage HV or a low potential emission control voltage LV to a plurality of first emission control lines VL1-1 to VL1-n by using an internal switch circuit structure. In some aspects, the emission driving circuit 120 selectively provides a high potential scan control voltage HGV or a low potential scan control voltage LGV to a plurality of second emission control lines VL2-1 to VL2-n by using an internal switch circuit structure.

[0186] When the high potential emission control voltage HV is input to the gate electrode of the emission control transistor STv through any one of the first emission control lines VL1-1 to VL1-n and the high potential scanning control voltage HGV is input to the first electrode of the emission control transistor STv through any one of the second emission control lines VL2-1 to VL2-n, the emission control transistor STv is turned on and the emission control signal VC is provided to the gate electrode of the j-th transistor STj. For example, for a given pixel driver (e.g., pixel driver DP1), when the high potential emission control voltage HV is input to the gate electrode of the emission control transistor STv through the first emission control line VL1 (e.g., any one of the first emission control lines VL1-1 to VL1-n) and the high potential scanning control voltage HGV is input to the first electrode of the emission control transistor STv through the second emission control line VL2 (e.g., any one of the second emission control lines VL2-1 to VL2-n), the emission control transistor STv is turned on and the emission control signal VC is provided to the gate electrode of the j-th transistor STj.

[0187] As described above, the emission driving circuit 120 distinguishes and sets the position of the organic light emitting display surface DA1 of the surface light source device 110 corresponding to the position of the emission area HLD by analyzing and setting the image data (ie, the emission area HLD of the organic light emitting display surface DA1).

[0188] The emission driving circuit 120 selectively provides the high potential emission control voltage HV to the first emission control lines VL1-1 to VL1-n set at a position or area corresponding to the emission area HLD of the organic light emitting display surface DA1. The high potential scanning control voltage HGV is also provided to the second emission control lines VL2-1 to VL2-n set to correspond to or overlap the emission area HLD of the organic light emitting display surface DA1. Therefore, for example, the high potential emission control voltage HV is input to the gate electrode of the emission control transistor STv through any one of the first emission control lines VL1-1 to VL1-n, and the high potential scanning control voltage HGV is applied to the first electrode of the emission control transistor STv through any one of the second emission control lines VL2-1 to VL2-n, thereby providing the emission control signal VC to the gate electrode of the j-th transistor STj.

[0189] The emission driving circuit 120 may selectively provide the low potential emission control voltage LV to the remaining area that does not correspond to or overlap the emission area HLD of the organic light emitting display surface DA1, that is, the first emission control lines VL1-1 to VL1-n that correspond to or overlap the blackened area of ​​the low gray level. In some aspects, the low potential scanning control voltage LGV may be provided to the second emission control lines VL2-1 to VL2-n that correspond to or overlap the blackened area of ​​the low gray level. Therefore, the light emitting element LEL disposed in the blackened area of ​​the low gray level may not emit light.

[0190] At the end of the detailed description, those skilled in the art will appreciate that many changes and modifications may be made to the preferred embodiment without departing substantially from the principles of the present disclosure. Therefore, the preferred embodiments of the present disclosure disclosed are used in an overview and descriptive sense, rather than for a limiting purpose.

Claims

1. A display device, comprising: at least one spatial light modulator, displaying an augmented reality content image; a surface light source device for providing image display light to the at least one spatial light modulator from a rear direction of the at least one spatial light modulator as background light; as well as at least one image transmission component, forming a display path of the extended reality content image, Wherein, the surface light source device comprises: an organic light emitting display unit including a plurality of light emitting pixels performing surface emission; and The emission driving circuit provides each of the emission control voltage and the scan timing control signal to the plurality of light-emitting pixels to control the light-emitting operation of the plurality of light-emitting pixels.

2. The display device according to claim 1, in, The plurality of light-emitting pixels include: A plurality of pixel drivers receive the scanning timing control signal according to the same timing; and a light emitting element that emits light based on one or more driving currents through at least one pixel driver among the plurality of pixel drivers, The plurality of pixel drivers receive the scanning timing control signal and the emission control voltage according to the same timing, so that the light emitting elements emit light at the same time.

3. The display device according to claim 2, in, The light emitting elements are formed on an organic light emitting display surface of the organic light emitting display unit in one or more of a sector shape, a triangle shape, a quadrangular shape, a circular shape, a semicircular shape, and an elliptical shape.

4. The display device according to claim 2, in, The plurality of pixel drivers include: a driving transistor to control a driving current applied by the driving transistor to at least one of the light emitting elements; a first transistor, which is turned on by an initialization scanning signal among the scanning timing control signals to connect the gate electrode of the driving transistor to a first driving voltage line; a second transistor, connected to the data line by connecting the first electrode of the driving transistor to the data line by being turned on by a display scanning signal among the scanning timing control signals; a third transistor, connected to the driving transistor in a diode structure by being turned on by the display scanning signal; a fourth transistor, connected to the first driving voltage line by connecting the anode electrode of the at least one light emitting element to the first driving voltage line by being turned on by the display control signal among the scanning timing control signals; a fifth transistor connected to a second driving voltage line by being turned on by an emission control signal among the scan timing control signals; and A sixth transistor connects the second electrode of the driving transistor to the anode electrode of the at least one light emitting element by being turned on by the emission control signal.

5. The display device according to claim 4, in, The emission driving circuit simultaneously provides the initialization scanning signal among the scanning timing control signals to the multiple pixel drivers according to the same timing during at least one frame, provides the display scanning signal to the multiple pixel drivers according to the same timing, provides the display control signal to the multiple pixel drivers according to the same timing, and provides the emission control signal to the multiple pixel drivers according to the same timing.

6. The display device according to claim 1, in, The plurality of light-emitting pixels include: A plurality of pixel drivers receive the scanning timing control signal according to the same timing; and a light emitting element that emits light based on one or more driving currents through at least one pixel driver among the plurality of pixel drivers, Wherein, the plurality of pixel drivers include: a driving transistor for controlling a driving current provided by the driving transistor to at least one of the light emitting elements; The i-th transistor is turned on by the display scanning signal among the scanning timing control signals to connect the driving transistor in a diode structure; a j-th transistor, which is turned on by the emission control signal among the scan timing control signals to connect the second electrode of the driving transistor to the anode electrode of the at least one light emitting element; and a capacitor voltage supply terminal for supplying a capacitor voltage based on the emission control voltage to a gate electrode of the driving transistor, The emission driving circuit simultaneously provides the display scanning signal among the scanning timing control signals to the multiple pixel drivers according to the same timing during at least one frame period, and provides the emission control signal to the multiple pixel drivers according to the same timing.

7. The display device according to claim 1, in, The plurality of light-emitting pixels are arranged in a matrix shape in vertical stripe directions and horizontal stripe directions in the organic light-emitting display unit, and Each of the plurality of light-emitting pixels includes at least one light-emitting element, and the at least one light-emitting element includes a first electrode connected to a data line of the display device and a second electrode connected to a display scan line of the display device.

8. The display device according to claim 7, in: The emission driving circuit selectively supplies the emission control voltage to at least one data line among the plurality of data lines arranged parallel to each other in a vertical direction or a horizontal direction, wherein the emission control voltage has a high potential or a low potential, and The emission driving circuit selectively supplies a scan control voltage to at least one display scan line among the plurality of display scan lines arranged parallel to each other in the vertical direction or the horizontal direction, wherein the scan control voltage has a second high potential or a second low potential.

9. The display device according to claim 8, in, The transmitting driving circuit: analyzing and setting at least one emission area for rear surface light emission based on a grayscale value or a brightness value for each pixel data of the image data, distinguishing and setting an organic light emitting display surface of the organic light emitting display unit corresponding to the position of the at least one emission area, selectively providing the emission control voltage to the at least one data line arranged to correspond to or overlap the emission area of ​​the organic light emitting display surface, wherein the emission control voltage has the high potential, and selectively providing the scan control voltage to the at least one display scan line arranged to correspond to or overlap the emission area of ​​the organic light emitting display surface, wherein the scan control voltage has the second low potential, When a high potential emission control voltage is applied to the first electrode of the at least one light emitting element through the data line and a low potential scanning control voltage is applied to the second electrode of the at least one light emitting element through the display scanning line, the at least one light emitting element included in the multiple light emitting pixels emits light.

10. The display device according to claim 1, in, The plurality of light-emitting pixels include: a plurality of pixel drivers receiving each of the emission control voltage and the scanning timing control signal according to the same timing; and a light emitting element that emits light based on one or more driving currents through at least one pixel driver among the plurality of pixel drivers, Wherein, the plurality of pixel drivers include: a driving transistor for controlling a driving current provided by the driving transistor to at least one of the light emitting elements; a capacitor voltage supply terminal for supplying a capacitor voltage based on the emission control voltage to a gate electrode of the driving transistor; The i-th transistor is turned on by the display scanning signal among the scanning timing control signals to connect the driving transistor in a diode structure; a j-th transistor, which is turned on by the emission control signal among the scan timing control signals to connect the second electrode of the driving transistor to the anode electrode of the at least one light emitting element; and The emission control transistor supplies the emission control signal to the gate electrode of the j-th transistor in response to an emission control voltage input through at least one first emission control line and a scan control voltage input through at least one second emission control line.

11. The display device according to claim 10, in, The plurality of pixel drivers further include an emission control signal input terminal connected to the second electrode of the emission control transistor in a parallel configuration with the gate electrode of the j-th transistor, and the emission control signal input terminal includes an emission control capacitor.

12. The display device according to claim 10, in: the emission driving circuit selectively supplies the emission control voltage to the at least one first emission control line so that the emission control voltage is supplied to the gate electrode of the emission control transistor, wherein the emission control voltage has a high potential or a low potential, and The emission driving circuit selectively supplies the scan control voltage to the at least one second emission control line so that the scan control voltage is supplied to the first electrode of the emission control transistor, wherein the scan control voltage has a second high potential or a second low potential.

13. The display device according to claim 10, in, The transmitting driving circuit: analyzing and setting at least one emission area for rear surface light emission based on a grayscale value or a brightness value for each pixel data of the image data, distinguishing and setting an organic light emitting display surface of the organic light emitting display unit corresponding to the position of the at least one emission area, selectively providing the emission control voltage to the at least one first emission control line disposed to correspond to or overlap the emission region of the organic light emitting display unit, wherein the emission control voltage has a high potential, and The scan control voltage is selectively provided to the at least one second emission control line disposed to correspond to or overlap the emission area of ​​the organic light emitting display surface, wherein the scan control voltage has a second high potential.

14. A display device comprising: at least one spatial light modulator, displaying an augmented reality content image; a surface light source device for providing image display light to the at least one spatial light modulator from a rear direction of the at least one spatial light modulator as background light; as well as at least one image transmission component, forming a display path of the extended reality content image, Wherein, the surface light source device comprises: an organic light emitting display unit including a plurality of light emitting pixels performing surface light emission; and an emission driving circuit for controlling the light emitting operation of the plurality of light emitting pixels by providing each of an emission control voltage and a scan timing control signal to the plurality of light emitting pixels, The emission driving circuit provides the scanning timing control signal and the emission control voltage to the plurality of light-emitting pixels according to the same timing, so that the plurality of light-emitting pixels are driven according to the same timing in at least one frame unit.

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