Array substrate and display device

Abstract

The invention discloses an array substrate and a display device. The array substrate comprises data lines, grid lines and fan-out wires. The data lines comprise data line groups arranged along a first direction, each data line group comprises N data lines, and in each data line group, the mth data line is electrically connected with the (m + N / 2) th data line; the fan-out traces comprise fan-out trace groups arranged along a first direction, each fan-out trace group comprises N / 2 fan-out traces, the fan-out traces in the same fan-out trace group are electrically connected with the data lines in the same data line group, and the N / 2 fan-out traces are electrically connected with the mth data line to the (m-1 + N / 2) th data line in a one-to-one correspondence manner; each data line in at least one data line group is electrically connected with the corresponding fan-out wire through the first switching part, the number of the first switching parts through which the mth data line is electrically connected with the fan-out wire is the same as the number of the first switching parts through which the (m + N / 2) th data line is electrically connected with the fan-out wire, and the vertical stripe risk caused by resistance difference can be avoided.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to an array substrate and a display device. Background Art

[0002] A display device using dual gate technology reduces the number of data lines by half, doubles the number of gate lines, and reduces the number of source driver integrated circuits (ICs) connected to the data lines by half, while doubling the number of gate driver integrated circuits connected to the gate lines, thereby reducing costs. Summary of the invention

[0003] Embodiments of the present disclosure provide an array substrate and a display device.

[0004] The present disclosure provides an array substrate, comprising a display area and a non-display area located at least on one side of the display area, the array substrate comprising: a plurality of sub-pixels located in the display area, a plurality of data lines, a plurality of gate lines, and a plurality of fan-out routing lines located in the non-display area. The plurality of data lines are arranged along a first direction; the plurality of gate lines are arranged along a second direction, and a gate line pair formed by two gate lines is arranged between two adjacent sub-pixels arranged along the second direction, the first direction intersects the second direction; the plurality of fan-out routing lines are configured to be electrically connected to the plurality of data lines. The plurality of data lines include a plurality of data line groups arranged along the first direction, each data line group includes N data lines, and in each data line group, the mth data line is electrically connected to the (m+N / 2)th data line, where m is a positive integer not greater than N / 2; the plurality of fan-out routing lines include a plurality of fan-out routing lines arranged along the first direction, each fan-out routing line group includes N / 2 fan-out routing lines, and the fan-out routing lines in the same fan-out routing line group are electrically connected to the data lines in the same data line group, and the N / 2 fan-out routing lines are electrically connected to the mth data line to the (m-1+N / 2)th data lines in a one-to-one correspondence; each data line in at least one data line group is electrically connected to the corresponding fan-out routing line through at least one first transfer portion, and in the at least one data line group, the number of the first transfer portions through which the mth data line is electrically connected to the fan-out routing is the same as the number of the first transfer portions through which the (m+N / 2)th data line is electrically connected to the fan-out routing.

[0005] For example, according to an embodiment of the present disclosure, the first transfer portion includes at least two first transfer holes, and in the at least one data line group, the number of the first transfer holes through which the mth data line is electrically connected to the fan-out routing is the same as the number of the first transfer holes through which the (m+N / 2)th data line is electrically connected to the fan-out routing.

[0006] For example, according to an embodiment of the present disclosure, the non-display area includes a first non-display area and a second non-display area respectively located on both sides of the display area in the second direction, and the multiple fan-out routings and the first transfer portion are both located in the first non-display area; the array substrate also includes an electrostatic release structure, and the electrostatic release structure includes a first electrostatic release structure and a second electrostatic release structure, wherein the first electrostatic release structure is located in the first non-display area, and the second electrostatic release structure is located in the second non-display area, and the first electrostatic release structure is located between the multiple data lines and the first transfer portion, and the multiple data lines are electrically connected to the multiple fan-out routings through the first electrostatic release structure and the first transfer portion; the multiple data lines are electrically connected to the second electrostatic release structure through multiple second transfer portions, and the second electrostatic release structure is located on a side of the second transfer portion away from the multiple data lines, and the number of the second transfer portions through which the mth data line is electrically connected to the second electrostatic release structure is the same as the number of the second transfer portions through which the (m+N / 2)th data line is electrically connected to the second electrostatic release structure.

[0007] For example, according to an embodiment of the present disclosure, each second transfer portion includes at least two second transfer holes, and the number of the second transfer holes through which the mth data line is electrically connected to the second electrostatic release structure is the same as the number of the second transfer holes through which the (m+N / 2)th data line is electrically connected to the second electrostatic release structure.

[0008] For example, according to an embodiment of the present disclosure, in the at least one fan-out routing group, two adjacent fan-out routings are respectively a first fan-out routing and a second fan-out routing, and the first fan-out routing and the second fan-out routing are arranged in different layers; a straight line extending along the first direction passes through the first adapter portion electrically connected to each fan-out routing in the at least one fan-out routing group.

[0009] For example, according to an embodiment of the present disclosure, the mth data line is electrically connected to the (m+N / 2)th data line through a first connecting line located in the first non-display area, the first connecting line is connected to the first transfer portion, and the first connecting line and the fan-out line electrically connected thereto are arranged on the same layer.

[0010] For example, according to an embodiment of the present disclosure, the mth data line is electrically connected to the (m+N / 2)th data line through a second connecting line located in the second non-display area, and the second electrostatic release structure is connected to the second transfer portion through a third connecting line, and the third connecting line is arranged on the same layer as the second connecting line.

[0011] For example, according to an embodiment of the present disclosure, the first transfer portion includes at least two layers of conductive portions and a first transfer hole; the at least two layers of conductive portions include three layers of conductive portions, including a first conductive portion, a third conductive portion, and a second conductive portion stacked with the first conductive portion and the third conductive portion, and one of the first conductive portion and the third conductive portion is connected to the fan-out routing and is arranged on the same layer, or the at least two layers of conductive portions include two layers of conductive portions, including a first conductive portion and a second conductive portion stacked with the first conductive portion, and the first conductive portion is connected to the fan-out routing and is arranged on the same layer.

[0012] For example, according to an embodiment of the present disclosure, each first transfer portion electrically connected to each fan-out routing in the at least one fan-out routing group includes two transfer sub-portions arranged along the second direction, the number of the first connecting routing is multiple, and at least one first connecting routing passes through the gap between the two transfer sub-portions included in the first transfer portion that is not connected to it.

[0013] For example, according to an embodiment of the present disclosure, each adapter sub-section includes two adapter blocks arranged along the second direction; in each first adapter section, the adapter block closest to the multiple data lines is arranged on the same layer as the data lines, the adapter block closest to the fan-out routing is arranged on the same layer as the fan-out routing connected to the adapter block, and the two adapter blocks in the middle are connected and arranged on the same layer.

[0014] For example, according to an embodiment of the present disclosure, in the at least one fan-out routing group, each fan-out routing is arranged on the same layer, and each first transfer part electrically connected to each fan-out routing in the at least one fan-out routing group includes a three-layer conductive part and a first transfer hole, the three-layer conductive part includes a first sub-conductive part, a second sub-conductive part, and a third sub-conductive part that is stacked with the first sub-conductive part and the second sub-conductive part, the first sub-conductive part is located between the second sub-conductive part and the multiple data lines, the data lines are arranged on the same layer as the first sub-conductive part, and the fan-out routing is connected to the second sub-conductive part and is arranged on the same layer.

[0015] For example, according to an embodiment of the present disclosure, the mth data line is electrically connected to the (m+N / 2)th data line through a first connecting routing, the first connecting routing is connected to the first transfer portion, and the first connecting routing and the fan-out routing electrically connected thereto are arranged on the same layer; there are multiple first connecting routings, and the multiple first connecting routings include at least two types of first connecting routings, one first connecting routing includes a portion located on a side of a first transfer portion not connected thereto that is away from the multiple data lines, and the other first connecting routing includes a portion located on a side of the first transfer portion not connected thereto that is close to the multiple data lines.

[0016] For example, according to an embodiment of the present disclosure, the second transfer portion includes a three-layer conductive portion and a second transfer hole, the three-layer conductive portion includes a fourth sub-conductive portion, a fifth sub-conductive portion and a sixth sub-conductive portion which is stacked with the fourth sub-conductive portion and the fifth sub-conductive portion, the fourth sub-conductive portion is located between the fifth sub-conductive portion and the plurality of data lines, the data lines are arranged on the same layer as the fourth sub-conductive portion, the fifth sub-conductive portion is arranged on the same layer as the second connecting trace, and the second connecting trace and the third connecting trace are both connected to the fifth sub-conductive portion.

[0017] For example, according to an embodiment of the present disclosure, one of the first fan-out routing and the second fan-out routing is disposed at the same layer as the plurality of data lines, and the other of the first fan-out routing and the second fan-out routing is disposed at the same layer as the plurality of gate lines.

[0018] For example, according to an embodiment of the present disclosure, the second connecting wiring and the third connecting wiring are both arranged on the same layer as the plurality of gate lines.

[0019] For example, according to an embodiment of the present disclosure, the mth data line is electrically connected to the (m+N / 2)th data line through a second connecting line located in the second non-display area, and the second electrostatic release structure is connected to the second transfer portion through a third connecting line, and the third connecting line and the second connecting line are located on different layers.

[0020] For example, according to an embodiment of the present disclosure, the array substrate further includes: a detection signal line and a switch component, which are located in the second non-display area. The detection signal line and the switch component are both located on a side of the second electrostatic release structure away from the display area, and the detection signal line is connected to the second electrostatic release structure through the switch component.

[0021] For example, according to an embodiment of the present disclosure, N is 12, and the multiple gate lines include a first gate line and a second gate line alternately arranged along the second direction, six columns of sub-pixels electrically connected to the first data line to the sixth data line in the same data line group are electrically connected to the first gate line, and six columns of sub-pixels electrically connected to the seventh data line to the twelfth data line in the same data line group are electrically connected to the second gate line.

[0022] For example, according to an embodiment of the present disclosure, at least one gate line is provided with a plurality of bends, the plurality of bends comprising a plurality of first bends and a plurality of second bends alternately arranged along the first direction, the orientation of the first bends being opposite to the orientation of the second bends; each sub-pixel comprises a transistor, and each bend surrounds the transistor in N sub-pixels electrically connected to a data line group.

[0023] An embodiment of the present disclosure provides an array substrate, including a display area and a first non-display area and a second non-display area respectively located on both sides of the display area, the array substrate including: a plurality of sub-pixels located in the display area; a plurality of data lines located in the display area, the plurality of data lines are arranged along a first direction; a plurality of gate lines located in the display area, the plurality of gate lines are arranged along a second direction, and a gate line pair formed by two gate lines is arranged between two adjacent sub-pixels arranged along the second direction, the first direction intersects with the second direction; a plurality of fan-out routing lines located in the first non-display area, the plurality of fan-out routing lines are configured to be electrically connected to the plurality of data lines. The multiple data lines include multiple data line groups arranged along the first direction, each data line group includes N data lines, and in each data line group, the mth data line is electrically connected to the (m+N / 2)th data line, where m is a positive integer not greater than N / 2; the array substrate also includes an electrostatic release structure located in the second non-display area, the multiple data lines are electrically connected to the electrostatic release structure through multiple transition parts, and the electrostatic release structure is located on a side of the transition part away from the multiple data lines, and in at least one data line group, the number of transition parts through which the mth data line is electrically connected to the electrostatic release structure is the same as the number of transition parts through which the (m+N / 2)th data line is electrically connected to the electrostatic release structure.

[0024] For example, according to an embodiment of the present disclosure, each adapter part includes at least two adapter holes, and in the at least one data line group, the number of the adapter holes through which the mth data line is electrically connected to the electrostatic release structure is the same as the number of the adapter holes through which the (m+N / 2)th data line is electrically connected to the electrostatic release structure.

[0025] For example, according to an embodiment of the present disclosure, the mth data line is electrically connected to the (m+N / 2)th data line through a first sub-connection line located in the second non-display area, the electrostatic release structure is connected to the transfer portion through a second sub-connection line, and the first sub-connection line and the second sub-connection line are arranged on the same layer.

[0026] For example, according to an embodiment of the present disclosure, the first sub-connection wiring and the second sub-connection wiring are both arranged on the same layer as the gate line.

[0027] The present disclosure provides a display device, comprising any of the above array substrates. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0029] Figure 1It is a schematic diagram of a partial planar structure of an array substrate provided according to an embodiment of the present disclosure.

[0030] Figure 2 for Figure 1 A schematic diagram of the planar structure of some sub-pixels, data lines and gate lines in the display area of ​​the array substrate is shown.

[0031] Figure 3 The diagram is a partial planar structural diagram of a non-display area where a fan-out wiring of an array substrate is located.

[0032] Figure 4 for Figure 3 A schematic diagram of the local planar structure of the array substrate is shown.

[0033] Figure 5 for Figure 3 and Figure 4 A circuit schematic diagram showing electrical connection between data lines and fan-out wiring in an array substrate.

[0034] Figure 6 for Figure 1 A schematic diagram of the local structure of the first non-display area in the array substrate is shown.

[0035] Figure 7 for Figure 6 A circuit schematic diagram showing electrical connection between data lines and fan-out wiring in an array substrate.

[0036] Figure 8 and Fig. 9 Along Figure 6 The partial cross-sectional view taken along the lines AA' and BB' is shown.

[0037] Fig.10 A schematic diagram of the positional relationship between a first adapter and a first connecting line provided according to another example of an embodiment of the present disclosure.

[0038] Fig.11 A schematic diagram of the positional relationship among a first transfer portion, a first connecting line, and a fan-out line is provided according to another example of an embodiment of the present disclosure.

[0039] Fig.12 for Figure 1 A schematic diagram of the partial structure of the second non-display area in an example is shown.

[0040] Fig.13 for Fig.12 A partial enlarged view of the array substrate shown.

[0041] Fig.14 for Fig.13 A circuit schematic diagram showing electrical connection between a data line and a second electrostatic release structure in an array substrate.

[0042] Fig.15 for Figure 1 A schematic diagram of the partial structure of the second non-display area in the array substrate in another example is shown.

[0043] Fig.16 for Fig.15 A circuit schematic diagram showing electrical connection between a data line and a second electrostatic release structure in an array substrate.

[0044] Fig.17 The present invention is a schematic block diagram of a display device according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0045] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0046] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Including" or "comprising" and similar words mean that the elements or objects appearing in front of the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. The features such as "parallel", "vertical" and "same" used in the embodiments of the present disclosure include the features such as "parallel", "vertical", "same" in the strict sense, and "approximately parallel", "approximately vertical", "approximately the same" and other situations containing certain errors, taking into account the measurement and the errors related to the measurement of a specific amount (for example, the limitations of the measurement system), indicating the acceptable deviation range for a specific value determined by ordinary technicians in the field. For example, "approximately" can be expressed within one or more standard deviations, or within 10% or 5% of the value. When the number of a component is not particularly indicated in the following of the embodiments of the present disclosure, it means that the component can be one or more, or can be understood as at least one. "At least one" refers to one or more, and "multiple" refers to at least two. The "same-layer arrangement" referred to in the present disclosure refers to a structure formed by two (or more) structures formed by the same deposition process and patterned by the same composition process, and their materials may be the same or different. The "integrated arrangement structure" referred to in the present disclosure refers to a structure formed by two (or more) structures formed by the same deposition process and patterned by the same composition process and connected to each other, and their materials may be the same or different.

[0047] The present disclosure provides an array substrate and a display device. The array substrate includes a display area and a non-display area located at least on one side of the display area, and the array substrate includes a plurality of sub-pixels, a plurality of data lines and a plurality of gate lines located in the display area, and a plurality of fan-out wirings located in the non-display area. The plurality of data lines are arranged along a first direction; the plurality of gate lines are arranged along a second direction, and a gate line pair formed by two gate lines is arranged between two adjacent sub-pixels arranged along the second direction, and the first direction intersects with the second direction; the plurality of fan-out wirings are configured to be electrically connected to the plurality of data lines. The plurality of data lines include a plurality of data line groups arranged along a first direction, each data line group includes N data lines, and in each data line group, the mth data line is electrically connected to the (m+N / 2)th data line, where m is a positive integer not greater than N / 2; the plurality of fan-out routing lines include a plurality of fan-out routing lines arranged along a first direction, each fan-out routing line group includes N / 2 fan-out routing lines, and the fan-out routing lines in the same fan-out routing line group are electrically connected to the data lines in the same data line group, and the N / 2 fan-out routing lines are electrically connected to the mth data line to the (m-1+N / 2)th data lines in a one-to-one correspondence; each data line in at least one data line group is electrically connected to the corresponding fan-out routing line through at least one first adapter, and in at least one data line group, the number of first adapters through which the mth data line is electrically connected to the fan-out routing is the same as the number of first adapters through which the (m+N / 2)th data line is electrically connected to the fan-out routing.

[0048] By setting the number of first adapters through which different data lines are electrically connected to the fan-out wiring to be the same, it is helpful to reduce the difference in transmission resistance of different data lines, thereby avoiding the risk of vertical stripes caused by the resistance difference.

[0049] The present disclosure provides another array substrate, including a display area and a first non-display area and a second non-display area respectively located on both sides of the display area, the array substrate comprising: a plurality of sub-pixels located in the display area, a plurality of gate lines, and a plurality of fan-out routing lines located in the first non-display area. A plurality of data lines are arranged along a first direction; a plurality of gate lines are arranged along a second direction, and a gate line pair formed by two gate lines is arranged between two adjacent sub-pixels arranged along the second direction, and the first direction intersects the second direction; and the plurality of fan-out routing lines are configured to be electrically connected to the plurality of data lines. The multiple data lines include multiple data line groups arranged along a first direction, each data line group includes N data lines, and in each data line group, the mth data line is electrically connected to the (m+N / 2)th data line, where m is a positive integer not greater than N / 2; the array substrate also includes an electrostatic release structure, the electrostatic release structure includes a first electrostatic release structure and a second electrostatic release structure, the first electrostatic release structure is located in a first non-display area and between the multiple data lines and the multiple fan-out wirings, the second electrostatic release structure is located in a second non-display area, the multiple data lines are electrically connected to the second electrostatic release structure through multiple transition parts, the second electrostatic release structure is located on a side of the transition part away from the multiple data lines, and in at least one data line group, the number of transition parts through which the mth data line is electrically connected to the second electrostatic release structure is the same as the number of transition parts through which the (m+N / 2)th data line is electrically connected to the second electrostatic release structure.

[0050] By setting the number of second adapters through which each data line is electrically connected to the second electrostatic release structure to be the same, the difference in on-resistance between the far end of each data line and the second electrostatic release structure can be made smaller, thereby reducing the risk of specific defects.

[0051] The array substrate and the display device provided by the embodiments of the present disclosure are described below with reference to the accompanying drawings.

[0052] Figure 1 It is a schematic diagram of a partial planar structure of an array substrate provided according to an embodiment of the present disclosure.

[0053] like Figure 1 As shown, the array substrate includes a display area 10 and a non-display area 20 located at least on one side of the display area 10. For example, the non-display area 20 may be located on one side of the display area 10, or the non-display area 20 may be located on both sides of the display area 10, or the non-display area 20 may surround the display area 10.

[0054] like Figure 1As shown, the array substrate includes a plurality of sub-pixels 100 located in the display area 10, a plurality of data lines 210, a plurality of gate lines 220, and a plurality of fan-out wirings 300 located in the non-display area 20. For example, the array substrate includes a base substrate 01, and the sub-pixels 100, the data lines 210, the gate lines 220, and the fan-out wirings 300 are all the base substrate 01. For example, the area where the sub-pixels 100 are located can be an area defined by the intersection of the data lines 210 and the gate lines 220.

[0055] Figure 2 for Figure 1 A schematic diagram of the planar structure of some sub-pixels, data lines and gate lines in the display area of ​​the array substrate is shown.

[0056] For example, Figure 2 As shown, each sub-pixel 100 may include a pixel electrode 110 and a common electrode (not shown), and the common electrode may be an electrode shared by a plurality of sub-pixels 100. For example, each sub-pixel 100 includes a transistor 120, and for example, the transistor 120 may be a thin film transistor 120. According to the characteristics of the transistor, the transistor may be divided into an N-type transistor and a P-type transistor. The transistor provided in the embodiment of the present disclosure may be an N-type transistor or a P-type transistor according to actual needs. For example, the gate of the transistor 120 is electrically connected to the gate line 220, one of the source and drain of the transistor 120 is electrically connected to the data line 210, and the other of the source and drain of the transistor 120 is electrically connected to the pixel electrode 110. For example, the gate line 220 controls the opening or closing of the transistor 120, and the data line 210 inputs the voltage signal required for displaying the picture to the pixel electrode 110 of the sub-pixel 100 through the transistor 120 to realize the display of the display device including the display substrate.

[0057] For example, the plurality of sub-pixels 100 may include sub-pixels of different colors, such as a blue sub-pixel that displays blue light, a green sub-pixel that displays green light, and a red sub-pixel that displays red light. Of course, the plurality of sub-pixels may also include a white sub-pixel. Figure 1 The schematic diagram shows that the plurality of sub-pixels 100 include red sub-pixels, green sub-pixels and blue sub-pixels which are repeatedly arranged in sequence along a first direction, such as an X direction, such that three adjacent sub-pixels of different colors form one pixel.

[0058] like Figure 1 As shown, a plurality of data lines 210 are arranged along a first direction, a plurality of gate lines 220 are arranged along a second direction, and the first direction intersects the second direction. Figure 1 The first direction is schematically shown as the X direction and the second direction is the Y direction. However, the first direction and the second direction can be interchanged. For example, the angle between the first direction and the second direction is 80 to 110 degrees. For example, the first direction is perpendicular to the second direction.

[0059] like Figure 1 As shown, a gate line pair formed by two gate lines 220 is arranged between two adjacent sub-pixels 100 arranged along the second direction. For example, the plurality of gate lines 220 include a first gate line 221 and a second gate line 222 alternately arranged along the second direction. For example, the gate line pair includes a first gate line 221 and a second gate line 222.

[0060] like Figure 1 As shown, the plurality of data lines 210 include a plurality of data line groups 2100 arranged along a first direction, each data line group 2100 includes N data lines, and in each data line group 2100, the mth data line is electrically connected to the (m+N / 2)th data line, where m is a positive integer not greater than N / 2. In the array substrate provided by the present disclosure, the mth data line in each data line group is electrically connected to the (m+N / 2)th data line, which is equivalent to each data line group including only N / 2 data lines, so as to halve the number of data lines. The above N is an even number.

[0061] For example, Figure 1 As shown, a plurality of sub-pixels 100 can be arranged in an array along a first direction and a second direction. For example, the sub-pixels 100 arranged along the Y direction can be a column of sub-pixels, and the plurality of sub-pixels 100 include a plurality of columns of sub-pixels. For example, each column of sub-pixels is electrically connected to a data line 210. For example, the plurality of columns of sub-pixels include a plurality of sub-pixel column groups, and the plurality of sub-pixel column groups are electrically connected to the plurality of data line groups 2100 in a one-to-one correspondence. For example, each sub-pixel column group includes N columns of sub-pixels, and in each sub-pixel column group, the data line 210 electrically connected to the mth column of sub-pixels and the data line 210 electrically connected to the (m+N / 2)th column of sub-pixels are electrically connected to each other, such as end-to-end connection, and the mth column of sub-pixels and the (m+N / 2)th column of sub-pixels are electrically connected to the first gate line 221 and the second gate line 222, respectively, which is equivalent to each sub-pixel column group being electrically connected to only N / 2 data lines, which is conducive to reducing the number of data lines, thereby reducing the number of source driver chips, so as to reduce costs. However, the arrangement is not limited thereto, and multiple sub-pixels may also be arranged in other ways, such as a triangle arrangement, a diamond arrangement, etc., and may be arranged according to requirements.

[0062] like Figure 1As shown, the plurality of fan-out routing lines 300 are configured to be electrically connected to the plurality of data lines 210. The plurality of fan-out routing lines 300 include a plurality of fan-out routing line groups 3100 arranged along a first direction, each fan-out routing line group 3100 includes N / 2 fan-out routing lines, and the fan-out routing lines 300 in the same fan-out routing line group 3100 are electrically connected to the data lines 210 in the same data line group 2100, and the N / 2 fan-out routing lines 300 are electrically connected to the mth data line to the (m-1+N / 2)th data line in a one-to-one correspondence. In the array substrate provided by the present disclosure, the mth data line in each data line group is electrically connected to the (m+N / 2)th data line, and the routing lines in the fan-out routing group are electrically connected to the mth data line to the (m-1+N / 2)th data line in a one-to-one correspondence, so that the number of routing lines in the fan-out routing group corresponding to each data line group is N / 2, which is equivalent to each data line group including only N / 2 data lines, so as to achieve halving the number of data lines and halving the number of fan-outs in the fan-out routing group, which is beneficial to reducing the resistance difference caused by the length difference of different fan-out routing lines.

[0063] In some examples, such as Figure 1 and Figure 2 As shown, N is 12, and m is a positive integer not greater than 6, such as m can be 1, 2, 3, 4, 5 or 6. The six columns of sub-pixels 100 electrically connected to the first to sixth data lines in the same data line group 2100 are electrically connected to the first gate line 221, and the six columns of sub-pixels 100 electrically connected to the seventh to twelfth data lines in the same data line group 2100 are electrically connected to the second gate line 222.

[0064] For example, Figure 1 and Figure 2 As shown, 12 adjacent columns of sub-pixels constitute a sub-pixel column group. For example, three adjacent sub-pixels of different colors arranged along the X direction constitute a pixel, and a sub-pixel column group includes four columns of pixels. For example, Figure 1 The array substrate shown can be applied to FHD (Full High Definition) HADS (High Advanced-Super Dimensional Switching) display devices, where FHD refers to full high definition and HADS refers to advanced super dimensional switching.

[0065] For example, Figure 1 and Figure 2 As shown, the column inversion method can be used to Figure 1The display device of the array substrate shown is driven. The column inversion method refers to inverting the polarity of the display data every predetermined number of sub-pixel columns. For the column inversion method, in a frame, the polarity of the data signal on each data line is always the same polarity (positive or negative). Figure 1 As shown, the voltage polarities stored in the two sub-pixel columns connected to the same data line 210 are the same, and the voltage polarities stored in the two sub-pixel columns connected to the two adjacent data lines 210 are opposite. Thus, although the m-th column sub-pixel and the (m+3)-th column sub-pixel are configured to display the same color light, the two data lines connected to the m-th column sub-pixel and the (m+3)-th column sub-pixel transmit data signals of opposite polarities, while the m-th column sub-pixel and the (m+6)-th column sub-pixel are configured to display the same color light, and the data lines electrically connected to the two columns of sub-pixels transmit data signals of the same polarity, and the data lines electrically connected to the m-th column sub-pixel and the (m+6)-th column sub-pixel are connected end to end, respectively, so that the number of data signal lines is halved, and the problems of head shaking lines, fine lines (Fine-pitch), and high power consumption of color mixing can be avoided.

[0066] For example, Figure 1 As shown, the number N of the data lines 210 in the data line group 2100 is not less than 4. For example, N may be an even number such as 6 or 8, and may be set according to product requirements.

[0067] By setting the data lines as data line groups, the thin film transistor of each sub-pixel can be electrically connected to the data line closest to it, thereby preventing the problem that the thin film transistor of a certain sub-pixel cannot be electrically connected to the data line closest to it during the process of electrically connecting the thin film transistors of adjacent sub-pixels to the corresponding data lines, resulting in a large difference in the length of the connection structure between the thin film transistors of adjacent sub-pixels and the corresponding data lines. Figure 1 The array substrate shown has the characteristics of low cost, low power consumption, and high aperture ratio.

[0068] Figure 3 The diagram is a partial planar structural diagram of a non-display area where a fan-out wiring of an array substrate is located. Figure 4 for Figure 3 A schematic diagram of the local planar structure of the array substrate is shown.

[0069] Figure 3 and Figure 4 The array substrate shown has Figure 1 and Figure 2 The display area shown includes a sub-pixel 100 , a data line 210 , and a gate line 220 .

[0070] like Figure 3 and Figure 4As shown, the array substrate further includes an electrostatic discharge unit 50, and the data line 210 is electrically connected to the fan-out wiring 300 through the electrostatic discharge unit (ESD) 50, or the data line 210 is electrically connected to the fan-out wiring 300 through the electrostatic discharge unit 50 and the adapter 51. Taking the connection of 12 adjacent data lines 210 to 6 adjacent fan-out wirings 300 as an example, two adjacent data lines 210 transmit data signals of different polarities, and the mth data line 210 is electrically connected to the (m+6)th data line 210 through the connecting wiring 51.

[0071] like Figure 3 and Figure 4 As shown, among the plurality of fan-out routing lines 300 , two adjacent fan-out routing lines 31 and 32 are respectively located at different layers, for example, the fan-out routing line 31 is arranged at the same layer as the data line 210 , and the fan-out routing line 32 is arranged at the same layer as the gate line 220 .

[0072] Figure 5 for Figure 3 and Figure 4 A circuit schematic diagram showing electrical connection between data lines and fan-out wiring in an array substrate. Figure 4 The positions of 12 adjacent data lines S1 to S12 are schematically shown.

[0073] During the research, the inventors of the present application found that: Figure 3 and Figure 4 As shown, the first data line S1 is directly connected to the fan-out wiring 31, and the seventh data line S7 is electrically connected to the same fan-out wiring 31 through two adapters 41; the second data line S2 is electrically connected to the fan-out wiring 32 through a adapter 41, and the eighth data line S8 is electrically connected to the same fan-out wiring 32 through a adapter 41; the third data line S3 is directly connected to the fan-out wiring 31, and the ninth data line S9 is electrically connected to the same fan-out wiring 31 through two adapters 41; the fourth data line S4 is electrically connected to the fan-out wiring 31 through two adapters 41; The line S4 is electrically connected to the fan-out routing 32 through a transfer portion 41, and the 10th data line S10 is electrically connected to the same fan-out routing 32 through a transfer portion 41; the 5th data line S5 is electrically connected to the fan-out routing 31 through two transfer portions 41, and the 11th data line S11 is directly connected to the same fan-out routing 31; the 6th data line S6 is electrically connected to the fan-out routing 32 through a transfer portion 41, and the 12th data line S12 is electrically connected to the same fan-out routing 32 through a transfer portion 41.

[0074] like Figures 3 to 5As shown, only an electrostatic release unit 50 is arranged between the 1st data line S1, the 3rd data line S3 and the 11th data line S11 and the corresponding fan-out wiring 300, and two adapters 41 arranged between the 7th data line S7, the 9th data line S9 and the 5th data line S5 and the corresponding fan-out wiring 300 are equivalent to two resistors R0 and R1; a adapter 41 arranged between the 2nd data line S2, the 4th data line S4 and the 6th data line S6 and the corresponding fan-out wiring 300 is equivalent to a resistor R2, and a adapter 41 arranged between the 8th data line S8, the 10th data line S10 and the 12th data line S12 and the corresponding fan-out wiring 300 is equivalent to a resistor R3.

[0075] There are differences in the overall resistance of different data lines and corresponding fan-out routings. For example, the data signal required by data line S1 is directly transmitted into the display area without passing through the adapter; while the data signal required by data line S7 connected to data line S1 needs to pass through two additional adapters before entering the display area. The adapter includes at least two stacked conductive layers, and the two conductive layers are electrically connected through vias. Compared with the resistance of the metal connection routing, the resistance of the adapter is larger. For example, the resistance of a adapter is usually above 50Ω, while the resistance of a metal connection routing is only 5Ω. Therefore, even if the data signal transmitted from the fan-out routing to data line S1 and data line S7 is the same, during the data signal transmission process, the signal resistance difference corresponding to the sub-pixel electrically connected to data line S1 and the sub-pixel electrically connected to data line S7 can reach at least 100Ω, causing the risk of vertical stripes to increase significantly.

[0076] Therefore, among the data signals transmitted from the fan-out routing to the data lines, part of the data signals are directly transmitted into the display area, while part of the data signals need to pass through one or two additional adapters before entering the display area. Therefore, the difference in resistance corresponding to different data lines causes the risk of vertical stripes to increase significantly.

[0077] Figure 6 for Figure 1 A schematic diagram of the local structure of the first non-display area in the array substrate is shown. Figure 6 The positions of the data lines S1 to S12 are schematically shown. Figure 6 The structure of the first transfer portion in the array substrate away from the fan-out wiring can be Figure 3 The structure of the first transfer portion in the array substrate away from the fan-out wiring has the same characteristics.

[0078] like Figure 1 and Figure 6As shown, each data line 210 in at least one data line group 2100 is electrically connected to the corresponding fan-out routing 300 through at least one first transfer portion 410, and in at least one data line group 2100, the number of first transfer portions 410 through which the mth data line 210 is electrically connected to the fan-out routing 300 is the same as the number of first transfer portions 410 through which the (m+N / 2)th data line 210 is electrically connected to the fan-out routing 300.

[0079] The array substrate provided by the present disclosure helps to reduce the load difference of signal lines electrically connected to at least two columns of sub-pixels, thereby reducing the risk of vertical lines caused by resistance differences, by arranging the data lines connected to each other to be electrically connected to the corresponding fan-out wiring through the same number of first adapters.

[0080] For example, Figure 1 and Figure 6 As shown, different data lines 210 are electrically connected to the corresponding fan-out wiring 300 through the same number of first adapters 410, which is beneficial to reducing the transmission resistance difference of different data lines and thus avoiding the risk of vertical stripes caused by the resistance difference.

[0081] In some examples, such as Figure 6 As shown, the first transfer portion 410 includes at least two first transfer holes 4100. In at least one data line group 2100, the number of first transfer holes 4100 through which the mth data line 210 is electrically connected to the fan-out wiring 300 is the same as the number of first transfer holes 4100 through which the (m+N / 2)th data line 210 is electrically connected to the fan-out wiring 300. By arranging the data lines connected to each other to be electrically connected to the same fan-out wiring through the same number of first transfer holes, it is beneficial to achieve consistent loads of signal lines electrically connected to at least two columns of sub-pixels, so as to avoid the risk of vertical stripes caused by resistance differences.

[0082] For example, Figure 6 As shown, each first adapter portion 410 includes the same number of first adapter holes 4100 .

[0083] In some examples, such as Figure 1 and Figure 6 As shown, the non-display area 20 includes a first non-display area 21 and a second non-display area 22 respectively located on both sides of the display area 10 in the second direction, and the plurality of fan-out wirings 300 and the first transfer portion 410 are both located in the first non-display area 21. The array substrate further includes an electrostatic release structure 500, the electrostatic release structure 500 includes a first electrostatic release structure 510 located in the first non-display area 21, the first electrostatic release structure 510 is located in the plurality of data lines 210, such as between the data lines 210 arranged in the display area and the first transfer portion 410, and the plurality of data lines 210 are electrically connected to the plurality of fan-out wirings 300 through the first electrostatic release structure 510 and the first transfer portion 410.

[0084] Figure 7 for Figure 6 A circuit schematic diagram showing electrical connection between data lines and fan-out wiring in an array substrate.

[0085] For example, Figure 6 and Figure 7 As shown, the electrostatic release structure 500 also includes an electrostatic ring (Shorting Ring, SR) 501, such as the first electrostatic release structure 510 includes a plurality of sub-electrostatic release structures, each of which may include a plurality of transistors M, such as two transistors M9 and M11 or two transistors M13 and M15; each sub-electrostatic release structure is connected to a data line 210, and a plurality of sub-electrostatic release structures are connected to the electrostatic ring 501. When there is a large impact current on the data line, the transistor in the sub-electrostatic release structure can be turned on to transmit the large impact current to the electrostatic ring for further release. When there is a large impact current on the electrostatic ring, the sub-electrostatic release structure may also be turned on, and the current may be transmitted to the data line.

[0086] For example, Figure 1 and Figure 6 As shown, a dummy gate region (not shown) can also be set between the display area 10 and the electrostatic release structure 500 to make the load of the GOA (Gate Driven on Array) Reset unit close to the load of the display area gate line. For example, a common electrode line (not shown) can also be set between the dummy gate region and the electrostatic release structure 500, which is electrically connected to the common signal line in the display area to provide a planar distributed VCOM signal. For example, a pad is set on the side of the fan-out line 300 away from the display area 10 to achieve binding with the circuit board.

[0087] In some examples, such as Figure 6 As shown, in at least one fan-out routing group 3100, two adjacent fan-out routings 300 are respectively a first fan-out routing 310 and a second fan-out routing 320, and the first fan-out routing 310 and the second fan-out routing 320 are arranged in different layers. For example, the first fan-out routing 310 and the second fan-out routing 320 are arranged alternately.

[0088] In some examples, such as Figure 6 As shown, one of the first fan-out routing 310 and the second fan-out routing 320 is disposed at the same layer as the plurality of data lines 210 , and the other of the first fan-out routing 310 and the second fan-out routing 320 is disposed at the same layer as the plurality of gate lines 220 . Figure 6 It is schematically shown that the first fan-out wiring 310 is arranged at the same layer as the data line, and the second fan-out wiring 320 is arranged at the same layer as the gate line, but the present invention is not limited thereto. The first fan-out wiring and the second fan-out wiring can be interchangeable.

[0089] For example, Figure 6 As shown, the first data line S1 is electrically connected to the first fan-out routing 310 through two first transfer parts 410, and the seventh data line S7 is electrically connected to the same first fan-out routing 310 through two first transfer parts 410; the second data line S2 is electrically connected to the second fan-out routing 320 through two first transfer parts 410, and the eighth data line S8 is electrically connected to the same second fan-out routing 320 through two first transfer parts 410; the third data line S3 is electrically connected to the first fan-out routing 310 through two first transfer parts 410, and the ninth data line S9 is electrically connected to the same first fan-out routing 310 through two first transfer parts 410; The four data lines S4 are electrically connected to the second fan-out routing 320 through the two first adapters 410, and the tenth data line S10 is electrically connected to the same second fan-out routing 320 through the two first adapters 410; the fifth data line S5 is electrically connected to the first fan-out routing 310 through the two first adapters 410, and the eleventh data line S11 is electrically connected to the same first fan-out routing 310 through the two first adapters 410; the sixth data line S6 is electrically connected to the second fan-out routing 320 through the two first adapters 410, and the twelfth data line S12 is electrically connected to the same second fan-out routing 320 through the two first adapters 410.

[0090] For example, Figure 1 , Figure 6 and Figure 7 As shown, the same number of first transfer parts 410 are set between the mth data line Sm and the S(m+6)th data line and the corresponding fan-out routing 300. For example, two first transfer parts 410 are set, and the two first transfer parts 410 set between the mth data line Sm and the corresponding fan-out routing 300 are equivalent to two resistors R4 and R5, and the two first transfer parts 410 set between the S(m+6)th data line and the corresponding fan-out routing 300 are equivalent to two resistors R6 and R7. As a result, the overall resistance of different data lines and the corresponding fan-out routing is basically the same, which is conducive to reducing the risk of vertical stripes.

[0091] In some examples, such as Figure 6 As shown, the straight line extending along the first direction passes through the first transfer portion 410 electrically connected to each fan-out routing 300 in at least one fan-out routing group 3100. For example, the straight line may pass through the geometric center of the first transfer portion 410 electrically connected to each fan-out routing 300 in at least one fan-out routing group 3100. For example, the straight line may pass through the edge of the first transfer portion 410 electrically connected to each fan-out routing 300 in at least one fan-out routing group 3100. For example, the straight line may pass through the first transfer hole 4100 in the first transfer portion 410 electrically connected to each fan-out routing 300 in at least one fan-out routing group 3100.

[0092] For example, Figure 6 As shown, the plurality of first transfer portions 410 connected to the fan-out routing 300 of each fan-out routing group 3100 are arranged along the first direction. For example, the edges of the plurality of first transfer portions 410 connected to the fan-out routing 300 of each fan-out routing group 3100 that are parallel to the first direction and closest to the display area are substantially located on the same straight line, and the edges of the plurality of first transfer portions 410 connected to the fan-out routing 300 of each fan-out routing group 3100 that are parallel to the first direction and farthest from the display area are substantially located on the same straight line.

[0093] For example, Figure 6 The first transition portion 410 can be connected to Figure 4 The transition portion 41 shown has the same shape and size as Figure 4 As shown, the arrangement of the adapter 41 connected to the data line S1 to the data line S12, the present disclosure provides Figure 6 The arrangement of the first adapter portion 410 shown only increases the length in the second direction by less than 40 microns, such as less than 35 microns, such as 34 microns, and has little impact on the frame of the product, which can be basically ignored.

[0094] In some examples, such as Figure 6 As shown, the mth data line 210 is electrically connected to the (m+N / 2)th data line 210 through the first connecting wire 610 located in the first non-display area, the first connecting wire 610 is connected to the first transfer portion 410, and the first connecting wire 610 and the fan-out wire 300 electrically connected thereto are arranged in the same layer. For example, there are multiple first connecting wires 610, some of which can be arranged in the same layer as the data line 210, and another part of which can be arranged in the same layer as the gate line 220.

[0095] In some examples, such as Figure 6 As shown, each first transfer portion 410 electrically connected to each fan-out routing line 300 in at least one fan-out routing line group 3100 includes two transfer sub-portions 4101 arranged along the second direction. For example, the two transfer sub-portions 4101 are electrically connected. For example, a gap is set between the two transfer sub-portions 4101.

[0096] For example, Figure 6 As shown, the first connection line 610 and the fan-out line 300 are both electrically connected to the transfer sub-section 4101 close to the fan-out line 300. For example, a part of the transfer sub-section 4101 and the first connection line 610 and the fan-out line 300 connected thereto can be an integrated structure.

[0097] In some examples, such as Figure 6As shown, there are multiple first connection lines 610, and at least one first connection line 610 passes through the gap between two transfer sub-parts 4101 included in the first transfer part 410 that is not connected to it. For example, a part of the multiple first connection lines 610 is located between the first transfer part 410 and the fan-out line 300, and another part of the multiple first connection lines 610 passes through the gap between the two transfer sub-parts 4101 included in at least one first transfer part 410, which is conducive to reducing the space occupied by the first transfer part and the first connection line, thereby reducing the impact on the product frame.

[0098] For example, Figure 6 As shown, the more the number of N first transfer parts 410 connected to the N data lines in the same data line group overlaps with the first connection line 610, the smaller the distance between the first electrostatic release structure 510 and the fan-out line 300 can be set, and the smaller the impact on the frame. For example, the first transfer part 410 connected to the second data line S2 to the first transfer part 410 connected to the eleventh data line S11 all overlap with the first connection line 610, which is conducive to maximizing the reduction of the distance between the first electrostatic release structure 510 and the fan-out line 300.

[0099] For example, Figure 6 As shown, the distance between two adjacent first transfer parts 410 is greater than the line width of the two first connecting lines 610, so that the first connecting line can pass through the gap between the two adjacent first transfer parts 410 and connect to the transfer block 4102 in the first transfer part 410 close to the fan-out line 300.

[0100] In some examples, such as Figure 6 As shown, each adapter sub-section 4101 includes two adapter blocks 4102 arranged along the second direction. For example, the two adapter blocks 4102 included in the same adapter sub-section 4101 are arranged at intervals. For example, the two adapter blocks 4102 included in the same adapter sub-section 4101 can be arranged in the same layer or in different layers. For example, the size of each adapter block 4102 in the X direction is larger than the size in the Y direction, so as to reduce the size in the Y direction while maintaining a good electrical connection relationship, thereby reducing the impact on the frame.

[0101] In some examples, such as Figure 6As shown, in each first adapter 410, the adapter block 4102 closest to the plurality of data lines is arranged in the same layer as the data lines, the adapter block 4102 closest to the fan-out routing 300 is arranged in the same layer as the fan-out routing 300 connected to the adapter block 4102, and the two adapter blocks 4102 located in the middle are connected and arranged in the same layer. For example, a connection structure is arranged at a distance between two adapter sub-sections 4101 included in the same first adapter 410, and the connection structure can be an integrated structure with the two adapter blocks 4102 located in the middle. For example, the two adapter blocks 4102 located in the middle can be arranged in the same layer as the data lines 210 or the gate lines 220.

[0102] For example, Figure 6 As shown, a connection structure is provided at the interval between two transfer sub-sections 4101 included in the same first transfer section 410, and the first connection line 610 can overlap with the connection structure, for example, the connection structure can be provided in the same layer as the data line 210, or in the same layer as the gate line 220. For example, the size of the connection structure in the Y direction is larger than the line width of the first connection line 610. For example, the size of the connection structure in the X direction is smaller than the size of the transfer block 4102 in the X direction, so as to reduce the overlapping area of ​​the connection structure and the first connection line.

[0103] Figure 8 and Fig. 9 Along Figure 6 The partial cross-sectional view taken along the lines AA' and BB' is shown.

[0104] In some examples, such as Figure 6 , Figure 8 and Fig. 9 As shown, each first transfer portion 410 includes at least two layers of conductive portions and a first transfer hole 4100 located between two layers of conductive portions stacked in the at least two layers of conductive portions.

[0105] In some examples, such as Figure 6 and Figure 8 As shown, at least two layers of conductive parts include three layers of conductive parts, and the three layers of conductive parts include a first conductive part 411, a third conductive part 413, and a second conductive part 412 stacked with the first conductive part 411 and the third conductive part 413. One of the first conductive part 411 and the third conductive part 413 is connected to the fan-out routing 300 and is arranged on the same layer. Figure 6 and Figure 8 It is schematically shown that the third conductive portion 413 is connected to the fan-out wiring 300 and is disposed in the same layer, but it is not limited to that in other first transfer portions, the first conductive portion is connected to the fan-out wiring and is disposed in the same layer.

[0106] For example, Figure 8As shown, the array substrate includes an insulating layer 02 located between the first conductive part 411 and the third conductive part 413 and an insulating layer 03 located between the first conductive part 411 and the second conductive part 412, the second conductive part 412 is located on the side of the first conductive part 411 away from the base substrate 01, and the third conductive part 413 is located between the first conductive part 411 and the base substrate 01.

[0107] For example, Figure 8 As shown, the first conductive part 411 is arranged in the same layer as the data line, the third conductive part 413 is arranged in the same layer as the gate line, and the second conductive part 412 is arranged in the same layer as the common electrode of the sub-pixel. Of course, the disclosed embodiment is not limited to this, and the first conductive part and the third conductive part can be interchangeable. For example, the connection structure between the two third conductive parts 413 overlaps with the first connection line 610, and the first connection line 610 is located on the side of the third conductive part 413 away from the base substrate 01.

[0108] In some examples, such as Figure 6 and Fig. 9 As shown, at least two layers of conductive parts include two layers of conductive parts, the two layers of conductive parts include a first conductive part 411 and a second conductive part 412 stacked with the first conductive part 411, and the first conductive part 411 is connected to the fan-out wiring 300 and is arranged in the same layer. For example, the first conductive part 411 is arranged in the same layer as the data line, and the second conductive part 412 is arranged in the same layer as the common electrode of the sub-pixel. For example, the connection structure between the two first conductive parts 411 overlaps with the first connection wiring 610, and the first connection wiring 610 is located between the first conductive part 411 and the base substrate 01.

[0109] For example, Figures 6 to 9 As shown, the adapter block 4102 may be the first conductive portion 411 or the third conductive portion 413. For example, the adapter block 4102 closest to the data line may be the first conductive portion 411. For example, the adapter block 4102 connected to the first fan-out trace 310 and arranged on the same layer is the first conductive portion 411, and the adapter block 4102 connected to the second fan-out trace 320 and arranged on the same layer is the third conductive portion 413. For example, the two adapter blocks 4102 located in the middle may select the first conductive portion 411 or the third conductive portion 413 according to needs.

[0110] For example, Figure 6As shown, among the plurality of first adapters 410 connected to the data lines S1 to S12, the first portion of the first adapters 410 do not overlap with the first connection wires 610, the second portion of the first adapters 410 overlap with one first connection wire 610, and the third portion of the first adapters 410 overlap with two first connection wires 610. For example, the first adapters 410 connected to the data lines S1 and S12 do not overlap with the first connection wires 610, the first adapters 410 connected to the data lines S2, S3, S6, S7, S10, and S11 overlap with one first connection wire 610, and the first adapters 410 connected to the data lines S4, S5, S8, and S9 overlap with two first connection wires 610. For example, two adjacent first transfer portions 410 overlap with two first connection traces 610 , and the first transfer traces 610 overlapping with the two adjacent first transfer portions 410 are all disposed in the same layer.

[0111] For example, Figure 6 As shown, the first connection line 610 connecting the data line S1 and the data line S7 and the first connection line 610 connecting the data line S12 and the data line S6 are arranged in different layers and are basically symmetrically distributed about the symmetry axis between the data line S6 and the data line S7. For example, the two first connection lines 610 overlap with the first transfer portion 410.

[0112] In some examples, such as Figure 2 and Figure 3 As shown, at least one gate line 220 is provided with a plurality of curved portions 2200, and the plurality of curved portions 2200 include a plurality of first curved portions 2201 and a plurality of second curved portions 2202 alternately arranged along a first direction, and the orientation of the first curved portion 2201 is opposite to the orientation of the second curved portion 2202. For example, the first curved portion 2201 is oriented in the direction indicated by the arrow in the Y direction, and the second curved portion 2202 is oriented in the direction opposite to the direction indicated by the arrow in the Y direction. Of course, the first curved portion and the second curved portion can be interchangeable.

[0113] In some examples, such as Figure 2 and Figure 3 As shown, each bent portion 2200 surrounds the transistors 120 in N sub-pixels 100 electrically connected to one data line group 2100. For example, each bent portion 2200 surrounds the transistors 120 in 12 sub-pixels 100 electrically connected to one data line group 2100.

[0114] Fig.10 A schematic diagram of the positional relationship between a first adapter and a first connecting line provided according to another example of an embodiment of the present disclosure.

[0115] Fig.10 The array substrate and Figure 6The difference between the array substrate shown in FIG. 1 is that the relative position relationship between the first connecting wire 610 and the first adapter 410 is different. Fig.10 The array substrate shown provides another wiring method for connecting the first connecting wire 610 to the first transfer portion 410 .

[0116] For example, Fig.10 As shown, the first connecting line 610 passes through the gap between two transfer sub-parts of the first transfer part 410 connected to the 2nd to 6th data lines, and the gap between two transfer sub-parts of other first transfer parts 410 is not passed through by the first connecting line 610.

[0117] For example, Fig.10 As shown, the following description is made with the direction opposite to the arrow indicated by the X direction as downward. For example, the three transfer sub-sections on the side away from the data line in the three first transfer sections 410 connected to the data line S4, the data line S5, and the data line S6 are all surrounded by the first connecting line 610. For example, the first connecting line 610 connecting the data line S1 and the data line S7 is a bent line, which bypasses the middle of the two first transfer sections 410 connected to the data line S2 and the data line S3 (i.e., between the two transfer sub-sections included in each first transfer section 410), the bottom of the first transfer section 410 connected to the data line S4, the middle of the first transfer section 410 connected to the data line S5, and the bottom of the first transfer section 410 connected to the data line S6. For example, the first connecting line 610 connecting the data line S2 and the data line S8 is a bent line, which bypasses the middle of the first adapter part 410 connected to the data line S4 (i.e., between the two adapter sub-parts included in each first adapter part 410), the bottom of the first adapter part 410 connected to the data line S5, the middle of the first adapter part 410 connected to the data line S6, and the bottom of the first adapter part 410 connected to the data line S7.

[0118] For example, Fig.10 As shown, the first adapter parts 410 connected to the data lines S1, S7-S12 do not overlap with the first connection wiring 610, the first adapter parts 410 connected to the data lines S2-S4 overlap with one first connection wiring 610, and the first adapter parts 410 connected to the data lines S5 and S6 overlap with two first connection wirings 610.

[0119] Fig.11 A schematic diagram of the positional relationship among a first transfer portion, a first connecting line, and a fan-out line is provided according to another example of an embodiment of the present disclosure. Fig.11 The data lines, gate lines and electrostatic discharge structures in the array substrate shown can be Figures 1 to 4 as well as Figure 6 The data lines, gate lines and electrostatic release structures shown have the same features, which will not be described in detail here.

[0120] In some examples, such as Fig.11 As shown, in at least one fan-out routing group, each fan-out routing 300 is arranged on the same layer. For example, the fan-out routing 300 in each fan-out routing group is arranged on the same layer.

[0121] In some examples, such as Fig.11 As shown, each first transfer portion 410 electrically connected to each fan-out routing 300 in at least one fan-out routing group includes a three-layer conductive portion and a first transfer hole 4100 located between two layers of conductive portions stacked in the three-layer conductive portion, and the three-layer conductive portion includes a first sub-conductive portion 4111, a second sub-conductive portion 4112, and a third sub-conductive portion 4113 stacked with the first sub-conductive portion 4111 and the second sub-conductive portion 4112. The first sub-conductive portion 4111 is located between the second sub-conductive portion 4112 and a plurality of data lines, the data lines are arranged in the same layer as the first sub-conductive portion 4111, the fan-out routing 300 is arranged in the same layer as the second sub-conductive portion 4112, and the fan-out routing 300 is connected to the second sub-conductive portion 4112. For example, the fan-out routing 300 and the second sub-conductive portion 4112 connected thereto can be an integrated structure.

[0122] Fig.11 In the provided array substrate, by setting the fan-out routing to a single-layer structure, and each data line is electrically connected to the corresponding fan-out routing through the same number of first adapters, such as one first adapter, it is helpful to reduce the difference in transmission resistance of different data lines, thereby avoiding the risk of vertical lines caused by resistance differences.

[0123] For example, Fig.11 As shown, the fan-out wiring 300 and the second sub-conductive portion 4112 are both arranged in the same layer as the gate line. For example, the third sub-conductive portion 4113 is arranged in the same layer as the common electrode of the sub-pixel. For example, a straight line extending along the X direction can only pass through a portion of the first transition portion 410.

[0124] In some examples, such as Fig.11 As shown, the first connection line 610 is connected to the first transfer part 410, and the first connection line 610 and the fan-out line 300 electrically connected thereto are arranged in the same layer. For example, the first connection line 610, the first transfer part 410 and the fan-out line 300 connected to each other can be an integrated structure.

[0125] In some examples, such as Fig.11As shown, there are multiple first connection lines 610, and the multiple first connection lines 610 include at least two types of first connection lines 6101 and 6102. One first connection line 6101 includes a portion located on a side of the first transfer portion 410 that is not connected to it and is away from the multiple data lines, and the other first connection line 6102 includes a portion located on a side of the first transfer portion 410 that is not connected to it and is close to the multiple data lines.

[0126] For example, Fig.11 As shown, six adjacent first adapters 410 electrically connected to the same data line group are arranged along a first direction, and part of the first connection lines 610 are located between the six first adapters 410 and the fan-out line 300; another six adjacent first adapters 410 electrically connected to the same data line group are arranged along a direction having a certain angle with the first direction, and another part of the first connection lines 610 are located on a side of the other six first adapters 410 away from the fan-out line 300.

[0127] Fig.12 for Figure 1 A schematic diagram of the partial structure of the second non-display area in an example is shown. Fig.13 for Fig.12 A partial enlarged view of the array substrate shown. Fig.14 for Fig.13 A circuit schematic diagram showing electrical connection between a data line and a second electrostatic release structure in an array substrate.

[0128] In some examples, such as Figure 1 , Fig.12 and Fig.13 As shown, the electrostatic release structure 500 includes a second electrostatic release structure 520 located in the second non-display area 22, and multiple data lines 210 are electrically connected to the second electrostatic release structure 520 through multiple second transition parts 420. The second electrostatic release structure 520 is located on the side of the second transition part 420 away from the multiple data lines 210.

[0129] For example, Fig.12 and Fig.14As shown, the electrostatic release structure 500 also includes an electrostatic ring (Shorting Ring, SR) 502, such as the second electrostatic release structure 520 includes a plurality of sub-electrostatic release structures, each of which may include a plurality of transistors M, such as two transistors M17 and M19 or two transistors M21 and M23; each sub-electrostatic release structure is connected to a data line 210, and a plurality of sub-electrostatic release structures are connected to the electrostatic ring 502. When there is a large impact current on the data line, the transistor in the sub-electrostatic release structure can be turned on to transmit the large impact current to the electrostatic ring for further release. When there is a large impact current on the electrostatic ring, the sub-electrostatic release structure may also be turned on, and the current will be transmitted to the data line.

[0130] For example, Fig.12 As shown, a common electrode wiring (not shown) may be further provided between the second transfer portion 420 and the display area, and electrically connected to the common signal line in the display area to provide a planar distributed VCOM signal.

[0131] In some examples, such as Fig.12 and Fig.13 As shown, the array substrate further includes a detection signal line 710 and a switch component 720 located in the second non-display area, and the detection signal line 710 and the switch component 720 are both located on the side of the second electrostatic release structure 520 away from the display area, and the detection signal line 710 is connected to the second electrostatic release structure 520 through the switch component 720. For example, the array substrate further includes a detection signal switch line 730 located in the second display area. For example, the plurality of data lines 210 are grouped according to signals transmitted according to sub-pixels of different colors, such as data lines S1, data lines S4, data lines S7 and data lines S10 are data line groups that transmit data signals of red sub-pixels; data lines S2, data lines S5, data lines S8 and data lines S11 are data line groups that transmit data signals of green sub-pixels; data lines S3, data lines S6, data lines S9 and data lines S12 are data line groups that transmit data signals of blue sub-pixels.

[0132] For example, Fig.12 and Fig.13As shown, when producing a display device including an array substrate, it is necessary to detect whether there is a problem with the display. In the detection stage, a high-level signal can be loaded on the detection signal switch line 730 (for example, when the switch component is an N-type transistor, a high-level signal is loaded; when the switch component is a P-type transistor, a low-level signal is loaded), and the control switch component 720 is in an open state, and the signal corresponding to the red sub-pixel transmitted by the detection signal line 710 (the first detection signal line 7101) is transmitted to the data lines S1, S4, S7, and S10 through the control switch component. When the control switch component 720 is in the on state, the signal corresponding to the green sub-pixel transmitted by the detection signal line 710 (the second detection signal line 7102) is transmitted to data lines such as data line S2, data line S5, data line S8 and data line S11 through the control switch component; when the control switch component 720 is in the on state, the signal corresponding to the blue sub-pixel transmitted by the detection signal line 710 (the third detection signal line 7103) is transmitted to data lines such as data line S3, data line S6, data line S9 and data line S12 through the control switch component.

[0133] For example, Fig.12 and Fig.13 As shown, when the display device including the array substrate works normally, a low level signal is loaded on the detection signal switch line 730 to control the switch component 720 to be in a closed state, and at this time only the data line Sm is connected to the data line S(m+6).

[0134] For example, Fig.12 As shown, at least one switch component 720 can be a thin film transistor, and the gate of the thin film transistor and the detection signal switch line 730 are an integrated structure. The thin film transistor includes a first pole and a second pole, the first pole is connected to the second electrostatic release structure 520, and the second pole is connected to the detection signal line 710 through a block connection portion 740. The second pole overlaps with other detection signal lines 710 that are not connected to it, and a pad 750 is provided at the overlapping position. For example, the pad 750 can be provided in the same layer as the active layer of the thin film transistor. By providing a pad at the overlapping position of the second pole of the thin film transistor and the detection signal line, the probability of electrostatic breakdown at the overlapping position of the second pole and the detection signal line can be reduced, and the step difference between the position and the position where the active layer of the thin film transistor is located can also be improved.

[0135] In some examples, such as Fig.13 As shown, the mth data line 210 is electrically connected to the (m+N / 2)th data line 210 via a second connecting wire 620 located in the second non-display area, and the second electrostatic release structure 520 is connected to the second transfer portion 420 via a third connecting wire 630, and the third connecting wire 630 and the second connecting wire 620 are located in different layers.

[0136] For example, Fig.13 As shown, the mth data line 210 is electrically connected to the (m+6)th data line 210 through the second connection wiring 620 located in the second non-display area. For example, one of the second connection wiring 620 and the third connection wiring 630 is disposed in the same layer as the data line, and the other is disposed in the same layer as the gate line.

[0137] For example, Fig.12 and Fig.13 As shown, the second adapter 420 includes two adapter blocks 4202, one adapter block 4202 is a first adapter block close to the data line 210, and the other adapter block 4202 is a second adapter block far away from the data line 210. The first adapter block is arranged in the same layer as the data line 210, and the second adapter block is arranged in the same layer as the gate line 220. For example, the third connecting wire 630 is arranged in the same layer as the data line 210, and the third connecting wire 630 is connected to the first adapter block. For example, the third connecting wire 630 is an integrated structure with the first adapter block. For example, the second connecting wire 620 is arranged in the same layer as the gate line 220, and the second connecting wire 620 is connected to the second adapter block. For example, the second connecting wire 620 is an integrated structure with the second adapter block.

[0138] During the research, the inventors of the present application found that: Figure 12 to Figure 14 As shown, the first data line S1, the second data line S2, the third data line S3, the tenth data line S10, the eleventh data line S11 and the twelfth data line S12 are directly connected to the third connection line 630; the remaining other data lines 210 are connected to the corresponding third connection lines 630 through two second adapters 420. For example, the two second adapters 420 provided between the seventh data line S7, the eighth data line S8 and the ninth data line S9 and the corresponding third connection lines 630 are equivalent to the two resistors R1 and R10, and the two second adapters 420 provided between the fourth data line S4, the fifth data line S5 and the sixth data line S6 and the corresponding third connection lines 630 are equivalent to the two resistors R14 and R15.

[0139] The overall resistance of different data lines and the corresponding third connection lines is different, so the remote antistatic ability of each data line is different for different data lines. For example, the impulse current transmission resistance between different data lines and the second electrostatic release structure is different. Fig.13As shown, compared with the 1st data line S1, the 2nd data line S2, the 3rd data line S3, the 10th data line S10, the 11th data line S11 and the 12th data line S12 which are all directly connected to the third connecting line 630, the remaining other data lines 210 are mostly connected to the corresponding third connecting lines 630 through two second adapters 420. When large external static electricity is introduced into the display device, the probability of inducing static electricity to pass through different static electricity release structures is different. For example, large static electricity is easily concentrated on the static electricity release structure that is not connected to the second adapter, resulting in electrostatic selectivity, that is, causing poor specificity.

[0140] Fig.15 for Figure 1 A schematic diagram of the local structure of the second non-display area in the array substrate is shown. Fig.15 The positions of the data lines S1 to S12 are schematically shown. Fig.15 The structure of the second transfer portion in the array substrate away from the second electrostatic release structure can be Fig.12 The structure of the second transfer portion in the array substrate away from the second electrostatic release structure has the same characteristics. Fig.15 The structure of the second transfer portion in the array substrate can be similar to Fig.12 The second transfer parts in the array substrate shown have the same structure.

[0141] In some examples, such as Fig.15 As shown, the number of second transition portions 420 through which the mth data line is electrically connected to the second electrostatic release structure 520 is the same as the number of second transition portions 420 through which the (m+N / 2)th data line is electrically connected to the second electrostatic release structure 520 .

[0142] By setting the number of second adapters through which each data line is electrically connected to the second electrostatic release structure to be the same, the difference in on-resistance between the far end of each data line and the second electrostatic release structure can be made smaller, thereby reducing the risk of specific defects.

[0143] In some examples, such as Fig.15 As shown, each second adapter part 420 includes at least two second adapter holes 4200, and the number of second adapter holes 4200 through which the m-th data line is electrically connected to the second electrostatic release structure 520 is the same as the number of second adapter holes 4200 through which the (m+N / 2)-th data line is electrically connected to the second electrostatic release structure 520. This can make the on-resistance between the far end of each data line and the second electrostatic release structure basically equal, further reducing the risk of specific adverse reactions.

[0144] In some examples, such as Fig.15As shown, the mth data line is electrically connected to the (m+N / 2)th data line through the second connection line 620 located in the second non-display area, the second electrostatic release structure 520 is connected to the second adapter 420 through the third connection line 630, and the third connection line 630 is arranged on the same layer as the second connection line 620. By arranging the second connection line and the third connection line on the same layer, it is beneficial to set the number of second adapters through which each data line is electrically connected to the corresponding third connection line to be the same.

[0145] In some examples, such as Fig.12 and Fig.15 As shown, the second connection wiring 620 and the third connection wiring 630 are both arranged in the same layer as the plurality of gate lines 220. For example, the second connection wiring 620 and the third connection wiring 630 are both connected to the second adapter block of the second adapter portion 420. For example, the second adapter block and the second connection wiring 620 and the third connection wiring 630 connected thereto are an integrated structure.

[0146] Fig.16 for Fig.15 A circuit schematic diagram showing electrical connection between a data line and a second electrostatic release structure in an array substrate.

[0147] For example, Fig.15 and Fig.16 As shown, the same number of second transfer parts 420 are set between the mth data line Sm and the S(m+6)th data line and the corresponding second electrostatic release structure 520. For example, one second transfer part 420 is set, and one second transfer part 420 set between the mth data line Sm and the corresponding second electrostatic release structure 520 is equivalent to a resistor R11, and one second transfer part 420 set between the S(m+6)th data line and the corresponding second electrostatic release structure 520 is equivalent to a resistor R8. As a result, the conduction resistance of the far end of each data line and the second electrostatic release structure is substantially equal, further reducing the risk of specific adverse effects.

[0148] In some examples, such as Fig.12 and Fig.15As shown, each second transfer portion 420 includes three layers of conductive portions and a second transfer hole 4200 located between two layers of conductive portions stacked in the three layers of conductive portions, the three layers of conductive portions include a fourth sub-conductive portion 4201, a fifth sub-conductive portion 4202, and a sixth sub-conductive portion 4203 stacked with the fourth sub-conductive portion and the fifth sub-conductive portion 4202, the fourth sub-conductive portion 4201 is located between the fifth sub-conductive portion 4202 and a plurality of data lines 210, the data lines 210 are arranged in the same layer as the fourth sub-conductive portion 4201, the fifth sub-conductive portion 4202 is arranged in the same layer as the second connection wiring 620, and the second connection wiring 620 and the third connection wiring 630 are both connected to the fifth sub-conductive portion 4202. For example, the sixth sub-conductive portion 4203 can be arranged in the same layer as the common electrode of the sub-pixel.

[0149] For example, Fig.15 As shown, the connection relationship between the fourth sub-conductive portion 4201 and the sixth sub-conductive portion 4203 can be referred to Fig. 9 The connection relationship between the second conductive part 412 and the first conductive part 411, and the connection relationship between the fifth sub-conductive part 4202 and the sixth sub-conductive part 4203 can be referred to Figure 8 The connection relationship between the third conductive portion 413 and the first conductive portion 411 is shown.

[0150] Another embodiment of the present disclosure provides an array substrate, which can be referred to as Figures 1 to 16 The array substrate shown includes a display area 10 and a first non-display area 21 and a second non-display area 22 respectively located on two sides of the display area 10 .

[0151] like Figure 1 As shown, the array substrate includes a plurality of sub-pixels 100 located in the display area 10, a plurality of data lines 210, a plurality of gate lines 220, and a plurality of fan-out wirings 300 located in the first non-display area 21. The plurality of data lines 210 are arranged along a first direction, the plurality of gate lines 220 are arranged along a second direction, and a gate line pair formed by two gate lines is arranged between two adjacent sub-pixels 100 arranged along the second direction, and the first direction intersects with the second direction; the plurality of fan-out wirings 300 are configured to be electrically connected to the plurality of data lines 210. The plurality of data lines 210 include a plurality of data line groups 2100 arranged along the first direction, each data line group 2100 includes N data lines, and in each data line group 2100, the mth data line 210 is electrically connected to the (m+N / 2)th data line 210, where m is a positive integer not greater than N / 2. The sub-pixels, data lines, gate lines and fan-out wiring in the array substrate provided in this embodiment may have the same features as the sub-pixels, data lines, gate lines and fan-out wiring in the above embodiments, and will not be described in detail here.

[0152] like Figures 1 to 16As shown, the array substrate also includes an electrostatic release structure 520 (equivalent to the second electrostatic release structure 520 in the above embodiment), which is located in the second non-display area 22. Multiple data lines 210 are electrically connected to the electrostatic release structure 520 through multiple transition parts 420 (equivalent to the second transition parts 420 in the above embodiment), and the electrostatic release structure 520 is located on the side of the transition part 420 away from the multiple data lines 210.

[0153] For example, the array substrate further includes a first electrostatic release structure 510 located in the first non-display area 21 and between the plurality of data lines 210 and the plurality of fan-out wirings 300 .

[0154] The first electrostatic release structure, fan-out wiring, and first transfer portion in the array substrate provided in this embodiment may have the same features as the first electrostatic release structure, fan-out wiring, and first transfer portion in the above-mentioned embodiment, and will not be described in detail here. The second electrostatic release structure and transfer portion in the array substrate provided in this embodiment may have the same features as the second electrostatic release structure and second transfer portion in the above-mentioned embodiment, and will not be described in detail here.

[0155] like Fig.15 and Fig.16 As shown, in at least one data line group, the number of transition portions 420 through which the mth data line is electrically connected to the second electrostatic release structure 520 is the same as the number of transition portions 420 through which the (m+N / 2)th data line is electrically connected to the second electrostatic release structure 520. For example, N may be the same as N in the above embodiment. The data line and the second electrostatic release structure connection method in the array substrate provided in this embodiment is only Fig.15 Examples shown, not including Fig.13 The example shown in the figure and the connection method between the data line and the fan-out line in the array substrate provided in this embodiment include: Figures 4 to 11 Any of the examples provided.

[0156] By setting the number of transition parts through which each data line is electrically connected to the second electrostatic release structure to be the same, the difference in on-resistance between the far end of each data line and the second electrostatic release structure can be made smaller, thereby reducing the risk of specific defects.

[0157] In some examples, such as Fig.15 As shown, each adapter part 420 includes at least two adapter holes 4200 (equivalent to the second adapter hole 4200 in the above embodiment). In at least one data line group, the number of adapter holes 4200 through which the mth data line 210 is electrically connected to the second electrostatic release structure 520 is the same as the number of adapter holes 4200 through which the (m+N / 2)th data line is electrically connected to the second electrostatic release structure 520. This can make the on-resistance between the far end of each data line and the second electrostatic release structure basically equal, thereby further reducing the risk of specific adverse reactions.

[0158] In some examples, such as Fig.15 As shown, the mth data line is electrically connected to the (m+N / 2)th data line through the first sub-connection wiring 620 (equivalent to the second connection wiring 620 in the above embodiment) located in the second non-display area, the second electrostatic release structure 520 is connected to the adapter 420 through the second sub-connection wiring 630 (equivalent to the third connection wiring 630 in the above embodiment), and the first sub-connection wiring 620 and the second sub-connection wiring 630 are arranged on the same layer. By arranging the first sub-connection wiring and the second sub-connection wiring on the same layer, it is beneficial to set the number of adapters through which each data line is electrically connected to the second electrostatic release structure to be the same.

[0159] In some examples, such as Fig.12 and Fig.15 As shown, the first sub-connection wiring 620 and the second sub-connection wiring 630 are both arranged in the same layer as the gate line 220. The first sub-connection wiring and the second sub-connection wiring in this embodiment may have the same features as the second connection wiring and the third connection wiring in the above embodiment, which will not be described in detail.

[0160] For example, Figure 6 and Fig.13 As shown, in an example of an embodiment of the present disclosure, the number of first transfer portions 410 through which the data line Sm is electrically connected to the fan-out routing 300 is the same as the number of first transfer portions 410 through which the data line S(m+N / 2) is electrically connected to the same fan-out routing 300, and the number of second transfer portions 420 through which the data line Sm is electrically connected to the second electrostatic release structure 520 is different from the number of second transfer portions 420 through which the data line S(m+N / 2) is electrically connected to the same second electrostatic release structure 520.

[0161] For example, Figure 6 and Fig.15 As shown, in an example of an embodiment of the present disclosure, the number of first transfer portions 410 through which the data line Sm is electrically connected to the fan-out routing 300 is the same as the number of first transfer portions 410 through which the data line S(m+N / 2) is electrically connected to the same fan-out routing 300, and the number of second transfer portions 420 through which the data line Sm is electrically connected to the second electrostatic release structure 520 is the same as the number of second transfer portions 420 through which the data line S(m+N / 2) is electrically connected to the same second electrostatic release structure 520.

[0162] For example, Figure 4 and Fig.15As shown, in an example of an embodiment of the present disclosure, the number of transition portions 41 through which the data line Sm is electrically connected to the fan-out routing 300 is different from the number of transition portions 41 through which the data line S(m+N / 2) is electrically connected to the same fan-out routing 300, and the number of second transition portions 420 through which the data line Sm is electrically connected to the second electrostatic release structure 520 is the same as the number of second transition portions 420 through which the data line S(m+N / 2) is electrically connected to the same second electrostatic release structure 520.

[0163] Fig.17 1 is a schematic block diagram of a display device according to another embodiment of the present disclosure. Another embodiment of the present disclosure provides a display device, the display device 800 comprising any one of the above array substrates 900 .

[0164] For example, the display device further includes an opposing substrate disposed opposite to the array substrate. For example, the opposing substrate may be a color filter substrate. For example, the display device further includes a liquid crystal layer located between the array substrate and the opposing substrate.

[0165] For example, the display device may be any product or component with a display function, such as a television, a digital camera, a mobile phone, a watch, a tablet computer, a laptop computer, a navigator, etc., but the present embodiment is not limited thereto.

[0166] There are a few points to note:

[0167] (1) In the drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are involved, and other structures can refer to the general design.

[0168] (2) In the absence of conflict, features in the same embodiment or in different embodiments of the present disclosure may be combined with each other.

[0169] The above description is merely an exemplary embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure. The protection scope of the present disclosure is determined by the appended claims.

Claims

1. An array substrate, comprising a display area and a non-display area located at at least one side of the display area, the array substrate comprising: A plurality of sub-pixels are located in the display area; A plurality of data lines are located in the display area, and the plurality of data lines are arranged along a first direction; A plurality of gate lines are located in the display area, the plurality of gate lines are arranged along a second direction, a gate line pair formed by two gate lines is arranged between two adjacent sub-pixels arranged along the second direction, and the first direction intersects the second direction; A plurality of fan-out wirings are located in the non-display area, and the plurality of fan-out wirings are configured to be electrically connected to the plurality of data lines. The plurality of data lines include a plurality of data line groups arranged along the first direction, each data line group includes N data lines, and in each data line group, the mth data line is electrically connected to the (m+N / 2)th data line, where m is a positive integer not greater than N / 2; The plurality of fan-out routing lines include a plurality of fan-out routing line groups arranged along the first direction, each fan-out routing line group includes N / 2 fan-out routing lines, and the fan-out routing lines in the same fan-out routing line group are electrically connected to the data lines in the same data line group, and the N / 2 fan-out routing lines are electrically connected to the mth data line to the (m-1+N / 2)th data line in a one-to-one correspondence; Each data line in at least one data line group is electrically connected to the corresponding fan-out routing through at least one first transfer portion, and in the at least one data line group, the number of the first transfer portions through which the mth data line is electrically connected to the fan-out routing is the same as the number of the first transfer portions through which the (m+N / 2)th data line is electrically connected to the fan-out routing.

2. The array substrate according to claim 1, wherein: The first transfer portion includes at least two first transfer holes, and in the at least one data line group, the number of the first transfer holes through which the mth data line is electrically connected to the fan-out routing is the same as the number of the first transfer holes through which the (m+N / 2)th data line is electrically connected to the fan-out routing.

3. The array substrate according to claim 1, wherein: The non-display area includes a first non-display area and a second non-display area respectively located on both sides of the display area in the second direction, and the plurality of fan-out wirings and the first transfer portion are both located in the first non-display area; The array substrate further includes an electrostatic release structure, the electrostatic release structure including a first electrostatic release structure and a second electrostatic release structure, wherein the first electrostatic release structure is located in the first non-display area, the second electrostatic release structure is located in the second non-display area, the first electrostatic release structure is located between the plurality of data lines and the first transfer portion, and the plurality of data lines are electrically connected to the plurality of fan-out routings through the first electrostatic release structure and the first transfer portion; The multiple data lines are electrically connected to the second electrostatic release structure through multiple second transfer parts, the second electrostatic release structure is located on a side of the second transfer part away from the multiple data lines, and the number of the second transfer parts through which the mth data line is electrically connected to the second electrostatic release structure is the same as the number of the second transfer parts through which the (m+N / 2)th data line is electrically connected to the second electrostatic release structure.

4. The array substrate according to claim 3, wherein: Each second transfer portion includes at least two second transfer holes, and the number of the second transfer holes through which the mth data line is electrically connected to the second electrostatic release structure is the same as the number of the second transfer holes through which the (m+N / 2)th data line is electrically connected to the second electrostatic release structure.

5. The array substrate according to any one of claims 1 to 4, wherein: In the at least one fan-out routing group, two adjacent fan-out routings are respectively a first fan-out routing and a second fan-out routing, and the first fan-out routing and the second fan-out routing are arranged in different layers; A straight line extending along the first direction passes through the first transfer portion electrically connected to each fan-out routing line in the at least one fan-out routing group.

6. The array substrate according to claim 5, wherein: The mth data line is electrically connected to the (m+N / 2)th data line via a first connecting line located in the first non-display area, the first connecting line is connected to the first transfer portion, and the first connecting line and the fan-out line electrically connected thereto are arranged on the same layer.

7. The array substrate according to claim 3, wherein: The mth data line is electrically connected to the (m+N / 2)th data line via a second connecting line located in the second non-display area, the second electrostatic release structure is connected to the second adapter via a third connecting line, and the third connecting line is arranged on the same layer as the second connecting line.

8. The array substrate according to claim 6, wherein: The first transfer portion includes at least two layers of conductive portions and a first transfer hole; The at least two layers of conductive parts include three layers of conductive parts, including a first conductive part, a third conductive part, and a second conductive part stacked with the first conductive part and the third conductive part, one of the first conductive part and the third conductive part is connected to the fan-out routing and is arranged on the same layer, or the at least two layers of conductive parts include two layers of conductive parts, including a first conductive part and a second conductive part stacked with the first conductive part, the first conductive part is connected to the fan-out routing and is arranged on the same layer.

9. The array substrate according to claim 8, wherein: Each first transfer portion electrically connected to each fan-out routing in the at least one fan-out routing group includes two transfer sub-portions arranged along the second direction, the number of the first connecting routing is multiple, and at least one first connecting routing passes through the gap between the two transfer sub-portions included in the first transfer portion that is not connected to it.

10. The array substrate according to claim 9, wherein: Each adapter sub-section includes two adapter blocks arranged along the second direction; In each first adapter part, the adapter block closest to the multiple data lines is arranged on the same layer as the data lines, the adapter block closest to the fan-out routing is arranged on the same layer as the fan-out routing connected to the adapter block, and the two adapter blocks in the middle are connected and arranged on the same layer.

11. The array substrate according to claim 1, wherein: In the at least one fan-out routing group, each fan-out routing is arranged in the same layer, each first transfer portion electrically connected to each fan-out routing in the at least one fan-out routing group includes a three-layer conductive portion and a first transfer hole, the three-layer conductive portion includes a first sub-conductive portion, a second sub-conductive portion, and a third sub-conductive portion which is stacked with the first sub-conductive portion and the second sub-conductive portion, the first sub-conductive portion is located between the second sub-conductive portion and the plurality of data lines, the data lines are arranged in the same layer as the first sub-conductive portion, and the fan-out routing is connected to the second sub-conductive portion and is arranged in the same layer.

12. The array substrate according to claim 11, wherein: The mth data line is electrically connected to the (m+N / 2)th data line via a first connecting line, the first connecting line is connected to the first transfer portion, and the first connecting line and the fan-out line electrically connected thereto are arranged on the same layer; There are multiple first connection routings, and the multiple first connection routings include at least two types of first connection routings, one first connection routing includes a portion located on a side of a first adapter portion that is not connected to it and is away from the multiple data lines, and the other first connection routing includes a portion located on a side of the first adapter portion that is not connected to it and is close to the multiple data lines.

13. The array substrate according to claim 7, wherein: The second transfer portion includes a three-layer conductive portion and a second transfer hole, the three-layer conductive portion includes a fourth sub-conductive portion, a fifth sub-conductive portion and a sixth sub-conductive portion which is stacked with the fourth sub-conductive portion and the fifth sub-conductive portion, the fourth sub-conductive portion is located between the fifth sub-conductive portion and the plurality of data lines, the data lines are arranged in the same layer as the fourth sub-conductive portion, the fifth sub-conductive portion is arranged in the same layer as the second connecting trace, and the second connecting trace and the third connecting trace are both connected to the fifth sub-conductive portion.

14. The array substrate according to claim 5, wherein: One of the first fan-out routing and the second fan-out routing is disposed at the same layer as the plurality of data lines, and the other of the first fan-out routing and the second fan-out routing is disposed at the same layer as the plurality of gate lines.

15. The array substrate according to claim 7, wherein: The second connecting wiring and the third connecting wiring are both arranged on the same layer as the plurality of gate lines.

16. The array substrate according to claim 3, wherein: The mth data line is electrically connected to the (m+N / 2)th data line via a second connecting line located in the second non-display area, the second electrostatic release structure is connected to the second adapter via a third connecting line, and the third connecting line and the second connecting line are located in different layers.

17. The array substrate according to claim 3, further comprising: The detection signal line and the switch component are located in the second non-display area, The detection signal line and the switch component are both located on a side of the second electrostatic release structure away from the display area, and the detection signal line is connected to the second electrostatic release structure through the switch component.

18. The array substrate according to any one of claims 1 to 4, wherein: N is 12, and the multiple gate lines include first gate lines and second gate lines alternately arranged along the second direction, six columns of sub-pixels electrically connected to the first data line to the sixth data line in the same data line group are electrically connected to the first gate line, and six columns of sub-pixels electrically connected to the seventh data line to the twelfth data line in the same data line group are electrically connected to the second gate line.

19. The array substrate according to any one of claims 1 to 4, wherein: At least one gate line is provided with a plurality of curved portions, wherein the plurality of curved portions include a plurality of first curved portions and a plurality of second curved portions alternately arranged along the first direction, and the orientation of the first curved portions is opposite to the orientation of the second curved portions; Each sub-pixel includes a transistor, and each bent portion surrounds the transistor in N sub-pixels electrically connected to one data line group.

20. An array substrate, comprising a display area and a first non-display area and a second non-display area respectively located on both sides of the display area, the array substrate comprising: A plurality of sub-pixels are located in the display area; A plurality of data lines are located in the display area, and the plurality of data lines are arranged along a first direction; A plurality of gate lines are located in the display area, the plurality of gate lines are arranged along a second direction, a gate line pair formed by two gate lines is arranged between two adjacent sub-pixels arranged along the second direction, and the first direction intersects the second direction; a plurality of fan-out wirings, located in the first non-display area, the plurality of fan-out wirings being configured to be electrically connected to the plurality of data lines, The plurality of data lines include a plurality of data line groups arranged along the first direction, each data line group includes N data lines, and in each data line group, the mth data line is electrically connected to the (m+N / 2)th data line, where m is a positive integer not greater than N / 2; The array substrate also includes an electrostatic release structure located in the second non-display area, the multiple data lines are electrically connected to the electrostatic release structure through multiple transition parts, the electrostatic release structure is located on a side of the transition part away from the multiple data lines, and in at least one data line group, the number of transition parts through which the mth data line is electrically connected to the electrostatic release structure is the same as the number of transition parts through which the (m+N / 2)th data line is electrically connected to the electrostatic release structure.

21. The array substrate according to claim 20, wherein: Each adapter portion includes at least two adapter holes. In the at least one data line group, the number of the adapter holes through which the mth data line is electrically connected to the electrostatic release structure is the same as the number of the adapter holes through which the (m+N / 2)th data line is electrically connected to the electrostatic release structure.

22. The array substrate according to claim 20 or 21, wherein: The mth data line is electrically connected to the (m+N / 2)th data line via a first sub-connection line located in the second non-display area, the electrostatic release structure is connected to the transfer portion via a second sub-connection line, and the first sub-connection line and the second sub-connection line are arranged on the same layer.

23. The array substrate according to claim 22, wherein: The first sub-connection wiring and the second sub-connection wiring are both arranged in the same layer as the gate line.

24. A display device comprising the array substrate according to any one of claims 1 to 23.

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