Chip layout splicing method, device, equipment and storage medium

Abstract

The application discloses a chip layout splicing method and device, equipment and a storage medium, and relates to the technical field of lithography simulation. The chip layout splicing method comprises the following steps: acquiring the size of a single pixel point of a chip layout; determining the mask optimization size of each sub-layout according to the size of a single pixel point and the memory size of an image processor, wherein each sub-layout is a plurality of local layouts obtained by cutting the chip layout; determining the redundancy size of each sub-layout according to the size of a single pixel point and the preset redundancy pixel point range of the sub-layout; and determining the splicing range when each sub-layout is spliced into the chip layout according to the mask optimization size and the redundancy size. The chip layout splicing method provided in the application can improve the accuracy of the splicing range of the sub-layout.

Description

Technical Field

[0001] The present application belongs to the field of photolithography simulation technology, and in particular relates to a chip layout splicing method, device, equipment and storage medium. Background Art

[0002] To overcome the distortion of mask imaging caused by the optical proximity effect, mask optimization technology is required to optimize the mask pattern. During the mask optimization process, the original layout needs to be cut, and then the cut sub-layouts are processed in parallel. After processing, they are spliced ​​together to obtain the optimized mask pattern.

[0003] In the existing methods, different attempts are made manually on the splicing range of the sub-layouts to obtain the most accurate splicing range of the sub-layouts.

[0004] However, this method cannot quantitatively calculate the splicing range of the sub-layout, resulting in poor accuracy of the splicing range. Summary of the Invention

[0005] The embodiments of the present application provide a chip layout splicing method, device, equipment and storage medium, which can improve the accuracy of the sub-layout splicing range.

[0006] In one aspect of an embodiment of the present application, a chip layout splicing method is provided, comprising:

[0007] Get the size of a single pixel of the chip layout;

[0008] Determine the optimal mask size for each sub-layout based on the size of a single pixel and the memory size of the image processor. Each sub-layout is a multiple local layout obtained by cutting the chip layout.

[0009] Determine the redundant size of each sub-layout based on the size of a single pixel and the redundant pixel range preset in the sub-layout;

[0010] Based on the optimized mask size and redundant size, the splicing range of each sub-layout when splicing into the chip layout is determined.

[0011] In one aspect of an embodiment of the present application, a chip layout splicing device is provided, comprising:

[0012] The size acquisition module is used to obtain the size of a single pixel of the chip layout;

[0013] The size calculation module is used to determine the optimal mask size of each sub-layout based on the size of a single pixel and the memory size of the image processor. Each sub-layout is a multiple local layout obtained by cutting the chip layout;

[0014] The size calculation module is further used to determine the redundant size of each sub-layout based on the size of a single pixel and the redundant pixel range preset in the sub-layout;

[0015] The range determination module is used to determine the splicing range of each sub-layout when splicing into a chip layout based on the mask optimization size and redundant size.

[0016] In one aspect of an embodiment of the present application, an electronic device is provided, which includes: a memory and a program or instruction stored in the memory and executable on a processor, wherein when the program or instruction is executed by the processor, a chip layout splicing method as provided in any one aspect of the above-mentioned embodiment of the present application is implemented.

[0017] In one aspect of an embodiment of the present application, a readable storage medium is provided, on which a program or instruction is stored. When the program or instruction is executed by a processor, a chip layout splicing method as provided in any aspect of the above-mentioned embodiment of the present application is implemented.

[0018] In one aspect of an embodiment of the present application, a computer program product is provided. When the instructions in the computer program product are executed by a processor of an electronic device, the electronic device executes the chip layout splicing method provided in any aspect of the above-mentioned embodiment of the present application.

[0019] In the chip layout splicing method provided in the embodiment of the present application, the mask optimization size of the sub-layout can be accurately calculated based on the single pixel size of the chip layout and the memory size of the image processor; at the same time, the redundant size of the sub-layout can be accurately calculated based on the single pixel size of the chip layout and the preset redundant pixel range. Finally, based on the mask optimization size and the redundant size, the splicing range when the sub-layout is spliced ​​into the chip layout can be determined. In this way, the embodiment of the present application realizes the quantification of the mask optimization size and the redundant size of the sub-layout based on the single pixel size and the corresponding pixel range, so that the splicing range of the sub-layout can be accurately determined based on the mask optimization size and the redundant size, which can improve the accuracy of the sub-layout splicing range. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0021] Figure 1 This is a flow chart of a chip layout splicing method provided by one embodiment of the present application;

[0022] Figure 2 This is a schematic diagram of a process for performing mask optimization on a chip layout according to an embodiment of the present application;

[0023] Figure 3 This is a schematic diagram of the splicing range of the sub-layout provided in one embodiment of the present application;

[0024] Figure 4 This is a schematic structural diagram of a chip layout splicing device provided by one embodiment of the present application;

[0025] Figure 5 It is a structural diagram of a chip layout splicing device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0026] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is merely to provide a better understanding of the present application by illustrating the examples of the present application.

[0027] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, the elements defined by the phrase "comprising..." do not exclude the presence of other identical elements in the process, method, article, or device comprising the elements.

[0028] It should be noted that the acquisition, storage, use, and processing of data in the technical solution of this application comply with the relevant provisions of national laws and regulations.

[0029] It should be noted that in the embodiments of the present application, certain software, components, models and other existing solutions in the industry may be mentioned. They should be regarded as exemplary. Their purpose is only to illustrate the feasibility of implementing the technical solution of the present application, but it does not mean that the applicant has or will necessarily use the solution.

[0030] Existing methods rely on manual attempts to determine the most accurate sub-layout splicing range. However, this method cannot quantitatively calculate the sub-layout splicing range, resulting in poor splicing range accuracy.

[0031] The purpose of the present application is to provide a chip layout splicing method, device, equipment and storage medium. In the chip layout splicing method provided in the embodiment of the present application, the mask optimization size of the sub-layout can be accurately calculated according to the single pixel size of the chip layout and the memory size of the image processor; at the same time, the redundant size of the sub-layout can be accurately calculated according to the single pixel size of the chip layout and the preset redundant pixel range. Finally, according to the mask optimization size and the redundant size, the splicing range when the sub-layout is spliced ​​into the chip layout can be determined. In this way, the embodiment of the present application realizes the quantification of the mask optimization size and the redundant size of the sub-layout based on the single pixel size and the corresponding pixel range, so that the splicing range of the sub-layout can be accurately determined according to the mask optimization size and the redundant size, which can improve the accuracy of the sub-layout splicing range.

[0032] The following describes specific embodiments of the chip layout splicing method, device, equipment, and storage medium provided by the embodiments of the present application.

[0033] Figure 1 A schematic flow chart of a chip layout splicing method is provided. The chip layout splicing method can be applied to a server. The chip layout splicing method can include the following steps S101 to S104.

[0034] S101, obtaining the size of a single pixel of the chip layout.

[0035] In this embodiment, the size of a single pixel of the chip layout may be preset or calculated.

[0036] S102, determining the optimal mask size of each sub-layout according to the size of a single pixel and the memory size of the image processor, where each sub-layout is a local layout obtained by cutting the chip layout.

[0037] In this embodiment, the maximum sub-layout size that can be processed simultaneously can be determined based on the memory size of the image processor. For example, if the image processor has limited memory, it may be necessary to cut the chip layout into smaller sub-layouts for processing.

[0038] The mask optimization size is used to characterize the size of a single sub-layout for mask optimization. For example, Figure 2, a schematic diagram of a chip layout mask optimization process is provided. Due to hardware resource limitations, mask optimization cannot be performed directly on the entire chip layout. Therefore, prior to optimization, the original chip layout 210 must be segmented to obtain multiple sub-layouts 220. Mask optimization is then performed on each segmented sub-layout 220 in parallel to obtain a processed mask sub-layout 230. Finally, each processed mask sub-layout 230 is spliced ​​together to obtain the final optimized mask processing layout 240.

[0039] As an example, the server matches the resolution of the sub-layout in the chip layout based on the memory size of the image processor. The sub-layout resolution is then multiplied by the size of a single pixel to calculate the optimized mask size of the sub-layout.

[0040] S103: Determine the redundant size of each sub-layout according to the size of a single pixel and the redundant pixel range preset in the sub-layout.

[0041] In this embodiment, in order to ensure Figure 2 The accuracy of the sub-layouts that are ultimately stitched together into the entire chip layout requires sufficient overlap for precise alignment and correction. Therefore, a redundancy range is typically set at the boundaries of the sub-layouts being optimized for mask processing. The size of this redundancy range is determined by the redundancy size of the sub-layouts.

[0042] The redundant pixel range is used to represent the number of pixels in the redundant range corresponding to each side of the sub-pattern.

[0043] As an example, the server presets a redundant pixel range based on the expected stitching accuracy of the sub-layout. The redundant size of the sub-layout is then calculated based on the redundant pixel range and the size of a single pixel. For example, assuming the redundant pixel range is 50 pixels per side and the size of a single pixel is 0.009754mm, the redundant size is 50*0.009754mm=0.4877mm.

[0044] S104 , determining a splicing range when the sub-layouts are spliced ​​into a chip layout based on the optimized mask size and the redundant size.

[0045] In this embodiment, the server determines the sub-layout's redundancy range settings based on the overall chip layout and the sub-layout's placement within the chip layout. Then, based on the sub-layout's redundancy range settings and the optimized mask size and redundancy size, the server determines the splicing range when the sub-layouts are spliced ​​into the chip layout.

[0046] For example, if a sub-layout is located at the upper left corner of the chip layout, a redundant range can be set only on the right and bottom edges of the sub-layout. This means that redundant ranges only need to be set on one side, both horizontally and vertically. The size of the redundant range can then be calculated based on the redundant size, and the size of the sub-layout's mask optimization range can be calculated based on the mask optimization size. Finally, the size of the redundant range is subtracted from the size of the mask optimization range to determine the splicing range when the sub-layout is spliced ​​into the chip layout.

[0047] In the chip layout splicing method provided in this embodiment, the mask optimization size of the sub-layout can be accurately calculated based on the single pixel size of the chip layout and the memory size of the image processor; at the same time, the redundant size of the sub-layout can be accurately calculated based on the single pixel size of the chip layout and the preset redundant pixel range. Finally, based on the mask optimization size and the redundant size, the splicing range when the sub-layout is spliced ​​into the chip layout can be determined. In this way, the embodiment of the present application realizes the quantification of the mask optimization size and the redundant size of the sub-layout based on the single pixel size and the corresponding pixel range, so that the splicing range of the sub-layout can be accurately determined based on the mask optimization size and the redundant size, which can improve the accuracy of the sub-layout splicing range.

[0048] As an optional embodiment, S101 may specifically include:

[0049] Obtain the wavelength of the lithography machine light source and the numerical aperture of the lithography machine projection lens corresponding to the chip layout;

[0050] Calculate the size of a single pixel on the chip layout based on the wavelength and numerical aperture.

[0051] In this embodiment, the wavelength of the lithography machine light source generally depends on the type of light source used. Different types of lithography machines use light sources of different wavelengths. For example, light source types mainly include ultraviolet light source (UV), deep ultraviolet light source (DUV) and extreme ultraviolet light source (EUV).

[0052] The numerical aperture (NA) usually depends on the model of the lithography machine used. The numerical aperture is an important parameter that describes the light-collecting ability and spatial resolution of the lens. The larger the value, the higher the resolution.

[0053] For example, the server determines the wavelength of the light source used by the lithography machine based on its type. It then determines the numerical aperture of the projection lens based on the lithography machine model. Finally, the wavelength of the light source is divided by the numerical aperture of the projection lens, and then multiplied by a preset adjustment factor to obtain the size of a single pixel on the chip layout.

[0054] For example, assuming that the wavelength of the light source is 134 nm, the numerical aperture of the projection objective is 0.9, and the preset adjustment coefficient is 0.3, the size of a single pixel of the chip layout is 0.3*134 nm / 0.9=44.67 nm.

[0055] This embodiment accurately calculates the size of a single pixel in a chip layout based on the wavelength of the lithography machine's light source and the numerical aperture of the lithography machine's projection lens. This facilitates the subsequent calculation of the optimal mask size and redundant size based on the individual pixel size, quantifying the optimal mask size and redundant size of the sub-layout, and improving the accuracy of the sub-layout splicing range.

[0056] As an optional embodiment, calculating the size of a single pixel of the chip layout according to the wavelength and the numerical aperture may specifically include:

[0057] Divide the wavelength by the numerical aperture to get the initial size;

[0058] Multiply the initial size by the corresponding preset adjustment coefficient to obtain the size of a single pixel in the chip layout.

[0059] In this embodiment, the size of a single pixel of the chip layout can be determined by the following formula 1:

[0060]

[0061] In the formula, size is used to represent the size of a single pixel in the chip layout, wavelength is used to represent the wavelength of the lithography machine light source, NA is used to represent the numerical aperture of the lithography machine projection lens, and 0.2 is the preset adjustment coefficient.

[0062] The value of the preset adjustment coefficient depends on the difficulty of the photolithography process. The greater the difficulty of the photolithography process, the larger the corresponding preset adjustment coefficient; the smaller the difficulty of the photolithography process, the smaller the corresponding preset adjustment coefficient.

[0063] Among them, the larger the wavelength of the lithography machine light source, the larger the size of a single pixel in the chip layout; the larger the numerical aperture of the lithography machine projection objective lens, the smaller the size of a single pixel in the chip layout.

[0064] This embodiment accurately calculates the size of a single pixel in a chip layout based on the wavelength of the lithography machine's light source, the numerical aperture of the lithography machine's projection lens, and a preset adjustment coefficient. This facilitates the subsequent calculation of the optimal mask size and redundant size based on the individual pixel size, quantifying the optimal mask size and redundant size of the sub-layout, and improving the accuracy of the sub-layout splicing range.

[0065] As an optional embodiment, S102 may specifically include:

[0066] According to the memory size of the image processor, determine the mask pixel range of the chip layout that matches the memory size of the image processor;

[0067] Determine the optimal mask size for each sub-layout based on the size of a single pixel and the range of mask pixels.

[0068] In this embodiment, the mask pixel range is used to represent the number of pixels in the mask optimization range corresponding to each side of the sub-layout. For example, the chip layout and the sub-layout can both be squares, and the mask optimization size of the sub-layout is the corresponding side length of the sub-layout during mask optimization.

[0069] If the image processor has 16GB of memory, the mask optimization range corresponding to the sub-layout is set to 1024 pixels; if the image processor has 32GB of memory, the mask optimization range corresponding to the sub-layout is set to 2048 pixels.

[0070] As an example, if the size of a single pixel is 0.009754mm and the image processor has 16GB of memory, the mask optimization range corresponding to the sub-layout is determined to be 1024 pixels based on the memory size of the image processor. Therefore, the optimized mask size of the sub-layout can be calculated as 0.009754mm*1024=9.988096mm.

[0071] This embodiment determines the chip layout's mask pixel range based on the image processor's memory size, thereby calculating the sub-layout's optimized mask size based on the chip layout's mask pixel range and the size of a single pixel. Thus, this embodiment determines the appropriate sub-layout's optimized mask size based on the image processor's memory size, avoiding the problem of poor sub-layout mask optimization results caused by an unreasonable mask optimization size and improving the effectiveness of sub-layout mask optimization.

[0072] As an optional embodiment, the mask pixel range includes the number of first mask pixels of the chip layout in a first direction and the number of second mask pixels of the chip layout in a second direction, and the first direction is perpendicular to the second direction;

[0073] The number of pixels in the first mask and the number of pixels in the second mask are both equal to 2 to the power of N.

[0074] In this embodiment, the first direction is perpendicular to the second direction. When the first direction is horizontal, the second direction is vertical; when the first direction is vertical, the second direction is horizontal.

[0075] The mask pixel range includes the first mask pixel number of the chip layout in the first direction and the second mask pixel number of the chip layout in the second direction, that is, the mask pixel range includes the mask pixel number corresponding to the length of the rectangle and the mask pixel number corresponding to the width of the rectangle.

[0076] When the chip layout and the sub-layout are both square, the length of the rectangle is equal to the width of the rectangle, that is, the number of pixels in the first mask is equal to the number of pixels in the second mask.

[0077] The number of pixels in the first mask and the number of pixels in the second mask are both equal to 2 to the power of N. That is, the number of pixels in the first mask and the number of pixels in the second mask can be 1024, 2048, 3072, etc., matching the processing size of the image.

[0078] This embodiment accurately determines the optimal mask size for each side of the sub-layout based on the number of mask pixels in both the first and second directions of the chip layout. Simultaneously, the number of first and second mask pixels is set to a power of 2 to match the image processing size, thereby facilitating image processing and calculations and improving resource utilization efficiency.

[0079] As an optional embodiment, S104 may specifically include:

[0080] Determine the sub-layout splicing size based on the mask optimization size and redundant size;

[0081] According to the stitching size, determine the stitching range of each sub-layout when stitching into the chip layout.

[0082] In this embodiment, the server determines the sub-layout's redundancy range settings based on the overall chip layout and the sub-layout's placement within the chip layout. Then, using the sub-layout's redundancy range settings, the server determines the splicing dimensions for the chip layout based on the optimized mask size and the redundancy dimensions. Finally, based on the sub-layout's splicing dimensions, the server determines the splicing range for the chip layout.

[0083] For example, when the sub-layout is the upper leftmost edge of the chip layout, a redundant range can be set only on the right and bottom boundaries of the sub-layout, that is, a redundant range only needs to be set on one side in both the horizontal and vertical directions.

[0084] Then, in the horizontal direction, the mask optimization size is subtracted by a redundant size to obtain the horizontal splicing size; in the vertical direction, the mask optimization size is subtracted by a redundant size to obtain the vertical splicing size.

[0085] Finally, multiply the horizontal stitching size by the vertical stitching size to get the stitching range when the sub-layouts are stitched into the chip layout.

[0086] This embodiment determines the sub-layout splicing size based on the optimized mask size and the redundant size. Finally, based on the sub-layout splicing size, the splicing range when the sub-layouts are spliced ​​into the chip layout can be calculated. Thus, this embodiment quantifies the sub-layout splicing size based on the optimized mask size and the redundant size, thereby improving the accuracy of the sub-layout splicing range.

[0087] As an optional embodiment, determining the splicing size of the sub-layouts according to the optimized mask size and the redundant size specifically includes:

[0088] Subtract twice the corresponding redundant size from the mask optimization size to obtain the splicing size of the chip layout.

[0089] In this embodiment, to ensure the accuracy of the sub-layout splicing and avoid missing sub-layouts, a redundant range can be set at each boundary of the sub-layout processed by the mask optimization process. That is, no matter where the sub-layout is located in the chip layout, a redundant range is set around it.

[0090] like Figure 3 As shown in the figure, a schematic diagram of the splicing range of the sub-layout is provided. It can be seen that the sub-layout with mask optimization processing Figure 4 A redundancy range is set for each week. The sub-layout is a square, with D1 representing the stitching size, D2 representing the mask optimization size, and D3 representing the redundancy size. Therefore, when the server calculates the stitching size D1 of the chip layout, it needs to subtract twice the corresponding redundancy size D3 from the mask optimization size D2.

[0091] Through this embodiment, a redundant range is set at each boundary of the sub-layout processed by mask optimization, which can ensure the accuracy of the sub-layout splicing. Then, the mask optimization size is subtracted from twice the corresponding redundant size to accurately determine the splicing size of the chip layout. In this way, the embodiment of the present application quantifies the splicing size of the sub-layout based on the mask optimization size and the redundant size, thereby improving the accuracy of the sub-layout splicing range.

[0092] Chip layout-based splicing method. Accordingly, the present application also provides a specific embodiment of a chip layout splicing device.

[0093] like Figure 4 As shown, the chip layout splicing device 400 provided in the embodiment of the present application includes a size acquisition module 410 , a size calculation module 420 and a range determination module 430 .

[0094] The size acquisition module 410 is used to obtain the size of a single pixel of the chip layout;

[0095] A size calculation module 420 is used to determine the optimal mask size for each sub-layout based on the size of a single pixel and the memory size of the image processor. Each sub-layout is a plurality of local layouts obtained by cutting the chip layout.

[0096] The size calculation module 420 is further configured to determine the redundant size of each sub-layout based on the size of a single pixel and a preset redundant pixel range of the sub-layout;

[0097] The range determination module 430 is used to determine the splicing range of each sub-layout when splicing the sub-layout into the chip layout according to the mask optimization size and the redundant size.

[0098] In the chip layout splicing device provided in the embodiment of the present application, the mask optimization size of the sub-layout can be accurately calculated based on the single pixel size of the chip layout and the memory size of the image processor; at the same time, the redundant size of the sub-layout can be accurately calculated based on the single pixel size of the chip layout and the preset redundant pixel range. Finally, based on the mask optimization size and the redundant size, the splicing range when the sub-layout is spliced ​​into the chip layout can be determined. In this way, the embodiment of the present application realizes the quantification of the mask optimization size and the redundant size of the sub-layout based on the single pixel size and the corresponding pixel range, so that the splicing range of the sub-layout can be accurately determined based on the mask optimization size and the redundant size, which can improve the accuracy of the sub-layout splicing range.

[0099] As an optional embodiment, the size acquisition module 410 specifically includes the following units:

[0100] A parameter acquisition unit, used to obtain the wavelength of the lithography machine light source and the numerical aperture of the lithography machine projection lens corresponding to the chip layout;

[0101] The pixel size calculation unit is used to calculate the size of a single pixel of the chip layout according to the wavelength and numerical aperture.

[0102] As an optional embodiment, the size calculation unit is specifically configured to:

[0103] Divide the wavelength by the numerical aperture to get the initial size;

[0104] Multiply the initial size by the corresponding preset adjustment coefficient to obtain the size of a single pixel in the chip layout.

[0105] As an optional embodiment, the size calculation module 420 specifically includes the following units:

[0106] A pixel range determination unit, configured to determine, based on the memory size of the image processor, a mask pixel range of the chip layout that matches the memory size of the image processor;

[0107] The mask size determination unit is used to determine the optimized mask size of each sub-layout according to the size of a single pixel and the range of mask pixels.

[0108] As an optional embodiment, the range determination module 430 specifically includes the following units:

[0109] A splicing size determination unit, configured to determine the splicing size of the sub-layout according to the mask optimization size and the redundant size;

[0110] The splicing range determining unit is used to determine the splicing range of each sub-layout when splicing into a chip layout according to the splicing size.

[0111] As an optional embodiment, the splicing size determining unit is specifically configured to:

[0112] Subtract twice the corresponding redundant size from the mask optimization size to obtain the splicing size of the chip layout.

[0113] Chip layout-based splicing method. Accordingly, the present application also provides a specific embodiment of a chip layout splicing device.

[0114] Figure 5 A schematic diagram of the hardware structure of a chip layout splicing device provided in an embodiment of the present application is shown.

[0115] The chip layout stitching device may include a processor 501 and a memory 502 storing computer program instructions.

[0116] Specifically, the processor 501 may include a central processing unit (CPU), or an application-specific integrated circuit (ASIC), or may be configured to implement one or more integrated circuits of the embodiments of the present application.

[0117] The memory 502 may include a large capacity memory for data or instructions. By way of example and not limitation, the memory 502 may include a hard disk drive (HDD), a floppy disk drive, a flash memory, an optical disk, a magneto-optical disk, a magnetic tape, or a universal serial bus (USB) drive, or a combination of two or more of these. Where appropriate, the memory 502 may include removable or non-removable (or fixed) media. Where appropriate, the memory 502 may be inside or outside the integrated gateway disaster recovery device. In a specific embodiment, the memory 502 is a non-volatile solid-state memory.

[0118] The processor 501 reads and executes computer program instructions stored in the memory 502 to implement any chip layout splicing method in the above embodiments.

[0119] In one example, the chip layout splicing device may further include a communication interface 503 and a bus 510. Figure 5 As shown, the processor 501, the memory 502, and the communication interface 503 are connected via a bus 510 and communicate with each other.

[0120] The communication interface 503 is mainly used to implement communication between various modules, devices, units and / or equipment in the embodiments of the present application.

[0121] Bus 510 includes hardware, software or both, couples the parts of the splicing equipment of chip layout to each other.For example, and not limitation, bus may include accelerated graphics port (AGP) or other graphics bus, enhanced industry standard architecture (EISA) bus, front side bus (FSB), hypertransport (HT) interconnection, industry standard architecture (ISA) bus, infinite bandwidth interconnection, low pin count (LPC) bus, memory bus, micro channel architecture (MCA) bus, peripheral component interconnection (PCI) bus, PCI-Express (PCI-X) bus, serial advanced technology attachment (SATA) bus, video electronics standard association local (VLB) bus or other suitable bus or two or more of these combinations. In appropriate cases, bus 510 may include one or more buses. Although the present application embodiment describes and shows specific bus, the application considers any suitable bus or interconnection.

[0122] In addition, in conjunction with the chip layout splicing method in the above embodiments, embodiments of the present application may provide a computer storage medium for implementation. The computer storage medium stores computer program instructions; when the computer program instructions are executed by a processor, any of the chip layout splicing methods in the above embodiments is implemented.

[0123] In addition, in combination with the chip layout splicing method in the above embodiments, the embodiments of the present application can provide a computer program product to implement, and the instructions in the computer program product are executed by the processor of the electronic device, so that the electronic device executes the chip layout splicing method provided by any one of the above embodiments of the present application.

[0124] It should be noted that the present application is not limited to the specific configurations and processes described above and shown in the drawings. For the sake of brevity, detailed descriptions of well-known methods are omitted. In the above embodiments, several specific steps are described and shown as examples. However, the method processes of the present application are not limited to the specific steps described and shown, and those skilled in the art can make various changes, modifications and additions, or change the order of the steps, after understanding the spirit of the present application.

[0125] The functional blocks shown in the structural block diagrams described above can be implemented as hardware, software, firmware or a combination thereof. When implemented in hardware, it can be, for example, an electronic circuit, an application specific integrated circuit (ASIC), appropriate firmware, a plug-in, a functional card, etc. When implemented in software, the elements of the present application are program or code segments used to perform the required tasks. The program or code segments can be stored in a machine-readable medium or transmitted through a data signal carried in a carrier wave over a transmission medium or communication link. The "machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, optical fiber media, radio frequency (RF) links, etc. The code segments can be downloaded via a computer network such as the Internet, an intranet, etc.

[0126] It should also be noted that the exemplary embodiments mentioned in the present application describe some methods or systems based on a series of steps or devices. However, the present application is not limited to the order of the above steps, that is, the steps can be executed in the order mentioned in the embodiments, or in an order different from the embodiments, or several steps can be executed simultaneously.

[0127] Aspects of the present disclosure have been described above with reference to the flowcharts and / or block diagrams of the methods, devices (systems) and computer program products according to the embodiments of the present disclosure. It should be understood that each box in the flowchart and / or block diagram and the combination of each box in the flowchart and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer or other programmable data processing device to produce a machine so that these instructions executed by the processor of the computer or other programmable data processing device enable the implementation of the function / action specified in one or more boxes of the flowchart and / or block diagram. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor or a field programmable logic circuit. It is also understood that each box in the block diagram and / or flowchart and the combination of the boxes in the block diagram and / or flowchart can also be implemented by dedicated hardware that performs the specified function or action, or can be implemented by a combination of dedicated hardware and computer instructions.

[0128] The above description is only a specific embodiment of the present application. Those skilled in the art will clearly understand that for the convenience and brevity of description, the specific working processes of the systems, modules and units described above can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here. It should be understood that the scope of protection of the present application is not limited thereto. Any person skilled in the art can easily think of various equivalent modifications or replacements within the technical scope disclosed in the present application, and these modifications or replacements should be included in the scope of protection of the present application.

Claims

1. A chip layout splicing method, characterized in that: The method is applied to an image processor and includes: Get the size of a single pixel of the chip layout; Determining the optimal mask size of each sub-layout according to the size of the single pixel and the memory size of the image processor, where each sub-layout is a plurality of local layouts obtained by cutting the chip layout; Determining the redundant size of each of the sub-layouts according to the single pixel size and the redundant pixel range preset in the sub-layout; The splicing range of each of the sub-layouts when splicing the chip layout is determined according to the optimized mask size and the redundant size.

2. The method according to claim 1, characterized in that The obtaining of the size of a single pixel of the chip layout includes: Obtaining the wavelength of the lithography machine light source and the numerical aperture of the lithography machine projection lens corresponding to the chip layout; The size of a single pixel of the chip layout is calculated according to the wavelength and the numerical aperture.

3. The method according to claim 2, characterized in that Calculating the size of a single pixel of the chip layout according to the wavelength and the numerical aperture includes: Dividing the wavelength by the numerical aperture to obtain an initial size; The initial size is multiplied by the corresponding preset adjustment coefficient to obtain the size of a single pixel of the chip layout.

4. The method according to claim 1, wherein Determining the optimized mask size of each sub-layout according to the single pixel size and the memory size of the image processor includes: Determining, according to the memory size of the image processor, a mask pixel range of the chip layout that matches the memory size of the image processor; The optimized mask size of each sub-layout is determined according to the single pixel size and the mask pixel range.

5. The method according to claim 4, characterized in that The mask pixel range includes the number of first mask pixels of the chip layout in a first direction and the number of second mask pixels of the chip layout in a second direction, wherein the first direction is perpendicular to the second direction; The number of pixels in the first mask and the number of pixels in the second mask are both equal to 2 to the power of N.

6. The method according to any one of claims 1 to 5, characterized in that The step of determining a splicing range when splicing the sub-layouts into the chip layout according to the optimized mask size and the redundant size includes: Determining a splicing size of the sub-layout according to the optimized mask size and the redundant size; According to the splicing size, a splicing range of each of the sub-layouts when splicing into the chip layout is determined.

7. The method according to claim 6, characterized in that The step of determining the splicing size of the sub-layout according to the optimized mask size and the redundant size includes: The mask optimization size is subtracted by twice the corresponding redundant size to obtain the splicing size of the chip layout.

8. A chip layout splicing device, characterized in that: The device is applied to an image processor, and includes: The size acquisition module is used to obtain the size of a single pixel of the chip layout; A size calculation module, configured to determine the optimal mask size of each sub-layout based on the size of a single pixel and the memory size of the image processor, wherein each sub-layout is a plurality of local layouts obtained by cutting the chip layout; The size calculation module is further configured to determine the redundant size of each of the sub-layouts based on the size of the single pixel and the redundant pixel range preset in the sub-layout; The range determination module is used to determine the splicing range when each of the sub-layouts is spliced ​​into the chip layout according to the mask optimization size and the redundant size.

9. An electronic device, characterized in that: The device includes: a processor and a memory storing computer program instructions; When the processor executes the computer program instructions, the chip layout splicing method according to any one of claims 1 to 7 is implemented.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer program instructions, and when the computer program instructions are executed by a processor, the chip layout splicing method according to any one of claims 1 to 7 is implemented.

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