Implementation method of high-speed DDS in radio frequency scene

Abstract

The invention belongs to the field of wireless communication, and provides a method for realizing a high-speed DDS (Direct Digital Synthesizer) in a radio frequency scene, which comprises the steps of double sine and cosine function lookup table construction, 16-bit phase input signal collection and splitting, reverse processing, radian system conversion, 14-bit radian value splitting, discrimination parameter acquisition, Taylor series interpolation and post-processing. According to the invention, through the double sine and cosine function lookup table, addend items of shift addition are reduced, and the operation speed of the system is improved; by replacing a multiplier with shift addition, the operation speed of the system is further improved; and through Taylor series interpolation, the scale of the double sine and cosine function lookup table is reduced, and the bandwidth occupation is reduced.

Description

Technical Field

[0001] The present invention relates to the field of wireless communications, and in particular to a method for implementing a high-speed DDS in a radio frequency scenario. Background Art

[0002] Direct frequency synthesizer is abbreviated as DDS, which is an important tool for signal processing. It is widely used in RF scenarios in the field of wireless communications. Traditional DDS implementation methods mainly use hardware methods based on lookup tables or cordic algorithms or software methods based on CPU calculations. Software implementation methods have higher accuracy, but the running speed is relatively low.

[0003] High-speed DDS in RF scenarios usually uses a hardware method based on a lookup table. The output spectrum purity of a DDS based on a lookup table is proportional to the size of the dual sine and cosine function lookup table. Using an interpolation algorithm can reduce the size of the sine and cosine function lookup table, but it will introduce multipliers, thereby increasing system complexity and slowing down system operation. Summary of the invention

[0004] In order to overcome the shortcomings of the prior art, the purpose of the present invention is to provide a method for implementing high-speed DDS in a radio frequency scenario, by reducing the addends of shift addition through a dual sine-cosine function lookup table and improving the system's operating speed; by using shift addition instead of a multiplier, the system's operating speed is improved; by Taylor series interpolation, the scale of the dual sine-cosine function lookup table is reduced and the bandwidth occupancy is reduced.

[0005] To achieve the above object, the present invention provides the following solutions:

[0006] A method for implementing high-speed DDS in a radio frequency scenario, comprising:

[0007] Constructing a double sine-cosine function lookup table; the radian range of the double sine-cosine function lookup table is 0 to π / 4;

[0008] Collecting a 16-bit phase input signal, splitting the upper 3 bits and lower 13 bits of the 16-bit phase input signal respectively to obtain an interval signal and an index signal;

[0009] Reverse the index signal corresponding to the interval signal having the lowest bit being 1;

[0010] Using 4 shift additions, the index signal corresponding to the lowest bit of the interval signal being 0 or the index signal completed in reverse order is converted into radians and the lowest 2 bits are discarded to obtain a 14-bit radian value;

[0011] The upper 5 bits and the lower 9 bits of the 14-bit radian value are split to obtain a main radian interval and an interval to be interpolated;

[0012] Calculate the number of 1s in the lower 9 bits of the 14-bit radian value to obtain a discrimination parameter;

[0013] According to the discrimination parameter, Taylor series interpolation is performed on the highest bit, the second highest bit and the lower 7 bits of the interval to be interpolated in sequence by using 4-term shift addition to obtain an unsigned sin / cos value;

[0014] The unsigned sin / cos value is post-processed according to the interval signal to obtain a target DDS output; the post-processing includes: any one of no operation, negation and exchange.

[0015] Preferably, the interpolation formula of the Taylor series interpolation is:

[0016] sin(θ)=sin(θ i )+cos(θ i )·β;

[0017] in, Look up two consecutive phases in the double sine-cosine function table; is the least significant bit of the preset phase accumulator output; M is θ i to θ i+1 The binary resolution of the interpolation points.

[0018] Preferably, the calculation formula of the 14-bit radian value is:

[0019] phi_rad=(phase_inv<<4)+(phase_inv<<2)+(phase_inv>>2)+(phase_inv>>5)+1;

[0020] Among them, phi_rad is the 14-bit radian value; phase_inv is the index signal corresponding to the lowest bit of the interval signal being 0 or the index signal completed in reverse order; << is the left shift symbol; >> is the right shift symbol.

[0021] The present invention discloses the following technical effects:

[0022] The present invention provides a method for realizing high-speed DDS in a radio frequency scenario. By using a double sine-cosine function lookup table, the problem of too many addends in conventional technology is solved, and the reduction of addends is achieved. By using shift addition, the problem of complex multiplier design and slow speed in conventional technology is solved, and the function of realizing multiplication by using shift addition is achieved. By using Taylor series interpolation, the problem of large scale and slow indexing speed of conventional lookup tables is solved, and the reduction of the scale of the lookup tables is achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0024] Figure 1 A schematic diagram of the implementation process of high-speed DDS in a radio frequency scenario provided by an embodiment of the present invention;

[0025] Figure 2 A schematic diagram of a dual search provided by an embodiment of the present invention;

[0026] Figure 3 A schematic diagram of simulation results provided by an embodiment of the present invention, Figure 3 (a) is a schematic diagram of the DDS comprehensive simulation results achieved by the improved method. Figure 3 (b) Schematic diagram of DDS comprehensive simulation results achieved using traditional methods. DETAILED DESCRIPTION

[0027] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0028] The purpose of the present invention is to provide a method for realizing high-speed DDS in a radio frequency scenario, by reducing the addend items of shift addition through a dual sine-cosine function lookup table, and improving the operation speed of the system; by using shift addition instead of a multiplier, the operation speed of the system is improved; by Taylor series interpolation, the scale of the dual sine-cosine function lookup table is reduced, and the bandwidth occupancy is reduced.

[0029] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0030] Figure 1 A schematic diagram of the implementation process of high-speed DDS in a radio frequency scenario provided by an embodiment of the present invention is shown in FIG. Figure 1 As shown, the present invention provides a method for implementing high-speed DDS in a radio frequency scenario, including:

[0031] Step 100: construct a double sine-cosine function lookup table; the radian range of the double sine-cosine function lookup table is 0 to π / 4;

[0032] Step 200: Collect a 16-bit phase input signal, and split the upper 3 bits and lower 13 bits of the 16-bit phase input signal to obtain an interval signal and an index signal;

[0033] Step 300: Reverse the index signal corresponding to the interval signal with the lowest bit being 1;

[0034] Step 400: using 4-term shift addition to convert the index signal corresponding to the interval signal with the lowest bit of 0 or the index signal completed in reverse order into radians and discard the lowest 2 bits to obtain a 14-bit radian value;

[0035] Step 500: Split the upper 5 bits and lower 9 bits of the 14-bit radian value to obtain a main radian interval and an interval to be interpolated;

[0036] Step 600: Calculate the number of 1s in the lower 9 bits of the 14-bit radian value to obtain a discrimination parameter;

[0037] Step 700: According to the discrimination parameter, Taylor series interpolation is performed on the highest bit, the second highest bit and the lower 7 bits of the interval to be interpolated in sequence by using 4-term shift addition to obtain an unsigned sin / cos value;

[0038] Step 800: Post-process the unsigned sin / cos value according to the interval signal to obtain a target DDS output; the post-processing includes: any one of no operation, negation, and exchange.

[0039] Furthermore, the interpolation formula of the Taylor series interpolation is:

[0040] sin(θ)=sin(θi)+cos(θi)·β;

[0041] in, θ i and θ i+1

[0042] Look up two consecutive phases in the table for the double sine-cosine function; is the least significant bit of the preset phase accumulator output; M is θ i to θ i+1 The binary resolution of the interpolation points.

[0043] Specifically, the calculation formula of the 14-bit radian value is:

[0044] phi_rad=(phase_inv<<4)+(phase_inv<<2)+(phase_inv>>2)+(phase_inv>>5)+1;

[0045] Among them, phi_rad is the 14-bit radian value; phase_inv is the index signal corresponding to the lowest bit of the interval signal being 0 or the index signal completed in reverse order; << is the left shift symbol; >> is the right shift symbol.

[0046] Specifically, the DDS phase-to-amplitude conversion is implemented through a lookup table. The phase accuracy is proportional to the address bit width of the lookup table. The use of an interpolation method can reduce the size of the lookup table to save resource consumption under the same accuracy. This embodiment uses an interpolation method based on the Taylor series. This method transforms the phase θ to sin(θ) through a small lookup table. This method not only uses the symmetry of the sinusoidal signal, but also uses linear interpolation for continuous points stored in the lookup table. Every two storage points (θ) in the lookup table are i and θ i+1 )The sine function in the middle can be expressed as:

[0047]

[0048] θ∈[θ i ,θ i+1 ]

[0049] in, θ i and θ i+1 are two corresponding consecutive phases in the lookup table; Represents the phase accumulator output The least significant bit of Indicates the most significant bit of the lookup table address; M indicates θ i to θ i+1 The binary resolution of the interpolation point; α represents the interpolation coefficient of the sine function in the lookup table: α = 2π·cos(θ i ) / 2 M ; δ sin It is the remainder of the Taylor expansion of the sine function. As shown below:

[0050]

[0051] Among them, θ δ ∈[θ i ,θ i+1 ]. Because: sin(θ δ )≤1, so we have:

[0052]

[0053] And because: So |δ sin | max =(θ i+1 -θ i ) 2 / 2, it can be seen that: choose the appropriate lookup table input resolution (θ i to θ i+1 The interval of ), after reaching the required accuracy, the remainder of Taylor expansion can be ignored. Therefore, only the first two terms need to be calculated to achieve interpolation. That is, the interpolation algorithm can be simplified to:

[0054] sin(θ)=sin(θ i )+cos(θ i )·β

[0055]

[0056] Furthermore, in digital design, using shift-add to replace multipliers is a common optimization method. Its principle is based on the properties of binary numbers, especially the relationship between multiplication and shift. The principle of shift-add to implement multiplication:

[0057] Suppose we want to calculate the product of two binary numbers A and B, we can expand B into a sum of a series of powers of 2. For example, the binary number B can be represented as:

[0058] B=b0×2 0 +b1×2 1 +...+b n ×2 n

[0059] Then A×B can be expanded as:

[0060] A×B=A×(b0×2 0 +b1×2 1 +...+b n ×2 n )

[0061] =A×b0×2 0 +A×b1×2 1 +...+A×b n ×2 n

[0062] Due to b i The only possible values ​​are 0 or 1, so each term A×b i ×2 i Either it is 0 or A is shifted left by i bits. Therefore, multiplication can be calculated through a series of shift operations and addition operations. In this way, the complexity of the multiplier can be reduced, especially in hardware design, which can significantly save resources and power consumption.

[0063] Preferably, this embodiment uses shift addition instead of multipliers in the process of converting the input phase to radian values, and this method is also used in the interpolation algorithm based on Taylor series.

[0064] Specifically, this embodiment uses a dual sine-cosine lookup table to reduce the complexity of shift addition. This embodiment needs to perform a 7-bit phase interpolation algorithm in the third-level interpolation calculation. The required shift addition terms require a total of 7 terms. However, if a dual sine-cosine lookup table is used, the addition terms can be reduced to 3 terms, thereby reducing system complexity and improving operating speed. Principle: Taking 3-bit interpolation as an example, explain how the dual lookup table reduces the shift addition terms. Figure 2 As shown: the input phase can get the corresponding lookup table value, lut0 and lut1. The 3-bit interpolation coefficient will give 8 cases of offset under the lookup table result. Using a lookup table will require 3 shift addition items to complete the multiplication operation (maximum interpolation point 111). After using the dual lookup table, use lut0 for the offset operation when the interpolation point is less than 2 1s, and use lut1 for the offset operation after the remaining points are inverted. In this way, the interpolation points processed by each lookup table are only 0 or 1 1 (only 1 addition item is required).

[0065] Further, a sine-cosine function lookup table is constructed. In this embodiment, phi_rad[13:9] is used as the index of the sine-cosine lookup table. The value of phi_rad[13:9] is an integer from 0 to 25, representing the radian. arrive In radians, the decimal part is defined as a signed offset, and the corresponding radians should be: arrive In this way, the interpolation calculation can be completed completely when using a single lookup table, but in this embodiment, shift addition is used instead of a multiplier. In order to simplify the shift addition operation, a double lookup table is used. The index radian definition of the double lookup table is:

[0066] lut0: arrive

[0067] lut1: arrive

[0068] Specifically, the specific implementation method of the present invention is:

[0069] S1: Input phase value compressed to 0 to π / 4 radians:

[0070] The 16-bit phase input signal phase_in[15:0] is unsigned data, ranging from 0 to 65535, corresponding to radians 0 to 2π. According to the symmetry of the sine and cosine functions, the sine and cosine functions corresponding to 0 to 2π radians can be calculated using the sine and cosine functions of 0 to π / 4 radians. Therefore, the sine and cosine function lookup table can be compressed to the phase range of 0 to π / 4 to reduce system consumption. The high 3 bits of phase_in, phase_in[15:13], are intercepted and used to represent 8 (0 to 7) intervals of size π / 4 from 0 to 2π radians. phase_in[12:0] is used as the index phase of the corresponding sine and cosine lookup table.

[0071] S2: The index phase in the π / 4 interval where phase_in

[13] is 1 is reversed:

[0072] The mathematical basis of this step is that 0 to 2π is divided into 8 π / 4 intervals. The sine and cosine functions of the intervals π / 4 to π / 2, 3π / 4 to π, 5π / 4 to 3π / 2, and 7π / 4 to 2π are symmetric with respect to the previous π / 4 intervals (or symmetric after the signs are reversed).

[0073] When phase_in

[13] is 1, it means that the π / 4 interval is an even number and the index phase needs to be in reverse order.

[0074] phase_in[12:0] reverse method:

[0075] If phase_in

[13] == 1: phase_inv = 2 14 -phase_in[12:0];

[0076] if phase_in

[13] == 0: phase_inv = phase_in[12:0];

[0077] S3: Convert the index phase into radians:

[0078] The index phase is converted into a radian value phase using the shift-and-add method to avoid introducing a multiplier.

[0079] phi_rad=(phase_inv<<4)+(phase_inv<<2)+(phase_inv>>2)+(phase_inv>>5)+1;

[0080] This step uses 4 shift-add operations to implement multiplication by 6.28125 (2π), which approximates the result of the operation phase_inv × 2π. If higher precision is required, the shift-addend term can be increased. The obtained phi_rad is output after the lowest two bits are cut off. The output phi_rad is 14 bits, of which the upper 5 bits (phi_rad[13:9]) range from 0 to 26 / 2^32 radians.

[0081] S4: phi_rad[8:0] is a 9-bit binary number. The number of 1s in it is calculated and stored in the register ones_cnt. This step is to simplify the computational complexity of the shift addition that replaces the multiplier.

[0082] S5: Taylor series interpolation of level 1:

[0083] Perform the first-level 1-bit Taylor series interpolation on phi_rad[8], and replace the multiplication with shift addition. Because of the multiplication by 2π, β can be directly represented by the bit of phi_rad to be interpolated, which is phi_rad[8] bit in this step.

[0084] First, determine the value of ones_cnt. If it is less than 4, use the first lookup table in the dual lookup table. Otherwise, use the second lookup table in the dual lookup table. Then, get the interpolation result based on the value of phi_rad[8].

[0085] If phi_rad[8] is 1:

[0086] x1=x0+(y0>>7)

[0087] y1=y0+(x0>>7)

[0088] If phi_rad[8] is 0:

[0089] x1=x0-(y0>>7)

[0090] y1=y0-(x0>>7)

[0091] S6: Taylor series interpolation of level 2:

[0092] Perform the second-order 1-bit Taylor series interpolation on phi_rad[7], same as S5.

[0093] If phi_rad[7] is 1:

[0094] x2=x1+(y1>>8)

[0095] y2=y1+(x1>>8)

[0096] If phi_rad[7] is 0:

[0097] x2=x1-(y1>>8)

[0098] y2=y1-(x1>>8)

[0099] S7: Taylor series interpolation of level 3:

[0100] The third-level 7-bit Taylor series interpolation is performed on phi_rad[6:0], and the principle is the same as S5 or S6. Because a dual lookup table is used, no matter which lookup table is used, the 7-digit binary representation of the interpolation point phi_rad[6:0] only contains less than or equal to 3 1s. Using A, B, C, the 3 items represent the shift number to see if the shift addition calculation can be completed.

[0101] If phi_rad[6] is 1:

[0102] x3=x2+(y2>>A)+(y2>>B)+(y2>>C)

[0103] y3=y2+(x2>>A)+(x2>>B)+(x2>>C)

[0104] If phi_rad[6] is 0:

[0105] x3=x2-(y2>>A)-(y2>>B)-(y2>>C)

[0106] y3=y2-(x2>>A)-(x2>>B)-(x2>>C)

[0107] S8: cos / sin output:

[0108] According to the value of the upper 3 bits of phase_in [15:13], it is selected whether to invert or swap the interpolated sin / cos values ​​obtained in S7, and then output to the final cos / sin signal as the final output of this DDS.

[0109] refer to Figure 3 (a) and Figure 3(b), DesignWNS represents the worst negative margin; TNS represents the sum of margins of all paths that do not meet the timing requirements; Number of Violating Paths, represents the number of paths that do not meet the timing requirements; in the initial synthesis stage, only the parameter Number of Violating Paths needs to be paid attention to. Effect display: After synthesis under the same timing constraints using the asic synthesis tool, the number of paths that do not meet the timing requirements of the DDS design implemented by this method after synthesis is 0, while the number of paths that do not meet the timing requirements in the DDS design implemented by the traditional method using multipliers and a set of sine and cosine lookup tables reaches 11. This shows that this method can have more advantages in optimizing system speed in logic implementation.

[0110] The beneficial effects of the present invention are as follows:

[0111] The present invention reduces the addend items of shift addition and improves the operation speed of the system by using a double sine-cosine function lookup table; further improves the operation speed of the system by using shift addition instead of a multiplier; and reduces the scale of the double sine-cosine function lookup table and reduces the bandwidth occupation by Taylor series interpolation.

[0112] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0113] The principles and implementation methods of the present invention are described in this article using specific examples. The description of the above embodiments is only used to help understand the method and core idea of ​​the present invention. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A method for implementing high-speed DDS in a radio frequency scenario, characterized in that: include: Construct a double sine and cosine function lookup table; The radian range of the double sine-cosine function lookup table is 0 to π / 4; Collecting a 16-bit phase input signal, splitting the upper 3 bits and lower 13 bits of the 16-bit phase input signal respectively to obtain an interval signal and an index signal; Reverse the index signal corresponding to the interval signal having the lowest bit being 1; Using 4 shift additions, the index signal corresponding to the lowest bit of the interval signal being 0 or the index signal completed in reverse order is converted into radians and the lowest 2 bits are discarded to obtain a 14-bit radian value; The upper 5 bits and the lower 9 bits of the 14-bit radian value are split to obtain a main radian interval and an interval to be interpolated; Calculate the number of 1s in the lower 9 bits of the 14-bit radian value to obtain a discrimination parameter; According to the discrimination parameter, Taylor series interpolation is performed on the highest bit, the second highest bit and the lower 7 bits of the interval to be interpolated in sequence by using 4-term shift addition to obtain an unsigned sin / cos value; The unsigned sin / cos value is post-processed according to the interval signal to obtain a target DDS output; the post-processing includes: any one of no operation, negation and exchange.

2. The method for implementing high-speed DDS in a radio frequency scenario according to claim 1, characterized in that: The interpolation formula of the Taylor series interpolation is: sin(θ)=sin(θ i )+cos(θ i )·b; in, θ i and θ i+1 Look up two consecutive phases in the double sine-cosine function table; is the least significant bit of the preset phase accumulator output; M is θ i to θ i+1 The binary resolution of the interpolation points.

3. The method for implementing high-speed DDS in a radio frequency scenario according to claim 1, characterized in that: The calculation formula for the 14-bit radian value is: phi_rad=(phase_inv<<4)+(phase_inv<<2)+(phase_inv>>2)+(phase_inv>>5)+1; Among them, phi_rad is the 14-bit radian value; phase_inv is the index signal corresponding to the lowest bit of the interval signal being 0 or the index signal completed in reverse order; << is the left shift symbol; >> is the right shift symbol.

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