A method for implementing high-speed DDS in radio frequency scenarios

Abstract

The present invention belongs to the field of wireless communications and provides a method for implementing a high-speed DDS in a radio frequency scenario, comprising: constructing a dual sine-cosine function lookup table, collecting and splitting 16-bit phase input signals, reversing the order of the signals, converting the signals to radians, splitting the signals into 14-bit radians, obtaining discrimination parameters, performing Taylor series interpolation, and post-processing. The present invention reduces the number of addends in shift addition by using a dual sine-cosine function lookup table, thereby increasing the system's operating speed; further increases the system's operating speed by using shift addition instead of a multiplier; and reduces the size of the dual sine-cosine function lookup table by using Taylor series interpolation, thereby reducing bandwidth occupancy.

Description

Technical Field

[0001] The present invention relates to the field of wireless communications, and in particular to a method for implementing high-speed DDS in a radio frequency scenario. Background Art

[0002] Direct frequency synthesizers, abbreviated as DDS, are important tools for signal processing. They are particularly widely used in radio frequency (RF) scenarios within the wireless communications field. Traditional DDS implementations primarily use hardware methods based on lookup tables or Cordic algorithms, or software methods based on CPU calculations. Software implementations offer higher accuracy but relatively low speed.

[0003] High-speed DDS in RF scenarios typically uses a hardware-based lookup table (LUT) approach. The output spectrum purity of a LUT-based DDS is proportional to the size of the dual sine and cosine lookup table. Using an interpolation algorithm can reduce the size of the sine and cosine lookup table, but this introduces multipliers, increasing system complexity and slowing down system operation. Summary of the Invention

[0004] In order to overcome the shortcomings of the existing technology, the purpose of the present invention is to provide a method for implementing high-speed DDS in a radio frequency scenario. By using a dual sine and cosine function lookup table, the addend items of shift addition are reduced, thereby improving the system's operating speed; by using shift addition instead of multipliers, the system's operating speed is improved; and by Taylor series interpolation, the scale of the dual sine and cosine function lookup table is reduced, thereby reducing bandwidth occupancy.

[0005] To achieve the above object, the present invention provides the following solutions:

[0006] A method for implementing high-speed DDS in a radio frequency scenario, comprising:

[0007] Constructing a double sine and cosine function lookup table; the radian range of the double sine and cosine function lookup table is 0 to π / 4;

[0008] Collecting a 16-bit phase input signal, and splitting the upper 3 bits and lower 13 bits of the 16-bit phase input signal to obtain an interval signal and an index signal;

[0009] Reversing the index signal corresponding to the lowest bit of the interval signal being 1;

[0010] Using 4 shift additions, the index signal corresponding to the interval signal having the lowest bit of 0 or the index signal completed in reverse order is converted into radians and the lowest 2 bits are discarded to obtain a 14-bit radian value;

[0011] Splitting the upper 5 bits and lower 9 bits of the 14-bit radian value to obtain a main radian interval and an interval to be interpolated;

[0012] Calculate the number of 1s in the lower 9 bits of the 14-bit radian value to obtain a discrimination parameter;

[0013] According to the discrimination parameter, Taylor series interpolation is performed on the highest bit, the second highest bit, and the lower 7 bits of the interpolation interval in sequence using 4 shift additions to obtain an unsigned sin / cos value;

[0014] The unsigned sin / cos value is post-processed according to the interval signal to obtain a target DDS output; the post-processing includes: any one of: no operation, inversion, and swap.

[0015] Preferably, the interpolation formula of the Taylor series interpolation is:

[0016] ;

[0017] in, ; ; and Two consecutive phases in the double sine-cosine function lookup table; is the least significant bit of the preset phase accumulator output; M is arrive The binary resolution of the interpolation points.

[0018] Preferably, the calculation formula of the 14-bit radian value is:

[0019] phi_rad=(phase_inv<<4)+(phase_inv<<2)+(phase_inv>>2)+(phase_inv>>5)+1;

[0020] Among them, phi_rad is the 14-bit radian value; phase_inv is the index signal corresponding to the lowest bit of the interval signal being 0 or the index signal completed in reverse order; << is the left shift symbol; >> is the right shift symbol.

[0021] The present invention discloses the following technical effects:

[0022] The present invention provides a method for implementing a high-speed DDS in a radio frequency scenario. By using a dual sine-cosine function lookup table, the problem of a large number of addends in conventional technologies is solved, thereby reducing the number of addends. By using shift addition, the problem of complex multiplier design and slow speed in conventional technologies is solved, thereby realizing the function of implementing multiplication by using shift addition. By using Taylor series interpolation, the problem of a large conventional lookup table and slow indexing speed is solved, thereby reducing the size of the lookup table. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0024] Figure 1 A schematic diagram of the implementation process of high-speed DDS in a radio frequency scenario provided by an embodiment of the present invention;

[0025] Figure 2 A schematic diagram of a dual search provided by an embodiment of the present invention;

[0026] FIG3 (a) is a schematic diagram of DDS comprehensive simulation results achieved by the improved method provided in an embodiment of the present invention;

[0027] FIG3( b ) is a schematic diagram of DDS comprehensive simulation results achieved using a traditional method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0028] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0029] The purpose of the present invention is to provide a method for implementing high-speed DDS in a radio frequency scenario. By using a dual sine-cosine function lookup table, the addend items of shift addition are reduced, thereby improving the operation speed of the system; by using shift addition instead of a multiplier, the operation speed of the system is improved; and by using Taylor series interpolation, the scale of the dual sine-cosine function lookup table is reduced, thereby reducing the bandwidth occupancy.

[0030] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0031] Figure 1 The following is a schematic diagram of the implementation process of high-speed DDS in a radio frequency scenario provided by an embodiment of the present invention, as shown in FIG. Figure 1 As shown, the present invention provides a method for implementing high-speed DDS in a radio frequency scenario, including:

[0032] Step 100: Construct a double sine and cosine function lookup table; the radian range of the double sine and cosine function lookup table is 0 to π / 4;

[0033] Step 200: Collect a 16-bit phase input signal, and split the upper 3 bits and lower 13 bits of the 16-bit phase input signal to obtain an interval signal and an index signal;

[0034] Step 300: Reverse the order of the index signal corresponding to the interval signal with the lowest bit being 1;

[0035] Step 400: using a 4-term shift addition operation to convert the index signal corresponding to the interval signal having the lowest bit of 0 or the index signal completed in reverse order into radians and discard the lowest 2 bits to obtain a 14-bit radian value;

[0036] Step 500: Split the upper 5 bits and lower 9 bits of the 14-bit radian value to obtain a main radian interval and an interval to be interpolated;

[0037] Step 600: Calculate the number of 1s in the lower 9 bits of the 14-bit radian value to obtain a discrimination parameter;

[0038] Step 700: Based on the discrimination parameter, Taylor series interpolation is performed on the highest bit, the second highest bit, and the lower 7 bits of the interval to be interpolated in sequence using 4-term shift addition to obtain an unsigned sin / cos value;

[0039] Step 800: Post-process the unsigned sin / cos value according to the interval signal to obtain a target DDS output; the post-processing includes: any one of: no operation, negation, and swap.

[0040] Furthermore, the interpolation formula of the Taylor series interpolation is:

[0041] ;

[0042] in, ; ; and Two consecutive phases in the double sine-cosine function lookup table; is the least significant bit of the preset phase accumulator output; M is arrive The binary resolution of the interpolation points.

[0043] Specifically, the calculation formula of the 14-bit radian value is:

[0044] phi_rad=(phase_inv<<4)+(phase_inv<<2)+(phase_inv>>2)+(phase_inv>>5)+1;

[0045] Among them, phi_rad is the 14-bit radian value; phase_inv is the index signal corresponding to the lowest bit of the interval signal being 0 or the index signal completed in reverse order; << is the left shift symbol; >> is the right shift symbol.

[0046] Specifically, the DDS phase-to-amplitude conversion is implemented through a lookup table. The phase accuracy is proportional to the address width of the lookup table. Using an interpolation method can reduce the size of the lookup table to save resource consumption while maintaining the same accuracy. This embodiment uses an interpolation method based on the Taylor series. This method transforms the phase θ to sin(θ) through a small lookup table. This method not only utilizes the symmetry of the sinusoidal signal, but also uses linear interpolation for consecutive points stored in the lookup table. Every two storage points in the lookup table ( and ) The sine function in the middle can be expressed as:

[0047]

[0048]

[0049] in, , and are two consecutive phases corresponding to each other in the lookup table; Represents the phase accumulator output The least significant bit of Indicates the most significant bit of the lookup table address; M indicates arrive The binary resolution of the interpolation points; Interpolation coefficients of the sine function representing the lookup table: ; It is the remainder of the Taylor expansion of the sine function. As shown below:

[0050]

[0051] in, .because: , so we have:

[0052]

[0053] And because: ,so , it can be seen that: choose the appropriate lookup table input resolution ( arrive Once the required accuracy is achieved, the remainder of the Taylor expansion can be ignored. Therefore, only the first two terms need to be calculated to achieve interpolation. That is, the interpolation algorithm can be simplified to:

[0054]

[0055]

[0056] Furthermore, in digital design, using shift-add to replace multipliers is a common optimization method. Its principle is based on the properties of binary numbers, especially the relationship between multiplication and shift. The principle of shift-add to implement multiplication:

[0057] Suppose we want to calculate the product of two binary numbers A and B, we can expand B into the sum of a series of powers of 2. For example, the binary number B can be expressed as:

[0058]

[0059] Then A×B can be expanded as:

[0060]

[0061] because The only possible values ​​are 0 or 1, so each Either 0 or A shifted left by i bits. Therefore, multiplication can be performed using a series of shift and addition operations. This approach reduces the complexity of the multiplier, significantly saving resources and power consumption in hardware design.

[0062] Preferably, this embodiment uses shift addition instead of multipliers in the process of converting the input phase to radian values. This method is also used in the Taylor series-based interpolation algorithm.

[0063] Specifically, this embodiment uses a dual sine and cosine lookup table to reduce the complexity of shift addition. This embodiment needs to perform a 7-bit phase interpolation algorithm in the third-level interpolation calculation. The required shift addition terms require a total of 7 terms. However, if a dual sine and cosine lookup table is used, the addition terms can be reduced to 3, thereby reducing system complexity and increasing operating speed. Principle: Taking 3-bit interpolation as an example, explain how the dual lookup table reduces the shift addition terms. Figure 2 As shown, the input phase generates the corresponding lookup table values, LUT0 and LUT1. The 3-bit interpolation coefficients provide eight offsets in the lookup table results. Using a single lookup table requires three shift and add operations to complete the multiplication (the maximum interpolation point is 111). With dual lookup tables, LUT0 is used for offsets when the interpolation point has fewer than two 1s. For the remaining points, LUT1 is used after inverting the value. This way, each lookup table handles interpolation points with only 0 or 1 1 (requiring only one addition operation).

[0064] Furthermore, a sine-cosine function lookup table is constructed. In this embodiment, phi_rad[13:9] is used as the index of the sine-cosine lookup table. The value of phi_rad[13:9] is an integer from 0 to 25, representing the radian. Radians, the decimal part is defined as a signed offset, then the corresponding radians should be: ( ). In this way, the interpolation calculation can be completed completely when using a single lookup table, but in this embodiment, shift addition is used instead of multipliers. In order to simplify the shift addition operation, a dual lookup table is used. The index radian definition of the dual lookup table is:

[0065] lut0: ( )

[0066] lut1: ( )

[0067] Specifically, the specific implementation method of the present invention is:

[0068] S1: Input phase value is compressed to 0 to / 4 radians:

[0069] The 16-bit phase input signal phase_in[15:0] is unsigned data, ranging from 0 to 65535, corresponding to radians 0 to 2 According to the symmetry of the sine and cosine functions, the sine and cosine functions corresponding to 0 to 2π radians can be used The sine and cosine functions of / 4 radians are calculated. Therefore, the sine and cosine function lookup table can be compressed to / 4 phase to reduce system consumption. Intercept the high 3 bits of phase_in phase_in[15:13] and use it to represent 8 (0 to 7) sizes from 0 to 2π radians / 4 interval. phase_in[12:0] is used as the index phase of the corresponding sine and cosine lookup table.

[0070] S2: phase_in

[13] is 1 The index phase in the / 4 interval is reversed:

[0071] The mathematical basis of this step is the 8 / 4 interval, / 4 to / 2, / 4 to , / 4 to 3 / 2, / 4 to 2 The sine and cosine functions of these intervals are relative to the previous ones. The interval is symmetric (or symmetric after the sign is reversed) within 4.

[0072] phase_in

[13] is 1, which means The / 4 interval is an even number, and the index phase needs to be in reverse order.

[0073] phase_in[12:0] reverse order method:

[0074] If phase_in

[13] ==1: ;

[0075] If phase_in

[13] ==0: ;

[0076] S3: Convert the index phase into radians:

[0077] The index phase is converted to radian phase using the shift-and-add method to avoid the introduction of multipliers.

[0078] phi_rad=(phase_inv<<4)+(phase_inv<<2)+(phase_inv>>2)+(phase_inv>>5)+1;

[0079] This step uses 4 shift additions to implement multiplication by 6.28125 (2π), which approximates the operation. If higher precision is required, further shift addends can be added. The resulting phi_rad is output after truncating the lowest two bits. The output phi_rad is 14 bits, of which the upper 5 bits (phi_rad[13:9]) range from 0 to 26 / 2^32 radians.

[0080] S4: phi_rad[8:0] is a 9-bit binary number. The number of 1s in it is calculated and stored in the register ones_cnt. This step is to simplify the computational complexity of the shift addition that replaces the multiplier.

[0081] S5: Taylor series interpolation of level 1:

[0082] Perform the first-level 1-bit Taylor series interpolation on phi_rad[8], and replace the multiplication with shift addition. Multiply The operation of It can be directly represented by the bit of phi_rad to be interpolated, which is the phi_rad[8] bit in this step.

[0083] First, determine the value of ones_cnt. If it is less than 4, use the first lookup table in the dual lookup table. Otherwise, use the second lookup table in the dual lookup table. Then, get the interpolation result based on the value of phi_rad[8].

[0084] If phi_rad[8] is 1:

[0085] x1=x0+(y0>>7)

[0086] y1=y0+(x0>>7)

[0087] If phi_rad[8] is 0:

[0088] x1=x0-(y0>>7)

[0089] y1=y0-(x0>>7)

[0090] S6: Taylor series interpolation of level 2:

[0091] Perform the second-order 1-bit Taylor series interpolation on phi_rad[7], same as S5.

[0092] If phi_rad[7] is 1:

[0093] x2=x1+(y1>>8)

[0094] y2=y1+(x1>>8)

[0095] If phi_rad[7] is 0:

[0096] x2=x1-(y1>>8)

[0097] y2=y1-(x1>>8)

[0098] S7: Taylor series interpolation of level 3:

[0099] Perform the third-level, 7-bit Taylor series interpolation on phi_rad[6:0], following the same principles as S5 or S6. Because dual lookup tables are used, the binary representation of the interpolated point phi_rad[6:0] will contain only three or fewer 1s, regardless of which lookup table is used. Using A, B, and C to represent the shift amount allows for a shift-and-add calculation.

[0100] If phi_rad[6] is 1:

[0101] x3=x2+(y2>>A)+(y2>>B)+(y2>>C)

[0102] y3=y2+(x2>>A)+(x2>>B)+(x2>>C)

[0103] If phi_rad[6] is 0:

[0104] x3=x2-(y2>>A)-(y2>>B)-(y2>>C)

[0105] y3=y2-(x2>>A)-(x2>>B)-(x2>>C)

[0106] S8: cos / sin output:

[0107] Based on the value of the upper 3 bits of phase_in[15:13], it is selected whether the interpolated sin / cos values ​​obtained in S7 are inverted or swapped, and then output to the final cos / sin signal as the final output of this DDS.

[0108] Referring to Figures 3(a) and 3(b), Design WNS stands for the worst negative slack; TNS represents the sum of the slack of all paths that fail to meet timing requirements; and Number of Violating Paths indicates the number of paths that fail to meet timing requirements. During the initial synthesis phase, only the Number of Violating Paths parameter should be considered. Demonstrating the effectiveness of this approach: Using an ASIC synthesis tool under the same timing constraints, the DDS design implemented with this approach has zero paths that fail to meet timing requirements, while the traditional DDS design using multipliers and a set of sine and cosine lookup tables has 11 paths that fail to meet timing requirements. This demonstrates that this approach offers advantages in optimizing system speed in logic implementation.

[0109] The beneficial effects of the present invention are as follows:

[0110] The present invention reduces the addends of shift addition by using a double sine-cosine function lookup table, thereby improving the operation speed of the system; further improves the operation speed of the system by using shift addition instead of a multiplier; and reduces the scale of the double sine-cosine function lookup table by Taylor series interpolation, thereby reducing bandwidth occupancy.

[0111] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0112] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The above examples are only intended to help understand the method and core concept of the present invention. At the same time, those skilled in the art will find that the specific implementation methods and application scopes may vary based on the concept of the present invention. In summary, the contents of this specification should not be construed as limiting the present invention.

Claims

1. A method for implementing high-speed DDS in a radio frequency scenario, characterized in that: include: Construct a double sine and cosine function lookup table; The radian range of the double sine and cosine function lookup table is 0 to π / 4; Collecting a 16-bit phase input signal, and splitting the upper 3 bits and lower 13 bits of the 16-bit phase input signal to obtain an interval signal and an index signal; Reversing the index signal corresponding to the lowest bit of the interval signal being 1; Using 4 shift additions, the index signal corresponding to the interval signal having the lowest bit of 0 or the index signal completed in reverse order is converted into radians and the lowest 2 bits are discarded to obtain a 14-bit radian value; Splitting the upper 5 bits and lower 9 bits of the 14-bit radian value to obtain a main radian interval and an interval to be interpolated; Calculate the number of 1s in the lower 9 bits of the 14-bit radian value to obtain a discrimination parameter; According to the discrimination parameter, Taylor series interpolation is performed on the highest bit, the second highest bit, and the lower 7 bits of the interpolation interval in sequence using 4 shift additions to obtain an unsigned sin / cos value; The unsigned sin / cos value is post-processed according to the interval signal to obtain a target DDS output; the post-processing includes: any one of: no operation, inversion, and swap.

2. The method for implementing high-speed DDS in a radio frequency scenario according to claim 1, wherein: The interpolation formula of the Taylor series interpolation is: ； in, ; ; and Two consecutive phases in the double sine-cosine function lookup table; is the least significant bit of the preset phase accumulator output; M is arrive The binary resolution of the interpolation points; is the phase accumulator output; The most significant bit of the lookup table address.

3. The method for implementing high-speed DDS in a radio frequency scenario according to claim 1, wherein: The calculation formula for the 14-bit radian value is: phi_rad=(phase_inv<<4)+(phase_inv<<2)+(phase_inv>>2)+(phase_inv>>5)+1; Among them, phi_rad is the 14-bit radian value; phase_inv is the index signal corresponding to the lowest bit of the interval signal being 0 or the index signal completed in reverse order; << is the left shift symbol; >> is the right shift symbol.

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