A control method, device and verification method for a clock signal

Abstract

The present application discloses a control method, device and verification method for a clock signal. The method includes: obtaining the original clock frequencies of each node on a data communication path, where the node is an object with an independent clock signal, and the node includes an internal node of a device and a peripheral node connected to the device; if the difference between the original clock frequency of the peripheral node and the maximum original clock frequency among the internal nodes of the device meets a set condition, determining a target matching frequency based on the original clock frequencies of each node on the communication path, where the target matching frequency includes the target clock frequencies of each node, and at least one node among each node has a target clock frequency greater than its original clock frequency; determining, based on the original clock frequencies and target clock frequencies of each node, the nodes that need to perform clock upscaling as target nodes; controlling the clock frequencies of the target nodes to be upscaled to the target clock frequencies of the target nodes, so as to improve the overall data transmission rate of the data communication path.

Description

Technical Field

[0001] This application relates to the field of technical signal control, and more specifically, to a method for controlling a clock signal, an apparatus, and a verification method thereof. Background Art

[0002] The clock frequency of the interfaces related to low-speed peripherals is often relatively low, resulting in a relatively slow data transmission speed. When a low-speed peripheral is jointly verified with other modules with relatively high data transmission or data processing speeds, the overall simulation speed will be slowed down due to its relatively low clock frequency. Summary of the Invention

[0003] In view of this, this application provides the following technical solutions:

[0004] In the first aspect of this application, a method for controlling a clock signal is provided. The method includes:

[0005] Obtain the original clock frequencies of each node on the data communication path. The node is an object with an independent clock signal, and the node includes internal nodes of the device and peripheral nodes connected to the device;

[0006] If the difference between the original clock frequency of the peripheral node and the maximum original clock frequency among the internal nodes of the device meets a set condition, determine a target matching frequency based on the original clock frequencies of each node on the communication path. The target matching frequency includes the target clock frequencies of each node, and at least one node among each node has a target clock frequency greater than its original clock frequency;

[0007] Determine the nodes that need to perform clock upscaling as target nodes based on the original clock frequencies and target clock frequencies of each node;

[0008] Control the clock frequency of the target node to be upscaled to the target clock frequency of the target node to improve the overall data transmission rate of the data communication path.

[0009] In a possible implementation, the determining the target matching frequency based on the original clock frequencies of each node on the communication path includes:

[0010] Determine the first node with the lowest original clock frequency;

[0011] Determine the data synchronization type between the first node and the second node connected to it;

[0012] Determine the relationship between the clock frequencies of the first node and the second node based on the data synchronization type.

[0013] In a possible implementation, determining the relationship between the clock frequencies of the first node and the second node based on the data synchronization type includes at least one of the following:

[0014] If the data synchronization type is the first type, determine that the ratio of the target clock frequency of the second node to the target clock frequency of the first node is at least 2, where the first type represents a synchronization method without data buffering;

[0015] If the data synchronization type is the second type, determine that the ratio of the target clock frequency of the second node to the target clock frequency of the first node is greater than 1, and the second type is a synchronization method with data buffering.

[0016] In a possible implementation, it further includes:

[0017] Determine whether there is a serial-to-parallel conversion between the first node and the second node;

[0018] If there is, determining the relationship between the clock frequencies of the first node and the second node based on the data synchronization type includes:

[0019] Determine the multiple relationship between the first node and the second node based on the data bit width of the data converted into parallel data and the data synchronization type.

[0020] In a possible implementation, the target clock frequencies of the nodes on the data communication path are all not higher than the highest operating frequency of the nodes in the device.

[0021] In a possible implementation, if the data communication path is a serial data path, among the target matching frequencies, in the data upstream direction, the clock frequency of the downstream node is not lower than the clock frequency of the upstream node.

[0022] In a possible implementation, the target nodes include at least two, and controlling the clock frequencies of the target nodes to be up-converted to the target clock frequencies of the target nodes includes at least one of the following:

[0023] Control the clock frequencies of the at least two target nodes to be synchronously up-converted to their respective corresponding target clock frequencies;

[0024] Control the at least two target nodes to perform up-conversion operations in sequence from downstream to upstream, and each target node is up-converted to its respective corresponding target clock frequency.

[0025] In a possible implementation, the target nodes include the first node, the second node, and the third node connected in sequence, and controlling the clock frequencies of the at least two target nodes to be synchronously up-converted to their respective corresponding target clock frequencies includes:

[0026] Synchronously determine the first target clock frequency of the first node and the second target clock frequency of the second node, so that the first target clock frequency and the second target clock frequency conform to the relationship of the clock frequencies between the first node and the second node;

[0027] If the second target clock frequency is higher than the original clock frequency of the third node, determine the third target clock frequency of the third node, where the third target clock frequency enables the data reception volume of the third node to be greater than the data output volume of the second node;

[0028] Control the clock frequencies of the first node, the second node, and the third node to synchronously increase to their respective corresponding target clock frequencies.

[0029] The second aspect of this application provides a verification method, and the verification method uses any of the above clock signal control methods to control the clock frequency.

[0030] The third aspect of this application provides a clock signal control device, including:

[0031] An original frequency acquisition module, configured to acquire the original clock frequencies of each node on the data communication path, where the node is an object with an independent clock signal, and the node includes internal nodes of the device and peripheral nodes connected to the device;

[0032] A target frequency determination module, configured to determine a target matching frequency based on the original clock frequencies of each node on the communication path when the difference between the original clock frequency of the peripheral node and the maximum original clock frequency among the internal nodes of the device satisfies a set condition, where the target matching frequency includes the target clock frequencies of each node, and at least one node among each node has a target clock frequency greater than its original clock frequency;

[0033] A target node determination module, configured to determine the node that needs to perform clock frequency upscaling as the target node based on the original clock frequencies and target clock frequencies of each node;

[0034] A frequency adjustment control module, configured to control the clock frequency of the target node to increase to the target clock frequency of the target node to improve the overall data transmission rate of the data communication path. Description of the Drawings

[0035] In order to more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of this application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on the provided drawings.

[0036] Figure 1 Flow chart of a method for controlling a clock signal disclosed in an embodiment of the present application;

[0037] Figure 2 Flow chart of determining a target matching frequency disclosed in an embodiment of the present application;

[0038] Figure 3 Flow chart of controlling a target node to perform frequency up - conversion disclosed in an embodiment of the present application;

[0039] Figure 4 Structural schematic diagram of a control device for a clock signal disclosed in an embodiment of the present application. Detailed implementation manners

[0040] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0041] The embodiments of the present application can be applied to electronic devices. The present application does not limit the product form of the electronic device, which may include but is not limited to smart phones, tablet computers, wearable devices, personal computers (PCs), netbooks, etc., and can be selected according to application requirements.

[0042] Figure 1 Flow chart of a method for controlling a clock signal disclosed in an embodiment of the present application. Figure 1 The shown solution is used to solve the problem that the clock frequency of a low - speed peripheral interface is quite different from the highest system - level clock frequency in a connected device, affecting the overall communication efficiency. Refer to Figure 1 As shown, the method for controlling a clock signal may include:

[0043] Step 101: Obtain the original clock frequencies of each node on the data communication path. The node is an object with an independent clock signal, and the node includes internal nodes of the device and peripheral nodes connected to the device.

[0044] The data communication path is a communication path including a peripheral and internal nodes of the device. The nodes in the data communication path may include, but are not limited to, the connection interface between a low - speed peripheral and the device, the data sampling interface of an internal processor of the device, the processor, etc. The connection interface between a low - speed peripheral and the device may be, for example, a JTAG interface, a PDM interface, an I2S interface, etc.

[0045] Generally speaking, the clock frequency of the peripheral interface is relatively low, resulting in a relatively slow corresponding data transfer rate. In this way, even if the clock frequencies of other nodes inside the device are very high, the data transfer rate of the overall data communication path will be limited by the data transfer rate of the low-speed peripheral interface. To improve the overall data transfer rate of the data transfer path, one can try to increase the clock frequencies of the nodes with the lowest and relatively low clock frequencies in the data communication path, so that the clock frequencies of all nodes in the data communication path are more balanced, thereby improving the overall data transfer rate of the data communication path.

[0046] In the embodiments of the present application, first, the original clock frequencies of each node on the data communication path need to be obtained. Subsequently, based on the original clock frequencies of each node, certain rules can be used to determine which nodes' clock frequencies need to be increased. Among them, the original clock frequency is the default clock frequency of the node without any later configuration, such as the clock frequency of the node when the electronic device is powered on.

[0047] Step 102: If the difference between the original clock frequency of the peripheral node and the maximum original clock frequency among the internal nodes of the device meets the set condition, determine the target matching frequency based on the original clock frequencies of each node on the communication path.

[0048] Among them, the target matching frequency includes the target clock frequencies of each node, and at least one node's target clock frequency in each node is greater than its original clock frequency. That is to say, in the target matching frequency, if a node's target clock frequency is the same as its original clock frequency, then this node does not need to perform clock upscaling; if a node's target clock frequency is greater than its original clock frequency, then this node needs to perform upscaling processing. The overall principle for determining the target matching frequency is to let the low clock frequency be upscaled close to the high clock frequency to overall improve the data transfer rate of the entire data communication path.

[0049] The difference between the original clock frequency of the peripheral node and the maximum original clock frequency among the internal nodes of the device meets the set condition. For example, if the maximum original clock frequency among the internal nodes of the device is more than 5 times the original clock frequency of the peripheral node, or the order of magnitude of the difference between the maximum original clock frequency among the internal nodes of the device and the original clock frequency of the peripheral node is greater than the order of magnitude of the original clock frequency of the peripheral node, then it is determined that the set condition is met.

[0050] It can be understood that if the clock frequencies of the nodes in the data communication path do not differ much, such as when an electronic device is connected to a high-speed peripheral and the data transmission rate at the connection port is similar to the data transmission rates and data processing rates of the internal nodes of the device, the "flow" speed of the data in the entire data communication path is balanced, and there is no situation where the data transmission speed of a few nodes is low and affects the overall data transmission rate. Then, there is no need to increase the frequency of the nodes in the data communication path, and thus there is no need to determine the target matching frequency. In this application, the set conditions are used as the basis for determining whether to determine the target matching frequency. The set conditions limit that the difference between the original clock frequency of the peripheral node and the maximum original clock frequency on the data communication path needs to be large enough, and then it is determined that the node with a low original clock frequency needs to have its frequency increased, so as to determine the target matching frequency and control the frequency increase of the corresponding node. In this way, it can be ensured that the data transmission rate of the entire data communication path is significantly improved after the frequency increase process.

[0051] To determine the target frequencies of each node in the target matching frequency, it is necessary to consider the upstream and downstream connection relationships of the nodes in the data communication path, and also need to consider the data sampling principle, synchronization method, etc. between adjacent nodes. On the premise of ensuring that there will be no data overflow in each node in the data communication path after the node frequency increase, the clock frequency of the node is increased as much as possible. The specific determination method of the target frequency of each node will be introduced in detail in the following embodiments and will not be elaborated here.

[0052] Step 103: Based on the original clock frequencies and target clock frequencies of each node, determine the nodes that need to have their clock frequencies increased as target nodes.

[0053] After determining the target matching frequency, the target clock frequencies and original clock frequencies of each node can be compared to determine which nodes in the data communication path need to perform frequency increase operations. The nodes that need to have their frequencies increased are target nodes.

[0054] Step 104: Control the clock frequency of the target node to increase to the target clock frequency of the target node to improve the overall data transmission rate of the data communication path.

[0055] Controlling the clock frequency increase of the target node has different implementations. For example, it can control the nodes that need to have their frequencies increased to synchronously complete the clock frequency increase, or it can also control the target nodes to sequentially increase the clock frequency in a certain order. This application does not have a fixed limit on this.

[0056] After the clock frequencies of all target nodes are increased, it is equivalent to increasing the data transmission rate of the nodes that originally pulled down the data transmission rate in the data communication path to a certain extent, thereby overall improving the data transmission rate of the data transmission path.

[0057] The control method of the clock signal in this embodiment determines the target nodes that can perform frequency up-conversion based on the original clock frequencies of the nodes in the data communication path, and performs frequency up-conversion processing on the target nodes, so as to improve the data transmission ability of the nodes that originally pulled down the data transmission rate of the entire data communication path, and improve the data transmission rate of the data communication path.

[0058] Figure 2 It is a flowchart for determining the target matching frequency disclosed in the embodiments of this application. Combining Figure 2 As shown, in the above embodiment, the determining the target matching frequency based on the original clock frequencies of the nodes on the communication path may include:

[0059] Step 201: Determine the first node with the lowest original clock frequency.

[0060] On the data communication path, the clock frequencies of different nodes may be the same or different. In this application, it is first necessary to determine the first node with the lowest original clock frequency in the data communication path. It can be understood that in the application scenario where a low-speed peripheral device is connected to an electronic device, since the clock frequencies of the internal nodes of the electronic device usually do not differ much, the first node with the lowest original clock frequency is usually the interface where the low-speed peripheral device is connected to the electronic device, such as a JTAG interface.

[0061] Since the overall data transmission rate of the data communication path is limited by the node with the lowest data transmission rate, in the embodiments of this application, it is necessary to first find the first node with the lowest original clock frequency and control its frequency up-conversion processing.

[0062] Step 202: Determine the data synchronization type between the first node and the second node connected to it.

[0063] After the first node performs frequency up-conversion, its data transmission rate will increase, which requires ensuring that its downstream second node also has sufficient data reception ability. If the second node can still fully receive the data output by the first node after the first node performs frequency up-conversion, the clock frequency of the second node can remain unchanged; if the second node no longer has the ability to fully receive the data output by the first node after the first node performs frequency up-conversion, then in order for the second node to fully receive the data output by the first node, the clock frequency of the second node also needs to follow the upstream node for frequency up-conversion to prevent the data output by the first node from overflowing and being lost. The same applies to other nodes. If a node on the data communication path cannot be fully received by its downstream node after frequency up-conversion, the downstream node also needs to follow for frequency up-conversion processing.

[0064] Those skilled in the art will know that when the data synchronization types between two nodes are different, the relationships that the clock frequencies of the two nodes need to satisfy are also different. The data synchronization type between nodes is determined during the chip design within the device. Therefore, when the data synchronization type is determined, the relationship that the clock frequencies of the two nodes that need to perform data synchronization need to satisfy is also determined.

[0065] Step 203: Determine the relationship between the clock frequencies of the first node and the second node based on the data synchronization type.

[0066] In one implementation, if the data synchronization type is the first type, determine that the ratio of the target clock frequency of the second node to the target clock frequency of the first node is at least 2. The first type represents a synchronization method without data buffering.

[0067] The first type may be data synchronization in a beating manner, which can perform data synchronization in two beats, three beats, or other numbers of beats. Since there is no buffer space for transmitting data during the data synchronization in the beating manner, in order to ensure that the data output from the first node to the second node does not overflow, it is required that the ratio of the target clock frequency of the second node to the target clock frequency of the first node is at least 2.

[0068] In another implementation, if the data synchronization type is the second type, determine that the ratio of the target clock frequency of the second node to the target clock frequency of the first node is greater than 1. The second type is a synchronization method with data buffering.

[0069] The second type may be fifo data synchronization. Since there is a data buffer storage space in the fifo data synchronization method, theoretically, the target clock frequency of the second node only needs to be not less than the target clock frequency of the first node. Even if the data of the first node suddenly increases during a certain period, under the action of the data buffer space, it will not cause the overflow of the data output from the first node.

[0070] The above content introduces the specific implementation of determining the target matching frequency, which is convenient for those skilled in the art to better understand and implement the technical solution of the present application.

[0071] Based on the content of the foregoing embodiments, the clock signal control method may further include: determining whether there is a serial-to-parallel conversion between the first node and the second node. If so, the determining the relationship between the clock frequencies of the first node and the second node based on the data synchronization type may include: determining the multiple relationship between the first node and the second node based on the data bit width of the data converted into parallel data and the data synchronization type.

[0072] For example, the first node outputs serial data to the second node. If the clock frequency of the serial bit stream is 3200 MHz, the second node performs serial-to-parallel conversion with 32 bits, and the first node and the second node are fifo-synchronized, then the clock frequency of the second node is theoretically not less than 3200÷32 = 100 MHz. If the first node and the second node are pipelined-synchronized, then the clock frequency of the second node is theoretically not less than 3200÷32×2 = 200 MHz.

[0073] To more clearly understand the relationship between the target clock frequencies of each node, the following content is introduced. Assume that the input / output frequency of the serial bit stream is x MHz, the sampling frequencies of the upstream and downstream are y MHz, the operating frequencies of the upstream and downstream are z MHz, and the highest operating frequency of other nodes in the device is h MHz. Check which synchronization type is used for sampling and driving the serial bit by the sampling frequencies of the upstream and downstream. If synchronization is performed using methods such as fifo, there is no need to worry about whether x will be greater than y / 2 after x is increased (that is, there is no need to meet the requirement that the clock frequency ratio of the downstream node to the upstream node in the pipelined-synchronized method is at least 2), which may cause sampling failure. If the upstream and downstream nodes perform serial-to-parallel conversion with 32 bits, then x can be increased to (32 / 2)*y MHz, or even higher, and theoretically it should not exceed 32y MHz.

[0074] In an example, at the original clock frequency, x = 100 MHz, y = 200 MHz, z = 500 MHz, h = 3000 MHz. To improve the overall data transmission rate of the data communication path, x needs to be increased. According to the Nyquist sampling theorem, when x is increased, y needs to be increased accordingly, otherwise data loss will occur. The increase in the clock frequency y of the downstream sampling module also requires the upsampling of the clock frequency z of the downstream node of the sampling module. How much x can be increased can be estimated based on the frequency values of x / y / z / h, etc. For example, the frequency of x / y can be increased as a whole. When the increased frequency of x / y exceeds z, then z is increased simultaneously.

[0075] In practical applications, when x is increased to a certain value, the overall data transmission rate of the data communication path may have reached saturation, and further increasing x will not result in an obvious increase in the data transmission rate. Therefore, finally, it is only necessary to make the clock frequencies of each node in the data communication path be at the same order of magnitude.

[0076] In practical applications, when determining the target clock frequencies of the respective nodes in a data communication path, the target clock frequencies of the respective nodes may be determined according to a set logic or the experience of relevant staff. To avoid data overflow and abnormal failure of related functions that may occur when the target clock frequency of a node is raised too high at one time, and also to avoid the amplitude of raising the target clock frequency of a node exceeding the amplitude required for the saturation state of the data transmission rate of the data communication path, the process of determining the target clock frequency may be carried out several times, that is, the clock frequency of the node may be controlled to be raised gradually. During the process of gradually raising the target clock frequency, if it is found that the overall data transmission rate of the data transmission path does not increase significantly after a certain frequency increase, it can be considered that the overall data transmission rate of the data communication path may have reached saturation, and even if the clock frequency of the node is further increased, it will not bring obvious positive effects, so the frequency increase control of the node can be stopped.

[0077] It should be noted that the target clock frequencies of the respective nodes on the data communication path are not higher than the highest working frequencies of the respective nodes in the device. For example, as described above, x, y, and z cannot be greater than h. That is, the processing logic of the solution of the present application is to improve the data transmission capacity of the nodes with low data transmission rates in the data communication path, so that their clock frequencies are close to higher clock frequencies, rather than raising the clock frequencies that are already high without limit.

[0078] If there is no serial-to-parallel conversion on the data communication path, that is, the data communication path is a serial data path, then in the target matching frequency, in the data upstream direction, that is, the direction in which the low-speed peripheral device transfers data to the inside of the device, the clock frequency of the downstream node is not lower than the clock frequency of the upstream node to ensure that the data transmitted by the upstream node will not overflow.

[0079] In one implementation of the foregoing embodiment content, the target node includes at least two. Controlling the clock frequency of the target node to be raised to the target clock frequency of the target node includes: controlling the clock frequencies of the at least two target nodes to be synchronously raised to their respective corresponding target clock frequencies; or, controlling the at least two target nodes to perform frequency increase operations in sequence from downstream to upstream, and each target node is raised to its respective corresponding target clock frequency.

[0080] Among them, the target node may include the first node, the second node, and the third node connected in sequence. The process of controlling the target node to perform frequency increase can be referred to Figure 3 . In combination with Figure 3 As shown, controlling the clock frequencies of the at least two target nodes to be synchronously raised to their respective corresponding target clock frequencies may include:

[0081] Step 301: Synchronously determine the first target clock frequency of the first node and the second target clock frequency of the second node, such that the first target clock frequency and the second target clock frequency conform to the relationship of the clock frequencies between the first node and the second node.

[0082] Step 302: If the second target clock frequency is higher than the original clock frequency of the third node, determine the third target clock frequency of the third node, where the third target clock frequency enables the data reception volume of the third node to be greater than the data output volume of the second node.

[0083] If the second target clock frequency is lower than or equal to the original clock frequency of the third node, it indicates that the data reception capability of the third node can cover the data output capability of the second node, that is, the third node can completely receive the data output by the second node without causing data overflow and loss. Therefore, it is not necessary to increase the clock frequency of the third node, that is, it is not necessary to determine the third target clock frequency of the third node.

[0084] Step 303: Control the clock frequencies of the first node, the second node, and the third node to synchronously increase to their respective corresponding target clock frequencies.

[0085] The up-frequencying is performed in the order from downstream to upstream to ensure that the downstream node can receive a larger amount of data. If the upstream node is up-frequencyed first, it may cause the downstream node to have insufficient data reception capability, resulting in data overflow and loss.

[0086] The control schemes for clock signals disclosed in the above multiple embodiments of the present application can be applied to verifications, including but not limited to IT (Integration Testing) verification, ST (System Testing) verification, SV (SystemVerilog) verification, etc. Referring to the content of the foregoing embodiments, the control method of the clock signal can improve the data transmission rate of the overall data communication path. Therefore, applying it in the verification field that requires a large amount of data transmission can effectively improve the simulation verification efficiency.

[0087] For example, when Coresight (a comprehensive debugging and tracing system) needs to be connected to an external host computer via JTAG, if the original clock frequency of JTAG is 50 MHz at this time, and a certain processing node of the host computer may run at 3 GHz, there is a 60-fold difference at this time. At this time, trace (in the field of simulation, trace usually refers to recording and tracking the behavior and state of a system or model during simulation) will require a very long time, generally about 4 ms. If discovery (scanning) and other related simulations are performed at this time, the required time will even reach 40 ms. This will result in a very slow verification speed, and the waveform will also be very large, with very high demands on processing resources and hard disk storage resources. If in the traditional way, without any control of the clock signal, the entire simulation process may take dozens of hours or even days, while adopting the clock signal control scheme provided by this application can effectively improve the overall data transmission rate and can increase the overall simulation speed by several times.

[0088] Based on the above, this application also discloses a verification method, and the verification method uses any one of the clock signal control methods in the foregoing embodiments to control the clock frequency.

[0089] It should be noted that when applying the clock signal control scheme of this application to verification implementation, in the case of limited simulation server resources and / or simulation time, the foregoing clock signal control scheme can be used in the pre-simulation and NLP simulation stages of the entire verification cycle. In the later simulation, since there are some works involving timing delays such as netlist adjustment, a standard clock, that is, the original clock frequency, needs to be used for simulation verification; however, in the later simulation, in the debugging stage without SDF (timing design file), the clock signal control scheme described in this application can also be used.

[0090] On the basis of the foregoing content, in the regression verification stage of simulation verification, the original clock frequency of each node can be used to verify the accuracy of the simulation results of the simulation using the target matching frequency. Each time a version regression verification is performed, several instance cases to be simulated can be first selected using the target matching frequency for regression simulation, and then other instance cases can be simulated using the standard clock frequency (original clock frequency) after the server is relieved of pressure, so as to reasonably utilize the acceleration scheme to help accelerate, complete, and authenticate the verification.

[0091] In addition, in SV verification, different instance cases can use different clock frequencies, that is, in order to improve the simulation efficiency, the target clock frequencies in the target matching frequency can be used; in order to ensure the authenticity of the simulation results, the original clock frequency can be used for simulation.

[0092] Combined with the foregoing content, the application of the clock signal control scheme in chip verification has the following advantages:

[0093] Simulations with large amounts of data can also achieve EDA (Electronics Design Automation) simulations;

[0094] In the early debugging stage of chip verification, it can reduce the case simulation time and server duration, quickly complete the execution of relevant test work, and thus accelerate case development, debugging, and Bug discovery;

[0095] During the regression of each version, it can quickly regress, without blocking other work tasks and without occupying work resources for a long time;

[0096] Reduce the use of the hard disk. The reduction of fsdb (Fast Signal Database, a file format used to store signal waveform information generated during simulation in the simulation field) and log (log) can both release hard disk resources;

[0097] Applicable to various integrations and system-level verifications with large frequency differences; it also has a certain effect on tranning in high-speed interfaces, can reduce tranning, and ensure the delivery of each link.

[0098] In addition, it should be noted that for some special projects, such as natural language processing applications, since the sign-off frequency is required for its backend simulation, during the debugging stage without SDF (Timing Design File), the target matching frequency determined by the solution of this application can be used. When there is SDF, the standard clock frequency needs to be used.

[0099] For the foregoing method embodiments, for the sake of simple description, they are all expressed as a series of action combinations. However, those skilled in the art should know that this application is not limited by the described action sequence, because according to this application, certain steps can be in other sequences or performed simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0100] In the foregoing embodiments disclosed in this application, the method is described in detail. The method of this application can be implemented by devices in various forms. Therefore, this application also discloses a device, and specific embodiments are given below for detailed description.

[0101] Figure 4 It is a schematic structural diagram of a control device for a clock signal disclosed in an embodiment of this application. See Figure 4As shown, the control device for the clock signal may include:

[0102] An original frequency acquisition module 401, configured to acquire the original clock frequencies of each node on the data communication path, where the node is an object with an independent clock signal, and the node includes an internal node of the device and a peripheral node connected to the device.

[0103] A target frequency determination module 402, configured to determine a target matching frequency based on the original clock frequencies of each node on the communication path when the difference between the original clock frequency of the peripheral node and the maximum original clock frequency among the internal nodes of the device meets a set condition. The target matching frequency includes the target clock frequencies of each node, and at least one node's target clock frequency in each node is greater than its original clock frequency.

[0104] A target node determination module 403, configured to determine the nodes that need to perform clock up - frequency as target nodes based on the original clock frequencies and target clock frequencies of each node.

[0105] A frequency adjustment control module 404, configured to control the clock frequency of the target node to be up - frequencyed to the target clock frequency of the target node, so as to improve the overall data transmission rate of the data communication path.

[0106] In this embodiment, the control device for the clock signal determines the target nodes that can be up - frequencyed among the nodes in the data communication path through the original clock frequencies of each node, and performs up - frequency processing on the clock signals of the target nodes, thereby enhancing the data transmission ability of the nodes that originally pulled down the data transmission rate of the entire data communication path and improving the data transmission rate of the data communication path.

[0107] The control device for the clock signal can be used as a verification device for performing IT verification, ST verification, SV verification, etc. Since the control device for the clock signal can improve the data transmission rate of the overall data communication path, applying it in the verification field that requires a large amount of data transmission can effectively improve the simulation verification efficiency. For the specific implementation and application effects, refer to the corresponding content introduction in the method embodiment.

[0108] In one implementation, the target frequency determination module may include: a first determination module, configured to determine a first node with the lowest original clock frequency; a synchronization type determination module, configured to determine the data synchronization type between the first node and a second node connected thereto; and a relationship determination module, configured to determine the relationship between the clock frequencies of the first node and the second node based on the data synchronization type.

[0109] In one implementation, the relationship determination module can specifically be used for at least one of the following: if the data synchronization type is the first type, determining that the ratio of the target clock frequency of the second node to the target clock frequency of the first node is at least 2, where the first type represents a synchronization method without data buffering; if the data synchronization type is the second type, determining that the ratio of the target clock frequency of the second node to the target clock frequency of the first node is greater than 1, where the second type is a synchronization method with data buffering.

[0110] In one implementation, the control device for the clock signal may further include: a serial-to-parallel conversion determination module, configured to determine whether there is a serial-to-parallel conversion between the first node and the second node; and then the relationship determination module is configured to: determine the multiple relationship between the first node and the second node based on the data bit width of the data converted into parallel data and the data synchronization type.

[0111] In one implementation, the target clock frequency of each node on the data communication path is not higher than the highest operating frequency of each node in the device.

[0112] In one implementation, if the data communication path is a serial data path, among the target matching frequencies, in the data upstream direction, the clock frequency of the downstream node is not lower than the clock frequency of the upstream node.

[0113] In one implementation, there are at least two target nodes, and the frequency adjustment control module is used for at least one of the following: controlling the clock frequencies of the at least two target nodes to synchronously increase to their respective target clock frequencies; controlling the at least two target nodes to perform frequency increase operations in sequence from downstream to upstream, and each target node increases its frequency to its respective target clock frequency.

[0114] In one implementation, the target nodes include the first node, the second node, and the third node connected in sequence. The frequency adjustment control module can specifically be used for: synchronously determining the first target clock frequency of the first node and the second target clock frequency of the second node, such that the first target clock frequency and the second target clock frequency conform to the relationship of the clock frequencies between the first node and the second node; if the second target clock frequency is higher than the original clock frequency of the third node, determining the third target clock frequency of the third node, where the third target clock frequency enables the data reception amount of the third node to be greater than the data output amount of the second node; controlling the clock frequencies of the first node, the second node, and the third node to synchronously increase to their respective target clock frequencies.

[0115] For the specific implementation of the above clock signal control device and each module it includes, reference can be made to the corresponding parts in the method embodiments for content introduction, which will not be repeated here.

[0116] Any one of the clock signal control devices in the above embodiments includes a processor and a memory. The original frequency acquisition module, target frequency determination module, target node determination module, frequency adjustment control module, etc. in the above embodiments are all stored in the memory as program modules, and the processor executes the above program modules stored in the memory to implement corresponding functions.

[0117] The processor contains a kernel, and the kernel retrieves the corresponding program module from the memory. One or more kernels can be set, and the processing of return visit data is achieved by adjusting the kernel parameters.

[0118] The memory may include non-permanent memory in a computer-readable medium, in the form of random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. The memory includes at least one storage chip.

[0119] In an exemplary embodiment, a computer-readable storage medium is also provided, which can be directly loaded into the internal memory of a computer and contains software code. After being loaded and executed by the computer, the computer program can implement the steps shown in any one of the above clock signal control methods.

[0120] In an exemplary embodiment, a computer program product is also provided, which can be directly loaded into the internal memory of a computer and contains software code. After being loaded and executed by the computer, the computer program can implement the steps shown in any one of the above clock signal control methods.

[0121] The various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the various embodiments can be referred to each other. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the description of the method part.

[0122] It should also be noted that, in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements not only includes those elements but also includes other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising said element.

[0123] The steps of the methods or algorithms described in connection with the embodiments disclosed herein can be implemented directly in hardware, in software modules executed by a processor, or in a combination thereof. The software modules can be placed in a random access memory (RAM), memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium well-known in the art.

[0124] The foregoing description of the disclosed embodiments enables those skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for controlling a clock signal, the method comprising: Obtaining the original clock frequency of each node on the data communication path, wherein the node is an object with an independent clock signal, and the node includes an internal node of the device and a peripheral node connected to the device; the original clock frequency is the default clock frequency of the node without any subsequent configuration; If the difference between the original clock frequency of the peripheral node and the maximum original clock frequency of the internal nodes of the device meets the set conditions, a target matching frequency is determined based on the original clock frequency of each node on the communication path, wherein the target matching frequency includes the target clock frequency of each node, and at least one of the nodes has a target clock frequency greater than its original clock frequency; wherein the determined target matching frequency needs to ensure that each node in the data communication path will not cause data overflow after the node frequency is increased; Based on the original clock frequency and the target clock frequency of each node, a node that needs to perform clock frequency increase is determined as a target node; The clock frequency of the target node is controlled to be increased to the target clock frequency of the target node, so as to increase the data transmission rate of the entire data communication path.

2. The clock signal control method according to claim 1, wherein the step of determining the target matching frequency based on the original clock frequency of each node on the communication path comprises: Determine a first node having the lowest original clock frequency; Determining a data synchronization type between the first node and a second node connected thereto; A relationship of clock frequencies between the first node and the second node is determined based on the data synchronization type.

3. The clock signal control method according to claim 2, wherein the determining the relationship between the clock frequencies of the first node and the second node based on the data synchronization type comprises at least one of the following: If the data synchronization type is a first type, determining that a ratio of a target clock frequency of the second node to a target clock frequency of the first node is at least 2, the first type representing a synchronization mode without data buffering; If the data synchronization type is the second type, it is determined that the ratio of the target clock frequency of the second node to the target clock frequency of the first node is greater than 1, and the second type is a synchronization mode with data buffering.

4. The clock signal control method according to claim 2, further comprising: Determine whether there is a serial-to-parallel conversion between the first node and the second node; If so, determining a relationship between clock frequencies of the first node and the second node based on the data synchronization type includes: The multiple relationship between the first node and the second node is determined based on the data bit width converted into parallel data and the data synchronization type.

5. The clock signal control method according to claim 1, wherein: The target clock frequency of each node on the data communication path is not higher than the highest operating frequency of each node in the device. 6 . The clock signal control method according to claim 1 , wherein if the data communication path is a serial data path, in the target matching frequency, in the data upstream direction, the clock frequency of the downstream node is not lower than the clock frequency of the upstream node.

7. The clock signal control method according to claim 2, wherein the target nodes include at least two, and the step of controlling the clock frequency of the target node to increase the clock frequency to the target clock frequency of the target node includes at least one of the following: Controlling the clock frequencies of the at least two target nodes to be synchronously increased to their respective corresponding target clock frequencies; The at least two target nodes are controlled to perform frequency up-conversion operations in sequence from downstream to upstream, and each target node is frequency up-converted to a corresponding target clock frequency.

8. The clock signal control method according to claim 7, wherein the target node comprises the first node, the second node and the third node connected in sequence, and the step of controlling the clock frequencies of the at least two target nodes to be synchronously increased to the respective corresponding target clock frequencies comprises: Synchronously determining a first target clock frequency of the first node and a second target clock frequency of the second node so that the first target clock frequency and the second target clock frequency conform to the relationship between the clock frequencies of the first node and the second node; If the second target clock frequency is higher than the original clock frequency of the third node, determining a third target clock frequency of the third node, wherein the third target clock frequency makes the data reception amount of the third node greater than the data output amount of the second node; The clock frequencies of the first node, the second node and the third node are controlled to be synchronously increased to their respective corresponding target clock frequencies.

9. A verification method, wherein the verification method adopts the clock signal control method described in any one of claims 1 to 8 to control the clock frequency.

10. A clock signal control device, comprising: The original frequency acquisition module is used to obtain the original clock frequency of each node on the data communication path, wherein the node is an object with an independent clock signal, and the node includes an internal node of the device and an external node connected to the device; the original clock frequency is the default clock frequency of the node without any subsequent configuration; A target frequency determination module, for determining a target matching frequency based on the original clock frequency of each node on the communication path when the difference between the original clock frequency of the peripheral node and the maximum original clock frequency of the internal node of the device meets a set condition, wherein the target matching frequency includes the target clock frequency of each node, and at least one of the nodes has a target clock frequency greater than its original clock frequency; wherein the determined target matching frequency needs to ensure that each node in the data communication path will not cause data overflow after the node frequency is increased; A target node determination module is used to determine the node that needs to perform clock frequency increase as the target node based on the original clock frequency and the target clock frequency of each node; The frequency adjustment control module is used to control the clock frequency of the target node to increase to the target clock frequency of the target node, so as to improve the data transmission rate of the entire data communication path.

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