CPU power supply circuit, power supply method and main control chip

Abstract

The invention relates to the technical field of power supply circuit design, and discloses a CPU power supply circuit, a power supply method and a main control chip, the CPU power supply circuit comprises the main control chip, a CPU and a power conversion circuit, and the main control chip is integrated with codes of at least two power communication protocols; the main control chip is used for determining a current available communication protocol in at least two power supply communication protocols according to the CPU type, and communicating with the CPU according to the current available communication protocol; the main control chip is also used for receiving a voltage regulation instruction from the CPU, generating a modulation signal according to the voltage regulation instruction, and sending the modulation signal to the power conversion circuit; and the power conversion circuit is used for receiving the modulation signal, adjusting an external input voltage according to the modulation signal and outputting the external input voltage to the CPU to supply power to the CPU. According to the scheme, one power supply chip is compatible with a multi-platform processor by adjusting chip software and hardware design, and the problems of low design flexibility and high complexity are solved.

Description

Technical Field

[0001] The present invention relates to the technical field of power supply circuit design, and in particular to a CPU power supply circuit, a power supply method and a main control chip. Background Art

[0002] The current server CPU (Central Processing Unit) power supply needs to use VRM (Voltage Regulator Module, digital voltage regulation module), such as Figure 1 As shown, compared with the traditional analog power supply solution, the digital multi-phase power supply solution has a faster response speed, and the digital multi-phase power supply can adjust the power supply parameters through the digital interface. Therefore, the digital multi-phase power supply has higher flexibility and can adapt to more application scenarios.

[0003] At present, different platforms have different requirements for the main control chip, which is mainly reflected in two aspects: one is software requirements and the other is hardware requirements. The software requirements are mainly in the power communication protocol part. Although the CPU communicates with the main control chip through clock signals (clock, CLK) and data (DATA), different platforms define different specifications for CLK and DATA. Therefore, even the same CLK and DATA waveforms convey different information. For the Intel (INTEL) platform, the main control chip needs to support SVID (SVID Power Management Protocol, System Voltage Identification Power Management Protocol), while the AMD (Advanced Micro Devices) platform requires the main control chip to support the SVI3 protocol, and the Ampere platform requires support for the AVSBUS protocol. At present, different platforms need to use different main control chips for design, which cannot achieve multi-platform compatibility, that is, the platform only supports one power communication protocol, which cannot meet the needs of multi-protocol and multi-platform operation. In addition, the current software and hardware design of the main control chip for a single platform also leads to high design complexity and low flexibility. Summary of the invention

[0004] In view of this, the present invention provides a CPU power supply circuit, a power supply method and a main control chip to solve the problem of low design flexibility and poor procurement due to the need to use different power chips for different CPU power supply protocols.

[0005] In a first aspect, the present invention provides a CPU power supply circuit, the CPU power supply circuit comprising: a main control chip, a CPU and a power conversion circuit, wherein the main control chip is integrated with codes of at least two power communication protocols, and is used to provide the CPU with communication functions of multiple power communication protocols; The main control chip is used to determine a currently available communication protocol among at least two power supply communication protocols according to the CPU type, and communicate with the CPU according to the currently available communication protocol; The main control chip is also used to receive a voltage regulation instruction from the CPU during the communication process, generate a modulation signal according to the voltage regulation instruction, and send the modulation signal to the power conversion circuit; The power conversion circuit is used to receive the modulation signal, adjust the external input voltage according to the modulation signal, and output it to the CPU to supply power to the CPU.

[0006] The CPU power supply circuit provided in this aspect is designed with a main control chip that is internally designed to be a flexibly adjustable code chip, and is integrated with codes of at least two power communication protocols, which can support multiple power communication protocols, and determine the currently available communication protocol among multiple power communication protocols according to the CPU type, and communicate with the CPU according to the currently available communication protocol. This design improves design flexibility and reuse rate of schematic diagrams of different platforms. By adjusting the chip software and hardware design, a power chip can be compatible with processors of multiple platforms, thereby solving the problem of low design flexibility and high design complexity caused by different processors needing to use different power chips.

[0007] In combination with the first aspect, in a possible implementation, the main control chip is also used to update the bit identifier corresponding to the currently available communication protocol after determining the currently available communication protocol, and the bit identifier has a unique corresponding relationship with the currently available communication protocol and is used to indicate the currently used power supply communication protocol.

[0008] In combination with the first aspect, in another possible implementation manner, the main control chip is connected to the CPU via a plurality of pins and a switch, and the plurality of pins at least include a first pin and a second pin; The main control chip is also used to control the switching switch to connect the communication link between the first pin and the CPU, and disconnect the communication link between the second pin and the CPU, wherein the communication link between the first pin and the CPU is used to transmit data or signals of the currently available communication protocol.

[0009] In combination with the first aspect, in another possible implementation, the main control chip is further used to transmit a clock signal and a digital signal on a communication link between the first pin and the CPU according to the currently available communication protocol.

[0010] In combination with the first aspect, in another possible implementation manner, the CPU power supply circuit further includes a baseboard management controller, and the baseboard management controller is connected to the main control chip and the CPU respectively; The baseboard management controller is used to communicate with the CPU, obtain the CPU type, and transmit the indication information containing the CPU type to the main control chip; The main control chip is further used to receive the indication information from the baseboard management controller, determine the CPU type according to the indication information, and after determining the currently available communication protocol according to the CPU type, return a message of the selected power communication protocol to the baseboard management controller; The baseboard management controller is further used to receive the selected message and forward it to the CPU.

[0011] In combination with the first aspect, in another possible implementation manner, the power conversion circuit includes a voltage input terminal, a voltage output terminal, an enable terminal and a pulse width modulation terminal; wherein the voltage input terminal is connected to the power supply, the voltage output terminal is connected to the CPU, and the enable terminal and the pulse width modulation terminal are respectively connected to the main control chip; The main control chip is further used to send an enable signal to the enable end of the power conversion circuit, and to send the modulation signal to the pulse width modulation end; The power conversion circuit is further used to adjust the voltage according to the enable signal and the modulation signal, and output the adjusted voltage to the CPU.

[0012] In combination with the first aspect, in another possible implementation manner, the power conversion circuit further includes a third pin and a fourth pin, and the third pin and the fourth pin are both connected to the main control chip; The power conversion circuit is further used to transmit the collected CPU current information to the main control chip through the third pin, and to transmit the collected CPU temperature information to the main control chip through the fourth pin; The main control chip is also used to receive and detect whether one or more of the current information and the temperature information is within a preset value range, and if it is within the preset value range, feed back an instruction of voltage regulation completion to the CPU.

[0013] Optionally, the at least two power supply communication protocols include at least two of SVID, SVI3 and AVSBUS.

[0014] In a second aspect, the present invention provides a CPU power supply method, the method being applied to the CPU power supply circuit described in the first aspect or any one of the embodiments of the first aspect, the method comprising: Get the CPU type; Determining a currently available communication protocol among at least two power supply communication protocols according to the CPU type, and communicating with the CPU according to the currently available communication protocol; During the communication process, a voltage regulation instruction is received from the CPU, a modulation signal is generated according to the voltage regulation instruction, and the modulation signal is sent to the power conversion circuit. The power conversion circuit is used to adjust the external input voltage according to the modulation signal and output it to the CPU to power the CPU.

[0015] In combination with the second aspect, in a possible implementation, the method further includes: after determining the currently available communication protocol, updating a bit identifier corresponding to the currently available communication protocol, the bit identifier having a unique corresponding relationship with the currently available communication protocol, and being used to indicate the currently used power supply communication protocol.

[0016] In combination with the second aspect, in another possible implementation manner, the main control chip is connected to the CPU via a plurality of pins and a switch, the plurality of pins at least include a first pin and a second pin, and the method further includes: The switching switch is controlled to connect the communication link between the first pin and the CPU and disconnect the communication link between the second pin and the CPU, wherein the communication link between the first pin and the CPU is used to transmit data or signals of the currently available communication protocol.

[0017] In combination with the second aspect, in another possible implementation, the communicating with the CPU according to the currently available communication protocol includes: transmitting a clock signal and a digital signal on a communication link between the first pin and the CPU according to the currently available communication protocol.

[0018] In a third aspect, the present invention further provides a main control chip, the main control chip comprising: a communication module, a computing module and a driving module; wherein the computing module is connected to the communication module and the driving module respectively, the communication module is connected to an external baseboard management controller and a CPU respectively, and the driving module is also connected to the CPU; Wherein, the communication module integrates codes of at least two power communication protocols, and is used to provide the CPU with communication functions of multiple power communication protocols; The communication module is used to determine a currently available communication protocol among at least two power supply communication protocols according to the CPU type, and communicate with the CPU according to the currently available communication protocol; The calculation module is used to receive the voltage regulation instruction from the CPU during the communication process, generate a driving instruction according to the voltage regulation instruction, and send the driving instruction to the driving module; The driving module is used to receive the driving instruction, generate a modulation signal, and send the modulation signal to the power conversion circuit, so that the power conversion circuit adjusts the external input voltage according to the modulation signal and outputs it to the CPU to power the CPU.

[0019] In combination with the third aspect, in a possible implementation, the communication module further includes a register for storing at least two power communication protocols and a bit identifier corresponding to each power communication protocol.

[0020] In combination with the third aspect, in another possible implementation, the communication module further includes a plurality of pins and a switch, and the plurality of pins includes at least a first pin and a second pin; A communication link is established between the first pin and the CPU for communicating with the main control chip according to the currently available communication protocol; A communication link is established between the second pin and the CPU for communicating with the main control chip according to other communication protocols, wherein the other communication protocols are protocols other than the currently available communication protocol among at least two power supply communication protocols; The switching switch is used to disconnect or connect the communication link.

[0021] In a fourth aspect, the present invention also provides a communication module, which includes a receiving unit, a determining unit and a sending unit. Specifically, the receiving unit is used to receive indication information containing a CPU type sent by a baseboard management controller; the determining unit is used to determine a currently available communication protocol among at least two power supply communication protocols according to the CPU type; and the sending unit is used to send a selected message for determining the currently available communication protocol through the board management controller to inform the CPU, so that the CPU communicates with the communication module according to the currently available communication protocol.

[0022] The present invention provides a CPU power supply circuit, power supply method and main control chip, which adjust the chip software and hardware design to achieve a power chip compatible with multi-platform processors, thereby solving the problem of low design flexibility and high design complexity caused by different processors needing to use different power chips. Specifically, it includes the following beneficial effects: The main control chip in the present invention adopts a flexibly adjustable code chip architecture and pre-integrates the codes of at least two power communication protocols. This design enables the main control chip to intelligently select the currently optimal power communication protocol from a variety of power communication protocols according to the type of CPU, and communicate efficiently with the CPU according to the currently selected power communication protocol. Not only does it improve the flexibility of communication, it also significantly enhances the compatibility of the circuit with different types of CPUs, and realizes the communication transmission of multiple power communication protocols on the main control chip.

[0023] The main control chip of the present invention realizes a rapid response to the voltage regulation instruction from the CPU, can accurately analyze the voltage regulation instruction, and generate an accurate modulation signal accordingly, and send it to the power conversion circuit to adjust the input voltage to provide a suitable output voltage for the CPU. The optimization of this process makes the voltage regulation faster and more accurate, effectively meets the CPU's fine requirements for power supply voltage under different workloads, and improves the performance stability and energy efficiency of the CPU.

[0024] In addition, this method can adjust the output voltage in real time to provide stable and reliable power supply for the CPU. Since the main control chip can intelligently select the optimal communication protocol according to the CPU type and ensure efficient communication with the CPU, this further enhances the response speed and stability of the power supply circuit. At the same time, the support of multiple power supply communication protocols also increases the adaptability of the circuit in complex environments and improves the reliability of the overall system.

[0025] In addition, normally three different models of power chips for SVID, SVI3 and AVSBUS protocols are required. The present invention uses a power main control chip compatible with multiple protocols, and the material models are reduced from 3 to 1, which is conducive to procurement and preparation of materials and reduces the risk of material stagnation or shortage. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0027] Figure 1 is a schematic diagram of a digital multi-phase power supply solution provided according to the present invention; Figure 2a It is a schematic diagram of the communication between the INTEL platform CPU and the main control chip provided according to an embodiment of the present invention; Figure 2b It is a schematic diagram of communication between an AMD platform CPU and a main control chip provided according to an embodiment of the present invention; Figure 3 is a schematic diagram of a multi-protocol integrated power supply main control chip provided according to an embodiment of the present invention; Figure 4 is a schematic diagram of the structure of a CPU power supply circuit provided according to an embodiment of the present invention; Figure 5 is a schematic diagram of software-level compatibility provided according to an embodiment of the present invention; Figure 6is a schematic diagram of hardware function compatibility provided according to an embodiment of the present invention; Figure 7 is a flow chart of a CPU power supply method provided according to an embodiment of the present invention; Figure 8 It is a structural block diagram of a communication module provided according to an embodiment of the present invention. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0029] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0030] Furthermore, the terms “first” and “second” are used for descriptive purposes only and should not be understood as indicating or implying relative importance.

[0031] The technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0032] The technical solution provided by the embodiment of the present invention can be applied to the application scenario of CPU (Central Processing Unit) power supply. The CPU power supply application scenario generally adopts a digital multi-phase power supply solution, such as Figure 1 As shown, this is a schematic diagram of a digital multi-phase power supply solution.

[0033] The solution includes: CPU, main control chip and power conversion module or power conversion chip. Since the CPU has high performance and low power consumption modes, different working voltages Vout need to be selected in different working scenarios. The voltage requirement is determined by the CPU and transmitted to the main control chip through clock signals and data signals to realize real-time voltage adjustment.

[0034] At present, different platforms have different requirements for the main control chip, which is mainly reflected in two aspects: software requirements and hardware requirements. Among them, the software requirements are mainly in the power communication protocol part, and the power communication protocols of different platforms are incompatible with each other. For example Figure 2a As shown, on the INTEL CPU platform, it is generally recommended to use the chip model XDPE1***4 as the main control chip. This active chip can support the SVID (SVID Power Management Protocol, system voltage identification power management protocol) communication of the INTEL CPU.

[0035] Among them, the SVID power management protocol is a communication protocol for power management. It defines the specifications for transmitting and interpreting power management related information in the system, aiming to achieve power management across suppliers. The SVID protocol helps improve energy efficiency, reduce power consumption, and simplify system integration and development processes by providing rich features, high flexibility, and strong scalability. This protocol has a wide range of applications in the field of power management, especially in systems that require efficient and reliable power management.

[0036] The AMD (Advanced Micro Devices) CPU platform uses the XDPE1***3 chip as the main control chip, such as Figure 2b As shown, it can support AMD SVI3 power protocol. In addition to the difference in power protocol, the two main control chips also have different definitions of PIN pins.

[0037] Specifically, the SVl3 version is a version that has been improved or upgraded based on the SVID interface. The AMD Serial VID Interface (SVID) is a communication interface between the AMD processor and the power management system, which is used to implement voltage identification (VID) and power management functions. The SVID interface allows the processor to send its required voltage and current requirements to the power management system so that the power management system can adjust the power supply parameters accordingly, thereby ensuring stable operation and efficient energy consumption of the processor.

[0038] In AMD Ryzen 6000 series processors, SVI3 (System Voltage Interface 3) is an advanced technology for faster, more accurate, and finer-grained platform-level power or power consumption control. SVI3 technology achieves more refined management of power control by improving the design of the system voltage interface. It allows the processor to more accurately monitor and control changes in voltage and current, thereby optimizing the balance between power consumption and performance. In the field of high-performance computing, SVI3 technology enables AMD Ryzen 6000 series processors to achieve better energy efficiency in these scenarios, as well as higher energy efficiency and lower operating costs in data center environments, and longer battery life.

[0039] At present, for the two types of main control chips, due to the different definitions of package PINs, different platforms need to use different main control chips for design in principle design, and multi-platform compatibility cannot be achieved. This not only leads to high complexity and low flexibility in principle design, but also the large number of selected materials is not conducive to material procurement.

[0040] In order to solve the above problems, an embodiment of the present invention provides a CPU power supply design solution that is compatible with multiple power supply protocols at the same time, that is, integrating the three power supply communication protocols of SVID, SVI3 and AVSBUS into a main control chip and adjusting the chip packaging design to achieve one power supply main control chip replacing three power supply main control chips in terms of function.

[0041] The technical solution provided by the embodiments of the invention is described in detail below.

[0042] In order to meet the design requirements, two aspects of the communication module need to be solved: one is the software level, and the other is the hardware level. In order to achieve a single main control chip compatible with multiple power communication protocols, it is necessary to improve the software level and the hardware level respectively.

[0043] Among them, improvements at the software level include: the need for compatible design of three power supply protocols: SVID, SVI3 and AVSBUS, such as Figure 3 As shown, first, when designing the hardware of the main control chip, the communication module is changed from an ASIC architecture chip to an ARM architecture chip, which is a flexibly adjustable code chip. This is because compared to ASIC architecture chips, ARM architecture chips can be repeatedly programmed and flexibly adjust code programs to achieve repeated switching between different protocols. In the past, ASIC architecture generally refers to the hardware structure and organization of an application-specific integrated circuit (Application-Specific Integrated Circuit). After a certain power supply protocol is stored in the chip, it cannot be changed, so it can only support a single platform.

[0044] Among them, ARM architecture, full name Advanced RISC Machine, means advanced reduced instruction set computer. It is a processor design scheme. ARM architecture chips have been widely used in mobile devices, IoT devices, servers, data centers and other fields due to their low power consumption, high performance, flexibility and scalability.

[0045] Then, the three power communication protocols OTP (One Time Programable) are compressed to reduce the code space occupied by each protocol. The compressed codes are implanted into the storage space of the ARM architecture chip for standby use, and a two-bit protocol setting register is defined in the storage space. Among them, the protocol selection register is placed in the storage space together with the communication protocol code, which is specifically used to set which power communication protocol the current power main control chip will use.

[0046] It should be noted that the register and the compressed protocol code may exist in parallel. As for the storage method, the compressed protocol code may be stored in a portion of the storage resources of the communication module, and the register of the communication module is used to store the two-bit protocol relationship, as shown in Table 1 below.

[0047] See also Figure 4 , is a schematic diagram of the structure of a CPU power supply circuit provided by an embodiment of the present invention. The CPU power supply circuit includes: a main control chip, a CPU and a power conversion circuit. In addition, the power supply circuit may also include other modules or circuits, such as a BMC (Baseboard Management Controller), wherein the main control chip is a flexibly adjustable code chip and integrates codes of at least two power communication protocols, and is used to provide the CPU with communication functions of multiple power communication protocols.

[0048] The main control chip is used to determine a currently available communication protocol among at least two power supply communication protocols according to the CPU type, and communicate with the CPU according to the currently available communication protocol.

[0049] Optionally, at least two power supply communication protocols include: at least two of SVID, SVI3 and AVSBUS. Among them, AVSBUS (Adaptive Voltage Scaling Bus) is a high-speed, point-to-point bus, mainly used to connect the CPU and the power supply to achieve efficient voltage regulation and power management, and is mainly used in scenarios requiring high performance, low power consumption and precise power management.

[0050] In addition, AVSBUS is designed to provide a mechanism that enables an ASIC (Application Specific Integrated Circuit), FPGA (Field Programmable Gate Array) or processor to change the voltage of its power supply by sending commands to the POL (Point of Load Converter). In addition, AVSBUS also supports reverse reading of the voltage and current of the POL, thereby enabling accurate monitoring and management of the power subsystem. Through AVSBUS, digital multiphase controllers can be directly connected to the load and dynamically adjust the voltage level to achieve efficiency savings.

[0051] Specifically, the main control chip is also used to determine the currently available communication protocol among at least two power communication protocols according to the CPU type, inform the CPU through the BMC, and communicate with the CPU according to the currently available communication protocol. For example, the previous communication protocol is one of SVID, SVI3 and AVSBUS. Furthermore, the communication module communicates with the CPU through CLK and DATA signals.

[0052] In addition, the main control chip is also used to receive a voltage regulation instruction from the CPU during the communication process, generate a modulation signal according to the voltage regulation instruction, and send the modulation signal to the power conversion circuit.

[0053] The power conversion circuit is used to receive the modulation signal, adjust the external input voltage according to the modulation signal and output it to the CPU to provide power for the CPU.

[0054] In addition, the BMC is connected to the main control chip and the CPU respectively; it is used to communicate with the CPU, obtain the CPU type, and transmit indication information including the CPU type to the main control chip.

[0055] The main control chip is also used to receive indication information from the BMC, determine the CPU type according to the indication information, and after determining the currently available communication protocol according to the CPU type, return a message of the selected power communication protocol to the BMC.

[0056] The BMC is also used to receive messages from selected devices and forward them to the CPU.

[0057] Optionally, the main control chip includes: a communication module, a computing module and a driving module. Figure 4 As shown, the connection relationship is as follows: the communication module is connected to the BMC and the CPU respectively, and the BMC and the CPU are connected through the I2C channel; the computing module is connected to the communication module and the driving module respectively, and the driving module is also connected to the CPU.

[0058] Furthermore, the calculation module is used to receive the voltage regulation instruction from the CPU during the communication process, and generate the driving instruction according to the voltage regulation instruction, and send it to the driving module. Furthermore, the calculation module is responsible for collecting the current, voltage and temperature information of the power conversion chip for instruction calculation.

[0059] The driving module is used to receive a driving instruction, and generate and output a modulation signal to the power conversion circuit according to the driving instruction.

[0060] In a specific implementation of this embodiment, the communication module of the main control chip includes registers, such as Figure 5 As shown, the register stores at least two power communication protocols and a bit identifier corresponding to each power communication protocol.

[0061] The protocol setting register sets different digital bits for selecting different communication protocols. The selection method is shown in Table 1 below, where 00 / 01 / 10 correspond to SVID / SVI3 / AVSBUS protocols respectively, and 11 represents that no communication protocol is selected.

[0062] Table 1

[0063] After the design of the main control chip is completed, the protocol setting register defaults to the "11" state. In the initial state, the power communication protocol recorded in the register is empty, indicating that the chip does not support any power protocol at this time. After the main control chip is soldered to the PCB board, the BMC on the board will work first and detect which platform's CPU solution is used by the CPU on the current board.

[0064] Initialization process: BMC communicates with CPU through I2C channel to detect CPU type. CPU will report the currently used platform to BMC. If BMC detects that the CPU is an INTEL platform, BMC will inform the communication module through PMBUS channel that the current CPU platform is INTEL.

[0065] Among them, PMBUS, the full name of Power Management Bus, is an open standard digital power management protocol. The PMBUS protocol is designed to facilitate communication with power converters or other devices by defining transmission and physical interfaces and command languages.

[0066] The main control chip is also used to update the bit identifier corresponding to the currently available communication protocol after determining the currently available communication protocol. The bit identifier has a unique corresponding relationship with the currently available communication protocol and is used to indicate the currently used power supply communication protocol.

[0067] A specific implementation method is that the communication module determines that the power communication protocol supported by the current INTELCPU platform is the SVID communication protocol, that is, the currently available communication protocol, based on the currently acquired platform, such as INTEL. After determining the currently available communication protocol, the bit identifier of the register is updated from empty to the target bit identifier, and the target bit identifier has a unique correspondence with the currently available communication protocol. For example, according to Table 1 above, "11" is updated to "00", where the corresponding target bit identifier is "00" in the SVID communication protocol scenario.

[0068] like Figure 4 As shown, when the communication protocol is selected, the main control chip notifies the BMC, and the BMC notifies the CPU. After receiving the completion instruction, the CPU starts communicating with the power main control chip.

[0069] Specifically, the BMC communicates with the CPU through the I2C channel, obtains the CPU type, and transmits the indication information containing the CPU type to the communication module of the main control chip through PMBUS; the communication module receives the indication information transmitted from the BMC, determines the currently available communication protocol according to the CPU type contained in the indication information, and returns the selected message to the BMC. The BMC receives the selected message sent by the communication module and forwards it to the CPU.

[0070] In a specific implementation of this embodiment, the process of the power supply main control chip communicating with the CPU includes: The main control chip first obtains the compressed code from the storage space, and then decompresses the code to obtain the source code of the SVID protocol, that is, the decompressed file. Specifically, when the CPU is detected to be an Intel platform, the protocol setting register is changed to 00. At this time, the SVID code pre-stored in the storage space will be decompressed and the function adaptation will be completed to achieve normal communication with the CPU.

[0071] The main control chip uses the decompressed source code to generate the corresponding DATA or CLK signal, confirms that the path of the SVID protocol is in the on state, and then uses the communication module to communicate CLK and digital signals with the CPU according to the current SVID protocol.

[0072] If the protocol setting is not successfully burned, the software will prompt an error, ensuring that the chip has selected the correct communication protocol before boarding to prevent CPU abnormality caused by different communication protocols. In this embodiment, the main control chip supports multiple burning, which can realize flexible conversion between different protocols.

[0073] After solving the software-level problems of the above-mentioned communication modules, it is also necessary to solve the hardware problems. Currently, there are many differences in the pin (PIN) functions of power controllers on different platforms. In order to achieve compatibility of a single chip with multiple platforms, compatibility in hardware design must also be achieved.

[0074] To achieve this goal, this embodiment achieves compatibility for different PINs by designing a multi-function multiplexed PIN, that is, one channel can be compatible with multiple PIN functions at the same time. For example, the three power communication protocols all need to communicate with the CPU through the CLK and DATA PIN pins. However, if each power protocol has a CLK and DATA PIN pin, the chip package will be larger, and since only one power communication protocol is effective and the other protocols are not effective during operation, the redundant PINs will also be wasted. Therefore, the internal hardware circuit is designed to be compatible with the requirements of different platform CPUs, such as Figure 6 As shown, the main control chip is connected to the CPU through a plurality of pins and a switching switch, wherein the plurality of pins at least include a first pin and a second pin.

[0075] Furthermore, the main control chip is also used to control the switching switch to conduct the communication link between the first pin and the CPU, and to disconnect the communication link between the second pin and the CPU, wherein the communication link between the first pin and the CPU is used to transmit data or signals of the currently available communication protocol (such as SVID). The communication link between the second pin and the CPU can be used to transmit data or signals of the SVI3 and AVSBUS protocols. Since the signals of the SVI3 and AVSBUS protocols do not need to be transmitted at present, these links are disconnected by switching the switch, and only the communication link of the data or signal that needs to be transmitted currently is conducted.

[0076] In this embodiment, the main control chip can conduct two communication links of the SVID protocol through the control unit, one for transmitting CLK1 and the other for transmitting DATA1, and at the same time disconnect the communication link between the SVI3 and AVSBUS protocols and the CPU.

[0077] In this embodiment, when different power communication protocols are selected, the control unit is used to close the hardware switches of the corresponding CLK and DATA channels, and the switches of other communication protocols are disconnected, so that only two multi-function PINs can replace the function of 6 PINs, thereby saving costs and simplifying the circuit.

[0078] The CPU power supply and voltage regulation process is described below.

[0079] like Figure 4As shown, the CPU power supply circuit also includes a power conversion circuit, which includes a voltage input terminal Vout, a voltage output terminal Vin, an enable terminal (enable, EN) and a PWM (Pulse Width Modulation) terminal. In addition, the power conversion circuit may also include more or fewer pins, such as a third pin and a fourth pin, and the third pin and the fourth pin are both connected to the main control chip.

[0080] The voltage input terminal Vin is connected to an external power supply, the voltage output terminal Vout is connected to a CPU, and the enable terminal EN and the PWM terminal are connected to the driving module respectively.

[0081] Optionally, the third pin is an Imon pin, the fourth pin is a Tmon pin, and the third pin and the fourth pin are respectively connected to the computing module.

[0082] The third pin is used for collecting current information and transmitting the current information to the calculation module; similarly, the fourth pin can be used for collecting temperature information of the CPU and reporting the collected temperature information to the calculation module.

[0083] The working process is as follows: the CPU sends a voltage regulation instruction to the communication module through CLK and DATA, and the communication module sends the received voltage regulation instruction to the calculation module.

[0084] After receiving the voltage regulation instruction, the calculation module sets the PWM drive instruction to be executed and sends the drive instruction to the drive module.

[0085] After receiving the driving instruction, the driving module sends an enable signal ENABLE and a PWM signal to the power conversion circuit. After the EN terminal and the PWM terminal of the power conversion circuit receive the enable signal ENABLE and the PWM signal respectively, the output voltage Vout is adjusted and output to the outside. Among them, part of Vout is used to power the CPU, and the other part is sampled back to the calculation module to detect whether the voltage reaches the expected set value. If the calculation module detects that the output voltage Vout reaches the set value, the calculation module sends a voltage regulation instruction feedback to the communication module to complete the voltage regulation process.

[0086] Specifically, the driving module is also used to send an enable signal EN to the enable terminal of the power conversion circuit, and to send a PWM drive signal to the PWM terminal. The power conversion circuit is used to adjust the output voltage according to the enable signal ENABLE and the PWM drive signal, and transmit the adjusted output voltage to the CPU. Among them, the PWM drive signal is a modulation signal.

[0087] In addition, the power conversion circuit also includes a third pin and a fourth pin, both of which are connected to the computing module. The power conversion circuit is also used to transmit the collected CPU current information to the main control chip through the third pin, and to transmit the collected CPU temperature information to the main control chip through the fourth pin.

[0088] The main control chip is also used to receive and detect whether one or more of the current information and the temperature information is within a preset value range, and if it is within the preset value range, feed back an instruction of voltage regulation completion to the CPU.

[0089] In this embodiment, the hardware of the main control chip is improved to realize the multi-channel switching function in the communication module. It should be understood that in addition to the communication module, the PINs of the computing module and the driving module that are different on different platforms can all be designed with hardware multi-function PINs. Figure 6 The PIN pins of the multi-protocol power control chip are defined. PINs 1-17 are universal on the three platforms and have the same definition. PINs 18-24 are reused for multi-function design in the manner shown in Table 2 to achieve hardware compatibility on the three platforms. The current tape-out has been verified through actual testing to verify the feasibility of the solution. See Table 2 for details.

[0090] Table 2

[0091] The difference between APWM and BPWM is that a master chip supports outputting up to two different voltages, voltage A and voltage B, or it can output only one voltage. If all 12 channels are used to output voltage A, the PWM voltage can be expressed as APWM1~APWM12. If 6 of the 12 channels are used to output voltage A and the other 6 channels are used to output voltage B, the voltage transmitted by the 6 channels is expressed as APWM 1~APWM 6, and the voltage transmitted by the other 6 channels is expressed as BPWM 1~BPWM6.

[0092] Table 2 shows the hardware definition of the chip when three power communication protocols are selected under three platforms, as well as the connection relationship of PIN pin multiplexing, which is used to implement multi-functional multiplexing design in hardware. Combined with the above-mentioned software improvements, the beneficial effect of one power chip being compatible with multi-platform processors is achieved.

[0093] The main control chip provided in this embodiment adopts a flexibly adjustable code chip architecture in terms of software design, and pre-integrates the code of at least two power communication protocols, and selects through the protocol setting register. At the hardware level, the hardware compatibility of the three protocols is achieved by designing a multi-functional multiplexing PIN. The chip design is carried out according to the theoretical design at the software level and the hardware level, and the feasibility of the solution is confirmed by the chip return test, which not only improves the flexibility of communication, but also significantly enhances the compatibility of the circuit with different types of CPUs, and realizes the communication transmission of multiple power communication protocols on the main control chip.

[0094] The present invention realizes a rapid response to the voltage regulation instruction from the CPU, can accurately analyze the voltage regulation instruction, and generate an accurate modulation signal accordingly, and send it to the power conversion circuit to adjust the input voltage to provide a suitable output voltage for the CPU. The optimization of this process makes the voltage regulation faster and more accurate, effectively meets the CPU's fine requirements for power supply voltage under different workloads, and improves the performance stability and energy efficiency of the CPU.

[0095] In addition, this method can adjust the output voltage in real time to provide stable and reliable power supply for the CPU. Since the main control chip can intelligently select the optimal communication protocol according to the CPU type and ensure efficient communication with the CPU, this further enhances the response speed and stability of the power supply circuit. At the same time, the support of multiple power supply communication protocols also increases the adaptability of the circuit in complex environments and improves the reliability of the overall system.

[0096] In addition, normally three different models of power chips are required for SVID, SVI3 and AVSBUS protocols. The present invention uses a power main control chip compatible with multiple protocols, and the material models are reduced from 3 to 1, which is conducive to purchasing and preparing materials and reduces the risk of material stagnation or shortage.

[0097] An embodiment of the present invention provides an embodiment of a CPU power supply method. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0098] In this embodiment, a CPU power supply method is provided, which can be used for the main control chip in the above embodiment. Figure 7 is a flow chart of a CPU power supply method according to an embodiment of the present invention, the method comprising: Step S101: Obtain the CPU type.

[0099] The CPU type may be acquired by the main control chip according to the indication information including the CPU type sent by the BMC.

[0100] Step S102: determining a currently available communication protocol from at least two power supply communication protocols according to the CPU type, and communicating with the CPU according to the currently available communication protocol.

[0101] Step S103: receiving a voltage regulation instruction from the CPU during the communication process, generating a modulation signal according to the voltage regulation instruction, and sending the modulation signal to the power conversion circuit.

[0102] The power conversion circuit is used to adjust the external input voltage according to the modulation signal and output it to the CPU to provide power for the CPU.

[0103] In addition, the method of this embodiment further includes: after the CPU receives the selected message, the CPU communicates with the communication module according to the currently available communication protocol.

[0104] In the above step S102, after the main control chip determines the currently available communication protocol, the bit identifier corresponding to the currently available communication protocol is updated. The bit identifier has a unique corresponding relationship with the currently available communication protocol and is used to indicate the currently used power supply communication protocol.

[0105] The above correspondence can be stored in a register of the communication module. In the initial state, the power communication protocol recorded in the register is empty; after determining the currently available communication protocol, the register identifier is updated from empty to the target bit identifier, and the target bit identifier has a unique correspondence with the currently available communication protocol.

[0106] In another possible implementation, the main control chip is connected to the CPU via a plurality of pins and a switch, the plurality of pins at least include a first pin and a second pin, and the method of this embodiment further includes: The main control chip controls the switching switch to turn on the communication link between the first pin and the CPU, and disconnect the communication link between the second pin and the CPU, wherein the communication link between the first pin and the CPU is used to transmit data or signals of the currently available communication protocol, and the second pin or other pins are used to establish a communication link of the SVI3 and / or AVSBUS protocol with the CPU.

[0107] The CPU communicates with the communication module according to the currently available communication protocol, including: transmitting a clock signal and a digital signal on the communication link between the first pin and the CPU according to the currently available communication protocol.

[0108] Specifically, the detailed process of the above method refers to the description of the above embodiment, and this embodiment will not be repeated here.

[0109] In the present embodiment, a communication module is also provided, and the communication module is used to implement the above-mentioned embodiment and preferred implementation mode, and the description has been made no further. As used below, the term "module" can implement a combination of software and / or hardware of a predetermined function. Although the device described in the following embodiments is preferably implemented in software, the implementation of hardware, or a combination of software and hardware is also possible and conceived.

[0110] This embodiment provides a communication module, such as Figure 8 As shown, the communication module includes: a receiving unit 810, a determining unit 820, and a sending unit 830. In addition, the communication module may also include other more or fewer modules, such as a storage module, etc., which is not limited in this embodiment.

[0111] The receiving unit 810 is configured to receive indication information including a CPU type sent by a baseboard management controller, and obtain the CPU type according to the indication information.

[0112] The determination unit 820 is used to determine a currently available communication protocol among at least two power supply communication protocols according to the CPU type, and communicate with the CPU according to the currently available communication protocol.

[0113] Specifically, the sending unit 830 is used to send the selected message of the currently available communication protocol to the CPU through the BMC, so that the CPU communicates with the communication module according to the currently available communication protocol, and uses the computing module and the driving module to power the CPU.

[0114] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

[0115] The communication module in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0116] The embodiment of the present invention also provides a main control chip having the above Figure 4 , Figure 5 , Figure 6 and Figure 8 Communication module shown.

[0117] Specifically, Figure 4 As shown, the main control chip includes: a communication module, a computing module and a driving module; wherein the computing module is connected to the communication module and the driving module respectively, the communication module is connected to the external BMC and the CPU respectively, and the driving module is also connected to the CPU.

[0118] The communication module is a flexibly adjustable code chip, such as an ARM architecture chip circuit, and the communication module is pre-implanted with codes of at least two power communication protocols to provide multi-power communication functions for the computing module. The communication module is used to execute the aforementioned Figure 7 The CPU power supply method shown.

[0119] Specifically, the communication module is used to determine a currently available communication protocol among at least two power supply communication protocols according to the CPU type, and communicate with the CPU according to the currently available communication protocol.

[0120] The calculation module is used to receive the voltage regulation instruction from the CPU during the communication process, generate the driving instruction according to the voltage regulation instruction, and send the driving instruction to the driving module.

[0121] The driving module is used to receive driving instructions, generate modulation signals, and send the modulation signals to the power conversion circuit, so that the power conversion circuit adjusts the external input voltage according to the modulation signals and outputs it to the CPU to power the CPU.

[0122] Furthermore, the communication module also includes a register, and the register is used to store at least two power communication protocols and a bit identifier corresponding to each power communication protocol.

[0123] In addition, the communication module provided in this embodiment also includes: a plurality of pins and a switching switch, wherein the plurality of pins includes at least a first pin and a second pin. A communication link is established between the first pin and the CPU, and is used to communicate with the main control chip according to the currently available communication protocol; a communication link is established between the second pin and the CPU, and the link is used to communicate with the main control chip according to other communication protocols, and the other communication protocols are protocols other than the currently available communication protocol in at least two power supply communication protocols. The switching switch is used to disconnect or conduct at least one communication link.

[0124] The functions of each module are described in the above embodiments and will not be repeated here.

[0125] In addition, in this embodiment, the CPU may be a central processing unit. The CPU may further include a hardware chip. The hardware chip may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic or any combination thereof.

[0126] In the communication module, the computing module may also be a processing circuit or a processing module, and may be a programmable logic device or a complex programmable logic device.

[0127] In addition, the communication module also includes a storage module or a storage unit, which may include a program storage area and a data storage area, wherein the program storage area may store an operating system and an application required for at least one function; the data storage area may store data created according to the use of the computer device, etc. In addition, the storage module or the storage unit may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage devices.

[0128] In addition, the registers in the communication module may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid state drive.

[0129] In addition, the above-mentioned main control chip also includes a plurality of pins or tube pins, and at least one communication interface for communicating with other devices or modules.

[0130] An embodiment of the present invention also provides a computer-readable storage medium, and the above-mentioned method according to the embodiment of the present invention can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented by downloading through a network and originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware.

[0131] The storage medium may be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid state drive, etc.; further, the storage medium may also include a combination of the above-mentioned types of memories. It is understood that a computer, a processor, a microprocessor controller or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by the computer, processor or hardware, the method shown in the above embodiment is implemented.

[0132] Embodiments of the present application may also provide a computer program product, including computer program instructions, which, when executed by a processor, cause the processor to perform the steps in the above method. Wherein, the computer program product may be written in any combination of one or more programming languages ​​to perform program codes for performing the operations of the disclosed embodiments, wherein the programming languages ​​include object-oriented programming languages, such as Java, C++, etc., and also include conventional procedural programming languages, such as "C" language or similar programming languages. The program code may be executed entirely on a user computing device, partially on a user device, as an independent software package, partially on a user computing device, partially on a remote computing device, or entirely on a remote computing device or server.

[0133] The above embodiments are only used to illustrate the technical solutions of the embodiments of the present invention, rather than to limit them. Although the embodiments of the present invention are described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some of the technical features therein by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A CPU power supply circuit, characterized in that: The CPU power supply circuit includes a main control chip, a CPU and a power conversion circuit, wherein; The main control chip is integrated with codes of at least two power communication protocols, and is used to provide the CPU with communication functions of multiple power communication protocols; The main control chip is used to determine a currently available communication protocol among at least two power supply communication protocols according to the CPU type, and communicate with the CPU according to the currently available communication protocol; The main control chip is also used to receive a voltage regulation instruction from the CPU during the communication process, generate a modulation signal according to the voltage regulation instruction, and send the modulation signal to the power conversion circuit; The power conversion circuit is used to receive the modulation signal, adjust the external input voltage according to the modulation signal, and output it to the CPU to supply power to the CPU.

2. The CPU power supply circuit according to claim 1, characterized in that: The main control chip is also used to update the bit identifier corresponding to the currently available communication protocol after determining the currently available communication protocol. The bit identifier has a unique corresponding relationship with the currently available communication protocol and is used to indicate the currently used power supply communication protocol.

3. The CPU power supply circuit according to claim 1, characterized in that: The main control chip is connected to the CPU via a plurality of pins and a switch, wherein the plurality of pins at least include a first pin and a second pin; The main control chip is also used to control the switching switch to connect the communication link between the first pin and the CPU, and disconnect the communication link between the second pin and the CPU, wherein the communication link between the first pin and the CPU is used to transmit data or signals of the currently available communication protocol.

4. The CPU power supply circuit according to claim 3, characterized in that: The main control chip is also used to transmit a clock signal and a digital signal on the communication link between the first pin and the CPU according to the currently available communication protocol.

5. The CPU power supply circuit according to any one of claims 1 to 4, characterized in that: The CPU power supply circuit also includes a baseboard management controller, which is connected to the main control chip and the CPU respectively; The baseboard management controller is used to communicate with the CPU, obtain the CPU type, and transmit the indication information containing the CPU type to the main control chip; The main control chip is further used to receive the indication information from the baseboard management controller, determine the CPU type according to the indication information, and after determining the currently available communication protocol according to the CPU type, return a message of the selected power communication protocol to the baseboard management controller; The baseboard management controller is further used to receive the selected message and forward it to the CPU.

6. The CPU power supply circuit according to claim 1, characterized in that: The power conversion circuit includes a voltage input terminal, a voltage output terminal, an enable terminal and a pulse width modulation terminal; wherein the voltage input terminal is connected to the power supply, the voltage output terminal is connected to the CPU, and the enable terminal and the pulse width modulation terminal are respectively connected to the main control chip; The main control chip is further used to send an enable signal to the enable end of the power conversion circuit, and to send the modulation signal to the pulse width modulation end; The power conversion circuit is further used to adjust the voltage according to the enable signal and the modulation signal, and output the adjusted voltage to the CPU.

7. The CPU power supply circuit according to claim 6, characterized in that: The power conversion circuit further includes a third pin and a fourth pin, and the third pin and the fourth pin are both connected to the main control chip; The power conversion circuit is further used to transmit the collected CPU current information to the main control chip through the third pin, and to transmit the collected CPU temperature information to the main control chip through the fourth pin; The main control chip is also used to receive and detect whether one or more of the current information and the temperature information is within a preset value range, and if it is within the preset value range, feed back an instruction of voltage regulation completion to the CPU.

8. The CPU power supply circuit according to claim 6, characterized in that: The at least two power supply communication protocols include: at least two of SVID, SVI3 and AVSBUS.

9. A CPU power supply method, characterized in that: The method is applied to a main control chip according to any one of claims 1 to 8, wherein the main control chip integrates codes of at least two power communication protocols and is used to provide a CPU with communication functions of multiple power communication protocols, and the method comprises: Get the CPU type; Determining a currently available communication protocol among at least two power supply communication protocols according to the CPU type, and communicating with the CPU according to the currently available communication protocol; During the communication process, a voltage regulation instruction is received from the CPU, a modulation signal is generated according to the voltage regulation instruction, and the modulation signal is sent to the power conversion circuit. The power conversion circuit is used to adjust the external input voltage according to the modulation signal and output it to the CPU to power the CPU.

10. The method according to claim 9, characterized in that The method further comprises: After determining the currently available communication protocol, the bit identifier corresponding to the currently available communication protocol is updated, the bit identifier has a unique corresponding relationship with the currently available communication protocol and is used to indicate the currently used power supply communication protocol.

11. The method according to claim 9, characterized in that The main control chip is connected to the CPU via a plurality of pins and a switch, wherein the plurality of pins at least include a first pin and a second pin, and the method further includes: The switching switch is controlled to connect the communication link between the first pin and the CPU and disconnect the communication link between the second pin and the CPU, wherein the communication link between the first pin and the CPU is used to transmit data or signals of the currently available communication protocol.

12. The method according to claim 11, characterized in that The communicating with the CPU according to the currently available communication protocol includes: According to the currently available communication protocol, a clock signal and a digital signal are transmitted on the communication link between the first pin and the CPU.

13. A main control chip, characterized in that: The main control chip includes: a communication module, a computing module and a driving module; wherein the computing module is connected to the communication module and the driving module respectively, the communication module is connected to an external baseboard management controller and a CPU respectively, and the driving module is also connected to the CPU; Wherein, the communication module integrates codes of at least two power communication protocols, and is used to provide the CPU with communication functions of multiple power communication protocols; The communication module is used to determine a currently available communication protocol among at least two power supply communication protocols according to the CPU type, and communicate with the CPU according to the currently available communication protocol; The calculation module is used to receive the voltage regulation instruction from the CPU during the communication process, generate a driving instruction according to the voltage regulation instruction, and send the driving instruction to the driving module; The driving module is used to receive the driving instruction, generate a modulation signal, and send the modulation signal to the power conversion circuit, so that the power conversion circuit adjusts the external input voltage according to the modulation signal and outputs it to the CPU to power the CPU.

14. The main control chip according to claim 13, characterized in that: The communication module further includes a register, and the register is used to store at least two power communication protocols and a bit identifier corresponding to each power communication protocol.

15. The main control chip according to claim 13 or 14, characterized in that: The communication module further includes a plurality of pins and a switch, wherein the plurality of pins includes at least a first pin and a second pin; A communication link is established between the first pin and the CPU for communicating with the main control chip according to the currently available communication protocol; A communication link is established between the second pin and the CPU for communicating with the main control chip according to other communication protocols, wherein the other communication protocols are protocols other than the currently available communication protocol among at least two power supply communication protocols; The switching switch is used to disconnect or connect the communication link.

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