Memory control method and memory storage device

Abstract

The present application provides a memory control method and a memory storage device, which can prolong the service life and ensure the data reliability. The memory control method is used in a rewritable non-volatile memory module. The rewritable non-volatile memory module includes a plurality of physical units. The memory control method includes: when an error occurs in a target operation performed on a first physical unit, obtaining the execution times of the first physical unit; if the execution times and the operation type of the target operation indicate that the first physical unit meets a first preset condition, determining whether the first physical unit is of a third type; if the first physical unit is not of the third type and the execution times indicate that the first physical unit meets a second preset condition, determining whether the first physical unit is of a second type; and if the first physical unit is not of the second type, marking the first physical unit as the second type.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of storage, and in particular to a memory control method and a memory storage device. BACKGROUND

[0002] In recent years, with the rapid progress of electronic product technology, consumers' experience requirements for electronic storage products are increasing, and the market demand for higher speed and more convenient storage solutions is also growing. NAND flash memory (FLASH) has shown outstanding advantages in mobile application fields such as mobile phones and smart sensing devices due to its characteristics such as data non-volatility, low power consumption, compact design, no moving parts, and fast read-write speed.

[0003] With the rapid evolution of flash memory technology, NAND flash memory has undergone a transition from two-dimensional (2D) to three-dimensional (3D), and on the storage unit, it has evolved from single-layer storage unit (SLC) to three-layer (TLC) and even four-layer (QLC) storage unit. This series of technological innovations has greatly improved the storage density of NAND flash memory and reduced the cost per unit capacity. However, as the thickness of the internal oxide layer of the flash memory continues to thin, the impact of the erase-write operation on the storage medium becomes more significant, affecting the durability and reliability of the flash memory.

[0004] In view of this, how to effectively manage NAND flash memory has become one of the core issues that engineers in the industry are concerned about. SUMMARY

[0005] The exemplary embodiments of the present application provide a memory control method and a memory storage device, which can extend the service life of the memory storage device while ensuring data reliability, further improve the overall performance and stability of the system, and ensure users to obtain a more smooth and reliable use experience.

[0006] An exemplary embodiment of the present invention provides a memory control method for a rewritable non-volatile memory module. The rewritable non-volatile memory module includes a plurality of physical units, and the plurality of physical units are respectively marked as a first type, a second type, a third type, or a fourth type. The memory control method includes: when an error occurs in a target operation performed on a first physical unit, obtaining the number of executions of the first physical unit; if the number of executions and the operation type of the target operation indicate that the first physical unit meets a first preset condition, determining whether the first physical unit is of the third type; if the first physical unit is not of the third type and the number of executions indicates that the first physical unit meets a second preset condition, determining whether the first physical unit is of the second type; and if the first physical unit is not of the second type, marking the first physical unit as the second type.

[0007] In an exemplary embodiment of the present invention, the first preset condition includes: the target operation is not a read operation, or the target operation is the read operation and the execution count is not greater than a read threshold, wherein the execution count is the read count.

[0008] In an exemplary embodiment of the present invention, the second preset condition includes: the execution count is not greater than an erase threshold, wherein the execution count is an erase count.

[0009] In an exemplary embodiment of the present invention, before the step of obtaining the execution number of the first physical unit, it also includes: determining whether the operating temperature or operating voltage corresponding to the target operation is abnormal; and if at least one of the operating temperature and the operating voltage is abnormal, temporarily not marking the first physical unit.

[0010] In an exemplary embodiment of the present invention, the memory control method further includes: temporarily not marking the first physical unit if the execution count and the operation type of the target operation indicate that the first physical unit does not meet the first preset condition.

[0011] In an exemplary embodiment of the present invention, the memory control method further includes: if the first physical unit is of the third type, marking the first physical unit as the fourth type.

[0012] In an exemplary embodiment of the present invention, the memory control method further includes: if the first physical unit is not of the third type and the execution count indicates that the first physical unit does not meet the second preset condition, marking the first physical unit as the third type.

[0013] In an exemplary embodiment of the present invention, the step of marking the first physical unit as the third type includes: determining whether the target operation is a read operation; if the target operation is a read operation, marking the first physical unit as the third type.

[0014] In an exemplary embodiment of the present invention, the memory control method further includes: if the target operation is not a read operation, marking the first physical unit as the fourth type.

[0015] In an exemplary embodiment of the present invention, the memory control method further includes: if the first physical unit is of the second type, marking the first physical unit as the third type.

[0016] In an exemplary embodiment of the present invention, the memory control method further includes: in an idle state, performing a target test operation on the first physical unit marked as the second type based on the access mode of the first physical unit marked as the second type; and if the target test operation is successful, re-marking the first physical unit marked as the second type as the first type.

[0017] In an exemplary embodiment of the present invention, the memory control method further includes: if the target test operation fails and the access mode is a single-level memory cell access mode, marking the first physical cell marked as the second type as the fourth type.

[0018] In an exemplary embodiment of the present invention, the memory control method further includes: if the target test operation fails and the access mode is not the single-level memory cell access mode, marking the first physical cell marked as the second type as the third type.

[0019] In an exemplary embodiment of the present invention, the operation type is used to indicate that the target operation is an erase operation, a write operation, or a read operation.

[0020] In an exemplary embodiment of the present invention, the plurality of solid elements are initially all of the first type.

[0021] In an exemplary embodiment of the present invention, the first physical cell marked as the third type can only be used in a single-level memory cell access mode.

[0022] An exemplary embodiment of the present application further provides a memory storage device, which includes a connection interface unit, a rewritable nonvolatile memory module, and a memory control circuit unit. The memory control circuit unit is coupled to the connection interface unit and the rewritable nonvolatile memory module. The connection interface unit is used to be coupled to a host system. The rewritable nonvolatile memory module includes a plurality of physical units, and the plurality of physical units are respectively marked as a first type, a second type, a third type, or a fourth type. When an error occurs in a target operation performed on a first physical unit, the memory control circuit unit is used to acquire a number of executions of the first physical unit. If the number of executions and an operation type of the target operation indicate that the first physical unit satisfies a first preset condition, the memory control circuit unit is further used to determine whether the first physical unit is of the third type. If the first physical unit is not of the third type and the number of executions indicates that the first physical unit satisfies a second preset condition, the memory control circuit unit is further used to determine whether the first physical unit is of the second type. If the first physical unit is not of the second type, the memory control circuit unit is further used to mark the first physical unit as the second type.

[0023] In an exemplary embodiment of the present application, before the memory control circuit unit acquires the number of executions of the first physical unit, the memory control circuit unit is further used to determine whether an operation temperature or an operation voltage corresponding to the target operation is abnormal. If at least one of the operation temperature and the operation voltage is abnormal, the memory control circuit unit is further used to temporarily not mark the first physical unit.

[0024] In an exemplary embodiment of the present application, if the number of executions and the operation type of the target operation indicate that the first physical unit does not satisfy the first preset condition, the memory control circuit unit is further used to temporarily not mark the first physical unit.

[0025] In an exemplary embodiment of the present application, if the first physical unit is of the third type, the memory control circuit unit is further used to mark the first physical unit as the fourth type.

[0026] In an exemplary embodiment of the present application, if the first physical unit is not of the third type and the number of executions indicates that the first physical unit does not satisfy the second preset condition, the memory control circuit unit is further used to mark the first physical unit as the third type.

[0027] In an example embodiment of this disclosure, wherein the memory control circuitry is further configured to determine whether the target operation is a read operation. If the target operation is a read operation, the memory control circuitry is further configured to mark the first physical unit as the third type.

[0028] In an example embodiment of this disclosure, wherein if the target operation is not a read operation, the memory control circuitry is further configured to mark the first physical unit as the fourth type.

[0029] In an example embodiment of this disclosure, wherein if the first physical unit is of the second type, the memory control circuitry is further configured to mark the first physical unit as the third type.

[0030] In an example embodiment of this disclosure, wherein in an idle state, the memory control circuitry is further configured to perform a target test operation on the first physical unit marked as the second type based on an access mode of the first physical unit marked as the second type. If the target test operation is successful, the memory control circuitry is further configured to re-mark the first physical unit marked as the second type as the first type.

[0031] In an example embodiment of this disclosure, wherein if the target test operation is unsuccessful and the access mode is a single-level cell access mode, the memory control circuitry is further configured to mark the first physical unit marked as the second type as the fourth type.

[0032] In an example embodiment of this disclosure, wherein if the target test operation is unsuccessful and the access mode is not the single-level cell access mode, the memory control circuitry is further configured to mark the first physical unit marked as the second type as the third type.

[0033] Based on the above, the present disclosure provides a memory control method and a memory storage device. When an environmental factor is abnormal, the memory storage device does not immediately mark a physical unit corresponding to a target operation with an error as a bad physical unit, thereby avoiding the problem of false marking. The memory storage device performs a classification management mechanism according to the actual usage of the physical unit corresponding to the target operation with an error, thereby prolonging the service life of the memory storage device while ensuring data reliability.

[0034] In order to make the above features and advantages of the present disclosure more apparent, specific examples are described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0035] Figure 1is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device shown in accordance with an example embodiment of the present invention;

[0036] Figure 2 is a schematic diagram of a host system, a memory storage device, and an I / O device shown in accordance with an example embodiment of the present invention;

[0037] Figure 3 is a schematic diagram of a host system and a memory storage device shown in accordance with an example embodiment of the present invention;

[0038] Figure 4 is a schematic diagram of a memory storage device shown in accordance with an example embodiment of the present invention;

[0039] Figure 5 is a schematic diagram of a memory control circuit unit shown in accordance with an example embodiment of the present invention;

[0040] Figure 6 is a schematic diagram of a management rewritable non-volatile memory module shown in accordance with an example embodiment of the present invention;

[0041] Figure 7 is a flowchart of a memory control method shown in accordance with an example embodiment of the present invention;

[0042] Figure 8 is a flowchart of a memory control method shown in accordance with an example embodiment of the present invention;

[0043] Figure 9 is a flowchart of a memory control method shown in accordance with an example embodiment of the present invention;

[0044] Figure 10 is a flowchart of a memory control method for an entity under inspection shown in accordance with an example embodiment of the present invention. DETAILED DESCRIPTION

[0045] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

[0046] Generally speaking, a memory storage device (also referred to as a memory storage system) includes a rewritable non-volatile memory module and a controller (also referred to as a control circuit). The memory storage device can be used with a host system so that the host system can write data to or read data from the memory storage device.

[0047] Figure 1 FIG. 1 is a schematic diagram illustrating a host system, a memory storage device, and an input / output (I / O) device according to an exemplary embodiment of the present invention. Figure 2 FIG. 1 is a schematic diagram illustrating a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention.

[0048] Please refer to Figure 1 and Figure 2 The host system 11 may include a processor 111 , a random access memory (RAM) 112 , a read only memory (ROM) 113 , and a data transmission interface 114 . The processor 111 , the RAM 112 , the ROM 113 , and the data transmission interface 114 may be coupled to a system bus 110 .

[0049] In one exemplary embodiment, the host system 11 may be coupled to the memory storage device 10 via a data transfer interface 114. For example, the host system 11 may store data in the memory storage device 10 or read data from the memory storage device 10 via the data transfer interface 114. Furthermore, the host system 11 may be coupled to the I / O device 12 via a system bus 110. For example, the host system 11 may transmit output signals to the I / O device 12 or receive input signals from the I / O device 12 via the system bus 110.

[0050] In one exemplary embodiment, the processor 111, the random access memory 112, the read-only memory 113, and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11. The number of the data transmission interface 114 may be one or more. Through the data transmission interface 114, the motherboard 20 may be coupled to the memory storage device 10 via a wired or wireless method.

[0051] In one exemplary embodiment, the memory storage device 10 may be, for example, a flash drive 201, a memory card 202, a solid-state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 may be, for example, a near field communication (NFC) memory storage device, a Wi-Fi (WiFi) memory storage device, a Bluetooth memory storage device, or a low-power Bluetooth memory storage device (e.g., iBeacon), or other memory storage devices based on various wireless communication technologies. Furthermore, the motherboard 20 may also be coupled to various I / O devices, such as a global positioning system (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a display 209, and a speaker 210, via the system bus 110. For example, in one exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.

[0052] In one exemplary embodiment, the host system 11 is a computer system. In one exemplary embodiment, the host system 11 can be any system that can substantially cooperate with a memory storage device to store data. In one exemplary embodiment, the host system 11 is a vehicle-mounted system. In one exemplary embodiment, the memory storage device 10 and the host system 11 can each include Figure 3 The memory storage device 30 and the host system 31 are connected.

[0053] Figure 3 FIG. 1 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention.

[0054] Please refer to Figure 3 , the memory storage device 30 can be used in conjunction with a host system 31 to store data. For example, the host system 31 can be a system such as a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer. For example, the memory storage device 30 can be various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34 used by the host system 31. The embedded storage device 34 includes various types of embedded storage devices that directly couple the memory module to the substrate of the host system, such as an embedded Multi Media Card (eMMC) 341 and / or an embedded Multi Chip Package (eMCP) storage device 342.

[0055] Figure 4 FIG. 1 is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention.

[0056] Please refer to Figure 4 The memory storage device 10 includes a connection interface unit 41 , a memory control circuit unit 42 and a rewritable non-volatile memory module 43 .

[0057] The connection interface unit 41 is used to couple the memory storage device 10 to the host system 11. The memory storage device 10 can communicate with the host system 11 via the connection interface unit 41. In one exemplary embodiment, the connection interface unit 41 is compatible with the Peripheral Component Interconnect Express (PCI Express) standard. In an exemplary embodiment, the connection interface unit 41 may also comply with the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (UFS) interface standard, the eMCP interface standard, the CF interface standard, the Integrated Device Electronics (IDE) standard, or other suitable standards. The connection interface unit 41 and the memory control circuit unit 42 may be packaged in one chip, or the connection interface unit 41 may be disposed outside a chip including the memory control circuit unit 42 .

[0058] The memory control circuit unit 42 is coupled to the connection interface unit 41 and the rewritable nonvolatile memory module 43. The memory control circuit unit 42 is used to execute a plurality of logic gates or control instructions implemented in a hardware type or a firmware type and perform operations such as writing, reading, and erasing data in the rewritable nonvolatile memory module 43 according to instructions of the host system 11.

[0059] The rewritable nonvolatile memory module 43 is used to store data written by the host system 11. The rewritable nonvolatile memory module 43 can include a single level cell (SLC) NAND type flash memory module (i.e., a flash memory module in which one storage cell can store one bit), a multi level cell (MLC) NAND type flash memory module (i.e., a flash memory module in which one storage cell can store two bits), a triple level cell (TLC) NAND type flash memory module (i.e., a flash memory module in which one storage cell can store three bits), a quad level cell (QLC) NAND type flash memory module (i.e., a flash memory module in which one storage cell can store four bits), other flash memory modules, or other memory modules with the same characteristics.

[0060] Each storage cell in the rewritable nonvolatile memory module 43 stores one or more bits by changing a voltage (hereinafter also referred to as a threshold voltage). Specifically, there is a charge trapping layer between a control gate and a channel of each storage cell. By applying a write voltage to the control gate, the amount of electrons of the charge trapping layer can be changed, thereby changing the threshold voltage of the storage cell. This operation of changing the threshold voltage of the storage cell is also referred to as "writing data to the storage cell" or "programming the storage cell". With the change in the threshold voltage, each storage cell in the rewritable nonvolatile memory module 43 has a plurality of storage states. By applying a read voltage, it can be determined which storage state a storage cell belongs to, thereby obtaining one or more bits stored in the storage cell.

[0061] In one exemplary embodiment, the memory cells of the rewritable non-volatile memory module 43 may constitute a plurality of physical programming cells, and these physical programming cells may constitute a plurality of physical cells. Specifically, the memory cells on the same word line may constitute one or more physical programming cells. If each memory cell can store more than two bits, the physical programming cells on the same word line may be classified into at least a lower physical programming cell and an upper physical programming cell. For example, the least significant bit (LSB) of a memory cell belongs to the lower physical programming cell, and the most significant bit (MSB) of a memory cell belongs to the upper physical programming cell. Generally speaking, in an MLC NAND flash memory, the write speed of the lower physical programming cell is greater than the write speed of the upper physical programming cell, and / or the reliability of the lower physical programming cell is higher than the reliability of the upper physical programming cell.

[0062] In one exemplary embodiment, a physical programming unit is the smallest unit of programming. That is, a physical programming unit is the smallest unit for writing data. For example, a physical programming unit may be a physical page or a physical sector. If a physical programming unit is a physical page, then these physical programming units may include a data bit area and a redundancy bit area. The data bit area includes multiple physical sectors for storing user data, while the redundancy bit area is used to store system data (e.g., management data such as error correction codes). In this exemplary embodiment, the data bit area includes 32 physical sectors, and the size of each physical sector is 512 bytes (bytes). However, in other exemplary embodiments, the data bit area may include 8, 16, or a larger or smaller number of physical sectors, and the size of each physical sector may also be larger or smaller. On the other hand, a physical unit is the smallest unit of erasure. That is, each physical unit contains the minimum number of storage cells that are erased together. For example, a physical unit is a physical block.

[0063] Figure 5 FIG. 1 is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention.

[0064] Please refer to Figure 5 The memory control circuit unit 42 includes a memory management circuit 51 , a host interface 52 and a memory interface 53 .

[0065] The memory management circuit 51 is used to control the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has a plurality of control instructions, and when the memory storage device 10 is in operation, these control instructions are executed to perform operations such as writing, reading, and erasing data. The following description of the operation of the memory management circuit 51 is equivalent to the description of the operation of the memory control circuit unit 42.

[0066] In one exemplary embodiment, the control instructions of the memory management circuit 51 are implemented in firmware. For example, the memory management circuit 51 includes a microprocessor unit (not shown) and a read-only memory (ROM) (not shown), and these control instructions are recorded into the ROM. When the memory storage device 10 is operating, these control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

[0067] In one exemplary embodiment, the control instructions of the memory management circuit 51 may also be stored in code form in a specific area of ​​the rewritable non-volatile memory module 43 (e.g., a system area of ​​the memory module dedicated to storing system data). Furthermore, the memory management circuit 51 includes a microprocessor unit (not shown), a read-only memory (not shown), and a random access memory (RAM) (not shown). Specifically, the ROM includes a boot code. When the memory control circuit unit 42 is enabled, the microprocessor unit first executes this boot code to load the control instructions stored in the rewritable non-volatile memory module 43 into the RAM of the memory management circuit 51. The microprocessor unit then executes these control instructions to perform operations such as writing, reading, and erasing data.

[0068] In one exemplary embodiment, the control instructions of the memory management circuit 51 can also be implemented in hardware. For example, the memory management circuit 51 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, the memory write circuit, the memory read circuit, the memory erase circuit, and the data processing circuit are coupled to the microcontroller. The memory cell management circuit is used to manage the memory cells or groups of memory cells in the rewritable non-volatile memory module 43. The memory write circuit is used to issue a write command sequence to the rewritable non-volatile memory module 43 to write data to the rewritable non-volatile memory module 43. The memory read circuit is used to issue a read command sequence to the rewritable non-volatile memory module 43 to read data from the rewritable non-volatile memory module 43. The memory erase circuit is used to issue an erase command sequence to the rewritable non-volatile memory module 43 to erase data from the rewritable non-volatile memory module 43. The data processing circuit is used to process data to be written to the rewritable non-volatile memory module 43 and data to be read from the rewritable non-volatile memory module 43. The write command sequence, read command sequence, and erase command sequence may each include one or more codes or instruction codes and are used to instruct the rewritable non-volatile memory module 43 to perform corresponding write, read, and erase operations. In an exemplary embodiment, the memory management circuit 51 may also issue other types of command sequences to the rewritable non-volatile memory module 43 to instruct it to perform corresponding operations.

[0069] The host interface 52 is coupled to the memory management circuit 51. The memory management circuit 51 can communicate with the host system 11 through the host interface 52. The host interface 52 can be used to receive and identify instructions and data transmitted by the host system 11. For example, the instructions and data transmitted by the host system 11 can be transmitted to the memory management circuit 51 through the host interface 52. In addition, the memory management circuit 51 can transmit data to the host system 11 through the host interface 52. In this exemplary embodiment, the host interface 52 is compatible with the PCI Express standard. However, it should be understood that the present invention is not limited to this, and the host interface 52 can also be compatible with the SATA standard, the PATA standard, the IEEE 1394 standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, the MS standard, the MMC standard, the eMMC standard, the UFS standard, the CF standard, the IDE standard, or other suitable data transmission standards.

[0070] The memory interface 53 is coupled to the memory management circuit 51 and is used to access the rewritable non-volatile memory module 43. For example, the memory management circuit 51 can access the rewritable non-volatile memory module 43 through the memory interface 53. That is, data to be written to the rewritable non-volatile memory module 43 is converted into a format acceptable to the rewritable non-volatile memory module 43 via the memory interface 53. Specifically, if the memory management circuit 51 wants to access the rewritable non-volatile memory module 43, the memory interface 53 will transmit a corresponding command sequence. For example, these command sequences may include a write command sequence instructing to write data, a read command sequence instructing to read data, an erase command sequence instructing to erase data, and corresponding command sequences for instructing various memory operations (e.g., changing a read voltage level or performing a garbage collection operation). These command sequences are generated by the memory management circuit 51 and transmitted to the rewritable non-volatile memory module 43 through the memory interface 53. These command sequences may include one or more signals or data on a bus. These signals or data may include instruction codes or codes. For example, in a read instruction sequence, information such as a read identification code, a memory address, etc. may be included.

[0071] In an exemplary embodiment, the memory control circuit unit 42 further includes an error checking and correction circuit 54 , a buffer memory 55 , and a power management circuit 56 .

[0072] The ECC circuit 54 is coupled to the memory management circuit 51 and is configured to perform error checking and correction operations to ensure data accuracy. Specifically, when the memory management circuit 51 receives a write command from the host system 11, the ECC circuit 54 generates an error correcting code (ECC) and / or an error detecting code (EDC) for the data corresponding to the write command. The memory management circuit 51 then writes the data corresponding to the write command and the corresponding ECC and / or EDC into the rewritable non-volatile memory module 43. Subsequently, when the memory management circuit 51 reads data from the rewritable non-volatile memory module 43, it simultaneously reads the ECC and / or EDC corresponding to the data. The ECC circuit 54 then performs error checking and correction operations on the read data based on the ECC and / or EDC.

[0073] The buffer memory 55 is coupled to the memory management circuit 51 and is used to temporarily store data. The power management circuit 56 is coupled to the memory management circuit 51 and is used to control the power supply of the memory storage device 10 .

[0074] In one exemplary embodiment, Figure 4 The rewritable non-volatile memory module 43 may include a flash memory module. In one exemplary embodiment, Figure 4 The memory control circuit unit 42 may include a flash memory controller. In one exemplary embodiment, Figure 5 The memory management circuit 51 may include a flash memory management circuit.

[0075] Figure 6 FIG. 1 is a schematic diagram showing management of a rewritable non-volatile memory module according to an exemplary embodiment of the present invention.

[0076] Please refer to Figure 6 The memory management circuit 51 may logically group the physical units 610(0)-610(B) in the rewritable non-volatile memory module 43 into a storage area 601 and a spare area 602. A physical unit is a virtual block (VB). A virtual block may include multiple physical programming units. For example, a virtual block may include one or more physical units.

[0077] The physical units 610(0)-610(A) in the storage area 601 are used to store user data (e.g. Figure 1 user data of the host system 11). For example, the physical units 610(0) to 610(A) in the storage area 601 can store valid data and invalid data. The physical units 610(A+1) to 610(B) in the idle area 602 do not store data (e.g., valid data). For example, if a physical unit does not store valid data, the physical unit can be associated (or added) to the idle area 602. In addition, the physical units in the idle area 602 (or the physical units that do not store valid data) can be erased. When writing new data, one or more physical units can be extracted from the idle area 602 to store the new data. In one exemplary embodiment, the idle area 602 is also called a free pool.

[0078] The memory management circuit 51 can configure logical units 612(0)-612(C) to map physical units 610(0)-610(A) in the storage area 601. In one exemplary embodiment, each logical unit corresponds to a logical address. For example, a logical address may include one or more logical block addresses (LBAs) or other logical management units.

[0079] It should be noted that one logical unit can be mapped to one or more physical units. If a physical unit is currently mapped by a logical unit, it means that the data packet currently stored in the physical unit contains valid data. On the contrary, if a physical unit is not currently mapped by any logical unit, it means that the data currently stored in the physical unit does not contain any valid data.

[0080] The memory management circuit 51 can record management data (also referred to as logical-to-physical mapping information) describing the mapping relationship between logical units and physical units in at least one logical-to-physical mapping table. When the host system 11 wants to read data from or write data to the memory storage device 10, the memory management circuit 51 can perform data access operations on the memory storage device 10 according to the information in the logical-to-physical mapping table.

[0081] When an error occurs in a data access operation, the conventional error handling method is to mark the physical unit corresponding to the data access operation as a bad physical unit and replace the physical unit to maintain the operation of the memory storage device 10. However, during the process of the memory management circuit 51 performing data access operations on the memory storage device 10, the memory storage device 10 can be affected by environmental factors (for example, abnormal operating voltage or abnormal temperature), which can cause errors in data access operations. In this case, the physical unit corresponding to the data access operation is not necessarily a damaged bad physical unit. The conventional error handling method can mistakenly mark the undamaged physical unit as a bad physical unit, which reduces the service life of the memory storage device 10.

[0082] To avoid the above problems, the present application provides a memory control method. When the memory storage device 10 is affected by environmental factors, the memory management circuit 51 can temporarily not mark the physical unit corresponding to the operation with an error as a bad physical unit to avoid the problem of mistaken marking, and establish a physical unit management mechanism for the physical units according to the actual operation of the rewritable non-volatile memory module 43. By classifying and marking the physical units in different use conditions, the service life of the memory storage device 10 is prolonged while ensuring data reliability and reducing the misjudgment of the classification of the physical units.

[0083] In one exemplary embodiment, the rewritable non-volatile memory module 43 may include multiple physical units, and the multiple physical units in the rewritable non-volatile memory module 43 are initially of the first type. That is, at the beginning of the life of the memory storage device 10, the multiple physical units in the rewritable non-volatile memory module 43 are all of the first type. As usage progresses, the multiple physical units in the rewritable non-volatile memory module 43 may be classified (or labeled) as the first type, the second type, the third type, or the fourth type based on actual usage.

[0084] For the definitions of the first type, the second type, the third type, and the fourth type, please refer to Table 1 below.

[0085]

[0086] Table 1

[0087] As shown in Table 1, the first and second types of physical cells can be used in various access modes. Access modes may include, but are not limited to, single-level cell (SLC) access mode, second-level cell (MLC) access mode, third-level cell (TLC) access mode, or fourth-level cell (QLC) access mode. The access modes supported by the memory storage device 10 depend on its specifications. In one exemplary embodiment, the first type of physical cell is also referred to as a good physical cell.

[0088] Furthermore, the second type of physical cell needs to be checked again in the idle state. That is, in the idle state, the memory management circuit 51 can perform a target test operation on a physical cell of the second type to determine whether the physical cell can be used for subsequent data access operations. In one exemplary embodiment, the second type of physical cell is also referred to as an inspected physical cell.

[0089] Furthermore, the third type of physical cell can only be used in a single-level memory cell access mode. In one exemplary embodiment, the third type of physical cell is also referred to as a weak physical cell.

[0090] Furthermore, the fourth type of physical unit is damaged and no longer used, that is, the fourth type of physical unit cannot be put into subsequent data access operations. In an exemplary embodiment, the fourth type of physical unit is also called a bad physical unit.

[0091] Figure 7 FIG is a flow chart of a memory control method according to an exemplary embodiment of the present invention. Figure 7When an error occurs in the target operation (eg, erase operation, write operation, or read operation) executed on the first physical unit, the memory management circuit 51 may, for example, execute the following Figure 7 The memory control method shown is used to extend the service life of the memory storage device 10.

[0092] In step S701 , when an error occurs in a target operation executed on a first entity unit, the execution count of the first entity unit is obtained.

[0093] In one exemplary embodiment, the execution count may include but is not limited to the read count (ReadCount) and erase count (PECount) of the first physical unit. Specifically, the memory management circuit 51 may obtain the execution count used to represent the actual usage status of the first physical unit and classify and mark the first physical unit accordingly.

[0094] In step S702 , if the execution times and the operation type of the target operation indicate that the first entity unit meets the first preset condition, it is determined whether the first entity unit is of the third type.

[0095] In one exemplary embodiment, the operation type can be used to characterize whether the target operation is an erase operation, a write operation, or a read operation. Specifically, the number of executions of the first physical unit and the operation type of the target operation can be used to indicate whether the first physical unit meets a first predetermined condition. In one exemplary embodiment, the first predetermined condition includes that the target operation is not a read operation, or that the target operation is a read operation and the number of reads of the first physical unit is not greater than a read threshold. If the target operation is not a read operation, or if the target operation is a read operation and the number of reads of the first physical unit is not greater than the read threshold, the memory management circuit 51 can further determine whether the first physical unit is of the third type (i.e., a weak physical unit in a relatively poor condition).

[0096] The read threshold may be related to the service life of the rewritable non-volatile memory module 43 or designed by the user according to actual needs, and the present invention is not limited thereto.

[0097] In step S703 , if the first entity unit is not of the third type and the execution count indicates that the first entity unit meets the second preset condition, it is determined whether the first entity unit is of the second type.

[0098] Specifically, the execution count of the first physical unit can be used to indicate whether the first physical unit meets a second predetermined condition. In one exemplary embodiment, the second predetermined condition includes the number of erases of the first physical unit being no greater than an erase threshold. If the first physical unit is not of the third type (i.e., the first physical unit is of the first type or the second type and in good condition) and the number of erases of the first physical unit is no greater than the erase threshold, the memory management circuit 51 can further determine whether the first physical unit is of the second type (i.e., a physical unit to be checked that is in good condition but has previously experienced an error).

[0099] The erasure threshold may be related to the service life of the rewritable non-volatile memory module 43 or may be designed by the user according to actual needs, and the present invention is not limited thereto.

[0100] In step S704 , if the first entity element is not of the second type, the first entity element is marked as the second type.

[0101] Specifically, if the first physical unit is neither of the third type nor of the second type (ie, the first physical unit is of the first type in good condition), the memory management circuit 51 may mark the first physical unit as the second type.

[0102] According to the above, if Figure 7 In the memory control method shown, the memory management circuit 51 can perform a classification management mechanism according to the actual usage status of the first physical unit, thereby extending the service life of the memory storage device 10 while ensuring data reliability.

[0103] Figure 8 FIG is a flow chart of a memory control method according to an exemplary embodiment of the present invention. Figure 8 . Figure 8 The memory control method shown is Figure 7 When an error occurs in the target operation executed on the first physical unit, the memory management circuit 51 may, for example, execute the following Figure 8 The memory control method shown is used to extend the service life of the memory storage device 10.

[0104] In step S801 , the memory management circuit 51 may determine whether an operating temperature or an operating voltage corresponding to a target operation is abnormal.

[0105] Specifically, the memory management circuit 51 can determine whether the target operation in which the error occurred is affected by environmental factors by determining whether the operating temperature or operating voltage corresponding to the target operation in which the error occurred is abnormal. If the operating temperature and / or operating voltage are abnormal, the process proceeds to step S802. Conversely, if both the operating temperature and operating voltage are normal, the process proceeds to step S803.

[0106] In step S802 , the memory management circuit 51 may temporarily not mark the first physical unit.

[0107] In one exemplary embodiment, if the operating temperature and / or operating voltage corresponding to the target operation are abnormal, it indicates that the memory management circuit 51 is interfered with by environmental factors when executing the target operation. Accordingly, when an error occurs in the target operation, the memory management circuit 51 may temporarily not mark the first physical unit corresponding to the operation (i.e., the memory management circuit 51 temporarily does not change the type of the first physical unit) to avoid the problem of unworn first physical units being mistakenly marked, thereby causing unnecessary reduction in the storage space of the rewritable non-volatile memory module 43.

[0108] In step S803 , the memory management circuit 51 may determine whether the first physical unit meets a first preset condition.

[0109] In one exemplary embodiment, the memory management circuit 51 may obtain the number of executions of a target operation by the first physical unit. The execution number may include, but is not limited to, the number of reads and erases of the first physical unit. The memory management circuit 51 may determine whether the first physical unit meets a first preset condition based on the execution number of the first physical unit and the operation type of the target operation, where the operation type may be used to indicate whether the target operation is an erase operation, a write operation, or a read operation. In other words, the execution number of the first physical unit and the operation type of the target operation may be used to indicate whether the first physical unit meets the first preset condition.

[0110] In an exemplary embodiment, the first preset condition includes that the target operation is not a read operation, or that the target operation is a read operation and the number of reads of the first physical unit is not greater than a read threshold.

[0111] The read threshold may be related to the service life of the rewritable non-volatile memory module 43 or designed by the user according to actual needs, and the present invention is not limited thereto.

[0112] If the execution count of the first physical unit and the operation type of the target operation indicate that the first physical unit does not meet the first preset condition (i.e., the target operation is a read operation and the read count is greater than the read threshold), then step S802 is entered and the memory management circuit 51 may temporarily not mark the first physical unit.

[0113] Specifically, a high read count for the first physical cell (i.e., a read count greater than a read threshold) only indicates that the first physical cell is frequently used, and does not indicate that the first physical cell is damaged. Therefore, the memory management circuit 51 may temporarily not change the type of the first physical cell to avoid unnecessary reduction in storage space of the rewritable non-volatile memory module 43 due to mislabeling.

[0114] On the contrary, if the execution count of the first physical unit and the operation type of the target operation indicate that the first physical unit meets the first preset condition, the process proceeds to step S804 , where the memory management circuit 51 determines whether the first physical unit is of the third type.

[0115] In an exemplary embodiment, the memory management circuit 51 may further determine whether the first physical cell that meets the first predetermined condition is a weak physical cell in a relatively poor condition.

[0116] If the first physical unit is of the third type, the process proceeds to step S805 , where the memory management circuit 51 may mark the first physical unit as of the fourth type.

[0117] Specifically, when an error occurs in a first physical cell in a poor condition (i.e., a first physical cell of the third type), the memory management circuit 51 may determine that the first physical cell is a damaged physical cell. Accordingly, the memory management circuit 51 may mark the first physical cell as the fourth type. In other words, the memory management circuit 51 may mark the first physical cell as a bad physical cell, so that the first physical cell is no longer used in subsequent data access operations to maintain data reliability.

[0118] On the contrary, if the first physical unit is not of the third type (ie, the first physical unit is of the first type or the second type in good condition), the process proceeds to step S806 , where the memory management circuit 51 further determines whether the first physical unit satisfies the second preset condition.

[0119] In an exemplary embodiment, the second preset condition includes that the number of erase times of the first physical unit is not greater than an erase threshold. In other words, the number of execution times of the first physical unit can be used to indicate whether the first physical unit meets the second preset condition.

[0120] The erasure threshold may be related to the service life of the rewritable non-volatile memory module 43 or may be designed by the user according to actual needs, and the present invention is not limited thereto.

[0121] If the execution count of the first physical unit indicates that the first physical unit does not meet the second preset condition (ie, the erase count of the first physical unit is greater than the erase threshold), the process proceeds to step S707 , where the memory management circuit 51 may mark the first physical unit as the third type.

[0122] Specifically, the first physical cell has a high erase count (i.e., the erase count is greater than the erase threshold), indicating that the first physical cell has been used multiple times. Therefore, when an error occurs in an operation corresponding to the first physical cell that has been used multiple times, the memory management circuit 51 may mark the first physical cell as a third type with a poorer condition.

[0123] In contrast, if the execution count of the first physical unit indicates that the first physical unit meets the second preset condition, the process proceeds to step S808 , where the memory management circuit 51 may further determine whether the first physical unit is of the second type.

[0124] If the first entity element is not of the second type, proceed to step S809.

[0125] On the contrary, if the first entity element is of the second type, the process proceeds to step S807.

[0126] Specifically, the first physical cell has a low erase count (i.e., the erase count is not greater than the erase threshold), indicating that the first physical cell has not been used multiple times. Therefore, when an error occurs in an operation corresponding to the first physical cell that has not been used multiple times, the memory management circuit 51 can further determine whether the first physical cell is of the first type or the second type, and accordingly perform corresponding marking on the first physical cell.

[0127] If the first physical unit is of the second type and is in good condition but has previously experienced an error, then in step S807 , the memory management circuit 51 may mark the first physical unit as the third type.

[0128] On the contrary, if the first physical unit is of the first type and is in good condition and has not experienced any error, then in step S809 , the memory management circuit 51 may mark the first physical unit as the second type.

[0129] It is worth mentioning that the second type of physical unit is the physical unit to be checked. In the idle state, the memory management circuit 51 can perform a target test operation on a physical unit of the second type to determine whether the physical unit can be used for subsequent data access operations, thereby improving data reliability.

[0130] According to the above, if Figure 8In the memory control method shown, when the memory is affected by environmental factors (i.e., abnormal operating temperature and / or abnormal operating voltage) or the first physical unit has a high number of read times, the memory management circuit 51 may temporarily not mark the first physical unit corresponding to the target operation where the error occurred as a bad physical unit, so as to avoid the problem of unnecessary reduction of storage space due to incorrect marking, and execute a classification management mechanism based on the actual usage status of the first physical unit, thereby extending the service life of the memory storage device 10 while ensuring data reliability.

[0131] Figure 9 FIG is a flow chart of a memory control method according to an exemplary embodiment of the present invention. Figure 9 . Figure 9 The memory control method shown is Figure 7 When an error occurs in the target operation executed on the first physical unit, the memory management circuit 51 can be used to perform the following Figure 9 The memory control method shown is used to extend the service life of the memory storage device 10.

[0132] In step S901 , the memory management circuit 51 may determine whether an operating temperature or an operating voltage corresponding to a target operation is abnormal, so as to determine whether the target operation in which the error occurs is interfered with by environmental factors.

[0133] If the operating temperature and / or operating voltage are abnormal (i.e., the erroneous target operation is interfered with by environmental factors), step S902 is entered, and the memory management circuit 51 may temporarily not mark the first physical unit to avoid the problem of unnecessary reduction of the storage space of the rewritable non-volatile memory module 43 due to erroneous marking.

[0134] On the contrary, if the operating temperature and the operating voltage are both normal (ie, the target operation in which the error occurs is not interfered with by environmental factors), the process proceeds to step S903 .

[0135] In step S903 , the memory management circuit 51 may determine whether the first physical unit meets a first preset condition.

[0136] In one exemplary embodiment, the memory management circuit 51 may obtain the execution count of the first physical unit. For example, the execution count may include, but is not limited to, the number of reads and erases of the first physical unit. The memory management circuit 51 may determine whether the first physical unit meets the first predetermined condition based on the execution count of the first physical unit and the operation type of the target operation, where the operation type may be used to indicate whether the target operation is an erase operation, a write operation, or a read operation.

[0137] In an example embodiment, if the target operation is a read operation and the read count of the first physical unit is greater than the read threshold, the memory management circuit 51 can determine that the first physical unit does not satisfy the first preset condition, and proceed to step S902. The memory management circuit 51 can temporarily not mark the first physical unit to avoid the problem of unnecessary reduction of storage space caused by false marking.

[0138] On the contrary, if the target operation is not a read operation, or the target operation is a read operation and the read count of the first physical unit is not greater than the read threshold, the memory management circuit 51 can determine that the first physical unit satisfies the first preset condition, and proceed to step S904. The memory management circuit 51 can determine whether the first physical unit is of the third type.

[0139] If the first physical unit is of the third type, which is in a poor condition, proceed to step S905. The memory management circuit 51 can mark the first physical unit as the fourth type, so that the first physical unit is no longer used in subsequent data access operations to maintain the reliability of the data.

[0140] On the contrary, if the first physical unit is not of the third type (i.e., the first physical unit is of the first type or the second type, which is in a good condition), proceed to step S906. The memory management circuit 51 can further determine whether the first physical unit satisfies the second preset condition.

[0141] If the erase count of the first physical unit is greater than the erase threshold, the memory management circuit 51 can determine that the first physical unit does not satisfy the second preset condition, and proceed to step S907. The memory management circuit 51 can determine whether the target operation is a read operation.

[0142] If the target operation is a read operation, proceed to step S909; on the contrary, if the target operation is not a read operation, proceed to step S905.

[0143] Specifically, the first physical unit has a high erase count (i.e., the erase count is greater than the erase threshold), which indicates that the first physical unit has been used many times. If the target operation that has occurred an error is a read operation, and the first physical unit has been used many times, in step S909, the memory management circuit 51 can mark the first physical unit as the third type.

[0144] The memory management circuit 51 can mark the first physical unit as the third type without marking the first physical unit that has been used many times and corresponds to the target operation that has occurred an error as the fourth type (i.e., a bad physical unit), in order to try to extend the service life of the memory storage device 10.

[0145] On the contrary, if the target operation in which the error occurs is an erase operation or a write operation, and the first physical unit has been used multiple times, then in step S905, the memory management circuit 51 may mark the first physical unit as the fourth type so that the first physical unit is no longer used in subsequent data access operations to maintain data reliability.

[0146] On the other hand, if the erase count of the first physical unit is not greater than the erase threshold, the memory management circuit 51 may determine that the first physical unit meets the second preset condition and proceed to step S908 , where the memory management circuit 51 may further determine whether the first physical unit is of the second type.

[0147] If the first entity element is of the second type, the process proceeds to step S909 ; otherwise, if the first entity element is not of the second type, the process proceeds to step S910 .

[0148] Specifically, the first physical unit has a low erase count (ie, the erase count is not greater than an erase threshold), which indicates that the first physical unit has not been used multiple times.

[0149] If the first physical unit is of the second type and is in good condition but has previously experienced an error, then in step S909 , the memory management circuit 51 may mark the first physical unit as the third type.

[0150] On the contrary, if the first physical unit is of the first type and is in good condition and has not experienced any error, then in step S909 , the memory management circuit 51 may mark the first physical unit as the second type.

[0151] According to the above, if Figure 9 In the memory control method shown, when the memory is affected by environmental factors (i.e., abnormal operating temperature and / or abnormal operating voltage) or the first physical unit has a high number of read times, the memory management circuit 51 may temporarily not mark the first physical unit corresponding to the target operation where the error occurred as a bad physical unit, so as to avoid the problem of unnecessary reduction of storage space due to incorrect marking, and execute a classification management mechanism based on the actual usage status of the first physical unit, thereby extending the service life of the memory storage device 10 while ensuring data reliability.

[0152] It should be noted that if the target operation where the error occurs is an erase operation or a write operation, in addition to the following Figures 7 to 9 In addition to the memory control method shown, the memory management circuit 51 can also select a second physical unit different from the first physical unit from the rewritable non-volatile memory module 43 to re-execute the erroneous erase operation or erroneous write operation, so that the operation of the memory storage device 10 is not interrupted.

[0153] In addition, if the target operation where the error occurs is a read operation and the first physical unit is not marked as the fourth type, except for the following Figures 7 to 9 In addition to the memory control method shown, the memory management circuit 51 may further determine, after a data consolidation operation (e.g., a garbage collection operation), whether a read operation corresponding to the first physical unit has recurred an error, provided that no abnormal environmental factors exist and the number of reads does not exceed a read threshold. If so, the memory management circuit 51 may mark the first physical unit of the second type (or third type) as the third type (or fourth type) to ensure data reliability. If not, the memory management circuit 51 may mark the first physical unit as the first type to extend the service life of the memory storage device 10.

[0154] Figure 10 FIG is a flow chart of a memory control method for a physical unit to be checked according to an exemplary embodiment of the present invention. Figure 10 It is worth mentioning that, Figure 10 The memory control method for the physical unit to be inspected is executed in an idle state and / or a background state.

[0155] In step S1001 , the memory management circuit 51 may perform a target test operation on the first physical cell marked as the second type based on an access pattern of the first physical cell marked as the second type.

[0156] In one exemplary embodiment, the target test operation may include, but is not limited to, an erase operation, a write operation, and a read-verify operation. For example, the access mode of the first physical cell marked as the second type (i.e., the physical cell to be tested) is the third-level memory cell access mode. The memory management circuit 51 may first perform an erase operation on the first physical cell marked as the second type, then write test data into the first physical cell marked as the second type based on the third-level memory cell access mode, and then perform a read-verify operation on the first physical cell marked as the second type based on the third-level memory cell access mode to determine whether the test data was correctly written.

[0157] In step S1002 , the memory management circuit 51 may determine whether the target test operation is successful.

[0158] In an exemplary embodiment, if the read verification operation is successful, ie, it indicates that the test data is correctly written into the first physical cell marked as the second type, the memory management circuit 51 may determine that the target test operation is successful.

[0159] In contrast, if the read verification operation fails, that means the test data is not correctly written into the first physical cell marked as the second type. Accordingly, the memory management circuit 51 may determine that the target test operation fails.

[0160] If the target test operation is successful, the process proceeds to step S1003 ; otherwise, if the target test operation is failed, the process proceeds to step S1004 .

[0161] In step S1003 , the memory management circuit 51 may re-mark the first physical unit marked as the second type as the first type.

[0162] Specifically, if the target test operation on the first physical cell marked as the second type is successful, indicating that the error previously occurring in the operation corresponding to the first physical cell marked as the second type is a temporary error, the memory management circuit 51 can re-mark the first physical cell marked as the second type as a healthy first type (i.e., a good physical cell) to increase the service life of the first physical cell, thereby extending the service life of the memory storage device 10 while ensuring data reliability.

[0163] On the other hand, in step S1004 , the memory management circuit 51 may further determine whether the access mode of the first physical unit marked as the second type is a single-level memory cell access mode.

[0164] If so, the process proceeds to step S1005 , where the memory management circuit 51 may mark the first physical unit marked as the second type as the fourth type.

[0165] In one exemplary embodiment, the third type of physical cell can only be used in the single-level memory cell access mode. Therefore, if a target test operation fails for a first physical cell marked as the second type and the access mode is the single-level memory cell access mode, i.e., at least in the single-level memory cell access mode, the first physical cell marked as the second type cannot be properly accessed, the memory management circuit 51 will mark it as the fourth type (i.e., a bad physical cell) and prevent it from participating in subsequent data access operations, thereby avoiding data loss and / or data corruption.

[0166] On the contrary, if not, the process proceeds to step S1006 , where the memory management circuit 51 may mark the first physical unit marked as the second type as the third type.

[0167] Specifically, if the target test operation of the first physical cell marked as the second type fails and the access mode is not the single-level memory cell access mode (for example, the third-level memory cell access mode), that is, perhaps the first physical cell marked as the second type can be correctly accessed in the single-level memory cell access mode, the memory management circuit 51 will mark it as the third type (that is, a weak physical cell) to use it to store data of lower importance.

[0168] According to the above, if Figure 10 The memory control method shown can perform a target test operation on the physical unit to be inspected (i.e., the second type of physical unit) in an idle state, restore the physical unit to be inspected for which the target test operation is successful to a good physical unit, and mark the physical unit to be inspected for which the target test operation is failed as a weak physical unit or a bad physical unit. By further executing a classification management mechanism for the physical unit to be inspected, it is possible to establish a physical unit management mechanism based on the actual operation of the storage device, classify and mark physical units in different usage conditions, thereby reducing misjudgment of physical unit classification and extending the service life of the memory storage device 10 while ensuring data reliability.

[0169] In summary, the memory control method and memory storage device proposed in the exemplary embodiments of the present invention can temporarily not perform the marking action when the environmental factors are abnormal to avoid the problem of incorrect marking, and perform a classification management mechanism based on the actual usage status of the physical unit corresponding to the target operation where the error occurs. In addition, in the idle state, the target test operation is performed on the physical unit to be inspected to perform further classification management mechanism on it, which can effectively extend the service life of the memory storage device while ensuring data reliability.

[0170] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory control method, characterized in that: For a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes a plurality of physical units, and the plurality of physical units are respectively marked as a first type, a second type, a third type, or a fourth type, and the memory control method includes: When an error occurs in a target operation executed on a first entity unit, obtaining the execution count of the first entity unit; If the execution count and the operation type of the target operation indicate that the first entity unit meets a first preset condition, determining whether the first entity unit is of the third type; If the first entity unit is not of the third type and the execution count indicates that the first entity unit satisfies a second preset condition, determining whether the first entity unit is of the second type; and If the first entity element is not of the second type, mark the first entity element as the second type, The first type is defined as being applicable to both single-level memory cell access mode and multi-level memory cell access mode, and having no errors. The second type is defined as being applicable to both the single-level memory cell access mode and the multi-level memory cell access mode, and the error has occurred. wherein the third type is defined as being applicable only to the single-level memory cell access mode, The fourth type is defined as damaged.

2. The memory control method according to claim 1, wherein: The first preset condition includes: The target operation is not a read operation, or the target operation is the read operation and the execution count is not greater than a read threshold, wherein the execution count is a read count.

3. The memory control method according to claim 1, wherein: The second preset condition includes: The execution number is not greater than an erasure threshold, wherein the execution number is an erasure number.

4. The memory control method according to claim 1, wherein: Before the step of obtaining the execution count of the first entity unit, the method further includes: determining whether an operating temperature or an operating voltage corresponding to the target operation is abnormal; and If at least one of the operating temperature and the operating voltage is abnormal, the first physical unit is temporarily not marked.

5. The memory control method according to claim 1 , further comprising: If the execution count and the operation type of the target operation indicate that the first entity unit does not meet the first preset condition, the first entity unit is temporarily not marked.

6. The memory control method according to claim 1 , further comprising: If the first entity element is of the third type, the first entity element is marked as the fourth type.

7. The memory control method according to claim 1 , further comprising: If the first entity unit is not of the third type and the execution count indicates that the first entity unit does not meet the second preset condition, the first entity unit is marked as the third type.

8. The memory control method according to claim 7, wherein the step of marking the first entity unit as the third type comprises: Determining whether the target operation is a read operation; If so, the first entity element is marked as the third type.

9. The memory control method according to claim 8, further comprising: If not, the first entity element is marked as the fourth type.

10. The memory control method according to claim 1, further comprising: If the first entity element is of the second type, the first entity element is marked as the third type.

11. The memory control method according to claim 1 , further comprising: In an idle state, based on an access pattern of the first physical unit marked as the second type, performing a target test operation on the first physical unit marked as the second type; as well as If the target test operation is successful, the first entity element marked as the second type is re-marked as the first type.

12. The memory control method according to claim 11, further comprising: If the target test operation fails and the access mode is the single-level memory cell access mode, the first physical cell marked as the second type is marked as the fourth type.

13. The memory control method according to claim 11, further comprising: If the target test operation fails and the access mode is not the single-level memory cell access mode, the first physical cell marked as the second type is marked as the third type.

14. The memory control method according to claim 1, wherein: The operation type is used to indicate whether the target operation is an erase operation, a write operation, or a read operation.

15. The memory control method according to claim 1, wherein: The plurality of solid elements are initially all of the first type.

16. A memory storage device, characterized in that: include: A connection interface unit for coupling to a host system; A rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of physical units, and the plurality of physical units are respectively marked as a first type, a second type, a third type, or a fourth type; and A memory control circuit unit is coupled to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is used to: When an error occurs in a target operation executed on a first entity unit, obtaining the execution count of the first entity unit; If the execution count and the operation type of the target operation indicate that the first entity unit meets a first preset condition, determining whether the first entity unit is of the third type; If the first entity unit is not of the third type and the execution count indicates that the first entity unit satisfies a second preset condition, determining whether the first entity unit is of the second type; as well as If the first entity element is not of the second type, mark the first entity element as the second type, The first type is defined as being applicable to both single-level memory cell access mode and multi-level memory cell access mode, and having no errors. The second type is defined as being applicable to both the single-level memory cell access mode and the multi-level memory cell access mode, and the error has occurred. wherein the third type is defined as being applicable only to the single-level memory cell access mode, The fourth type is defined as damaged.

17. The memory storage device of claim 16, wherein: The first preset condition includes: The target operation is not a read operation, or the target operation is the read operation and the execution count is not greater than a read threshold, wherein the execution count is a read count.

18. The memory storage device of claim 16, wherein: The second preset condition includes: The execution number is not greater than an erasure threshold, wherein the execution number is an erasure number.

19. The memory storage device of claim 16, wherein: Before the memory control circuit unit obtains the execution count of the first physical unit, the memory control circuit unit is further configured to determine whether an operating temperature or an operating voltage corresponding to the target operation is abnormal, and If at least one of the operating temperature and the operating voltage is abnormal, the memory control circuit unit is further configured to temporarily not mark the first physical unit.

20. The memory storage device of claim 16, wherein: If the execution count and the operation type of the target operation indicate that the first physical unit does not meet the first preset condition, the memory control circuit unit is further configured to temporarily not mark the first physical unit.

21. The memory storage device of claim 16, wherein: If the first physical unit is of the third type, the memory control circuit unit is further configured to mark the first physical unit as the fourth type.

22. The memory storage device of claim 16, wherein: If the first physical unit is not of the third type and the execution count indicates that the first physical unit does not meet the second preset condition, the memory control circuit unit is further configured to mark the first physical unit as the third type.

23. The memory storage device according to claim 22, wherein the memory control circuit unit is further configured to determine whether the target operation is a read operation, If the target operation is a read operation, the memory control circuit unit is further configured to mark the first physical unit as the third type.

24. The memory storage device of claim 23, wherein: If the target operation is not a read operation, the memory control circuit unit is further configured to mark the first physical unit as the fourth type.

25. The memory storage device of claim 16, wherein: If the first physical unit is of the second type, the memory control circuit unit is further configured to mark the first physical unit as the third type.

26. The memory storage device of claim 16, wherein: In an idle state, the memory control circuit unit is further configured to perform a target test operation on the first physical unit marked as the second type based on an access pattern of the first physical unit marked as the second type, and If the target test operation is successful, the memory control circuit unit is further configured to re-mark the first physical unit marked as the second type as the first type.

27. The memory storage device of claim 26, wherein: If the target test operation fails and the access mode is the single-level memory cell access mode, the memory control circuit unit is further configured to mark the first physical cell marked as the second type as the fourth type.

28. The memory storage device of claim 26, wherein: If the target test operation fails and the access mode is not the single-level memory cell access mode, the memory control circuit unit is further configured to mark the first physical cell marked as the second type as the third type.

29. The memory storage device of claim 16, wherein: The operation type is used to indicate whether the target operation is an erase operation, a write operation, or a read operation.

30. The memory storage device of claim 16, wherein: The plurality of solid elements are initially all of the first type.

Images