First-in first-out memory capable of achieving random address access and data processing method

Abstract

The invention relates to the technical field of computers, and discloses a first-in first-out memory capable of achieving random address access and a data processing method in order to solve the problem that data written into an FIFO (First In First Out) memory cannot be modified in a current-level circuit. Each storage block is used for storing an Ethernet frame; the write control logic and the read control logic are used for performing read-write access on the current storage block according to a first-in first-out sequence through the first external interface signal, and further used for performing data backward reading / rewriting on a specified address of the current storage block through the first external interface signal and the second external interface signal; the second external interface signal comprises an in-block write enable signal, an in-block write address signal, an in-block read enable signal, an in-block read address signal, a block write end signal and a block read end signal. By adopting the first-in first-out memory capable of being accessed by the random address, data in the FIFO memory can be modified in a current-stage circuit.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and more specifically, to a first-in-first-out memory capable of random address access and a data processing method. Background Art

[0002] In a network data processing system, due to the different data processing performance of each circuit in the system, there will be a mismatch between the data input speed and the output speed in the interface part of the system. In order to avoid the loss of transmitted data, a first-in-first-out (FIFO) memory is generally used to store data frames, and the empty and full indication of the FIFO memory is used to control the data processing speed of the front and rear circuits, thereby achieving speed matching of the data processing system.

[0003] In computer networks, FIFO memories usually store Ethernet data frames. According to the working characteristics of the network data processing system, some fields of the data frames often need to be modified. Since FIFO memories have the first-in-first-out characteristic, the data written into the FIFO memory cannot be modified in the current level circuit and can only be modified after the next level circuit reads it from the current level FIFO, which increases the complexity of the network data processing system. Summary of the invention

[0004] In order to solve the above problems, the present invention provides a first-in-first-out memory and a data processing method with random address access, which can modify the data written into the FIFO memory in the circuit of this level, effectively reducing the complexity of the network data processing system.

[0005] To achieve the above object, according to a first aspect of the present invention, there is provided a first-in-first-out memory capable of random address access, comprising a random access memory, a write control logic, and a read control logic;

[0006] The random access memory includes a plurality of fixed-size storage blocks, each storage block is used to store an Ethernet frame, and the size of the storage block is not less than the frame length of the Ethernet frame;

[0007] The write control logic and the read control logic are used to perform read and write access to the current storage block in a first-in-first-out order through a first external interface signal; the first external interface signal includes a write enable signal, a write data signal, a read enable signal, and a read data signal;

[0008] The write control logic and the read control logic are also used to read back / rewrite data at the specified address of the current storage block through the first external interface signal and the second external interface signal; the second external interface signal includes a write enable signal within the block, a write address signal within the block, a read enable signal within the block, a read address signal within the block, a block write end signal, and a block read end signal; the write control logic and the read control logic are also used to determine whether to jump out of the current storage block and access the next storage block through the block write end signal and the block read end signal.

[0009] Furthermore, the write control logic and the read control logic are also used to perform read and write access to the specified address of the current storage block through the intra-block write enable signal, the intra-block write address signal, the intra-block read enable signal, and the intra-block read address signal.

[0010] Furthermore, the first external interface signal also includes a status signal, which includes a full mark signal, an almost full signal, an empty mark signal, and an almost empty signal, which are used to identify the empty / full status of a first-in-first-out memory that can be accessed by a random address; the write control logic and the read control logic are also used to count the block write end signal and the block read end signal to generate a full mark signal, an almost full signal, an empty mark signal, or an almost empty signal.

[0011] According to a second aspect of the present invention, there is also provided a data processing method, which is applied to the above-mentioned first-in-first-out memory accessible by random addresses, and the data to be processed is data in the form of Ethernet frames, and the method comprises:

[0012] According to the order of received Ethernet frames, each Ethernet frame is stored in each storage block in sequence;

[0013] Operate the write enable signal and the write data signal to write the Ethernet frame in the current storage block from the frame start position to the frame end position;

[0014] Operate the write enable signal and write address signal within the block to directly jump to the data location to be modified for data rewriting;

[0015] The operation block write end signal controls the jump to the next frame start position of the next storage block and starts processing the next frame of data.

[0016] Furthermore, the above-mentioned data processing method also includes storing each Ethernet frame in each storage block in sequence according to the order of the received Ethernet frames; operating the read enable signal and the read data signal to read the Ethernet frame in the current storage block from the frame start position to the frame end position; operating the read enable signal within the block and the read address signal within the block to directly jump to the data position to be read back for data reading; operating the block read end signal to control the jump to the next frame start position of the next storage block to start processing the next frame data.

[0017] Furthermore, the data processing method further comprises, when the in-block write enable signal and the in-block read enable signal are valid, performing read and write access to the specified address of the current storage block according to the in-block write address signal and the in-block read address signal.

[0018] Furthermore, the above-mentioned data processing method also includes counting block write end signals and block read end signals to generate a full mark signal, an almost full signal, an empty mark signal or an almost empty signal to identify the empty / full status of a first-in-first-out memory that can be accessed by a random address.

[0019] According to a third aspect of the present invention, there is also provided a computer device, which includes a memory, a processor and a computer program stored in the memory, and the processor executes the computer program to implement the steps of any one of the above-mentioned data processing methods.

[0020] According to a fourth aspect of the present invention, there is also provided a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, the steps of any of the above-mentioned data processing methods are implemented.

[0021] According to a fifth aspect of the present invention, there is also provided a computer program product, comprising a computer program, which implements the steps of any of the above-mentioned data processing methods when executed by a processor.

[0022] In general, the above technical solutions conceived by the present invention can achieve the following beneficial effects compared with the prior art:

[0023] The present invention provides a FIFO memory capable of random address access. By changing the storage structure of the RAM cache of the FIFO memory and adding a group of external interface signals, random address access of Ethernet data frames stored in the FIFO memory is realized. The FIFO memory has the first-in-first-out characteristic of a common FIFO memory and supports the function of reading and writing data at a specified address. The data written into the FIFO memory can be modified in the circuit of the current level, and the complexity of the network data processing system is effectively reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0025] Figure 1 A schematic diagram of the structure of a conventional FIFO memory provided in an embodiment of the present application;

[0026] Figure 2 A schematic diagram of the format of an Ethernet frame provided in an embodiment of the present application;

[0027] Figure 3 A network data processing system based on a conventional FIFO isolation multi-stage circuit is provided in an embodiment of the present application;

[0028] Figure 4 Another network data processing system based on a conventional FIFO isolation multi-stage circuit provided in an embodiment of the present application;

[0029] Figure 5 A schematic diagram of the structure of a FIFO memory with random address access provided in an embodiment of the present application;

[0030] Figure 6 A schematic diagram of a data processing flow based on a FIFO memory accessible by random addresses provided in an embodiment of the present application;

[0031] Figure 7 A network data processing system based on a FIFO memory accessible by random addresses provided in an embodiment of the present application;

[0032] Figure 8 A schematic diagram of the structure of a computer device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0033] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0034] The terms "first", "second", "third", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices.

[0035] This embodiment provides a first-in-first-out (FIFO) memory that can be accessed by random addresses, such as Figure 1As shown, like a conventional FIFO memory, it includes RAM (random access memory), write control logic, and read control logic. The external interface signal includes a first external interface signal, namely, write data, write enable, read data, read enable, and status signal. The status signal includes a full mark, almost full, an empty mark, and almost empty, which are used to identify the empty / full state of the first-in-first-out memory that can be accessed by a random address.

[0036] like Figure 2 As shown, in a network data processing system, the processed data is usually an Ethernet frame, which consists of the following data segments in sequence: destination MAC address, source MAC address, Ethernet type, IP header, payload, padding, and FCS (Frame Check Sequence).

[0037] Since the FIFO memory has a first-in-first-out feature, that is, the writing order of the Ethernet frame is from the destination MAC address to the FCS check code, and the reading order is also from the destination MAC address to the FCS check code, therefore, the circuits at all levels of the network data processing system write the data segments of the Ethernet frame into the FIFO memory in sequence from left to right, or read them from the FIFO memory by controlling the external interface signal of the FIFO memory.

[0038] like Figure 3 As shown, the network data processing system is composed of multiple circuits, and each circuit is isolated by a FIFO memory, that is, the network data processing system is composed of a previous circuit, a current circuit and a subsequent circuit, and the previous circuit and the current circuit are isolated by a FIFO memory (i.e., ordinary fifo1), and the current circuit and the subsequent circuit are also isolated by a FIFO memory (i.e., ordinary fifo2). Thus, the pipeline parallel processing of each circuit and the matching of processing speed can be achieved, and each circuit reads out each data segment of the Ethernet frame from the previous FIFO memory and performs corresponding processing, and then writes each processed data segment into the subsequent FIFO memory for caching. Taking the current circuit as an example, the current circuit reads each data segment of the Ethernet frame from the ordinary fifo1 and processes it, and writes the processed data into the ordinary fifo2 for caching.

[0039] like Figure 4 As shown, a certain level of circuit reads out all the data segments of the Ethernet frame from the previous level FIFO memory (such as Figure 2After all the data (from the destination MAC address to the FCS check code) are written into the post-stage FIFO memory, it is often necessary to modify one of the data segments according to all the data read out, such as the IP length information of the IP header data segment, the IP header check, etc. Due to the first-in-first-out feature of the ordinary fifo1, after the IP header field is written and modified in the order from the destination MAC address to the FCS check code, and the Ethernet frame with the modified IP header is written into the ordinary fifo2, the order read out from the ordinary fifo2 by the post-stage circuit is no longer from the destination MAC address to the FCS check code. Therefore, Figure 4 As shown, a first-level circuit 2 and a common fifo3 are added, and the function of modifying the IP header field is placed in circuit 2, and the function of modifying the IP header field is simply realized. In this way, the function of modifying the IP header is realized, and the order of the Ethernet frame content is guaranteed to be correct. However, this method increases the complexity of the network data processing system.

[0040] In order to solve the problem that data written into the FIFO memory cannot be modified in the current level circuit without increasing the complexity of the network data processing system, the present embodiment provides a FIFO memory that can be accessed by a random address, wherein the RAM is divided into a plurality of storage blocks of a fixed size, and the Ethernet frame can be stored in each storage block in sequence, and the external interface signal also includes a second external interface signal, namely, block write enable, block write address, block read enable, block read address, block write end, and block read end.

[0041] Like conventional FIFOs, the randomly addressable FIFO memory performs read and write access to the current storage block in a first-in-first-out order through external interface signals such as write enable, write data, read enable, and read data; and achieves performance matching between the front-end and rear-end circuits through status signals such as full mark, almost full, empty mark, and almost empty. Generally speaking, the front-end circuit controls the write enable signal based on the full mark and almost full indications, and the rear-end circuit controls the read enable signal based on the empty mark and almost empty indications.

[0042] Taking the RAM depth of ordinary fifo1 as 64k as an example, the read address is incremented by 1 each time it is read (read enable is valid), and the write address is incremented by 1 each time it is written (write enable is valid). It can only be read or written sequentially, and cannot read back or write back to access the previous address. That is, write from address 0 to address 64k-1 in a loop, and read from 0 to address 64k-1 in a loop; at the same time, the difference between the write address and the read address generates status signals such as full mark, almost full, empty mark, and almost empty.

[0043] Unlike conventional FIFOs, the FIFO memory with random address access uses the storage block as the data basic processing unit, and generates status signals such as full mark, almost full, empty mark, and almost empty of the FIFO memory with random address access by counting the block write end and block read end signals; read and write access is performed to the specified address of the current storage block through the block write enable, block write address, block read enable, and block read address signals; through the block write end and block read end signals, it is determined whether to jump out of the current storage block and access the next storage block; through the first external interface signal and the second external interface signal, data is read back / rewritten at the specified address of the current storage block.

[0044] In this embodiment, the data at the specified address of the current storage block is read back / rewritten through the FIFO memory which can be accessed by random addresses, and the data written into the FIFO memory can be modified in the circuit of this level.

[0045] In one embodiment, Figure 5 As shown, the FIFO memory with random address access divides the RAM into N storage blocks of the same size. In the network data processing system, considering that the frame length of the stored Ethernet frame does not exceed 1518 bytes, the size of the storage block is not less than the frame length of the Ethernet frame. The storage block size is usually set to 2K bytes, and each storage block stores an Ethernet frame. According to the order of the received Ethernet frames, they are stored in storage blocks 1 to N in a cyclic manner. By controlling the write enable, write data, read enable, and read data signals, the current storage block is read and written in the order of first-in-first-out; when the write enable and read enable signals in the block are valid, the specified address is read and written according to the instructions of the write address and read address in the block; before the block write end and block read end signals are operated, data is always read and written in the current storage block, and it will not jump to the first address of the next storage block until the block write end and block read end signals are operated.

[0046] In one embodiment, for a write operation, such as Figure 6 As shown, a data processing method based on a first-in-first-out memory accessible by random addresses is provided, comprising the following steps: by controlling the write enable and write data signals of the FIFO memory accessible by random addresses, the Ethernet frame is sent from Figure 6 The "frame start position" shown is written to the "frame end position", and then through the block write enable and block write address signals, it directly jumps to the "data position to be modified" for data rewriting, and finally controls the jump to the "next frame start position" of the next storage block through the block write end signal to start processing the next frame of data.

[0047] For the read operation, the operation process is similar to the write operation, including the following steps: store each Ethernet frame in each storage block in sequence according to the order of the received Ethernet frames; operate the read enable signal and the read data signal to read the Ethernet frame in the current storage block from the frame start position to the frame end position; operate the read enable signal within the block and the read address signal within the block to directly jump to the data position to be read back for data reading; operate the block read end signal to control the jump to the next frame start position of the next storage block and start processing the next frame of data.

[0048] In one embodiment, Figure 7 As shown, the network data processing system based on the FIFO memory which can be accessed by random addresses directly completes the Ethernet frame data storage and the reading back or modification operation of a certain field data therein in the current circuit.

[0049] A FIFO memory with random address access provided in this embodiment realizes random address access of Ethernet data frames stored in the FIFO memory by changing the storage structure of the RAM cache of the FIFO memory and adding a group of external interface signals. It has the first-in-first-out characteristics of an ordinary FIFO memory and supports the function of reading and writing data at a specified address. It can achieve the purpose of modifying the data written into the FIFO memory in the circuit of this level, effectively reducing the complexity of the network data processing system, having strong versatility and having certain practical value.

[0050] The present application also provides a computer device, which may be a computer device, and its internal structure diagram may be as shown in Figure 8As shown. The computer device includes a processor, a memory, an input / output interface, a communication interface, a display unit and an input device. Among them, the processor, the memory and the input / output interface are connected through a system bus, and the communication interface, the display unit and the input device are connected to the system bus through the input / output interface. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal in a wired or wireless manner, and the wireless manner can be implemented through WIFI, a mobile cellular network, NFC (near field communication) or other technologies. When the computer program is executed by the processor, the above-mentioned data processing method is implemented. The display unit of the computer device is used to form a visually visible image, and can be a display screen, a projection device or a virtual reality imaging device. The input device of the computer device can be a touch layer covered on the display screen, or a button, trackball or touchpad set on the computer device casing, or an external keyboard, touchpad or mouse, etc.

[0051] Those skilled in the art will understand that Figure 8 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0052] like Figure 8 As shown, the present application also provides a computer device, which includes a memory, a processor, and a computer program stored in the memory, and the processor executes the computer program to implement the steps in the above-mentioned method embodiments.

[0053] The present application also provides a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, the steps in the above-mentioned data processing method embodiments are implemented. The computer-readable storage medium may include, but is not limited to, any type of disk, including a floppy disk, an optical disk, a DVD, a CD-ROM, a micro drive, and a magneto-optical disk, a ROM, a RAM, an EPROM, an EEPROM, a DRAM, a VRAM, a flash memory device, a magnetic card or an optical card, a nanosystem (including a molecular memory IC), or any type of medium or device suitable for storing instructions and / or data.

[0054] The present application also provides a computer program product, including a computer program, which implements the steps in the above-mentioned method embodiments when executed by a processor.

[0055] It should be noted that, for the aforementioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the described order of actions, because according to the present application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present application.

[0056] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0057] The above is only an exemplary embodiment of the present disclosure, and the scope of the present disclosure cannot be limited thereto. That is, any equivalent changes and modifications made according to the teachings of the present disclosure are still within the scope of the present disclosure. After considering the specification and practicing the disclosure here, those skilled in the art will easily think of the implementation scheme of the present disclosure. This application is intended to cover any modification, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary technical means in the technical field not recorded in the present disclosure. The description and examples are only regarded as exemplary, and the scope and spirit of the present disclosure are defined by the claims.

[0058] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0059] It will be easily understood by those skilled in the art that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A first-in-first-out memory with random address access, characterized in that: Includes random access memory, write control logic, and read control logic; The random access memory includes a plurality of fixed-size storage blocks, each storage block is used to store an Ethernet frame, and the size of the storage block is not less than the frame length of the Ethernet frame; The write control logic and the read control logic are used to perform read and write access to the current storage block in a first-in-first-out order through a first external interface signal; the first external interface signal includes a write enable signal, a write data signal, a read enable signal, and a read data signal; The write control logic and the read control logic are also used to read back / rewrite data at a specified address of a current storage block through a first external interface signal and a second external interface signal; the second external interface signal includes an intra-block write enable signal, an intra-block write address signal, an intra-block read enable signal, an intra-block read address signal, a block write end signal, and a block read end signal; The write control logic and the read control logic are also used to determine whether to jump out of the current storage block and access the next storage block through the block write end signal and the block read end signal.

2. The first-in-first-out memory capable of random address access as claimed in claim 1, characterized in that: The write control logic and the read control logic are also used to perform read and write access to the specified address of the current storage block through an intra-block write enable signal, an intra-block write address signal, an intra-block read enable signal, and an intra-block read address signal.

3. The first-in-first-out memory with random address access as claimed in claim 1, characterized in that: The first external interface signal also includes a status signal, which includes a full mark signal, an almost full signal, an empty mark signal, and an almost empty signal, which are used to identify the empty / full status of the first-in-first-out memory that can be accessed by a random address; the write control logic and the read control logic are also used to count the block write end signal and the block read end signal to generate a full mark signal, an almost full signal, an empty mark signal or an almost empty signal.

4. A data processing method, applied to the first-in-first-out memory with random address access as claimed in claim 1, characterized in that: The data to be processed is data in the form of Ethernet frames, and the method comprises: According to the order of received Ethernet frames, each Ethernet frame is stored in each storage block in sequence; Operate the write enable signal and the write data signal to write the Ethernet frame in the current storage block from the frame start position to the frame end position; Operate the write enable signal and write address signal within the block to directly jump to the data location to be modified for data rewriting; The operation block write end signal controls the jump to the next frame start position of the next storage block and starts processing the next frame of data.

5. The data processing method according to claim 4, characterized in that: The method further comprises: According to the order of received Ethernet frames, each Ethernet frame is stored in each storage block in sequence; Operate the read enable signal and the read data signal to read the Ethernet frame in the current storage block from the frame start position to the frame end position; Operate the read enable signal and the read address signal within the block to directly jump to the location of the data to be read back for data reading; The operation block reads the end signal, and the control jumps to the next frame start position of the next storage block to start processing the next frame of data.

6. The data processing method according to claim 4 or 5, characterized in that: The method further comprises: When the write enable signal and the read enable signal in the block are valid, read and write access is performed on the specified address of the current storage block according to the instructions of the write address signal and the read address signal in the block.

7. The data processing method according to claim 4 or 5, characterized in that: The method further comprises: The block write end signal and the block read end signal are counted to generate a full mark signal, an almost full signal, an empty mark signal or an almost empty signal for identifying the empty / full state of the first-in-first-out memory accessible by random addresses.

8. A computer device, characterized in that: The method comprises a memory, a processor and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the method according to any one of claims 4 to 7.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 4 to 7 are implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 4 to 7 are implemented.

Images