Address processing structure and memory

Abstract

The invention relates to the field of memorizers, in particular to an address processing structure and a memorizer, and the address processing structure comprises a compiling module which is configured to receive an access command and obtain an initial access address based on the access command; the processing module is configured to receive the access command and judge whether address replacement is executed or not based on the access command; the processing module is further connected with the compiling module and stores preset information, and the processing module is further configured to adjust the initial access address based on the preset information to obtain the access address if address replacement needs to be executed. The address processing structure provided by the embodiment of the invention is used for improving the addressing flexibility of the phase change memory, so that the performance of a memory module of the phase change memory is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of memory, and in particular to an address processing structure and a memory. Background Art

[0002] Memory is a component of a computer that implements memory functions and is used to store programs and data. It is an important component of a microcomputer system. The larger the memory capacity, the more information can be stored, and the more fully the computer's processing capabilities can be demonstrated.

[0003] For the memory, each memory includes multiple memory chips (die), each die selects the corresponding memory block (bank) through a block address (bank address), and each bank is addressed through a row address (row address) and a column address (column address).

[0004] When a phase change memory (PCM) memory module reads or writes a channel, all dies on the channel access the same bank address, row address, or column address. Addressing through the same bank address, row address, or column address may cause the memory chip to exhibit poor performance at a specific address. Summary of the invention

[0005] The purpose of the present disclosure is to provide an address processing structure and a memory to improve the addressing flexibility of a phase change memory, thereby improving the performance of a phase change memory module.

[0006] In a first aspect, an embodiment of the present disclosure provides an address processing structure, including: a compilation module, configured to: receive an access command, and obtain an initial access address based on the access command; a processing module, configured to: receive an access command, and determine whether to perform address replacement based on the access command; the processing module is also connected to the compilation module and stores preset information, and the processing module is also configured to: if address replacement needs to be performed, adjust the initial access address based on the preset information to obtain the access address.

[0007] In some embodiments, the processing module includes: a judgment unit, configured to: receive and judge whether the access command meets the preset conditions, and if the access command meets the preset conditions, generate an adjustment signal; a replacement unit, configured to: in response to the adjustment signal, adjust the initial access address based on preset information to obtain the access address.

[0008] In some embodiments, the processing module is configured to obtain the access address by performing a logical operation, negation, address left shift or address right shift based on the preset information and the character of the corresponding bit of the initial access address.

[0009] In some embodiments, the replacement unit is arranged based on at least one of an AND gate, a NAND gate, an OR gate, a NOR gate, an XOR gate and an XNOR gate.

[0010] In some embodiments, the initial access address includes at least one of an initial block address, an initial row address, and an initial column address; the preset information includes a preset block character, a preset row character, and a preset column character corresponding to the initial access address; the access address includes an access block address, an access row address, and an access column address corresponding to the initial access address; the processing module is configured to: adjust the initial block address based on the preset block character to obtain the access block address; adjust the initial row address based on the preset row character to obtain the access row address; adjust the initial column address based on the preset column character to obtain the access column address.

[0011] In some embodiments, the preset block characters, the preset row characters, and the preset column characters are set to different character strings.

[0012] In some embodiments, the processing module includes a mode register.

[0013] In a second aspect, an embodiment of the present disclosure further provides a memory, comprising: a storage controller for outputting access commands; a plurality of storage chips, the storage chips performing data access based on the access commands; and at least one of the plurality of storage chips comprising an address processing structure as provided in the first aspect above.

[0014] In some embodiments, the preset information corresponding to the address processing structures in different memory chips is different.

[0015] In some embodiments, the address processing structures in different memory chips adjust the initial access address in different ways.

[0016] The address processing structure provided by the present disclosure obtains the access address by replacing the initial access address corresponding to the access command, and performs actual access with the access address, so that the memory can achieve controllable addressing when reading / writing a channel, and avoids the situation where the poor performance area of ​​the poor performance Bank is accessed during unified addressing.

[0017] Other features and advantages of the present disclosure will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can obtain other drawings based on these drawings without creative work.

[0019] Figure 1 A schematic diagram of the structure of the address processing structure provided in the embodiment of the present disclosure;

[0020] Figure 2 A schematic diagram of replacement logic of different memory chips provided by the embodiment of the present disclosure;

[0021] Figure 3 A schematic diagram of different initial block address replacement logics corresponding to different storage chips provided in an embodiment of the present disclosure;

[0022] Figure 4 A schematic diagram of replacement logic for different initial row addresses and initial column addresses corresponding to different memory chips provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0023] The technical solutions in the embodiments of the present disclosure will be described clearly and completely below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present disclosure.

[0024] In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the described features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0025] In this disclosure, the word "exemplary" is used to mean "serving as an example, illustration, or illustration." Any embodiment described in this disclosure as "exemplary" is not necessarily to be construed as being preferred or advantageous over other embodiments. The following description is given to enable any person skilled in the art to implement and use the invention. In the following description, details are listed for the purpose of explanation. It should be understood that a person of ordinary skill in the art can recognize that the invention can be implemented without using these specific details. In other instances, well-known structures and processes are not elaborated in detail to avoid obscuring the description of the invention with unnecessary details. Therefore, the present invention is not intended to be limited to the embodiments shown, but is consistent with the widest scope consistent with the principles and features disclosed in this disclosure.

[0026] At the same time, the present disclosure uses specific words to describe the embodiments of the present disclosure. For example, "one embodiment", "an embodiment", and / or "some embodiments" refer to a certain feature, structure or characteristic related to at least one embodiment of the present disclosure. Therefore, it should be emphasized and noted that "one embodiment" or "an embodiment" or "an alternative embodiment" mentioned twice or more in different locations in this specification does not necessarily refer to the same embodiment. In addition, certain features, structures or characteristics in one or more embodiments of the present disclosure may be appropriately combined.

[0027] Similarly, it should be noted that in order to simplify the description of the disclosure and thus facilitate the understanding of one or more disclosed embodiments, in the foregoing description of the embodiments of the disclosure, multiple features are sometimes grouped into one embodiment, drawing, or description thereof. However, this disclosure method does not mean that the disclosed object requires more features than those mentioned in the claims. In fact, the features of the embodiments are less than all the features of the single embodiment disclosed above.

[0028] In some embodiments, numbers are used to describe the number of components and attributes. It should be understood that such numbers used to describe the embodiments are modified by the modifiers "about", "approximately" or "substantially" in some examples. Unless otherwise specified, "about", "approximately" or "substantially" indicate that the numbers are allowed to vary by ±20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximate values, which may change according to the required features of individual embodiments. In some embodiments, numerical parameters should consider specifying significant digits and adopting a general method of retaining digits. Although the numerical domains and parameters used to confirm the breadth of their range in some embodiments of the present disclosure are approximate values, in specific embodiments, such numerical values ​​are set as accurately as possible within the feasible range.

[0029] Each patent, patent application, patent application publication, and other materials, such as articles, books, specifications, publications, documents, etc., cited in this disclosure are hereby incorporated by reference in their entirety, except for application history documents that are inconsistent with or conflicting with the content of this disclosure, and documents that limit the broadest scope of the claims of this disclosure (currently or later attached to this disclosure). It should be noted that if the descriptions, definitions, and / or use of terms in the accompanying materials of this disclosure are inconsistent or conflicting with the examples of this disclosure, the descriptions, definitions, and / or use of terms in this disclosure shall prevail.

[0030] Based on the background technology, it is known that when a phase change memory (PCM) memory module reads or writes a channel, all dies on the channel access the same bank address, row address or column address.

[0031] For the actual memory chips, due to the limitation of process level, there are performance differences between each bank, and the performance of different areas within the bank may also be different. At this time, addressing through the same bank address, row address or column address will cause the memory chip to show poor performance at a specific address.

[0032] Based on this problem, the present disclosure provides an address processing structure to improve the addressing flexibility of the phase change memory, thereby improving the performance of the phase change memory module. The address processing structure provided by the present embodiment is described in detail below in conjunction with the accompanying drawings, as follows:

[0033] refer to Figure 1 , Figure 1 A schematic diagram of the structure of the address processing structure provided in the embodiment of the present disclosure is provided, wherein the memory chip 100 includes at least one memory block 200 (bank), each memory block 200 includes at least one memory array 204 (array), and the memory array 204 includes a plurality of memory cells arranged based on an array.

[0034] In one example, the memory block 200 includes bank 0 and bank 1 -bank N.

[0035] In one example, the memory cells are arranged in a row-column array to form the memory array 204 .

[0036] Continue to refer Figure 1The memory chip 100 further includes a bank decoder 201 , a row decoder 202 , and a column decoder 203 .

[0037] The block decoder 201 selects the target storage block based on the block address bank address, the row decoder 202 selects the target word line based on the row address row address, and the column decoder 203 selects the target bit line based on the column address column decoder. The target word line and the target bit line are respectively used to indicate the row and column where the storage cell is located, so as to select the target storage cell in the storage block 200.

[0038] It should be noted that Figure 1 The example uses the specific structure of bank0 to illustrate the structure of the storage block 200 , which is only used to exemplify the structure of the storage block 200 and does not constitute an addressing limitation for multiple storage blocks 200 .

[0039] In this embodiment, the memory chip 100 further includes an address processing structure, and the address processing structure includes: a compiling module 101 and a processing module 102 .

[0040] The compiling module 101 is configured to receive an access command and obtain an initial access address based on the access command. The processing module 102 is configured to receive an access command and determine whether to perform address replacement based on the access command. The processing module 102 is also connected to the compiling module 101 and stores preset information. The processing module 102 is also configured to adjust the initial access address based on the preset information if address replacement is required to obtain an adjusted access address.

[0041] Specifically, the compiling module 101 is connected to the input pin CAPIN of the memory chip 100, the input pin CAPIN is connected to the memory controller, the memory controller issues an access command, the access command is input into the memory chip 100 through the input pin CAPIN, the compiling module 101 receives the access command, and obtains the initial access address corresponding to the access command. The processing module 102 determines whether address replacement is required based on the access command, and if address replacement is required, replaces the initial access address with the access address.

[0042] In some embodiments, the initial access address includes an initial block address bank address, an initial row address rowaddress, and an initial column address column address. Specifically, the bank address is used to select a target storage block from a plurality of storage blocks, and the row address and column address are used to select a target storage unit in the target storage block, thereby accessing the target storage unit. At this time, the process of replacing the initial access address with the access address includes: replacing the initial block address bank address with the access block address, replacing the initial row address row address with the access row address, and replacing the initial column address column address with the access column address.

[0043] In other embodiments, the initial access address includes at least one of an initial block address bank address, an initial row address rowaddress, and an initial column address column address. In this case, the process of replacing the initial access address with the access address includes: replacing the initial block address bank address with the access block address, replacing the initial row address rowaddress with the access row address, and replacing the initial column address column address with at least one of the access column addresses.

[0044] In one example, when a phase change memory PCM memory module reads / writes a channel, (1) it is assumed that die1, die2, and die3 on the channel are all accessing a memory cell with bank address = "00000000", row address = "00000000", and column address = "00000000". If the performance of this memory cell (bank address = "00000000", row address = "00000000", and column address = "00000000") in die1, die2, and die3 is better, the memory will show better performance. (2) It is assumed that die1, die2, and die3 on the channel are all accessing a memory cell with bank address = "11000000", row address = "11000000", and columnaddress = "11000000". If the performance of the storage unit (bankaddress="11000000", row address="11000000" and column address="11000000") of die1 among die1, die2 and die3 is poor, the memory as a whole will show poor performance.

[0045] At this time, if die1 replaces the initial access address bank address = "11000000", rowaddress = "11000000" and column address = "11000000" with storage units with better performance during the addressing process, the memory can show better performance.

[0046] Based on the above discussion, it can be known that for the address processing structure provided in this embodiment, the access address is obtained by replacing the initial access address corresponding to the access command, and the access address is used for actual access, so that the memory can achieve controllable addressing when reading / writing a channel, avoiding the situation where the poor performance area of ​​the poor performance Bank is accessed during unified addressing.

[0047] Regarding the processing module 102, in one example, the processing module 102 determines whether address replacement is required based on a flag bit in the access command. For example, the processing module 102 determines whether the flag bit in the access command is "1".

[0048] In another example, the processing module 102 determines whether address replacement is required based on the initial access address corresponding to the access command. For example, the processing module 102 determines whether the initial access address is a preset address.

[0049] In another example, the processing module 102 determines whether address replacement is required based on the configuration instruction included in the access command. For example, the processing module 102 determines whether the access command includes the configuration instruction.

[0050] In some embodiments, the processing module 102 includes a determination unit and a replacement unit.

[0051] The judgment unit is configured to: receive and judge whether the access command meets the preset conditions, and if the access command meets the preset conditions, generate an adjustment signal; the replacement unit is configured to: respond to the adjustment signal and adjust the initial access address based on preset information to obtain the access address.

[0052] In short, the judgment unit judges whether address replacement needs to be performed based on preset conditions; when the judgment unit judges that address replacement needs to be performed, the judgment unit generates an adjustment signal, and the replacement unit adjusts the initial access address in response to the adjustment signal to obtain the access address.

[0053] The preset condition is used to determine whether address replacement is required, and the preset information is used to execute address replacement.

[0054] If the processing module 102 determines whether to continue address replacement based on the flag bit in the access command, the preset condition can be set to whether the value of the flag bit is the target value; if the processing module 102 determines whether address replacement is required based on the initial access address corresponding to the access command, the preset condition can be set to whether the initial address is the target address; if the processing module 102 determines whether address replacement is required based on the configuration instruction contained in the access command, the preset adjustment can be set to whether there is a configuration instruction in the access command, or whether the value of the configuration instruction is the target value.

[0055] The adjustment of the access address may adjust one or more of the initial block address, the initial row address, and the initial column address.

[0056] In some embodiments, the initial access address includes at least one of an initial block address bank address, an initial row address rowaddress, and an initial column address column address, the preset information includes a preset block character, a preset row character, and a preset column character corresponding to the initial access address; the access address includes an access block address, an access row address, and an access column address corresponding to the initial position address. The processing module 102 is configured to adjust the initial block address based on the preset block character to obtain the access block address; adjust the initial row address based on the preset row character to obtain the access row address; and adjust the initial column address based on the preset column character to obtain the access column address.

[0057] Specifically, if the initial access address includes an initial block address bank address, then the preset information needs to include a preset block character, the access address needs to include an access block address, and the processing module 102 is configured to: adjust the initial block address bank address based on the preset block character to obtain the access block address; if the initial access address includes an initial row address row address, then the preset information needs to include a preset row character, the access address needs to include an access row address, and the processing module 102 is configured to adjust the initial row address row address based on the preset row character to obtain the access row address; if the initial access address includes an initial column address column address, then the preset information needs to include a preset column character, the access address needs to include an access column address, and the processing module 102 is configured to adjust the initial column address column address based on the preset column character to obtain the access column address.

[0058] In some embodiments, the initial access address may be adjusted by adjusting one or more bits based on preset information, and the adjustment method may be based on at least one of logical operations, negation, address left shift, address right shift, etc. It should be noted that the adjustment method of the initial access address is introduced in the form of logical operations in the following embodiments, which does not constitute a limitation on the adjustment method of the initial access address. In other embodiments, at least one of negation, address left shift, address right shift, etc. may be superimposed on the adjustment method of logical operations, or directly replaced by at least one of negation, address left shift, address right shift, etc.

[0059] Specifically, the processing module 102 is configured to obtain the access address after performing a logical operation, negation, address left shift or address right shift based on the preset information and the character of the corresponding bit of the initial access address. The logical operation method includes at least one of an AND logical operation, an NAND logical operation, an OR logical operation, an NOR logical operation, an XOR logical operation and an XNOR logical operation.

[0060] In some embodiments, the specific executor of the address replacement by the processing module 102 is a replacement unit, that is, the replacement unit obtains the access address after performing a preset logical operation on the character of the corresponding position of the initial access address based on the preset information. In some embodiments, the replacement unit is set based on at least one of an AND gate, a NAND gate, an OR gate, a NOR gate, an XOR gate, and an XNOR gate to realize the logical operation of the character of the corresponding position of the initial access address based on the preset information. Through the logical operation, the bank with poor performance in the die is replaced with a bank with better performance, and / or the storage area with poor performance in the bank is replaced with a storage area with better performance through row and column address remapping. In addition, through the replacement of the corresponding bit character, each bit address is independently controllable in the address replacement process. No matter which address or which bit data causes the final storage performance to be poor, it can be corrected through flexible and configurable preset information, thereby realizing the demand for improving the performance of the PCM memory module.

[0061] This embodiment takes the initial row address as an example to introduce some methods of replacing the initial access address, and those skilled in the art can apply them to the replacement of the initial block address or the initial column address accordingly.

[0062] In some embodiments, the replacement of the initial row address may be for all bits of the initial row address, or only for one or more preset bits. The preset information includes a value for performing a logical operation with the initial row address, and position information for performing a logical operation with the initial row address.

[0063] (1) When the logic operation uses the XOR budget of all bits and "1", the row address obtained after the initial row address "01010101" is replaced is "10101010".

[0064] (2) When the logic operation adopts the XOR budget of the preset bit (1234th bit) and "1", the row address obtained after the initial row address "01010101" is replaced is "10100101".

[0065] (3) When the logic operation uses the initial row address and the preset address "00110011" to perform a bitwise XOR operation, the row address obtained after the initial row address "01010101" is replaced is "01100110". By setting the preset information with the same bit width as the initial access address, the preset information is bitwise XORed with the initial block address, the initial row address and the initial column address to obtain the remapped address, so that the access to each storage block and storage array can be independently controlled.

[0066] In some embodiments, the logic operations for different bits in the initial row address may be different.

[0067] In one example, the replacement logic for the first address in the initial row address is an AND operation, and the replacement logic for the second address in the initial row address is an OR operation, etc.

[0068] In some embodiments, the logic operation on the initial row address may be a single logic operation or a compound logic operation.

[0069] In one example, the first bit address in the initial row address is firstly ANDed with "1" and then XORed with "0".

[0070] In some embodiments, the preset block character, the preset row character, and the preset column character are set to different character strings. That is, the initial block address bank address, the initial row address row address, and the initial column address column address are adjusted in different ways to improve the diversity of address replacement, thereby providing targeted settings for the performance of different storage blocks or different storage arrays.

[0071] Accordingly, the replacement of the initial block address bank address, the initial row address row address and the initial column address column address may be for all bits of the initial row address, or only for one or more preset bits; in addition, the logical operation methods for different bits in the initial block address bank address, the initial row address row address and the initial column address columnaddress may be different.

[0072] In some embodiments, the processing module 102 includes a mode register. The mode register is used to determine the access command and replace the initial access address, which basically does not require changing the hardware structure of the memory and improves chip performance with almost no change in cost.

[0073] In some embodiments, different memory chips 100 may replace the initial block address bank address, the initial row address rowaddress and the initial column address column address in different ways.

[0074] In one example, refer to Figure 2 , Figure 2 The replacement logic diagram of different memory chips provided in this embodiment, the mode register Mode Reg0 in Die0 includes the pre-block character M_RA_0, the preset row character M_CA_0 and the preset column character M_BA_0; the mode register Mode Reg1 in Die1 includes the pre-block character M_RA_1, the preset row character M_CA_1 and the preset column character M_BA_1; the mode register Mode Reg2 in Die2 includes the pre-block character M_RA_2, the preset row character M_CA_2 and the preset column character M_BA_2. Different memory chips 100 realize different replacement methods for the initial block address bank address, the initial row address row address and the initial column address columnaddress by configuring different preset block characters, preset row characters and preset column characters.

[0075] In one example, different memory chips 100 replace the initial block address bank address in different ways.

[0076] refer to Figure 3 , Figure 3 A schematic diagram of different initial block address replacement logics corresponding to different memory chips provided in this embodiment, assuming that the access command received by the input pin CAPIN is used to access bank 15+column nn+row nn, the address processing structure in die1 can enable die1 to access bank 8+column nn+row nn, and the address processing structure in die2 can enable die2 to access bank 0+column nn+row nn.

[0077] In one example, different memory blocks 200 replace the initial row address row address and the initial column address columnaddress in different ways.

[0078] refer to Figure 4 , Figure 4A schematic diagram of the replacement logic of different initial row addresses and initial column addresses corresponding to different memory chips provided in this embodiment, assuming that the access command received by the input pin CA PIN is used to access bank 15+column nn+row nn, the address processing structure in die1 can enable die1 to access bank15+column mm+row nn, and the address processing structure in die2 can enable die2 to access bank 15+column nn+row mm.

[0079] In summary, for the address processing structure provided in this embodiment, the access address is obtained by replacing the initial access address corresponding to the access command, and the access address is used for actual access, so that the memory can achieve controllable addressing when reading / writing a channel, and avoids the situation where the poor performance area of ​​the poor performance Bank is accessed during unified addressing. It should be noted that, in the absence of conflict, the features disclosed in the address processing structure provided in the above embodiment can be randomly combined to obtain a new address processing structure embodiment.

[0080] Another embodiment of the present disclosure further provides a memory to improve the addressing flexibility of the phase change memory, thereby improving the performance of the phase change memory module.

[0081] Specifically, the memory includes a storage controller and multiple storage chips, the storage controller is used to output access commands, the storage chips access data based on the access commands, and at least one of the multiple storage chips includes the address processing structure provided in the above embodiment.

[0082] By setting the address processing structure, different memory chips that originally used the same area of ​​the same memory block each time according to unified addressing will become different areas using different memory blocks each time. The performance of these memory blocks and areas are different, thereby balancing and improving chip performance.

[0083] In some embodiments, the preset information corresponding to the address processing structures in different memory chips is different.

[0084] In one example, refer to Figure 2 , Figure 2The replacement logic diagram of different memory chips provided in this embodiment, the mode register Mode Reg0 in Die0 includes the pre-block character M_RA_0, the preset row character M_CA_0 and the preset column character M_BA_0; the mode register Mode Reg1 in Die1 includes the pre-block character M_RA_1, the preset row character M_CA_1 and the preset column character M_BA_1; the mode register Mode Reg2 in Die2 includes the pre-block character M_RA_2, the preset row character M_CA_2 and the preset column character M_BA_2. Different memory chips 100 realize different replacement methods for the initial block address bank address, the initial row address row address and the initial column address columnaddress by configuring different preset block characters, preset row characters and preset column characters.

[0085] In one example, different memory chips 100 replace the initial block address bank address in different ways.

[0086] refer to Figure 3 , Figure 3 A schematic diagram of different initial block address replacement logics corresponding to different memory chips provided in this embodiment, assuming that the access command received by the input pin CAPIN is used to access bank 15+column nn+row nn, the address processing structure in die1 can enable die1 to access bank 8+column nn+row nn, and the address processing structure in die2 can enable die2 to access bank 0+column nn+row nn.

[0087] In one example, different memory blocks 200 replace the initial row address row address and the initial column address columnaddress in different ways.

[0088] refer to Figure 4 , Figure 4 A schematic diagram of the replacement logic of different initial row addresses and initial column addresses corresponding to different memory chips provided in this embodiment, assuming that the access command received by the input pin CA PIN is used to access bank 15+column nn+row nn, the address processing structure in die1 can enable die1 to access bank15+column mm+row nn, and the address processing structure in die2 can enable die2 to access bank 15+column nn+row mm.

[0089] In some embodiments, the address processing structures in different memory chips adjust the initial access address in different ways.

[0090] This embodiment takes the initial row address as an example to introduce some methods of replacing the initial access address, and those skilled in the art can apply them to the replacement of the initial block address or the initial column address accordingly.

[0091] In some embodiments, the replacement of the initial row address may be for all bits of the initial row address, or only for one or more preset bits. The preset information includes the value of the logic operation with the initial row address and the position information of the logic operation with the initial row address.

[0092] (1) When the logic operation uses the XOR budget of all bits and "1", the row address obtained after the initial row address "01010101" is replaced is "10101010".

[0093] (2) When the logic operation adopts the XOR budget of the preset bit (1234th bit) and "1", the row address obtained after the initial row address "01010101" is replaced is "10100101".

[0094] (3) When the logic operation uses the initial row address and the preset address "00110011" to perform a bitwise XOR operation, the row address obtained after the initial row address "01010101" is replaced is "01100110". By setting the preset information with the same bit width as the initial access address, the preset information is bitwise XORed with the initial block address, the initial row address and the initial column address to obtain the remapped address, so that the access to each storage block and storage array can be independently controlled.

[0095] In some embodiments, the logic operations for different bits in the initial row address may be different.

[0096] In one example, the replacement logic for the first address in the initial row address is an AND operation, and the replacement logic for the second address in the initial row address is an OR operation, etc.

[0097] In some embodiments, the logic operation on the initial row address may be a single logic operation or a compound logic operation.

[0098] In one example, the first bit address in the initial row address is firstly ANDed with "1" and then XORed with "0".

[0099] In some embodiments, the preset block character, the preset row character, and the preset column character are set to different character strings. That is, the initial block address bank address, the initial row address row address, and the initial column address column address are adjusted in different ways to improve the diversity of address replacement, thereby providing targeted settings for the performance of different storage blocks or different storage arrays.

[0100] Accordingly, the replacement of the initial block address bank address, the initial row address row address and the initial column address column address may be for all bits of the initial row address, or only for one or more preset bits; in addition, the logical operation methods for different bits in the initial block address bank address, the initial row address row address and the initial column address columnaddress may be different.

[0101] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the detailed description of other embodiments above, and will not be repeated here.

[0102] The basic concepts have been described above. Obviously, for those skilled in the art, the above detailed disclosure is only for example and does not constitute a limitation of the present disclosure. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements and corrections to the present disclosure. Such modifications, improvements and corrections are suggested in the present disclosure, so such modifications, improvements and corrections still belong to the spirit and scope of the exemplary embodiments of the present disclosure.

[0103] The above is a detailed introduction to an address processing structure and a memory provided by an embodiment of the present disclosure. Specific examples are used in this article to illustrate the principles and implementation methods of the present disclosure. The description of the above embodiments is only used to help understand the method of the present disclosure and its core idea. At the same time, for technical personnel in this field, according to the idea of ​​the present disclosure, there will be changes in the specific implementation method and application scope. In summary, it can be seen that the content of this specification should not be understood as a limitation on the present disclosure.

Claims

1. An address processing structure, characterized in that: include: A compiling module is configured to: receive an access command, and obtain an initial access address based on the access command; A processing module is configured to: receive the access command, and determine whether to perform address replacement based on the access command; The processing module is also connected to the compiling module and stores preset information. The processing module is also configured to: if the address replacement needs to be performed, adjust the initial access address based on the preset information to obtain an access address.

2. The address processing structure according to claim 1, characterized in that: The processing module comprises: a determination unit configured to: receive and determine whether the access command satisfies a preset condition, and generate an adjustment signal if the access command satisfies the preset condition; The replacement unit is configured to: in response to the adjustment signal, adjust the initial access address based on the preset information to obtain the access address.

3. The address processing structure according to claim 1 or 2, characterized in that: The processing module is configured to obtain the access address by performing a logical operation, inversion, address left shift or address right shift based on the preset information and the character of the corresponding bit of the initial access address.

4. The address processing structure according to claim 2, characterized in that: The replacement unit is arranged based on at least one of an AND gate, a NAND gate, an OR gate, a NOR gate, an XOR gate, and an XNOR gate.

5. The address processing structure according to claim 1, characterized in that: The initial access address includes at least one of an initial block address, an initial row address, and an initial column address; The preset information includes a preset block character, a preset row character, and a preset column character corresponding to the initial access address; The access address includes an access block address, an access row address, and an access column address corresponding to the initial access address; The processing module is configured to: adjust the initial block address based on the preset block character to obtain the access block address; Adjusting the initial row address based on the preset row character to obtain the access row address; The initial column address is adjusted based on the preset column character to obtain the access column address.

6. The address processing structure according to claim 5, characterized in that: The preset block characters, the preset row characters, and the preset column characters are set as different character strings.

7. The address processing structure according to claim 1, characterized in that: The processing module includes a mode register.

8. A memory, characterized in that: include: A storage controller, configured to output an access command; A plurality of storage chips, wherein the storage chips access data based on the access command; At least one of the plurality of memory chips comprises the address processing structure according to any one of claims 1 to 7.

9. The memory according to claim 8, characterized in that The preset information corresponding to the address processing structure in different storage chips is different.

10. The memory according to claim 8 or 9, characterized in that: The address processing structures in different memory chips adjust the initial access address in different ways.

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