Distributed implementation method and device of data fetch instruction emission queue

Abstract

The present invention provides a distributed implementation method and device of a fetch instruction emission queue, which relates to the field of computer technology. The method includes: transmitting fetch instructions in a fetch instruction emission queue; in the case of failure in the execution of the fetch instruction, according to the execution failure reason corresponding to the fetch instruction, storing the fetch instruction in a target queue to re-execute the fetch instruction; the target queue does not include the fetch instruction emission queue. The method of the embodiment of the present application implements the re-execution of the fetch instruction in a distributed manner based on the reason for the failure of the execution of the fetch instruction, avoiding the queue blocking existing in the prior art of controlling the emission of the fetch instruction and the re-execution after emission through a queue, as well as the high difficulty in implementing the fetch instruction emission queue, large resource requirements and long time consumption, effectively reducing the control complexity of the fetch instruction emission queue, reducing processing delays, improving the execution efficiency of memory access instructions, and reducing resource consumption.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a distributed implementation method and device of a data fetch instruction emission queue. Background Art

[0002] The processor's memory access instructions generally include load instructions and store instructions. The data fetched by the load instruction is usually the source operand required by the following instructions. The following instructions need to wait for the result of the load instruction before they can be executed, so the execution efficiency of the load instruction is particularly important.

[0003] In the related art, a queue is used to control the transmission of fetch instructions and the re-execution of multiple situations after transmission. However, the implementation of the fetch instruction transmission queue is difficult, resource-intensive and time-consuming. Therefore, how to reduce the control complexity of the fetch instruction transmission queue and improve the processing efficiency of the fetch instructions is a technical problem that needs to be solved urgently by those skilled in the art. Summary of the invention

[0004] The present invention provides a distributed implementation method and device for a data fetch instruction emission queue, which implements the re-execution of the data fetch instruction in a distributed manner based on the cause of the failure of the data fetch instruction execution, thereby avoiding the queue blocking existing in the prior art of controlling the emission of data fetch instructions and re-execution after emission through one queue, as well as the high difficulty, large resource demand and long time consumption in the implementation of the data fetch instruction emission queue, effectively reducing the control complexity of the data fetch instruction emission queue, reducing processing delays, improving the execution efficiency of memory access instructions, and reducing resource consumption.

[0005] The present invention provides a distributed implementation method of a data fetch instruction emission queue, comprising the following steps.

[0006] The fetch instruction in the fetch instruction emission queue is emitted;

[0007] In the case where the fetch instruction fails to execute, the fetch instruction is stored in a target queue according to the execution failure reason corresponding to the fetch instruction, so as to re-execute the fetch instruction; the target queue does not include the fetch instruction issuance queue.

[0008] According to a distributed implementation method of a data fetch instruction emission queue provided by the present invention, according to the execution failure reason corresponding to the data fetch instruction, the data fetch instruction is stored in a target queue to re-emit the data fetch instruction, including:

[0009] When the execution failure reason corresponding to the fetch instruction is related to the read-after-write RAW of the fetch instruction, the fetch instruction is stored in a queue related to the fetch instruction RAW;

[0010] When the target condition is met, the fetch instruction in the fetch instruction RAW related queue is sent to the fetch instruction re-execution queue and re-issued.

[0011] According to a distributed implementation method of a fetch instruction emission queue provided by the present invention, when a target condition is met, the fetch instruction in the fetch instruction RAW related queue is sent to the fetch instruction re-execution queue and re-emitted, including:

[0012] When it is determined that the target store instruction has been executed or after waiting for a preset time period, the fetch instruction in the fetch instruction RAW related queue is sent to the fetch instruction re-execution queue and re-issued; the execution order of the target store instruction is before the execution order of the fetch instruction that failed to execute.

[0013] According to a distributed implementation method of a fetch instruction emission queue provided by the present invention, the fetch instruction RAW related queue allocates queue items when a store instruction is emitted, and releases them when all fetch instructions before the execution sequence of the store instruction are submitted.

[0014] According to a distributed implementation method of a data fetch instruction emission queue provided by the present invention, according to the execution failure reason corresponding to the data fetch instruction, the data fetch instruction is stored in a target queue to re-emit the data fetch instruction, including:

[0015] When the execution failure reason corresponding to the fetch instruction is related to the read-after-read RAR of the fetch instruction, the fetch instruction is stored in the fetch instruction RAR related queue;

[0016] When the target condition is met, the fetch instruction in the fetch instruction RAR related queue is sent to the fetch instruction re-execution queue and re-issued.

[0017] According to a distributed implementation method of a fetch instruction emission queue provided by the present invention, when a target condition is met, the fetch instruction in the fetch instruction RAR related queue is sent to the fetch instruction re-execution queue and re-emitted, comprising:

[0018] When it is determined that the target fetch instruction has been executed or after waiting for a preset time period, the fetch instruction in the fetch instruction RAR related queue is sent to the fetch instruction re-execution queue and re-issued; the execution order of the target fetch instruction is before the execution order of the failed fetch instruction.

[0019] According to a distributed implementation method of a fetch instruction emission queue provided by the present invention, the fetch instruction RAR related queue allocates queue items when a fetch instruction is emitted, and releases them when all fetch instructions before the execution sequence of the fetch instruction are submitted.

[0020] According to a distributed implementation method of a fetch instruction emission queue provided by the present invention, according to the execution failure reason corresponding to the fetch instruction, the fetch instruction is stored in a target queue to re-execute the fetch instruction, including:

[0021] When the execution failure reason corresponding to the fetch instruction is data cache access failure and / or TLB access failure, the fetch instruction is stored in a fetch instruction re-execution queue and re-issued.

[0022] The present invention also provides a distributed implementation device of a data fetch instruction emission queue, comprising the following modules:

[0023] A transmitting module, used for transmitting the fetch instruction in the fetch instruction transmitting queue;

[0024] The processing module is used for storing the fetch instruction into a target queue according to the execution failure reason corresponding to the fetch instruction when the fetch instruction fails to execute, so as to re-execute the fetch instruction; the target queue does not include the fetch instruction emission queue.

[0025] The present invention also provides an electronic device, comprising a memory, a processor and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the distributed implementation method of the data fetch instruction emission queue as described in any one of the above is implemented.

[0026] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the distributed implementation method of the data fetch instruction emission queue as described in any one of the above is implemented.

[0027] The present invention also provides a computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the distributed implementation method of the data fetch instruction emission queue as described above is implemented.

[0028] The distributed implementation method and device of the data fetch instruction emission queue provided by the present invention divides the existing data fetch instruction emission queue into multiple queues according to function based on the reason for the failure of the data fetch instruction execution, so that the data fetch instruction can be re-executed in a distributed manner based on the reason for the failure of the data fetch instruction execution, avoiding the queue blocking existing in the prior art of controlling the emission of data fetch instructions and re-execution after emission through one queue, as well as the high difficulty, large resource demand and long time consumption in implementing the data fetch instruction emission queue, effectively reducing the control complexity of the data fetch instruction emission queue, reducing processing delays, improving the execution efficiency of memory access instructions, and reducing resource consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0030] Figure 1 It is one of the flow charts of the distributed implementation method of the data fetch instruction emission queue provided by the present invention.

[0031] Figure 2 This is the second flow chart of the distributed implementation method of the data fetch instruction emission queue provided by the present invention.

[0032] Figure 3 It is a structural schematic diagram of a distributed implementation device of a data fetch instruction emission queue provided by the present invention.

[0033] Figure 4 It is a structural schematic diagram of the electronic device provided by the present invention. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0035] Combine the following Figure 1-Figure 4 The distributed implementation method and device of the fetch instruction issuing queue of the present invention are described.

[0036] In order to facilitate a clearer understanding of the technical solutions of the embodiments of the present application, some technical contents related to the embodiments of the present application are first introduced.

[0037] The development of processor memory access speed is far behind the development of processor computing speed. The increasingly severe memory access speed problem has seriously restricted the further improvement of processor performance. Improving the execution speed of processor memory access instructions is the key to improving processor performance.

[0038] The memory access instructions of the processor generally include load instructions and store instructions. The data fetched by the load instruction is usually the source operand required by the subsequent instructions. The subsequent instructions need to wait for the result of the load instruction before they can be executed. Therefore, the execution efficiency of the load instruction is particularly important. However, the processing of the load instruction is complex. In the prior art, the load instruction emission queue adopts a centralized implementation method, using one queue to control the emission of the load instruction and the various situations of re-execution after emission. As a result, the implementation of the load instruction emission queue is difficult, resource-intensive, and time-consuming, making it a timing critical path of the processor. Therefore, it is necessary to reduce the control complexity of the load instruction emission queue and improve the processing efficiency of the load instruction.

[0039] The situations that the fetch instruction issue queue needs to handle include: (1) issuing fetch instructions, allowing the fetch instructions to access the data cache (DCache). If the access to the data cache fails, the fetch instruction needs to return to the issue queue and be re-executed; (2) fetch instruction-related processing. If there is a correlation, the fetch instruction needs to return to the issue queue and be re-executed; (3) other situations encountered by the fetch instruction that require re-execution, such as a translation backup buffer access failure (TLB miss).

[0040] Load instructions generally include a load address, while store instructions generally include a store address and store data. When a load instruction is executed, the load address of the load instruction is compared with the store addresses of all store instructions that precede the load instruction in the execution sequence. The address comparison is matched in bytes. If they match, it means that the load instruction and the store instruction are related, and the store data of the store instruction needs to be passed to the load instruction (Store to Load Forwarding).

[0041] In the processor, memory access instructions generally access memory through register indirect addressing. Therefore, only after the address of the memory access instruction is calculated, the relevant judgment of the load instruction and the store instruction, that is, the relevant judgment of RAW (read after write), can be performed. There is a situation where the address of the related Store instruction before the Load instruction has not been determined. In this case, there are two processing methods for the Load instruction in the prior art:

[0042] The first processing method is to wait for the addresses of all the Store instructions with undetermined addresses before the Load instruction to be determined before performing the data fetching operation. In essence, the Load instruction and the Store instructions with undetermined addresses are still executed sequentially. After waiting for the addresses of all the Store instructions before the Load instruction to be determined, the Load instruction is executed and the related judgment of the Load instruction and the Store instruction is performed. If the addresses match, the data is transferred from the Store instruction to the Load instruction.

[0043] The second processing method is to guess that the Load instruction will not be related to the Store instruction whose address is not determined in the execution sequence, which is referred to as the Load instruction guess irrelevant. Execute the Load instruction first. If the address of the previous Store instruction is determined and it is proved to be related to the Load instruction, a guess error of the Load instruction guess irrelevant occurs. In this case, the Load instruction needs to be set as an exception, and the emission queue re-transmits the Load instruction with the guess error and all instructions after the Load instruction. Modern high-performance processors usually use the second processing method to further improve the degree of out-of-order execution of memory access instructions.

[0044] Multi-core processors may also have RAR (read after read) dependencies, that is, the out-of-order processor may have the program sequence behind the fetch instruction executed first, and the program sequence after the fetch instruction with the same address. If there is an external consistency request with the same address from other processor cores, such as an external invalidation request, it means that other processor cores may have modified the data, which will cause the program sequence in the front fetch instruction to read the newly modified data, while the program sequence in the back fetch instruction reads the old data. At this time, the fetch instruction in the back of the program sequence must be set as an exception, and the transmission queue must be returned to re-transmit and execute the fetch instruction and all instructions behind it.

[0045] If a data cache (DCache) access failure or a TLB (Translation Lookaside Buffer) access failure occurs in a data fetch instruction, the data fetch instruction issue queue needs to reissue the data fetch instruction for execution.

[0046] In addition, due to the possibility of re-execution and the need to maintain the order mentioned above, the fetch instruction issuance queue cannot exit after issuing the instruction and needs to wait for the instruction to be submitted before exiting, which also wastes the valuable resources of the fetch instruction issuance queue.

[0047] In summary, the functions of the various operations that the data fetch instruction emission queue is responsible for processing vary greatly. If unified control is required, a large number of control queue items are required, and a large number of functions are completed. The queue has many ports for address comparison, resulting in high difficulty in implementation, large resource requirements, and a long time to complete each operation, making it a timing critical path for the processor, which also wastes processor area and increases costs.

[0048] Figure 1 It is one of the flow charts of the distributed implementation method of the data fetch instruction emission queue provided by the present invention, such as Figure 1 As shown, the method includes the following:

[0049] Step 101: Issue the fetch instruction in the fetch instruction issue queue.

[0050] Specifically, in the related art, the fetch instruction emission queue is used to control the emission of the fetch instruction and the various situations of re-execution after emission. There are problems such as high difficulty in implementing the fetch instruction emission queue, large resource requirements and long time consumption. In order to solve the above problems, in the embodiment of the present application, the fetch instruction to be processed is first obtained, and the fetch instruction is stored in the fetch instruction emission queue for emission.

[0051] Step 102: When the fetch instruction fails to execute, according to the execution failure reason corresponding to the fetch instruction, the fetch instruction is stored in a target queue to re-execute the fetch instruction; the target queue does not include a fetch instruction issuing queue.

[0052] Specifically, in an embodiment of the present application, after the fetch instruction in the fetch instruction emission queue is emitted, if there is a situation where the fetch instruction fails to execute, the fetch instruction is stored in the target queue according to the execution failure reason corresponding to the fetch instruction to re-execute the fetch instruction. Optionally, a corresponding target queue can be established based on the reason for the execution failure of the fetch instruction. If the execution failure reason corresponding to the fetch instruction includes fetch instruction RAW related, a fetch instruction RAW related queue can be established. Optionally, other corresponding queues can also be established based on the reason for the execution failure of the fetch instruction, which is not specifically limited in the embodiment of the present application.

[0053] It should be noted that in the embodiment of the present application, based on the reasons for the failure of the execution of the fetch instruction, the existing fetch instruction emission queue is divided into multiple queues according to function, so that the fetch instruction can be re-executed in a distributed manner based on the reasons for the failure of the execution of the fetch instruction, thereby avoiding the queue blocking existing in the prior art of controlling the emission of the fetch instruction and the re-execution after the emission by one queue, as well as the high difficulty, large resource demand and long time consumption in implementing the fetch instruction emission queue, effectively reducing the control complexity of the fetch instruction emission queue, reducing processing delays, improving the execution efficiency of memory access instructions, and reducing resource consumption.

[0054] For example, the execution failure reasons corresponding to the fetch instruction A include fetch instruction RAW related. If the fetch instruction A is directly stored in the fetch instruction emission queue, the length of the fetch instruction emission queue will increase. Furthermore, if the RAW related problems corresponding to the fetch instruction A are not solved, the fetch instruction A will repeatedly fail to execute and be stored in the fetch instruction emission queue for repeated emission, thereby causing queue blocking and the implementation difficulty of the fetch instruction emission queue is high, resource requirements are large, and time-consuming. In the embodiment of the present application, after the fetch instruction A is stored in the fetch instruction RAW related queue, it is possible to wait for a preset time or determine that the RAW related problems are solved before re-executing the fetch instruction A, thereby effectively reducing the control complexity of the fetch instruction emission queue, reducing processing delays, improving the execution efficiency of memory access instructions, and reducing resource consumption.

[0055] The method of the above embodiment divides the existing data fetch instruction emission queue into multiple queues according to function based on the reason for the failure of the data fetch instruction execution. It can also implement the re-execution of the data fetch instruction in a distributed manner based on the reason for the failure of the data fetch instruction execution. It avoids the queue blocking existing in the prior art of controlling the emission of data fetch instructions and re-execution after emission by one queue, as well as the high difficulty, large resource demand and long time consumption in implementing the data fetch instruction emission queue. It effectively reduces the control complexity of the data fetch instruction emission queue, reduces processing delays, improves the execution efficiency of memory access instructions, and reduces resource consumption.

[0056] In one embodiment, according to the execution failure reason corresponding to the fetch instruction, the fetch instruction is stored in the target queue to re-issue the fetch instruction, including:

[0057] When the execution failure reason corresponding to the fetch instruction is related to the fetch instruction RAW, the fetch instruction is stored in the fetch instruction RAW related queue;

[0058] When the target condition is met, the fetch instruction in the fetch instruction RAW related queue is sent to the fetch instruction re-execution queue and re-issued.

[0059] Specifically, in the embodiment of the present application, when it is determined that the execution failure reason corresponding to the fetch instruction is related to the fetch instruction RAW, the fetch instruction is stored in the fetch instruction RAW related queue; and when it is judged that the target condition is met, the fetch instruction in the fetch instruction RAW related queue is sent to the fetch instruction re-execution queue and re-transmitted. Optionally, after the fetch instruction A is stored in the fetch instruction RAW related queue, it is possible to wait for a preset time or judge that the RAW related problem is solved, and then re-execute the fetch instruction A, thereby improving the execution efficiency of the memory access instruction and reducing the processing delay and resource consumption. Optionally, the target condition can also be other conditions, which are not specifically limited in the embodiment of the present application.

[0060] The method of the above embodiment, when it is determined that the execution failure reason corresponding to the data fetch instruction is related to the data fetch instruction RAW, stores the data fetch instruction in the data fetch instruction RAW related queue; and when it is judged that the target condition is met, sends the data fetch instruction in the data fetch instruction RAW related queue to the data fetch instruction re-execution queue and re-transmits it, which can effectively improve the execution efficiency of memory access instructions and reduce processing delays and resource consumption.

[0061] In one embodiment, when the target condition is met, the fetch instruction in the fetch instruction RAW related queue is sent to the fetch instruction re-execution queue and re-issued, including:

[0062] When it is determined that the target store instruction has been executed or after waiting for a preset time period, the fetch instruction in the fetch instruction RAW related queue is sent to the fetch instruction re-execution queue and re-issued; the execution order of the target store instruction is before the execution order of the failed fetch instruction.

[0063] Specifically, in the embodiment of the present application, when it is determined that the execution failure reason corresponding to the fetch instruction A is related to the fetch instruction RAW, and after the fetch instruction A is stored in the fetch instruction RAW related queue, if it is determined that the storage instructions before the execution sequence of the fetch instruction A have been successfully executed, it indicates that the RAW related problem corresponding to the fetch instruction A has been solved, and the fetch instruction in the fetch instruction RAW related queue can be sent to the fetch instruction re-execution queue and re-transmitted, thereby improving the execution efficiency of the memory access instruction and reducing the processing delay and resource consumption. Optionally, after waiting for a preset time period, the fetch instruction in the fetch instruction RAW related queue can be sent to the fetch instruction re-execution queue and re-transmitted, thereby reducing resource consumption.

[0064] In one embodiment, according to the execution failure reason corresponding to the fetch instruction, the fetch instruction is stored in the target queue to re-issue the fetch instruction, including:

[0065] When the execution failure reason corresponding to the fetch instruction is related to the fetch instruction RAR, the fetch instruction is stored in the fetch instruction RAR related queue;

[0066] When the target condition is met, the fetch instruction in the fetch instruction RAR related queue is sent to the fetch instruction re-execution queue and re-issued.

[0067] Specifically, in the embodiment of the present application, when it is determined that the execution failure reason corresponding to the fetch instruction is related to the fetch instruction RAR, the fetch instruction is stored in the fetch instruction RAR related queue; and when it is judged that the target condition is met, the fetch instruction in the fetch instruction RAR related queue is sent to the fetch instruction re-execution queue and re-transmitted. Optionally, after the fetch instruction A is stored in the fetch instruction RAR related queue, it can wait for a preset time or judge that the RAR related problem is solved, and then re-execute the fetch instruction A, thereby improving the execution efficiency of the memory access instruction and reducing the processing delay and resource consumption. Optionally, the target condition can also be other conditions, which are not specifically limited in the embodiment of the present application.

[0068] The method of the above embodiment, when it is determined that the execution failure reason corresponding to the data fetch instruction is related to the data fetch instruction RAR, stores the data fetch instruction in the data fetch instruction RAR related queue; and when it is judged that the target condition is met, sends the data fetch instruction in the data fetch instruction RAR related queue to the data fetch instruction re-execution queue and re-transmits it, which can effectively improve the execution efficiency of memory access instructions and reduce processing delays and resource consumption.

[0069] In one embodiment, when the target condition is met, the fetch instruction in the fetch instruction RAR related queue is sent to the fetch instruction re-execution queue and re-issued, including:

[0070] When it is determined that the target fetch instruction has been executed or after waiting for a preset time period, the fetch instruction in the fetch instruction RAR related queue is sent to the fetch instruction re-execution queue and re-issued; the execution order of the target fetch instruction is before the execution order of the failed fetch instruction.

[0071] Specifically, in the embodiment of the present application, when it is determined that the execution failure reason corresponding to the fetch instruction A is related to the fetch instruction RAR, and after the fetch instruction A is stored in the fetch instruction RAR related queue, if it is determined that the fetch instructions before the execution sequence of the fetch instruction A have been successfully executed, it indicates that the RAR related problem corresponding to the fetch instruction A has been solved, and the fetch instruction in the fetch instruction RAR related queue can be sent to the fetch instruction re-execution queue and re-transmitted, thereby improving the execution efficiency of the memory access instruction and reducing the processing delay and resource consumption. Optionally, after waiting for a preset time period, the fetch instruction in the fetch instruction RAR related queue can be sent to the fetch instruction re-execution queue and re-transmitted, thereby reducing resource consumption.

[0072] In one embodiment, according to the execution failure reason corresponding to the fetch instruction, the fetch instruction is stored in the target queue to re-execute the fetch instruction, including:

[0073] When the execution failure reason corresponding to the fetch instruction is data cache access failure and / or TLB access failure, the fetch instruction is stored in the fetch instruction re-execution queue and re-issued.

[0074] Specifically, in the embodiment of the present application, when it is determined that the execution failure reason corresponding to the fetch instruction A is data cache access failure and / or TLB access failure, the fetch instruction is stored in the fetch instruction re-execution queue and re-transmitted. Optionally, the fetch instruction A can be re-executed after the data cache access failure and / or TLB access failure problem is solved or after waiting for a preset time, thereby improving the execution efficiency of the memory access instruction and reducing the processing delay and resource consumption. Optionally, the target condition can also be other conditions, which are not specifically limited in the embodiment of the present application.

[0075] The method of the above embodiment, when it is determined that the execution failure reason corresponding to the data access instruction A is data cache access failure and / or TLB access failure, stores the data access instruction in the data access instruction re-execution queue and re-issues it, which can effectively improve the execution efficiency of the memory access instruction and reduce processing delay and resource consumption.

[0076] For example, Figure 2 As shown, a distributed implementation method of a fetch instruction emission queue is provided in an embodiment of the present application, which is as follows:

[0077] Through the distributed implementation method and device of the data fetch instruction issue queue, the data fetch instruction issue queue is separated into: a data fetch instruction issue queue (Load Issue Queue), a data fetch instruction read-after-write (RAW) related queue (Load RAW Queue), a data fetch instruction read-after-read (RAR) related queue (Load RAR Queue) and a data fetch instruction re-execution queue (LoadReplay Queue).

[0078] (1) The fetch instruction emission queue allocates (Allocate) queue items when the fetch instruction is dispatched (Dispatch), and releases (Deallocate) queue items when the fetch instruction is submitted, completing the emission function of the fetch instruction emission queue in the prior art. It no longer handles the re-emission and execution of fetch instructions. All re-emission and execution are initiated by the fetch instruction re-execution (Replay) queue. The processing related to fetch instructions is no longer the responsibility of the emission queue, but is handled by the special RAW-related queue and RAR-related queue. The fetch instruction re-execution (Replay) queue, the fetch instruction read-after-write (RAW)-related queue, and the fetch instruction read-after-read (RAR)-related queue are all allocated out of order.

[0079] Load Replay Queue: Data cache access failure and TLB (Translation Lookaside Buffer) access failure return to the Load Replay Queue for re-execution. Allocate queue items when load replay occurs, and deallocate queue items when the load is executed.

[0080] The Load RAW Queue allocates (Allocate) queue items when a store instruction is issued (Issue), and releases (Deallocate) queue items when all load instructions older than the store instruction are submitted. If a load instruction is re-issued and executed due to RAW correlation, it is sent to the Load Replay Queue for re-issuance and execution.

[0081] Load RAR Queue allocates queue items when a load instruction is issued, and releases queue items when all older load instructions are submitted. If a load instruction is re-issued due to RAR correlation, it is sent to Load Replay Queue for re-issuance.

[0082] The method of the above embodiment divides the existing data fetch instruction emission queue into multiple queues according to function based on the reason for the failure of the data fetch instruction execution. It can also implement the re-execution of the data fetch instruction in a distributed manner based on the reason for the failure of the data fetch instruction execution. It avoids the queue blocking existing in the prior art of controlling the emission of data fetch instructions and re-execution after emission by one queue, as well as the high difficulty, large resource demand and long time consumption in implementing the data fetch instruction emission queue. It effectively reduces the control complexity of the data fetch instruction emission queue, reduces processing delays, improves the execution efficiency of memory access instructions, and reduces resource consumption.

[0083] The following is a description of the distributed implementation device of the fetch instruction emission queue provided by the present invention. The distributed implementation device of the fetch instruction emission queue described below and the distributed implementation method of the fetch instruction emission queue described above can be referred to each other. Figure 3 As shown, including:

[0084] The transmitting module 310 is used to transmit the fetch instruction in the fetch instruction transmitting queue;

[0085] The processing module 320 is used for storing the fetch instruction into a target queue according to the execution failure reason corresponding to the fetch instruction when the fetch instruction fails to execute, so as to re-execute the fetch instruction; the target queue does not include the fetch instruction issuing queue.

[0086] Optionally, the processing module 320 is specifically configured to:

[0087] When the execution failure reason corresponding to the fetch instruction is related to the fetch instruction RAW, the fetch instruction is stored in the fetch instruction RAW related queue;

[0088] When the target condition is met, the fetch instruction in the fetch instruction RAW related queue is sent to the fetch instruction re-execution queue and re-issued.

[0089] Optionally, the processing module 320 is specifically configured to:

[0090] When it is determined that the target store instruction has been executed or after waiting for a preset time period, the fetch instruction in the fetch instruction RAW related queue is sent to the fetch instruction re-execution queue and re-issued; the execution order of the target store instruction is before the execution order of the failed fetch instruction.

[0091] Optionally, the RAW-related queue of the fetch instruction allocates queue entries when the store instruction is issued, and releases them when all the fetch instructions before the execution sequence of the store instruction are submitted.

[0092] Optionally, the processing module 320 is specifically configured to:

[0093] When the execution failure reason corresponding to the fetch instruction is related to the fetch instruction RAR, the fetch instruction is stored in the fetch instruction RAR related queue;

[0094] When the target condition is met, the fetch instruction in the fetch instruction RAR related queue is sent to the fetch instruction re-execution queue and re-issued.

[0095] Optionally, the processing module 320 is specifically configured to:

[0096] When it is determined that the target fetch instruction has been executed or after waiting for a preset time period, the fetch instruction in the fetch instruction RAR related queue is sent to the fetch instruction re-execution queue and re-issued; the execution order of the target fetch instruction is before the execution order of the failed fetch instruction.

[0097] Optionally, the RAR-related queue of the fetch instruction allocates queue entries when the fetch instruction is issued, and releases them when all the fetch instructions before the execution sequence of the fetch instruction are submitted.

[0098] Optionally, the processing module 320 is specifically configured to:

[0099] When the execution failure reason corresponding to the fetch instruction is data cache access failure and / or TLB access failure, the fetch instruction is stored in the fetch instruction re-execution queue and re-issued.

[0100] Figure 4 An example of a physical structure diagram of an electronic device is provided, and the electronic device may include: a processor 410, a communication interface 420, a memory 430, and a communication bus 440, wherein the processor 410, the communication interface 420, and the memory 430 communicate with each other through the communication bus 440. The processor 410 may call the logic instructions in the memory 430 to execute a distributed implementation method of a fetch instruction emission queue, and the method includes: transmitting the fetch instruction in the fetch instruction emission queue; in the case of failure of the fetch instruction execution, according to the execution failure reason corresponding to the fetch instruction, the fetch instruction is stored in the target queue to re-execute the fetch instruction; the target queue does not include the fetch instruction emission queue.

[0101] In addition, the logic instructions in the above-mentioned memory 430 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0102] On the other hand, the present invention also provides a computer program product, which includes a computer program. The computer program can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the distributed implementation method of the fetch instruction emission queue provided by the above methods, the method including: transmitting the fetch instructions in the fetch instruction emission queue; in the event that the fetch instruction fails to execute, according to the execution failure reason corresponding to the fetch instruction, storing the fetch instruction in a target queue to re-execute the fetch instruction; the target queue does not include the fetch instruction emission queue.

[0103] On the other hand, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, it is implemented to execute the distributed implementation method of the fetch instruction emission queue provided by the above-mentioned methods. The method includes: transmitting the fetch instructions in the fetch instruction emission queue; in the event that the fetch instruction fails to execute, according to the execution failure reason corresponding to the fetch instruction, storing the fetch instruction in a target queue to re-execute the fetch instruction; the target queue does not include the fetch instruction emission queue.

[0104] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Those of ordinary skill in the art may understand and implement it without creative effort.

[0105] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0106] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A distributed implementation method of a data fetch instruction emission queue, characterized in that: include: The fetch instruction in the fetch instruction emission queue is emitted; In the case where the fetch instruction fails to execute, according to the execution failure reason corresponding to the fetch instruction, the fetch instruction is stored in the target queue to re-execute the fetch instruction; the target queue does not include the fetch instruction emission queue; According to the execution failure reason corresponding to the fetch instruction, the fetch instruction is stored in the target queue to re-issue the fetch instruction, including: When the execution failure reason corresponding to the fetch instruction is related to the read-after-write RAW of the fetch instruction, the fetch instruction is stored in a queue related to the fetch instruction RAW; When the target condition is met, the fetch instruction in the fetch instruction RAW related queue is sent to the fetch instruction re-execution queue and re-issued.

2. The distributed implementation method of the fetch instruction emission queue according to claim 1, characterized in that: When the target condition is met, the fetch instruction in the fetch instruction RAW related queue is sent to the fetch instruction re-execution queue and re-issued, including: When it is determined that the target store instruction has been executed or after waiting for a preset time period, the fetch instruction in the fetch instruction RAW related queue is sent to the fetch instruction re-execution queue and re-issued; the execution order of the target store instruction is before the execution order of the fetch instruction that failed to execute.

3. The distributed implementation method of the fetch instruction emission queue according to claim 2, characterized in that: The RAW-related queue for the fetch instruction allocates queue entries when a store instruction is issued, and releases them when all the fetch instructions before the execution sequence of the store instruction are submitted.

4. The distributed implementation method of the data fetch instruction emission queue according to any one of claims 1 to 3, characterized in that: According to the execution failure reason corresponding to the fetch instruction, the fetch instruction is stored in the target queue to re-issue the fetch instruction, including: When the execution failure reason corresponding to the fetch instruction is related to the read-after-read RAR of the fetch instruction, the fetch instruction is stored in the fetch instruction RAR related queue; When the target condition is met, the fetch instruction in the fetch instruction RAR related queue is sent to the fetch instruction re-execution queue and re-issued.

5. The distributed implementation method of the fetch instruction emission queue according to claim 4 is characterized in that: When the target condition is met, sending the fetch instruction in the fetch instruction RAR related queue to the fetch instruction re-execution queue and re-issuing it includes: When it is determined that the target fetch instruction has been executed or after waiting for a preset time period, the fetch instruction in the fetch instruction RAR related queue is sent to the fetch instruction re-execution queue and re-issued; the execution order of the target fetch instruction is before the execution order of the fetch instruction that failed to execute.

6. The distributed implementation method of the fetch instruction emission queue according to claim 5, characterized in that: The RAR-related queue of the fetch instruction allocates queue entries when the fetch instruction is issued, and releases them when all the fetch instructions before the execution sequence of the fetch instruction are submitted.

7. The distributed implementation method of the data fetch instruction emission queue according to any one of claims 1 to 3, characterized in that: According to the execution failure reason corresponding to the fetch instruction, the fetch instruction is stored in the target queue to re-execute the fetch instruction, including: When the execution failure reason corresponding to the fetch instruction is data cache access failure and / or translation lookaside buffer TLB access failure, the fetch instruction is stored in the fetch instruction re-execution queue and re-issued.

8. A distributed implementation device for a fetch instruction emission queue, characterized in that: include: A transmitting module, used for transmitting the fetch instruction in the fetch instruction transmitting queue; A processing module, for storing the fetch instruction in a target queue according to the execution failure reason corresponding to the fetch instruction, so as to re-execute the fetch instruction when the fetch instruction fails to execute; the target queue does not include the fetch instruction emission queue; storing the fetch instruction in the target queue according to the execution failure reason corresponding to the fetch instruction, so as to re-emit the fetch instruction, comprising: When the execution failure reason corresponding to the fetch instruction is related to the read-after-write RAW of the fetch instruction, the fetch instruction is stored in a queue related to the fetch instruction RAW; When the target condition is met, the fetch instruction in the fetch instruction RAW related queue is sent to the fetch instruction re-execution queue and re-issued.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the program, the distributed implementation method of the data fetch instruction issuance queue according to any one of claims 1 to 7 is implemented.

10. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the distributed implementation method of the data fetch instruction issue queue according to any one of claims 1 to 7 is implemented.

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