Chip test system, method, device and equipment

Abstract

The invention provides a chip testing system, method, device and equipment, the system comprises an instruction initiating end, a communication board card and a first resource board card, a testing unit is arranged in the first resource board card, the instruction initiating end is in communication connection with the communication board card, and the communication board card is connected with the testing unit through at least two transmission lines; the communication board card is used for analyzing the test instructions sent by the instruction initiating end and identifying a target test instruction from the test instructions; sending a target test instruction to the test unit through a first transmission line in the at least two transmission lines; the other test instructions in the test instructions are sent to the test unit through the second transmission line in the at least two transmission lines, a transmission channel is independently added for the target test instruction in the chip test system, and the target test instruction and the other test instructions are transmitted in different channels, so that the transmission delay of the target test instruction is controllable, and the test efficiency is improved. The test efficiency can be improved.

Description

Technical Field

[0001] The present disclosure relates to chip testing technology, and in particular to a chip testing system, method, device and equipment. Background Art

[0002] During chip testing, when multiple resource boards of the lower computer need to be soft-triggered synchronously, the host computer usually initiates a trigger (Trig) instruction, which is transmitted to each resource board through the service bus, so that each chip under test can complete the measurement action synchronously. The Trig instruction shares communication resources and bandwidth with other instructions. In order to ensure that the Trig instruction reaches multiple resource boards synchronously so that the measurement action is performed synchronously, it is necessary to ensure that the arbitration priority of the Trig instruction is higher than the priority of other instructions through logic design.

[0003] However, when the Trig instruction is mixed with other instructions for transmission, the received instruction needs to be unpacked in advance, and the Trig instruction needs to be extracted from it for priority control, which makes the circuit structure design more complicated. In addition, when the Trig instruction is mixed with other instructions for transmission, although the Trig instruction has the highest priority, if there is a current instruction occupying the bus and has not been transmitted, the Trig instruction also needs to wait for the instruction on the bus to be transmitted before sending it. Therefore, the delay of the Trig instruction on the bus is still uncontrollable, which causes the overall trigger time of the resource board to be forced to be extended, affecting the chip test efficiency. Summary of the invention

[0004] The embodiments of the present disclosure provide a chip testing system, method, apparatus and device, which can control the transmission delay of target test instructions and improve chip testing efficiency.

[0005] In one aspect of an embodiment of the present disclosure, a chip testing system is provided, the system comprising an instruction initiator, a communication board and a first resource board, the first resource board being provided with a test unit, the instruction initiator being communicatively connected to the communication board, the communication board being connected to the test unit via at least two transmission lines; the communication board being used to:

[0006] Parsing the test instructions sent by the instruction initiator, identifying a target test instruction from the test instructions, wherein the priority of the target test instruction is higher than the priority of other test instructions;

[0007] Sending the target test instruction to the test unit through a first transmission line of the at least two transmission lines;

[0008] The other test instructions among the test instructions are sent to the test unit through a second transmission line among the at least two transmission lines.

[0009] Optionally, the system includes at least two test units, the communication board includes a first communication unit and a second communication unit connected to each other, the instruction initiator is communicatively connected to the first communication unit, and the first communication unit and the second communication unit are respectively connected to different test units among the at least two test units;

[0010] The first communication unit is used for parsing the test instruction, identifying the target test instruction from the test instruction, forwarding the target test instruction to the second communication unit, and sending the target test instruction to the test unit corresponding to the first communication unit through the first transmission line;

[0011] The second communication unit is used to receive the target test instruction sent by the first communication unit, and send the target test instruction to the test unit corresponding to the second communication unit through the first transmission line.

[0012] Optionally, the first communication unit and the second communication unit are connected via a low-voltage differential signaling (LVDS) transmission line, and the first transmission line is an LVDS transmission line.

[0013] Optionally, the instruction initiator includes at least one of a host computer and a second resource board;

[0014] The host computer is provided with a host bus adapter, and the host bus adapter is communicatively connected with the communication board through a preset communication interface;

[0015] The second resource board is communicatively connected to the communication board via a preset communication link transmission line.

[0016] Another aspect of the embodiments of the present disclosure provides a chip testing method, which is applied to a communication board in the chip testing system described in the above aspect, and the method includes:

[0017] Receiving and parsing the test instruction sent by the instruction initiator in the system;

[0018] Based on the operation code of the test instruction, identifying a target test instruction from the test instruction, wherein the priority of the target test instruction is higher than the priority of other test instructions;

[0019] The target test instruction is sent to a test unit in the system through a first transmission line, and other test instructions among the test instructions are sent to the test unit through a second transmission line.

[0020] Optionally, the system includes at least two test units, the communication board includes a first communication unit and a second communication unit connected to each other, and the first communication unit and the second communication unit are respectively connected to different test units of the at least two test units;

[0021] The receiving and parsing the test instruction sent by the instruction initiator in the system includes:

[0022] Controlling the first communication unit to receive and parse the test instruction;

[0023] The sending the target test instruction to the test unit in the system through the first transmission line includes:

[0024] Controlling the first communication unit to forward the target test instruction to the second communication unit;

[0025] The first communication unit and the second communication unit are controlled to send the target test instruction to the corresponding test units respectively through the first transmission line.

[0026] Optionally, the method further includes:

[0027] Performing parameter training on the first transmission line in a first transmission direction until a first delay parameter in the first transmission direction meets a preset training condition;

[0028] Performing parameter training on the first transmission line in a second transmission direction until a second delay parameter in the second transmission direction meets the preset training condition;

[0029] The first transmission direction is the transmission direction from the test unit to the communication board, and the second transmission direction is the transmission direction from the communication board to the test unit.

[0030] Optionally, the performing parameter training on the first transmission line in the first transmission direction until the first delay parameter in the first transmission direction meets a preset training condition includes:

[0031] During the process of data collection by the communication board on the training message sent by the test unit, the delay parameter of the first transmission direction is adjusted to obtain message sampling data corresponding to each group of first candidate delay parameters;

[0032] Based on the training message and the message sampling data corresponding to each group of first candidate delay parameters, determining a first delay parameter that meets the preset training condition from each group of first candidate delay parameters;

[0033] The performing parameter training on the first transmission line in the second transmission direction until the second delay parameter in the second transmission direction meets the preset training condition includes:

[0034] In the process of the communication board continuously sending training messages to the test unit, the delay parameter of the second transmission direction is adjusted, and the message sampling data corresponding to each group of second candidate delay parameters fed back by the test unit through the first transmission line is received;

[0035] Based on the training message and the message sampling data corresponding to each group of second candidate delay parameters, a second delay parameter satisfying the preset training condition is determined from each group of second candidate parameters.

[0036] Another aspect of the embodiments of the present disclosure provides a chip testing device, which is applied to a communication board in the chip testing system described in the above aspect, and the device includes:

[0037] A receiving module, used for receiving and parsing a test instruction sent by an instruction initiator in the system;

[0038] an identification module, configured to identify a target test instruction from the test instructions based on an operation code of the test instruction, wherein the priority of the target test instruction is higher than the priority of other test instructions;

[0039] The sending module is used to send the target test instruction to the test unit in the system through a first transmission line, and to send other test instructions in the test instructions to the test unit through a second transmission line.

[0040] Another aspect of the present disclosure provides an electronic device, including:

[0041] Memory for storing computer programs;

[0042] The processor is used to execute the computer program stored in the memory, and when the computer program is executed, the method described in the above aspects is implemented.

[0043] Another aspect of the embodiments of the present disclosure provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the method described in the above aspects is implemented.

[0044] Another aspect of the embodiments of the present disclosure provides a computer program, including computer program instructions, which implement the methods described in the above aspects when executed by a processor.

[0045] Based on the embodiment of the present disclosure, at least two transmission lines are set between the communication board and the test unit, and the test instructions sent by the instruction initiator are parsed through the communication board. For target test instructions with higher priority than other test instructions, they are sent to the test unit through the first transmission line of at least two transmission lines, and for other test instructions, they are sent to the test unit through the second transmission line. In the chip test system, a transmission channel is separately added for the target test instructions, and the target test instructions and other test instructions are transmitted through different channels. In the case where a large number of test instructions are sent by the instruction initiator, other test instructions will not occupy the transmission channel, so that the transmission delay of the target test instructions can be controlled. For the target test instructions that need to be executed synchronously by the test unit, there is no need to set a large offset time to ensure that the instructions arrive at the test unit synchronously, which can improve the test efficiency.

[0046] The technical solution of the present disclosure is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The accompanying drawings, which constitute a part of the specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0048] The present disclosure may be more clearly understood from the following detailed description with reference to the accompanying drawings, in which:

[0049] Figure 1 A schematic diagram of the structure of an embodiment of a chip testing system disclosed in the present invention;

[0050] Figure 2 It is a structural schematic diagram of another embodiment of the chip testing system disclosed in the present invention;

[0051] Figure 3 A flowchart of an embodiment of the chip testing method disclosed in the present invention;

[0052] Figure 4 A flowchart of another embodiment of the chip testing method disclosed herein;

[0053] Figure 5 This is a schematic diagram of the data transmission direction of a first transmission line in an exemplary embodiment of the present disclosure;

[0054] Figure 6 It is a structural schematic diagram of an embodiment of a chip testing device disclosed in the present invention;

[0055] Figure 7 It is a structural schematic diagram of another embodiment of the chip testing device disclosed in the present invention;

[0056] Figure 8 The figure is a schematic diagram of the structure of an application embodiment of the electronic device disclosed in the present invention. DETAILED DESCRIPTION

[0057] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that the relative arrangement of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present disclosure unless otherwise specifically stated.

[0058] Those skilled in the art can understand that the terms "first" and "second" in the embodiments of the present disclosure are only used to distinguish different steps, devices or modules, etc., and neither represent any specific technical meaning nor indicate the necessary logical order between them.

[0059] It should also be understood that in the embodiments of the present disclosure, “plurality” may refer to two or more than two, and “at least one” may refer to one, two, or more than two.

[0060] It should also be understood that any component, data or structure mentioned in the embodiments of the present disclosure can generally be understood as one or more, unless explicitly limited or otherwise indicated in the context.

[0061] In addition, the term "and / or" in the present disclosure is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in the present disclosure generally indicates that the associated objects before and after are in an "or" relationship.

[0062] It should also be understood that the description of the various embodiments in the present disclosure focuses on the differences between the various embodiments, and the same or similar aspects thereof can be referenced to each other, and for the sake of brevity, they will not be described one by one.

[0063] At the same time, it should be understood that for the convenience of description, the sizes of the various parts shown in the drawings are not drawn according to the actual proportional relationship.

[0064] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the present disclosure, its application, or uses.

[0065] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered as part of the specification.

[0066] It should be noted that like reference numerals and letters refer to similar items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0067] Please refer to Figure 1, which shows a block diagram of a chip test system provided by an exemplary embodiment of the present disclosure. The system includes an instruction initiator 101, a communication board 102 and a first resource board 103, wherein a test unit 104 is provided in the first resource board 103, the instruction initiator 101 is in communication connection with the communication board 102, and the communication board 102 is connected with the test unit 104 via at least two transmission lines.

[0068] In a possible implementation, the instruction initiator 101 runs a chip test program, which is used to control the test unit to execute the test instruction and obtain the instruction execution result, so as to detect whether there is an abnormality in the function or structure of the test unit. The instruction initiator 101 sends a test instruction to the test unit 104 in the first resource board 103 during the test. The first resource board 103 may include one or more test units 104, and the communication board 102 is used to receive the test instruction sent by the instruction initiator 101, and parse the test instruction, obtain relevant information such as instruction priority, instruction type, target test unit, etc., and then forward the test instruction to the corresponding test unit 104.

[0069] Optionally, the test unit 104 may be a chip under test, or a chip combination consisting of multiple chips under test, wherein the chips under test may include, for example, but are not limited to, field programmable gate array (FPGA) chips, graphics processing units (GPU), digital signal processors (DSP) chips, etc. The present disclosure embodiment does not limit the specific structure and chip type of the test unit 104.

[0070] Optionally, the first transmission line 105 and the second transmission line 106 between the communication board 102 and the test unit 104 may be transmission lines of the same model or transmission lines of different models. The transmission line model may include, but is not limited to, LVDS×1 transmission line, LVDS×8 transmission line, complementary metal oxide semiconductor (CMOS) transmission line, etc.

[0071] The communication board 102 is used to: parse the test instructions sent by the instruction initiator 101, identify the target test instructions from the test instructions, wherein the priority of the target test instructions is higher than the priority of other test instructions; send the target test instructions to the test unit 104 through the first transmission line 105 of at least two transmission lines; send other test instructions in the test instructions to the test unit 104 through the second transmission line 106 of at least two transmission lines.

[0072] In a possible implementation, the instruction initiator 101 may add an instruction identifier (eg, an operation code) to the test instruction, where the instruction identifier is used to indicate the type of the test instruction, and the communication board 102 may identify the target test instruction by parsing the instruction identifiers of each test instruction.

[0073] Schematically, the target test instruction includes a trigger (Trig) instruction, and each test unit 104 needs to execute the Trig instruction synchronously, so the Trig instruction can be executed only after all test units 104 receive the Trig instruction. If the system uses a transmission bus to mix the Trig instruction and other test instructions, when other test instructions occupy the bus and have not been transmitted, the Trig instruction needs to wait, resulting in uncontrollable delay of the Trig instruction on the bus, and a larger offset time needs to be set, and the time for the test unit 104 to instruct the Trig instruction is forced to be delayed. By adopting the chip testing system of the embodiment of the present disclosure, after the communication board 102 identifies the Trig instruction from the test instruction, it sends the Trig instruction to the test unit 104 through the first transmission line 105, and sends other test instructions to the test unit 104 through the second transmission line 106. Since the first transmission line 105 is a transmission line specifically used to transmit the Trig instruction, there is no situation where other test instructions are occupied, so that the transmission delay of the Trig instruction between the communication board 102 and the test unit 104 is controllable, and there is no need to set a large offset time, which can improve the efficiency of the test unit 104 in executing the Trig instruction.

[0074] Based on the embodiment of the present disclosure, at least two transmission lines are set between the communication board and the test unit, and the test instructions sent by the instruction initiator are parsed through the communication board. For target test instructions with higher priority than other test instructions, they are sent to the test unit through the first transmission line of at least two transmission lines, and for other test instructions, they are sent to the test unit through the second transmission line. In the chip testing system, a transmission channel is separately added for the target test instructions, and the target test instructions and other test instructions are transmitted through different channels. In the case where a large number of test instructions are sent by the instruction initiator, other test instructions will not occupy the transmission channel, so that the transmission delay of the target test instructions can be controlled. For the target test instructions that need to be executed synchronously by the test unit, there is no need to set a large offset time to ensure that the instructions arrive at the test unit synchronously, which can improve the chip testing efficiency.

[0075] In one possible implementation, please refer to Figure 2 , which shows a structural block diagram of a chip testing system provided by another exemplary embodiment of the present disclosure. Figure 2The chip testing system shown includes at least two test units 104, the communication board 102 includes a first communication unit 102a and a second communication unit 102b connected to each other, the instruction initiator 101 is in communication connection with the first communication unit 102a, and the first communication unit 102a and the second communication unit 102b are respectively connected to different test units 104 in the at least two test units 104. The first communication unit 102a and the second communication unit 102b can be a chip (such as an FPGA chip) with data receiving and sending functions, or a chip combination composed of multiple chips.

[0076] Among them, at least two test units 104 can be located in the same first resource board 103, or in different first resource boards 103. It is also possible that some of the test units 104 are located in the same first resource board 103, and other parts of the test units 104 are located in different first resource boards 103. The embodiment of the present disclosure does not limit the deployment method of at least two test units 104 in the first resource board 103.

[0077] The first communication unit 102a is used to parse the test instruction, identify the target test instruction from the test instruction, forward the target test instruction to the second communication unit 102b, and send the target test instruction to the test unit 104 corresponding to the first communication unit through the first transmission line 105a.

[0078] The second communication unit 102b is used to receive the target test instruction sent by the first communication unit 102a, and send the target test instruction to the test unit 104 corresponding to the second communication unit 102b through the first transmission line 105b.

[0079] In a possible implementation, a first communication unit 102a or multiple first communication units 102a may be provided in the communication board 102, and a second communication unit 102b or multiple second communication units 102b may also be provided. The first communication unit 102a is responsible for receiving the test instructions sent by the instruction initiator 101, parsing the test instructions and forwarding the target test instructions therein to the second communication unit 102b. The first communication unit 102a and the second communication unit 102b are responsible for sending the target test instructions to different test units 104, respectively. Optionally, the first communication unit 102a may also send some other test instructions to the second communication unit 102b, for example, the second communication unit 102b is responsible for forwarding other test instructions that the test unit 104 corresponding to the second communication unit 102b needs to execute.

[0080] The first communication unit 102a and its corresponding test unit 104 are connected by at least two transmission lines, namely, at least a first transmission line 105a and a second transmission line 106a; the second communication unit 102b and its corresponding test unit 104 are also connected by at least two transmission lines, namely, at least a first transmission line 105b and a second transmission line 106b. Among them, the first transmission lines 105a and 105b refer to transmission lines used to transmit target test instructions, and the first transmission line 105a between the first communication unit 102a and its corresponding test unit 104, and the first transmission line 105b between the second communication unit 102b and its corresponding test unit 104 are two independent transmission lines. The second transmission lines 106a and 106b refer to transmission lines used to transmit other test instructions, and the second transmission line 106a between the first communication unit 102a and its corresponding test unit 104, and the second transmission line 106b between the second communication unit 102b and its corresponding test unit 104 are two independent transmission lines.

[0081] Based on the embodiment of the present disclosure, when the system includes at least two test units, at least two communication units are set in the communication board, each communication unit is connected to the corresponding test unit through at least two transmission lines, and different communication units are responsible for forwarding target test instructions to different test units through the first transmission line, thereby further improving the transmission efficiency of the target test instructions.

[0082] Optionally, the transmission line between the first communication unit and the second communication unit, and the first transmission line between each communication unit and each test unit, can adopt an LVDS transmission line. Schematically, the first transmission line can adopt an LVDS×1 transmission line. In order to improve the data transmission efficiency within the board, the transmission line between the first communication unit and the second communication unit can adopt an LVDS×8 transmission line. Among them, the LVDS×1 transmission line represents a single-channel LVDS transmission line, and the LVDS×8 transmission line represents an LVDS transmission line containing 8 channels. The LVDS×8 transmission line has a larger data transmission bandwidth than the LVDS×1 transmission line, thereby improving the transmission efficiency between the internal communication units of the communication board and reducing the instruction transmission delay caused by instruction forwarding within the board.

[0083] Optionally, the instruction initiator 101 includes at least one of a host computer and a second resource board. When the instruction initiator 101 is a host computer, a host bus adapter (Adapter) is provided in the host computer, and the host bus adapter is connected to the communication board through a preset communication interface, for example, it can be connected through at least one interface such as an optical fiber interface, a Universal Serial Bus (USB) interface or a Universal Asynchronous Receiver / Transmitter (UART) interface. When the instruction initiator 101 is a second resource board, the second resource board is connected to the communication board through a preset communication link transmission line, for example, it can be connected through an LVDS transmission line, a CMOS transmission line, etc.

[0084] Please refer to Figure 3 , which shows a flow chart of a chip testing method provided by an exemplary embodiment of the present disclosure. Figure 1 The communication board 102 in the chip testing system shown. The method comprises the following steps:

[0085] Step 301, receiving and parsing a test instruction sent by an instruction initiator in the system.

[0086] In a possible implementation, the instruction initiator runs a chip test program, and during the test process, the communication board sends a test instruction to the test unit in the first resource board. The communication board receives the test instruction sent by the instruction initiator, parses the test instruction, and obtains relevant information such as instruction priority, instruction type, target test unit, etc.

[0087] The device type of the command initiator and the connection method between the command initiator and the communication board can be referred to above. Figure 1 and Figure 2 The corresponding embodiments are not described in detail in the embodiments of the present disclosure.

[0088] Step 302 : Based on the operation code of the test instruction, a target test instruction is identified from the test instructions, and the priority of the target test instruction is higher than the priorities of other test instructions.

[0089] In a possible implementation, the instruction initiator can add an operation code (op code) to the test instruction, and the operation code is used to indicate the type of the test instruction. The communication board can identify the target test instruction by parsing the operation code of each test instruction. For example, if the operation code of the target test instruction is 0xa, when the communication board parses the test instruction with the operation code 0xa, it will confirm the test instruction as the target test instruction.

[0090] Step 303: Send the target test instruction to the test unit in the system through the first transmission line, and send other test instructions in the test instructions to the test unit through the second transmission line.

[0091] At least two transmission lines are provided between the communication board and each test unit, including a first transmission line and a second transmission line. The first transmission line is used to transmit the target test instruction, and the second transmission line is used to transmit other test instructions. Schematically, the target test instruction is a Trig instruction. After the communication board identifies the Trig instruction from the test instruction, it sends the Trig instruction to the test unit through the first transmission line and sends other test instructions to the test unit through the second transmission line.

[0092] Based on the embodiments of the present disclosure, the test instructions sent by the instruction initiator are parsed through the communication board. For target test instructions with a higher priority than other test instructions, they are sent to the test unit through the first transmission line, and for other test instructions, they are sent to the test unit through the second transmission line. The target test instructions and other test instructions are transmitted through different channels. When a large number of test instructions are sent by the instruction initiator, other test instructions will not occupy the transmission channel, so that the transmission delay of the target test instructions can be controlled. For target test instructions that need to be executed synchronously by the test unit, there is no need to set a large offset time to ensure that the instructions arrive at the test unit synchronously, which can improve the chip testing efficiency.

[0093] In a possible implementation, the chip testing system includes at least two testing units, and the communication board includes a first communication unit and a second communication unit connected to each other, wherein the first communication unit and the second communication unit are respectively connected to different test units of the at least two testing units.

[0094] The above step 301 may include the following steps:

[0095] The first communication unit is controlled to receive and parse the test instruction.

[0096] The step of sending the target test instruction to the test unit in the system through the first transmission line may specifically include:

[0097] Step 303a: Control the first communication unit to forward the target test instruction to the second communication unit.

[0098] Step 303b: Control the first communication unit and the second communication unit to send target test instructions to their corresponding test units through the first transmission line respectively.

[0099] That is, when there are multiple test units in the system, at least two communication units can be set in the communication board, which are responsible for forwarding test instructions to different test units respectively. Among them, the first communication unit is also responsible for receiving and parsing the test instructions sent by the instruction initiator, and forwarding the target test instructions to the second test unit.

[0100] The specific configuration of the first communication unit and the second communication unit and the connection method between them and the test unit can be found in Figure 2 The embodiment shown.

[0101] In a possible implementation, since the communication board and the first resource board are two independent boards, their hardware conditions may be different. Therefore, before the communication board sends the target test instruction to the test unit using the first transmission line, it first performs parameter training on the first transmission line and adjusts the delay parameters in the first transmission line to ensure the stability of data transmission and reception between boards on the first transmission line. Figure 4 As shown, the method provided by the embodiment of the present disclosure may also include the following steps:

[0102] Step 401 : Perform parameter training in a first transmission direction on a first transmission line until a first delay parameter in the first transmission direction meets a preset training condition.

[0103] Step 402, performing parameter training in a second transmission direction on the first transmission line until a second delay parameter in the second transmission direction meets a preset training condition;

[0104] The first transmission direction is the transmission direction from the test unit to the communication board, and the second transmission direction is the transmission direction from the communication board to the test unit.

[0105] Optionally, the preset training conditions may include at least one of the following conditions, such as the highest integrity of received data, the minimum data transmission delay, etc.

[0106] Figure 4 A training process is shown in which parameter training is first performed in a first transmission direction and then parameter training is performed in a second transmission direction. In other possible implementations, parameter training may be performed in the second transmission direction first and then parameter training in the first transmission direction, or parameter training may be performed in both directions at the same time. The order of parameter training is not limited in the embodiments of the present disclosure.

[0107] Schematically, the first transmission line is an LVDS transmission line, Figure 5A schematic diagram of data transmission of an LVDS transmission line is shown. The delay parameter determines the clock frequency in the corresponding transmission direction. In the figure, the communication board sends data TX_DATA_P / N to the test unit under the clock TX_CLK_P / N in the first transmission direction (TX direction), and the test unit sends data RX_DATA_P / N to the communication board under the clock RX_CLK_P / N in the second transmission direction (RX direction). The communication board needs to be trained with parameters to adjust the delay parameters corresponding to the clock TX_CLK_P / N and the clock RX_CLK_P / N.

[0108] Specifically, firstly, the communication board is used as the main body to perform parameter training in the first transmission direction. The above step 401 may include the following steps:

[0109] Step 401a, in the process of the communication board collecting data on the training message sent by the test unit, the delay parameter of the first transmission direction is adjusted to obtain message sampling data corresponding to each group of first candidate delay parameters.

[0110] Step 401b: Based on the training message and the message sampling data corresponding to each group of first candidate delay parameters, determine the first delay parameter that meets the preset training condition from each group of first candidate delay parameters.

[0111] In one possible implementation, after parameter training of the first transmission direction begins, the test unit sends training messages to the communication board through the first transmission line at a first preset frequency, for example, sending training messages consisting of 100 fixed groups of data to the communication board every 1 second, and the communication board collects data on the training messages sent from the first transmission line to obtain message sampling data.

[0112] During data collection, the communication board adjusts the delay parameter of the first transmission direction according to a preset time interval, thereby obtaining the message sampling data corresponding to each group of first candidate delay parameters. By comparing the training message with the message sampling data corresponding to each group of first candidate delay parameters, the first candidate delay parameter with the highest integrity of the message sampling data (i.e., closest to the training message) is selected as the first delay parameter, and the delay parameter of the first transmission direction is adjusted to the first delay parameter for subsequent data transmission.

[0113] In schematic form, if the communication board detects that the message sampling data collected within a certain delay parameter range has the highest and identical integrity (for example, all complete training messages can be collected), then the middle value of the first candidate delay parameter within the delay parameter range can be taken as the first delay parameter, or the first candidate delay parameter with the smallest delay within the delay parameter range can be taken as the first delay parameter.

[0114] Secondly, still taking the communication board as the main driver, parameter training of the second transmission direction is performed. The above step 402 may include the following steps:

[0115] Step 402a, while the communication board continuously sends training messages to the test unit, adjust the delay parameter of the second transmission direction, and receive message sampling data corresponding to each group of second candidate delay parameters fed back by the test unit through the first transmission line.

[0116] Step 402b: Based on the training message and the message sampling data corresponding to each group of second candidate delay parameters, determine the second delay parameters that meet the preset training conditions from each group of second candidate parameters.

[0117] In one possible implementation, after parameter training of the second transmission direction begins, the communication board sends training messages to the test unit through the second transmission line at a second preset frequency. For example, a training message consisting of 100 fixed groups of data is sent to the test unit every 1 second. The training message sent from the first transmission line of the test unit is used for data collection to obtain message sampling data.

[0118] During the data collection process of the test unit, the communication board adjusts the delay parameter of the second transmission direction according to the preset time interval. The test unit can obtain the message sampling data corresponding to each group of second candidate delay parameters, and feed back the message sampling data corresponding to each group of second candidate delay parameters to the communication board through the first transmission line (since the first transmission direction of the first transmission line has been trained, the data transmission is relatively stable). The communication board compares the training message and the message sampling data corresponding to each group of second candidate delay parameters, selects the second candidate delay parameter with the highest message sampling data integrity (i.e., closest to the training message) as the second delay parameter, and adjusts the delay parameter of the second transmission direction to the second delay parameter for subsequent data transmission.

[0119] Based on the embodiments of the present disclosure, before the communication board uses the first transmission line to send a target test instruction to the test unit, it first performs parameter training on the first transmission line and adjusts the delay parameters in the first transmission line to ensure the stability of inter-board data transmission and reception on the first transmission line. In addition, the communication board is responsible for parameter adjustment and screening in both the first transmission direction and the second transmission direction, which can reduce the variables in the parameter training process of the two transmission directions and further improve the data transmission stability of the first transmission line.

[0120] Please refer to Figure 6 , which shows a block diagram of a chip testing device provided by an exemplary embodiment of the present disclosure. The chip testing device provided by this embodiment can be applied to Figure 1 and Figure 2 The communication board in the corresponding chip testing system embodiment includes:

[0121] Receiving module 601, used for receiving and parsing the test instruction sent by the instruction initiator in the system;

[0122] The identification module 602 is used to identify a target test instruction from the test instructions based on the operation code of the test instruction received by the receiving module 601, and the priority of the target test instruction is higher than the priority of other test instructions;

[0123] The sending module 603 is used to send the target test instruction identified by the identification module 602 to the test unit in the system through the first transmission line, and to send other test instructions in the test instructions to the test unit through the second transmission line.

[0124] In a possible implementation manner, at least one communication unit is disposed in the communication board, and the receiving module 601 , the identifying module 602 , and the sending module 603 may be composed of one or more communication units.

[0125] Optionally, in a possible implementation, the system includes at least two test units, the communication board includes a first communication unit and a second communication unit connected to each other, and the first communication unit and the second communication unit are respectively connected to different test units of the at least two test units;

[0126] The receiving module 601 is used for:

[0127] Control the first communication unit to receive and parse the test instruction received by the receiving module 601;

[0128] The sending module 603 is used to:

[0129] Control the first communication unit to forward the target test instruction identified by the identification module 602 to the second communication unit;

[0130] The first communication unit and the second communication unit are controlled to send the target test instruction to the corresponding test units respectively through the first transmission line.

[0131] Optionally, in a possible implementation manner, as Figure 7 As shown, the device may also include:

[0132] A first training module 701 is used to perform parameter training on the first transmission line in a first transmission direction until the first delay parameter of the first transmission direction meets a preset training condition; for example, the first training module may include the first communication unit and the second communication unit, and the first communication unit and the second communication unit are respectively responsible for parameter training of the first transmission line corresponding to themselves;

[0133] A second training module 702 is used to perform parameter training on the first transmission line in a second transmission direction until the second delay parameter in the second transmission direction meets a preset training condition; for example, the second training module may include the first communication unit and the second communication unit, and the first communication unit and the second communication unit are respectively responsible for parameter training of the first transmission line corresponding to themselves;

[0134] The first transmission direction is the transmission direction from the test unit to the communication board, and the second transmission direction is the transmission direction from the communication board to the test unit.

[0135] Optionally, in a possible implementation manner, the first training module 701 may also be used to:

[0136] During the process of data collection of the training message sent by the test unit by the communication board, the delay parameter of the first transmission direction is adjusted to obtain message sampling data corresponding to each group of first candidate delay parameters;

[0137] Based on the training message and the message sampling data corresponding to each group of first candidate delay parameters, determine the first delay parameter that meets the preset training condition from each group of first candidate delay parameters;

[0138] The second training module 702 may also be used to:

[0139] In the process of the communication board continuously sending training messages to the test unit, the delay parameter of the second transmission direction is adjusted, and the message sampling data corresponding to each group of second candidate delay parameters fed back by the test unit through the first transmission line is received;

[0140] Based on the training message and the message sampling data corresponding to each group of second candidate delay parameters, a second delay parameter satisfying a preset training condition is determined from each group of second candidate parameters.

[0141] In addition, an embodiment of the present disclosure further provides an electronic device, including:

[0142] Memory for storing computer programs;

[0143] The processor is used to execute the computer program stored in the memory, and when the computer program is executed, the chip testing method described in any of the above embodiments of the present disclosure is implemented.

[0144] Figure 8 This is a schematic diagram of the structure of an application embodiment of the electronic device disclosed in the present invention. Figure 8 The electronic device according to the embodiment of the present disclosure is described. The electronic device may be any one or both of the first device and the second device, or a stand-alone device independent of them, and the stand-alone device may communicate with the first device and the second device to receive the collected input signals from them.

[0145] like Figure 8 As shown, the electronic device includes one or more processors and memory.

[0146] The processor may be a central processing unit (CPU) or other forms of processing units having data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device to perform desired functions.

[0147] The memory may include one or more computer program products, and the computer program product may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may include, for example, a random access memory (RAM) and / or a cache memory (cache), etc. The non-volatile memory may include, for example, a read-only memory (ROM), a hard disk, a flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor may execute the program instructions to implement the chip testing method of each embodiment of the present disclosure described above and / or other desired functions.

[0148] In one example, the electronic device may further include: an input device and an output device, and these components are interconnected via a bus system and / or other forms of connection mechanisms (not shown).

[0149] In addition, the input device may also include, for example, a keyboard, a mouse, and the like.

[0150] The output device can output various information to the outside, including the determined distance information, direction information, etc. The output device can include, for example, a display, a speaker, a printer, a communication network and a remote output device connected thereto, and the like.

[0151] Of course, to simplify, Figure 8 Only some of the components related to the present disclosure in the electronic device are shown, and components such as a bus, an input / output interface, etc. are omitted. In addition, according to specific application situations, the electronic device may further include any other appropriate components.

[0152] In addition to the above-mentioned methods and devices, an embodiment of the present disclosure may also be a computer program product, which includes computer program instructions, which, when executed by a processor, enable the processor to execute the steps of the chip testing method according to various embodiments of the present disclosure described in the above part of this specification.

[0153] The computer program product may be written in any combination of one or more programming languages ​​to write program code for performing the operations of the disclosed embodiments, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0154] In addition, an embodiment of the present disclosure may also be a computer-readable storage medium having computer program instructions stored thereon, which, when executed by a processor, enables the processor to execute the steps of the chip testing method according to various embodiments of the present disclosure described in the above part of this specification.

[0155] The computer readable storage medium can adopt any combination of one or more readable media. The readable medium can be a readable signal medium or a readable storage medium. The readable storage medium can include, for example, but is not limited to, a system, device or device of electricity, magnetism, light, electromagnetic, infrared, or semiconductor, or any combination of the above. More specific examples (non-exhaustive list) of readable storage media include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0156] A person of ordinary skill in the art can understand that all or part of the steps of implementing the above method embodiment can be completed by hardware related to program instructions, and the aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps of the above method embodiment; and the aforementioned storage medium includes: ROM, RAM, magnetic disk or optical disk, etc., various media that can store program codes.

[0157] The basic principles of the present disclosure are described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, effects, etc. mentioned in the present disclosure are only examples and not limitations, and it cannot be considered that these advantages, strengths, effects, etc. are required by each embodiment of the present disclosure. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, and are not limitations. The above details do not limit the present disclosure to the necessity of adopting the above specific details to be implemented.

[0158] Each embodiment in this specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the system embodiment, since it basically corresponds to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0159] The block diagrams of the devices, apparatuses, equipment, and systems involved in this disclosure are only illustrative examples and are not intended to require or imply that they must be connected, arranged, and configured in the manner shown in the block diagrams. As will be appreciated by those skilled in the art, these devices, apparatuses, equipment, and systems can be connected, arranged, and configured in any manner. Words such as "including," "comprising," "having," and the like are open words, referring to "including but not limited to," and can be used interchangeably therewith. The words "or" and "and" used herein refer to the words "and / or," and can be used interchangeably therewith, unless the context clearly indicates otherwise. The word "such as" used herein refers to the phrase "such as but not limited to," and can be used interchangeably therewith.

[0160] The method and apparatus of the present disclosure may be implemented in many ways. For example, the method and apparatus of the present disclosure may be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware. The above order of steps for the method is for illustration only, and the steps of the method of the present disclosure are not limited to the order specifically described above, unless otherwise specifically stated. In addition, in some embodiments, the present disclosure may also be implemented as a program recorded in a recording medium, which includes machine-readable instructions for implementing the method according to the present disclosure. Therefore, the present disclosure also covers a recording medium storing a program for executing the method according to the present disclosure.

[0161] It should also be noted that in the apparatus, device and method of the present disclosure, each component or each step can be decomposed and / or recombined. Such decomposition and / or recombination should be regarded as equivalent solutions of the present disclosure.

[0162] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the aspects shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

[0163] The above description has been given for the purpose of illustration and description. In addition, this description is not intended to limit the embodiments of the present disclosure to the forms disclosed herein. Although multiple example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, changes, additions and sub-combinations thereof.

Claims

1. A chip testing system, characterized in that: The system comprises an instruction initiator, a communication board and a first resource board, wherein the first resource board is provided with a test unit, the instruction initiator is in communication connection with the communication board, and the communication board is connected with the test unit via at least two transmission lines; the communication board is used to: Parsing the test instructions sent by the instruction initiator, identifying a target test instruction from the test instructions, wherein the priority of the target test instruction is higher than the priority of other test instructions; Sending the target test instruction to the test unit through a first transmission line of the at least two transmission lines; The other test instructions among the test instructions are sent to the test unit through a second transmission line among the at least two transmission lines.

2. The system according to claim 1, characterized in that The system comprises at least two test units, the communication board comprises a first communication unit and a second communication unit connected to each other, the instruction initiator is in communication connection with the first communication unit, and the first communication unit and the second communication unit are respectively connected to different test units of the at least two test units; The first communication unit is used for parsing the test instruction, identifying the target test instruction from the test instruction, forwarding the target test instruction to the second communication unit, and sending the target test instruction to the test unit corresponding to the first communication unit through the first transmission line; The second communication unit is used to receive the target test instruction sent by the first communication unit, and send the target test instruction to the test unit corresponding to the second communication unit through the first transmission line.

3. The system according to claim 2, characterized in that The first communication unit and the second communication unit are connected via a low voltage differential signal (LVDS) transmission line, and the first transmission line is an LVDS transmission line.

4. The system according to any one of claims 1 to 3, characterized in that: The instruction initiator includes at least one of a host computer and a second resource board; The host computer is provided with a host bus adapter, and the host bus adapter is communicatively connected with the communication board through a preset communication interface; The second resource board is communicatively connected to the communication board via a preset communication link transmission line.

5. A chip testing method, characterized in that: The method for the communication card used in the chip testing system according to any one of claims 1 to 4 comprises: Receiving and parsing the test instruction sent by the instruction initiator in the system; Based on the operation code of the test instruction, identifying a target test instruction from the test instruction, wherein the priority of the target test instruction is higher than the priority of other test instructions; The target test instruction is sent to a test unit in the system through a first transmission line, and other test instructions among the test instructions are sent to the test unit through a second transmission line.

6. The method according to claim 5, characterized in that The system comprises at least two test units, the communication board comprises a first communication unit and a second communication unit connected to each other, the first communication unit and the second communication unit are respectively connected to different test units of the at least two test units; The receiving and parsing the test instruction sent by the instruction initiator in the system includes: Controlling the first communication unit to receive and parse the test instruction; The sending the target test instruction to the test unit in the system through the first transmission line includes: Controlling the first communication unit to forward the target test instruction to the second communication unit; The first communication unit and the second communication unit are controlled to send the target test instruction to the corresponding test units respectively through the first transmission line.

7. The method according to claim 5, characterized in that The method further comprises: Performing parameter training on the first transmission line in a first transmission direction until a first delay parameter in the first transmission direction meets a preset training condition; Performing parameter training on the first transmission line in a second transmission direction until a second delay parameter in the second transmission direction meets the preset training condition; The first transmission direction is the transmission direction from the test unit to the communication board, and the second transmission direction is the transmission direction from the communication board to the test unit.

8. The method according to claim 7, characterized in that The performing parameter training on the first transmission line in the first transmission direction until the first delay parameter in the first transmission direction meets a preset training condition includes: During the process of data collection by the communication board on the training message sent by the test unit, the delay parameter of the first transmission direction is adjusted to obtain message sampling data corresponding to each group of first candidate delay parameters; Based on the training message and the message sampling data corresponding to each group of first candidate delay parameters, determining a first delay parameter that meets the preset training condition from each group of first candidate delay parameters; The performing parameter training on the first transmission line in the second transmission direction until the second delay parameter in the second transmission direction meets the preset training condition includes: In the process of the communication board continuously sending training messages to the test unit, the delay parameter of the second transmission direction is adjusted, and the message sampling data corresponding to each group of second candidate delay parameters fed back by the test unit through the first transmission line is received; Based on the training message and the message sampling data corresponding to each group of second candidate delay parameters, a second delay parameter satisfying the preset training condition is determined from each group of second candidate parameters.

9. A chip testing device, characterized in that: A communication card used in a chip testing system according to any one of claims 1 to 4, the device comprising: A receiving module, used for receiving and parsing a test instruction sent by an instruction initiator in the system; an identification module, configured to identify a target test instruction from the test instructions based on an operation code of the test instruction, wherein the priority of the target test instruction is higher than the priority of other test instructions; The sending module is used to send the target test instruction to the test unit in the system through a first transmission line, and to send other test instructions in the test instructions to the test unit through a second transmission line.

10. An electronic device, characterized in that: include: Memory for storing computer programs; A processor is used to execute the computer program stored in the memory, and when the computer program is executed, the method described in any one of claims 5 to 8 is implemented.

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