System-on-chip verification method, device, electronic device and readable storage medium

Abstract

The present application provides a system-on-chip verification method, device, electronic device and computer-readable storage medium, which obtains multiple random excitation components and tags associated with each random excitation component, obtains a basic excitation component and a random seed sequence according to the recorded tags, and uses the basic excitation component and the random seed sequence to reproduce the verification failure signal. The present application associates tags with multiple random excitation components, uses tags to record the random seeds used by the random excitation components, obtains the basic excitation component and the random seed sequence according to the recorded tags, and obtains the specific random seeds in the random excitation component by reading the tags associated with the random excitation components, so that in the reproduction process, the same random excitation component as when the failure signal first appeared can be generated according to the tags, and the verification failure signal is reproduced using the basic excitation component and the random seed sequence, making it easier to reproduce the failure signal and improving the verification efficiency.

Description

Technical Field

[0001] The present application relates to the field of chip verification technology, and in particular to a system-on-chip verification method, device, electronic device, and computer-readable storage medium. Background Art

[0002] System on Chip (SOC) verification refers to the verification of communication, control and data transmission between various modules inside the chip to ensure that the chip can work normally.

[0003] When performing SOC verification, the related technology usually uses a random excitation method, that is, in one round of regression, all random excitations are run once to obtain verification results.

[0004] However, when errors occur in the verification results, it is difficult to reproduce the errors, resulting in low verification efficiency. Summary of the invention

[0005] The embodiments of the present application provide a system-on-chip verification method, device, electronic device, and computer-readable storage medium to solve the problems in the related art.

[0006] In a first aspect, an embodiment of the present application provides a system-on-chip verification method, the method comprising:

[0007] Acquire multiple random excitation components and labels associated with each of the random excitation components; the random excitation components are obtained by combining preset basic excitation components and random seeds in a random seed sequence; the labels are used to mark the basic excitation components and random seeds corresponding to each random excitation component, and different random excitation components are associated with different labels; the number of the random excitation components is the same as the number of random seeds in the random seed sequence.

[0008] During the process of verifying the design file of the system on chip by the verification platform, the random stimulus component is compiled and run to obtain a verification result, and when the verification result is a verification failure signal, a label corresponding to the running random stimulus component is recorded.

[0009] The basic excitation component and the random seed sequence are obtained according to the recorded label, and the verification failure signal is reproduced using the basic excitation component and the random seed sequence.

[0010] In a second aspect, an embodiment of the present application provides a system-on-chip verification device, the device comprising:

[0011] A random excitation module is used to obtain multiple random excitation components and a label associated with each of the random excitation components; the random excitation components are obtained by combining preset basic excitation components and random seeds in a random seed sequence; the labels are used to mark the basic excitation components and random seeds corresponding to each random excitation component, and different random excitation components are associated with different labels; the number of the random excitation components is the same as the number of random seeds in the random seed sequence.

[0012] The verification module is used to compile and run the random stimulus component during the verification of the design file of the system on chip by the verification platform to obtain the verification result, and when the verification result is a verification failure signal, record the label corresponding to the running random stimulus component.

[0013] The reproduction module is used to obtain the basic excitation component and the random seed sequence according to the recorded label, and reproduce the verification failure signal using the basic excitation component and the random seed sequence.

[0014] In a third aspect, an embodiment of the present application provides an electronic device, comprising a processor and a memory, wherein the memory stores programs or instructions that can be run on the processor, and when the programs or instructions are executed by the processor, the steps of one or more methods described in the embodiments of the present application are implemented.

[0015] In a fourth aspect, an embodiment of the present application provides a readable storage medium. When instructions in the readable storage medium are executed by a processor of an electronic device, the electronic device can execute one or more methods described in the embodiments of the present application.

[0016] In an embodiment of the present application, by associating tags with multiple random excitation components and using tags to record random seeds used by random excitation components, the random excitation components can be associated with basic excitation components and random seeds composed of the random excitation components, so as to provide a basis for the reproduction of random excitation components. In the process of verifying the design files of the system on chip by the verification platform, the random excitation components are compiled and run to obtain verification results. When the verification result is a verification failure signal, the tags corresponding to the running random excitation components are recorded, and the basic excitation components and random seed sequences are obtained according to the recorded tags. The random seed sequence includes many random seeds. By reading the tags associated with the random excitation components, the specific random seeds that constitute the random excitation components are obtained, so that in the reproduction process, the same random excitation components as when the failure signal first appeared can be generated according to the tags, and the verification failure signal is reproduced using the basic excitation components and random seed sequences, so that the failure signal can be reproduced more easily, thereby improving the verification efficiency.

[0017] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0019] Figure 1 It is a flowchart of the steps of a system-on-chip verification method provided by an embodiment of the present application;

[0020] Figure 2 It is a flowchart of the specific steps of a system-on-chip verification method provided by an embodiment of the present application;

[0021] Figure 3 It is a block diagram of a system-on-chip verification device provided in an embodiment of the present application;

[0022] Figure 4 is a block diagram of an electronic device provided in an embodiment of the present application;

[0023] Figure 5 It is a block diagram of another electronic device according to another embodiment of the present application. DETAILED DESCRIPTION

[0024] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0025] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally a class, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the association relationship of associated objects, indicating that three kinds of relationships can exist, for example, A and / or B can be represented: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the front and back associated objects are a kind of "or" relationship. In the embodiment of the present application, the term "multiple" refers to two or more, and other quantifiers are similar.

[0026] Figure 1 is a flowchart of a method for verifying a system on a chip provided by an embodiment of the present application. Figure 1 As shown, the method may include:

[0027] Step 101: Acquire multiple random excitation components and a label associated with each of the random excitation components.

[0028] Among them, the stimulus component is a file designed according to the integrated circuit chip to verify its function, so as to judge the correctness and stability of the integrated circuit chip design. By generating stimulus signals through the stimulus component, the correctness and stability of the design can be effectively verified, and potential design defects and problems can be discovered, thereby improving the quality and reliability of the design.

[0029] In some related technologies, verification is performed by directed testing. However, in the simulation process with limited time, all possible behaviors cannot be verified. Therefore, directed testing has defects. The main reason for this problem is that the directed testing of the chip is only for the known test space, not for the unknown test space. Even the test of the known test space alone takes a long time. A small design may require hundreds of different test vectors. When the scale and function of the design gradually increase and become more complex, we may need thousands of directed stimuli to verify the function of the design. As the logic becomes more and more complex, the verification space will also increase accordingly, which not only requires a lot of manpower, but also significantly increases the probability of code errors as the number of lines of code increases. Therefore, the use of random stimulus components for verification can significantly shorten the length of the verification code, and a large amount of stimulus data can be generated with only a few lines of code, thereby expanding the test space for verification. In addition, random stimulus can more comprehensively detect the function of the entire design, find hidden dangers under corner conditions, and improve the reliability of verification.

[0030] In an embodiment of the present application, a random excitation component is used to verify the function of an integrated circuit chip. During the verification process, it is necessary to generate an excitation to drive the design. The random excitation component is obtained by combining a preset basic excitation component and a random seed in a random seed sequence. A label is associated with the random excitation component. The label is used to mark the basic excitation component and the random seed corresponding to each random excitation component. Different random excitation components are associated with different labels. The number of random excitation components is the same as the number of random seeds in the random seed sequence. Through the label associated with the random stimulus, the basic stimulus component and random seed of the random stimulus component can be found. When the random stimulus component is used to verify the function of the design, the functional defects need to be tested. When the test result of the random stimulus component is inconsistent with the expected result, it proves that the function of the design is not perfect enough and needs to be further improved. At this time, the random stimulus component is an effective random stimulus component of the integrated circuit chip. Since the random stimulus component is composed of the basic stimulus component and the random seed, the random seed is a random number sequence in the random number list, and the random seed sequence is the random number list. Using different random seeds does not necessarily make the composed random stimulus component the same as the first verification when reproduced. Therefore, associating labels with the basic stimulus component and the random seed in the random stimulus component can make it easier to achieve the same result as the first verification in the reproduction result, thereby improving the verification efficiency.

[0031] For example, a random excitation component A_1## <seed1>, where the marked basic incentive component part is A_1, and the marked random seed part is <seed1>, the label associated with the basic incentive component A is A_1, and the random seed <seed>The associated label is 1. Through the random stimulus component and its associated label, the basic stimulus component and random seed can be obtained, providing a basis for reproducing the verification results.

[0032] Step 102, during the process of verifying the design file of the system on chip by the verification platform, compile and run the random stimulus component to obtain a verification result, and when the verification result is a verification failure signal, record a label corresponding to the running random stimulus component.

[0033] Among them, the system on chip is a system or product formed by combining multiple integrated circuits with specific functions on a chip, which includes a complete hardware system and the embedded software it carries. Its related contents include integrated circuit design, system integration, chip design, production, packaging, testing, etc.

[0034] Optionally, in the verification process of the integrated circuit design, a universal verification methodology (UVM) based on the SystemVerilog language is used for verification. UVM can support large-scale verification projects, optimize resource usage and improve verification quality and efficiency. The core of UVM is an object-oriented verification platform, which is built on the classes and interfaces in the SystemVerilog language. UVM creates a predictable and controllable test environment through component reuse, configuration and message mechanism. By building a verification platform (test bench), random stimulus components are generated, and the random stimulus components are sent to the integrated circuit design to be tested (DUT, Design Under Test) and the reference model at the same time. Then, the output of the DUT is detected and compared with the output of the reference model. If they are the same, a verification pass signal is output, and if they are different, a verification fail signal is output.

[0035] In an embodiment of the present application, a random excitation component is compiled and run. When the verification result obtained is a verification failure signal, the label corresponding to the random excitation component being run is recorded. In reproducing the verification failure signal, the random excitation component needs to be reproduced first. Therefore, the corresponding basic excitation component and random seed can be found according to the label recorded when the verification failure signal appears in the first verification. By combining the basic excitation component and the random seed, the random excitation component can be reproduced, thereby making it easier to reproduce the verification failure signal during re-verification, thereby improving verification efficiency.

[0036] For example, when a random excitation component A_2## <seed5>When a verification failure signal appears during verification, the label A_2 and random seed of the basic incentive component corresponding to the random incentive component are recorded. <seed>Tag 5, when reproducing, the random incentive component A_2## can be reproduced through the tag <seed5>This prevents the random stimulus component from using different random seeds for the first verification and the re-verification, which results in the re-verification result being different from the first run verification result.

[0037] Step 103: Obtain the basic excitation component and the random seed sequence according to the recorded tag, and use the basic excitation component and the random seed sequence to reproduce the verification failure signal.

[0038] In the embodiment of the present application, the basic incentive component and the random seed sequence are obtained by recording the tags, which is equivalent to recording the random incentive component used in the first verification. The basic incentive component and the random seed used by the random incentive component can be clearly found through the recorded tags. For example, when the random incentive component A_1## <seed1> 、B_3## <seed2>When a verification failure signal appears during verification, the random incentive component A_1## can be identified based on label A_1 <seed1>The basic incentive component used is the first component in the basic incentive component A group. According to the label B_3, it can be identified that this random incentive component is B_3## <seed2>The basic incentive component used is the third component in the basic incentive component group B. The random seed is one of the groups in the random seed sequence, and the data of each group is fixed data. Repeated calls <seed1>The output data is the same, so the random excitation component A_1## can be known from label 1 <seed1>The random seed used is <seed1>According to label 2, we can know the random incentive component B_3## <seed2>The random seed used is <seed2>Therefore, the random seed sequence used when the verification result shows a verification failure signal can be accurately obtained based on the recorded tags.

[0039] In an embodiment of the present application, by associating tags with multiple random excitation components and using tags to record random seeds used by random excitation components, the random excitation components can be associated with basic excitation components and random seeds composed of the random excitation components, so as to provide a basis for the reproduction of random excitation components. In the process of verifying the design files of the system on chip by the verification platform, the random excitation components are compiled and run to obtain verification results. When the verification result is a verification failure signal, the tags corresponding to the running random excitation components are recorded, and the basic excitation components and random seed sequences are obtained according to the recorded tags. The random seed sequence includes many random seeds. By reading the tags associated with the random excitation components, the specific random seeds that constitute the random excitation components are obtained, so that in the reproduction process, the same random excitation components as when the failure signal first appeared can be generated according to the tags, and the verification failure signals are reproduced using the basic excitation components and the random seed sequence, so that the reproduction of the failure signals is relatively easy and the verification efficiency is improved.

[0040] Reference Figure 2 , the system-on-chip verification method may include the following steps:

[0041] Step 201, by setting a random number, the basic incentive component is copied according to the random number.

[0042] In some related technologies, when UVM-based SOC verification is adopted, a random excitation component is used to accelerate the convergence of verification. In order to ensure that the random excitation component has a sufficient number of random numbers, multiple rounds of regression are used to achieve this, wherein each round of regression compiles and runs a random excitation component used for verification. For example, when 10 random excitation component verifications need to be completed, batch regression needs to be performed and 10 tasks need to be submitted to achieve this. The operation is relatively cumbersome, resulting in reduced verification efficiency.

[0043] In an embodiment of the present application, a random number is set to generate enough random excitation components to speed up the convergence of verification, and a random number of random excitation components are executed in one regression task. Therefore, in an embodiment of the present application, only one task needs to be submitted to complete the task that requires 10 submissions in the related technology of the above example, thereby simplifying the execution operation and improving the verification efficiency.

[0044] For example, by using a markup language (YAML, YAML Ain't Markup Language) data format to construct a stimulus component set, and setting an application programming interface (API, Application Programming Interface) to control the random number in the verification random list, taking the YAML array name of the stimulus component as noc_pmu_wr_rd_reg_test as an example, the elements in the YAML array include: key-value pairs of the stimulus component name and key-value pairs of the number of random seeds, where the key of the stimulus component name is v_test, the value of the stimulus component name is noc_pmu_wr_rd_reg_test, the key of the number of random seeds is seed, and the value of the number of random seeds is (1...10). In one round of regression, 10 random stimulus components will be compiled and run. The YAML array corresponding to the stimulus component in the stimulus component set is as follows:

[0045] noc_pmu_wr_rd_reg_test:

[0046] v_test: noc_pmu_wr_rd_reg_test

[0047] seed: (1…10)

[0048] Specifically, by setting a random number, the basic incentive component is copied according to the random number, so that when generating a random incentive component, the basic incentive components used are all copied from the same basic incentive component, so that a large number of random incentive components can be generated using the basic incentive component, thereby expanding the test space for verification.

[0049] Step 202: Add labels to the copied basic incentive component and the random number of random seeds according to a preset method.

[0050] In an embodiment of the present application, the copied basic incentive components are all the same basic incentive components, and labels are added to the basic incentive components in the order of copying. The way of adding labels to random seeds is determined according to the group number of the random seed in the random seed sequence.

[0051] For example, the basic incentive component A is copied 10 times according to the preset random number 10, and the basic incentive component group A including A_1, A_2, ..., A_10 is obtained. At the same time, the labels of the basic incentive components are also A_1, A_2, ..., A_10. At this time, the 10 basic incentive components in the basic incentive component group A are the same. Add labels to the random number of random seeds, and the added labels are the group numbers of the random seeds in the random seed sequence, that is, <seed1> 、 <seed2> 、......、 <seed10>The number of random seeds is the same as the basic incentive component.

[0052] In addition, by adding labels to the copied basic incentive component and random seed, the generated random incentive component can find out which specific basic incentive component and random seed the random incentive component is obtained from according to the associated label, so that the random incentive component can be traced according to the label, avoiding the problem that the random seed is not associated with the basic incentive component, resulting in the generated random incentive component having a verification failure signal, and the random seed used again when reproducing the signal is inconsistent with the random seed used for the first time, which makes it difficult to reproduce the verification failure signal.

[0053] Step 203: According to a preset method, a basic excitation component and a random seed with a corresponding label are searched and combined to obtain the random excitation component.

[0054] In an embodiment of the present application, a basic incentive component with a corresponding label and a random seed are merged to obtain a random incentive component, wherein the basic incentive component used is obtained by copying, that is, only one basic incentive component is required, and a random number of random incentive components can be generated through a random seed, thereby expanding the test space for verification and improving test efficiency.

[0055] For example, a basic incentive component A is used, the random number is set to 10, 10 random seeds are selected, and 10 random seeds are combined with 10 copies of the basic incentive component to obtain 10 random incentive components, thereby achieving the effect of converting one basic incentive component into 10 or more random incentive components.

[0056] Optionally, step 203 may specifically include:

[0057] Sub-step 2031, when the mapping relationship between the basic incentive component and the random seed is not specified, the random incentive component is obtained by combining the basic incentive component and the random seed with the same label.

[0058] In an embodiment of the present application, when the mapping relationship between the basic incentive component and the random seed is not specified, labels are added to the basic incentive component and the random seed according to the default method, thereby simplifying the steps of generating the random incentive component and avoiding invalid verification caused by forgetting to specify the mapping relationship.

[0059] Specifically, the basic incentive components are labeled in sequence according to the order of replication. When the mapping relationship between the basic incentive components and the random seeds is not specified, the basic incentive components and the random seeds whose replication order is the same as the number of groups in the random seed sequence where the random seeds are located are combined to obtain the random incentive components.

[0060] For example, when the base incentive component A and the random seed are not specified <seed>, the labels added to the basic incentive components are A_1, A_2, ..., A_10, where A_6 represents the basic incentive component obtained by copying the basic incentive component A for the sixth time. At this time, the ordinal number of the basic incentive component is 6, and the random seed with the same ordinal number 6 in the random seed sequence is <seed6>, combined in this way, we get the random excitation component A_6## <seed6>.

[0061] Optionally, step 203 may specifically include:

[0062] Sub-step 2032: selecting the random number of target random seeds from the random seed sequence according to the random seed label specified by the specified mapping relationship.

[0063] In an embodiment of the present application, a mapping relationship between a basic excitation component and a random seed can be specified and combined to obtain a random excitation seed. According to the specified mapping relationship, random seeds that meet the number of mapping relationship groups are selected from the random seed sequence.

[0064] For example, when executing a regression task, the bsim platform can use the -seed option to specify the seed the user wants. Taking the bsim -t soc::full.yml -seed 111000 instruction as an example, the random seed specified by this instruction is the 111000th group in the random seed sequence, which is equivalent to the specified mapping relationship of A_1 –seed111000.

[0065] Sub-step 2033, when the mapping relationship between the label of the target basic incentive component and the label of the target random seed is specified, according to each mapping relationship, a corresponding combination consisting of the target basic incentive and the target random seed is obtained.

[0066] In an embodiment of the present application, by specifying the mapping relationship between the target basic incentive component and the label of the target random seed, and obtaining the combination of the target basic incentive component and the target random seed according to the mapping relationship, the target basic incentive component can specify the target random seed according to the needs of the user, and when performing more complex designated tasks, the user is left with the function of independent control.

[0067] For example, when executing a more complex designated task, each target basic incentive component has an irregular mapping relationship with the target random seed. When the random number is set to seed: (1..3), three mapping relationships are required to indicate the target random seed corresponding to the target basic incentive component. By specifying the mapping relationship between the target basic incentive component and the target random seed: A_1 –seed 3, A_2 –seed 2, A_3 –seed 1, the target basic incentive component and target random seed referred to by the mapping relationship are obtained according to the mapping relationship.

[0068] Sub-step 2034, combining the target basic incentive component and the target random seed to obtain the random incentive component having the random number.

[0069] In an embodiment of the present application, the target basic incentive component is copied according to a set random number, and different target random seeds are specified for target basic incentive components with a random number, where the target random seed also has a random number, so after combining the target basic incentive component and the target random seed, a random incentive component with a random number will be obtained.

[0070] Optionally, step 203 may specifically include:

[0071] Sub-step 2035, when the mapping relationship between the labels of part of the target basic incentive components and the labels of the target random seeds is specified, the specified labels of the target basic incentives and the labels of the target random seeds are obtained, and the combination function is obtained according to the mapping relationship of the labels.

[0072] In an embodiment of the present application, when the mapping relationship between the labels of some target basic incentive components and the labels of the target random seeds is specified, the ordinal number of the replication represented by the label of the target basic incentive component is used as the input value of the combining function, and the number of groups in the random seed sequence represented by the label of the target random seed is used as the output value of the combining function to obtain the combining function.

[0073] For example, when the mapping relationship between the label of the specified target basic incentive component and the label of the target random seed is A_2-seed 3, A_3-seed 4, when the input value of the combination function is 2, the output value of the combination function is 3; when the input value of the combination function is 3, the output value of the combination function is 4, the combination function can be obtained as f(x)=x+1, that is, the ordinal number of the copy represented by the label of the target basic incentive component + 1, and the number of groups in the random seed sequence represented by the label of the target random seed can be obtained.

[0074] Optionally, the mapping relationship between the label of the target basic stimulus component and the label of the target random seed can be indicated by directly specifying a combination function.

[0075] Sub-step 2036, sequentially bringing the labels of the basic excitation components into the combining function to obtain a random seed with the label output by the combining function; the random seed is selected from the random seed sequence according to the label output by the combining function.

[0076] In the embodiment of the present application, the label of the basic excitation component is brought into the combination function to obtain the label of the random seed, and the random seed with a random number is selected according to the number of groups of the label of the random seed in the random seed sequence.

[0077] For example, if the combination function is f(x)=x+1 and the random number is seed: (1..10), then the labels of the basic incentive components are: A_1, A_2, ..., A_10, and the label of the random seed is: <seed2> 、 <seed3> 、......、 <seed11>.

[0078] Sub-step 2037, sequentially combining the label-based excitation components having the input of the combining function and the random seeds of the labels output by the combining function to obtain the random excitation components having the random number.

[0079] In the embodiment of the present application, since the basic incentive component is obtained by copying a random number, the random seeds need to be different in order to combine different random incentive components. Therefore, the combination function needs to be a monotonic function within the range of natural numbers to ensure that the generated random seed labels are unique.

[0080] Step 204, during the process of verifying the design file of the system on chip by the verification platform, compile and run the random stimulus component to obtain a verification result, and when the verification result is a verification failure signal, record a label corresponding to the running random stimulus component.

[0081] This step may be specifically referred to as the above step 102, which will not be described in detail here.

[0082] Optionally, step 204 may specifically include:

[0083] Sub-step 2041 , compile and run the random stimulus component through the unit under test to obtain a measurement result.

[0084] In the embodiment of the present application, the unit under test is the unit carried by the design file of the system on chip, and the unit under test can be a module-level unit, a chip-level unit or a system-level unit. The actual measurement results can be used to know the results obtained by the random stimulus component after the unit under test is compiled and run.

[0085] Sub-step 2042, compile and run the random excitation component through a reference unit to obtain a reference result.

[0086] In an embodiment of the present application, the reference compilation unit may provide a reference result based on a random stimulus component, wherein the reference result is an expected result that is expected to be achieved by the design file of the system on chip.

[0087] Sub-step 2043, compares the measured result with the reference result to obtain a verification result. When the verification result indicates that the measured result and the reference result are the same, a verification pass signal is output; when the verification result indicates that the measured result and the reference result are different, a verification fail signal is output.

[0088] In an embodiment of the present application, when the measured result and the reference result are the same, it indicates that the effect achieved by the unit under test is consistent with the expected effect of the reference unit, and the unit under test is verified to meet the verification of the random excitation component. When the measured result and the reference result are different, it indicates that the effect achieved by the unit under test is different from the expected effect of the reference unit, and a verification failure signal is output. There are still loopholes in the design of the unit under test. At this time, the random excitation component is an effective stimulus that can verify the design loopholes of the unit under test. In order to further study the cause of the verification failure, the reproduction of this verification failure signal is essential.

[0089] Step 205: Obtain the basic excitation component and the random seed sequence according to the recorded tag, and use the basic excitation component and the random seed sequence to reproduce the verification failure signal.

[0090] This step may be specifically referred to as the above step 103, which will not be described in detail here.

[0091] Optionally, step 205 may specifically include:

[0092] Sub-step 2051, according to the tag, searching for a basic incentive component and a random seed with the tag.

[0093] In the embodiment of the present application, the specific basic incentive component and random seed constituting the random incentive component can be found through the tag associated with the random incentive component. For example, when the random incentive component is associated with the A_2 tag, it indicates that the basic incentive component constituting the random incentive component is obtained by copying the basic incentive component A for the first time; when the random incentive component is associated with the B_5 tag, it indicates that the basic incentive component constituting the random incentive component is obtained by copying the basic incentive component B for the fifth time; when the random incentive component is associated with the 2 tag, it indicates that the random seed constituting the random incentive component at this time is <seed2>, from which the basic excitation components and random seeds that make up the random excitation components can be found.

[0094] Sub-step 2052, combining the basic incentive component with the corresponding label and the random seed to obtain a recurring incentive component.

[0095] For example, the random excitation component A_2## <seed5> 、B_1## <seed2>If a verification failure signal appears during the verification process, the random excitation component needs to be obtained again and verified. <seed5>From the A_2 label, we can see that the basic incentive component used to make up this random incentive component is the second component in the basic incentive component A class. Through this random incentive component B_1## <seed2>From the B_1 label, we can see that the basic incentive component used to make up this random incentive component is the first component in the basic incentive component class B. Label 5 indicates that the random incentive component A_2## <seed5>The random seed used is <seed5>, label 2 indicates the random excitation component B_1## <seed2>The random seed used is <seed2>, the basic incentive component A_2 and the random seed <seed5>Combined with random excitation component A_2## <seed5>The same recurrence incentive component A_2## <seed5>, and the basic excitation component B_1 and the random seed <seed2>Combined with random excitation component B_1## <seed2>The same recurrence incentive component B_1## <seed2>.

[0096] Sub-step 2053, during the process of the verification platform verifying the design file of the system on chip, compile and run the reproduction stimulus component to obtain a verification failure signal after reproduction.

[0097] Optional, when you need to reproduce a specific random stimulus component, such as A_2## <seed2>, then run the corresponding A_2## <seed2>That’s it. If you need to reproduce in batches, just re-execute the last specified instruction.

[0098] Optionally, step 205 may specifically include:

[0099] Sub-step 2054, according to each tag associated with the mapping relationship, search for the target basic incentive component and the target random seed with the tag in turn, and combine them to obtain the recurrence incentive component with the random number.

[0100] In an embodiment of the present application, when the basic incentive components and random seeds that constitute the random incentive components are specified, according to the specified mapping relationship, the target basic incentive components and target random seeds corresponding to the labels associated with the mapping relationship are searched and combined in turn to obtain a preset random number of reproduction incentive components, so as to further perform reproduction verification and obtain a reproduction verification failure result, thereby avoiding the situation where the random seed used in the reproduction process is different from that used in the first verification, resulting in the inability to reproduce, and improving the verification efficiency.

[0101] Optionally, step 205 may specifically include:

[0102] Sub-step 2055, sequentially bringing the labels of the basic excitation components into the combining function, and outputting the label of the random seed.

[0103] In an embodiment of the present application, the correspondence between the label of the basic incentive component and the label of the random seed is determined by a combination function, wherein the combination function is a function determined by the label of the basic incentive component and the label of the random seed during the first verification, and the combination function is a monotonic function within the domain of natural numbers to ensure that the random seeds combined with each basic incentive component are different. According to the combination function, when reproducing the result of the first verification, the reproduction incentive component that is the same as the random incentive component used in the first verification can be obtained according to the combination function, thereby improving the ease of reproduction.

[0104] Sub-step 2056, sequentially combining the basic incentive components with the labels input by the combining function and the random seeds with the labels output by the combining function to obtain the recurring incentive components with the random number.

[0105] Specifically, if you need to reproduce the verification result of the random incentive component with the basic incentive component A_2, you only need to bring the label A_2 into the combination function, use the obtained label to find the corresponding random seed and combine it to get the reproduction incentive component. When batch reproduction is required, bring in the basic incentive component labels in turn, and generate a preset number of random reproduction incentive components according to the above process.

[0106] In an embodiment of the present application, by setting a random number, the basic incentive component is copied according to a preset random number, and the copied basic incentive component and a random number of random seeds are labeled according to a preset method. According to the preset method, the basic incentive component and the random seed with the corresponding label are found and combined to obtain a random incentive component. A sufficient number of random incentive components can be run in a regression task, thereby reducing the number of task submissions. In the process of the verification platform verifying the design file of the system on chip, the random incentive component is compiled and run to obtain a verification result, and when the verification result is a verification failure signal, the label corresponding to the running random incentive component is recorded, and the basic incentive component and the random seed sequence are obtained according to the recorded label. The random seed sequence includes many random seeds. By reading the label associated with the random incentive component, the specific random seed constituting the random incentive component is obtained, so that in the reproduction process, the same random incentive component as when the failure signal first appears can be generated according to the label, and the verification failure signal is reproduced using the basic incentive component and the random seed sequence, so that the reproduction of the failure signal is relatively easy, thereby improving the verification efficiency.

[0107] Figure 3 is a system-on-chip verification device provided by an embodiment of the present application, such as Figure 5 As shown, the device may include:

[0108] The random excitation module 301 is used to obtain multiple random excitation components and labels associated with each of the random excitation components; the random excitation components are obtained by combining preset basic excitation components and random seeds in a random seed sequence; the labels are used to mark the basic excitation components and random seeds corresponding to each random excitation component, and different random excitation components are associated with different labels; the number of the random excitation components is the same as the number of random seeds in the random seed sequence.

[0109] The verification module 302 is used to compile and run the random stimulus component during the verification of the design file of the system on chip by the verification platform to obtain the verification result, and when the verification result is a verification failure signal, record the label corresponding to the running random stimulus component.

[0110] The reproduction module 303 is used to obtain the basic excitation component and the random seed sequence according to the recorded label, and reproduce the verification failure signal using the basic excitation component and the random seed sequence.

[0111] Optionally, the random excitation module 301 may specifically include:

[0112] The random number submodule is used to copy the basic stimulus component according to the random number by setting the random number; the random number is used to specify the number of stimulus verifications for the design file of the system on chip.

[0113] The label adding submodule is used to add labels to the copied basic incentive component and the random number of random seeds according to a preset method.

[0114] The combination submodule is used to search for and combine the basic excitation component and the random seed with the corresponding label according to a preset method to obtain the random excitation component.

[0115] Optionally, the reproducing module 303 may specifically include:

[0116] The search submodule is used to search for a basic stimulus component and a random seed with the label according to the label.

[0117] The first reproduction incentive submodule is used to combine the basic incentive component with the corresponding label and the random seed to obtain the reproduction incentive component.

[0118] The reproduction verification submodule is used to compile and run the reproduction stimulus component during the process of verifying the design file of the system on chip on the verification platform to obtain a verification failure signal after reproduction.

[0119] Optionally, the verification module 302 may specifically include:

[0120] The actual measurement submodule is used to compile and run the random excitation component through the unit to be tested to obtain the actual measurement result.

[0121] The reference submodule is used to compile and run the random excitation component through a reference unit to obtain a reference result; the reference result is an expected result achieved by the design file.

[0122] The signal submodule is used to compare the measured result with the reference result to obtain a verification result. When the verification result indicates that the measured result and the reference result are the same, a verification pass signal is output; when the verification result indicates that the measured result and the reference result are different, a verification failure signal is output.

[0123] Optionally, the first combination submodule may specifically include:

[0124] The unspecified unit is used to obtain the random stimulus component by combining the basic stimulus component and the random seed with the same label when the mapping relationship between the basic stimulus component and the random seed is not specified.

[0125] Optionally, the first combination submodule may specifically include:

[0126] A specifying unit, configured to select the random number of target random seeds from the random seed sequence according to the random seed label specified by the specified mapping relationship;

[0127] A mapping unit, configured to obtain, when a mapping relationship between a label of a target basic stimulus component and a label of a target random seed is specified, a corresponding combination of the target basic stimulus and the target random seed according to each mapping relationship;

[0128] A first combining unit, configured to combine the target basic excitation and the target random seed to obtain the random excitation component having the random number;

[0129] Optionally, the reproducing module 303 may specifically include:

[0130] The second recurrence incentive submodule is used to search for the target basic incentive component and the target random seed with the label in turn according to the label associated with each mapping relationship, and combine them to obtain the recurrence incentive component with the random number.

[0131] Optionally, the first combination submodule may specifically include:

[0132] A partial specifying unit, configured to obtain the specified label of the target basic stimulus and the label of the target random seed when a mapping relationship between labels of a part of the target basic stimulus components and labels of the target random seed is specified, and obtain a combining function according to the mapping relationship of the labels;

[0133] A combining function unit, used for sequentially bringing the labels of the basic excitation components into the combining function to obtain a random seed with the label output by the combining function; the random seed is selected from the random seed sequence according to the label output by the combining function;

[0134] A second combining unit is used to sequentially combine the label-based excitation component having the combination function input and the random seed of the label output by the combination function to obtain the random excitation component having the random number;

[0135] Optionally, the reproducing module 303 may specifically include:

[0136] A combination function submodule sequentially brings the labels of the basic excitation components into the combination function and outputs the label of the random seed;

[0137] The third recurrence incentive submodule is used to sequentially combine the basic incentive components with the labels input by the combining function and the random seeds of the labels output by the combining function to obtain the recurrence incentive components with the random number.

[0138] In an embodiment of the present application, by associating tags with multiple random excitation components and using tags to record random seeds used by random excitation components, the random excitation components can be associated with basic excitation components and random seeds composed of the random excitation components, so as to provide a basis for the reproduction of random excitation components. In the process of verifying the design files of the system on chip by the verification platform, the random excitation components are compiled and run to obtain verification results. When the verification result is a verification failure signal, the tags corresponding to the running random excitation components are recorded, and the basic excitation components and random seed sequences are obtained according to the recorded tags. The random seed sequence includes many random seeds. By reading the tags associated with the random excitation components, the specific random seeds that constitute the random excitation components are obtained, so that in the reproduction process, the same random excitation components as when the failure signal first appeared can be generated according to the tags, and the verification failure signal is reproduced using the basic excitation components and random seed sequences, so that the failure signal can be reproduced more easily, thereby improving the verification efficiency.

[0139] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0140] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0141] Regarding the device in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0142] An embodiment of the present application provides a data row protection device for a dynamic random access memory, comprising a memory and one or more programs, wherein the one or more programs are stored in the memory and are configured to be executed by one or more processors to include methods for performing one or more of the methods described in the above-mentioned embodiments.

[0143] Figure 4 4 is a block diagram of an electronic device 400 provided in an embodiment of the present application. For example, the electronic device 400 may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

[0144] Reference Figure 4 , the electronic device 400 may include one or more of the following components: a processing component 402 , a memory 404 , a power component 406 , a multimedia component 408 , an audio component 410 , an input / output (I / O) interface 412 , a sensor component 414 , and a communication component 416 .

[0145] The processing component 402 generally controls the overall operation of the electronic device 400, such as operations associated with display, phone calls, data communications, camera operations, and recording operations. The processing component 402 may include one or more processors 420 to execute instructions to complete all or part of the steps of the above-mentioned method. In addition, the processing component 402 may include one or more modules to facilitate the interaction between the processing component 402 and other components. For example, the processing component 402 may include a multimedia module to facilitate the interaction between the multimedia component 408 and the processing component 402.

[0146] The memory 404 is used to store various types of data to support the operation of the electronic device 400. Examples of such data include instructions for any application or method operating on the electronic device 400, contact data, phone book data, messages, pictures, multimedia, etc. The memory 404 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0147] The power supply component 406 provides power to the various components of the electronic device 400. The power supply component 406 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the electronic device 400.

[0148] The multimedia component 408 includes a screen that provides an output interface between the electronic device 400 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the boundaries of the touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 408 includes a front camera and / or a rear camera. When the electronic device 400 is in an operating mode, such as a shooting mode or a multimedia mode, the front camera and / or the rear camera may receive external multimedia data. Each front camera and rear camera may be a fixed optical lens system or have a focal length and optical zoom capability.

[0149] The audio component 410 is used to output and / or input audio signals. For example, the audio component 410 includes a microphone (MIC), and when the electronic device 400 is in an operation mode, such as a call mode, a recording mode, and a voice recognition mode, the microphone is used to receive an external audio signal. The received audio signal can be further stored in the memory 404 or sent via the communication component 416. In some embodiments, the audio component 410 also includes a speaker for outputting audio signals.

[0150] The input / output interface 412 provides an interface between the processing component 402 and the peripheral interface modules, which may be keyboards, click wheels, buttons, etc. These buttons may include but are not limited to: a home button, a volume button, a start button, and a lock button.

[0151] The sensor assembly 414 includes one or more sensors for providing various aspects of status assessment for the electronic device 400. For example, the sensor assembly 414 can detect the open / closed state of the electronic device 400, the relative positioning of the components, such as the display and keypad of the electronic device 400, and the sensor assembly 414 can also detect the position change of the electronic device 400 or a component of the electronic device 400, the presence or absence of contact between the user and the electronic device 400, the orientation or acceleration / deceleration of the electronic device 400, and the temperature change of the electronic device 400. The sensor assembly 414 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. The sensor assembly 414 may also include an optical sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 414 may also include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0152] The communication component 416 is used to facilitate wired or wireless communication between the electronic device 400 and other devices. The electronic device 400 can access a wireless network based on a communication standard, such as WiFi, a carrier network (such as 2G, 3G, 4G or 5G), or a combination thereof. In an exemplary embodiment, the communication component 416 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 416 also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technologies.

[0153] In an exemplary embodiment, the electronic device 400 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to implement the methods provided in the embodiments of the present application.

[0154] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 404 including instructions, and the instructions can be executed by a processor 420 of an electronic device 400 to perform the above method. For example, the non-transitory storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, etc.

[0155] Figure 5 is a block diagram of another electronic device 500 provided in an embodiment of the present application. For example, the electronic device 500 may be provided as a server. Figure 5 , the electronic device 500 includes a processing component 522, which further includes one or more processors, and a memory resource represented by a memory 532, for storing instructions that can be executed by the processing component 522, such as an application. The application stored in the memory 532 may include one or more modules, each corresponding to a set of instructions. In addition, the processing component 522 is configured to execute instructions to perform the method provided in the embodiment of the present application.

[0156] The electronic device 500 may further include a power supply component 526 configured to perform power management of the electronic device 500, a wired or wireless network interface 550 configured to connect the electronic device 500 to a network, and an input / output interface 558. The electronic device 500 may operate based on an operating system stored in the memory 532, such as Windows Server TM, Mac OS X TM, Unix TM, Linux TM, FreeBSD TM or the like.

[0157] An embodiment of the present application further provides a computer program product, including a computer program, which implements the method described in the above embodiment when executed by a processor.

[0158] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the application disclosed herein. The present application is intended to cover any variations, uses or adaptations of the present application, which follow the general principles of the present application and include common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0159] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims. < / seed5> < / seed3> < / seed2> < / seed> < / seed2> < / seed1> < / seed1> < / seed> < / seed>

Claims

1. A system-on-chip verification method, characterized in that: The method comprises: Specify a mapping relationship between labels of some target basic incentive components and labels of target random seeds, obtain the specified labels of the target basic incentives and the labels of the target random seeds, and obtain a combination function according to the mapping relationship of the labels; The labels of the basic excitation components are sequentially brought into the combination function to obtain a random seed with the label output by the combination function; the random seed is selected from the random seed sequence according to the label output by the combination function; Combining the label-based excitation components having the combination function input and the random seeds of the labels output by the combination function in sequence to obtain a plurality of random excitation components; Acquire multiple random excitation components and labels associated with each of the random excitation components; the random excitation components are obtained by respectively combining a preset basic excitation component and a random seed in a random seed sequence; the labels associated with the random excitation components are obtained by combining the labels of the basic excitation components and the labels of the random seeds, the labels are used to mark the basic excitation components and random seeds corresponding to each random excitation component, and different random excitation components are associated with different labels; the number of the random excitation components is the same as the number of random seeds in the random seed sequence; In the process of verifying the design file of the system on chip by the verification platform, compiling and running the random stimulus component to obtain a verification result, and when the verification result is a verification failure signal, recording a label corresponding to the running random stimulus component; The basic excitation component and the random seed sequence are obtained according to the recorded label, and the verification failure signal is reproduced using the basic excitation component and the random seed sequence.

2. The method according to claim 1, characterized in that The step of obtaining a plurality of random excitation components and a label associated with each of the random excitation components includes: By setting a random number, the basic stimulus component is copied according to the random number; the random number is used to specify the number of stimulus verifications for the design file of the system on chip; Adding labels to the copied basic incentive component and the random number of random seeds according to a preset method; According to a preset method, a basic excitation component and a random seed with a corresponding label are searched and combined to obtain the random excitation component.

3. The method according to claim 1, characterized in that The step of obtaining the basic excitation component and the random seed sequence according to the recorded label, and reproducing the verification failure signal by using the basic excitation component and the random seed sequence, includes: According to the label, searching for a basic incentive component and a random seed with the label; Combine the basic incentive component with the corresponding label and the random seed to obtain the recurrence incentive component; During the process of verifying the design file of the system on chip by the verification platform, the reproduction stimulus component is compiled and run to obtain a verification failure signal after reproduction.

4. The method according to claim 1, characterized in that In the process of verifying the design file of the system on chip by the verification platform, compiling and running the random stimulus component to obtain the verification result includes: Compile and run the random excitation component through the unit under test to obtain a measured result; Compiling and running the random excitation component through a reference unit to obtain a reference result; the reference result is an expected result achieved by the design file; The measured result is compared with the reference result to obtain a verification result. When the verification result indicates that the measured result is the same as the reference result, a verification pass signal is output; when the verification result indicates that the measured result is different from the reference result, a verification fail signal is output.

5. The method according to claim 2, characterized in that: The method of combining the basic incentive component with the specified label and the random seed according to the preset method to obtain the random incentive component includes: When the mapping relationship between the basic incentive component and the random seed is not specified, the random incentive component is obtained by combining the basic incentive component and the random seed having the same label.

6. The method according to claim 2, characterized in that The method of combining the basic incentive component with the specified label and the random seed according to the preset method to obtain the random incentive component includes: According to the random seed label specified by the specified mapping relationship, selecting the random number of target random seeds from the random seed sequence; When a mapping relationship between a label of a target basic incentive component and a label of a target random seed is specified, a corresponding combination consisting of the target basic incentive and the target random seed is obtained according to each mapping relationship; Combining the target basic incentive and the target random seed to obtain the random incentive component having the random number; The step of obtaining the basic excitation component and the random seed sequence according to the recorded label, and reproducing the verification failure signal by using the basic excitation component and the random seed sequence, includes: According to the label associated with each of the mapping relationships, the target basic incentive components and target random seeds with the labels are searched in turn, and combined to obtain the recurrence incentive components with the random number.

7. The method according to claim 2, characterized in that The step of obtaining the basic excitation component and the random seed sequence according to the recorded label, and reproducing the verification failure signal by using the basic excitation component and the random seed sequence, includes: Submit the labels of the basic excitation components into the combination function in sequence, and output the label of the random seed; The basic incentive components with the labels input by the combining function and the random seeds of the labels output by the combining function are sequentially combined to obtain the recurring incentive components with the random number.

8. A system-on-chip verification device, characterized in that: The device comprises: A combining function module is used to specify a mapping relationship between labels of some target basic incentive components and labels of target random seeds, obtain the specified labels of the target basic incentive and the labels of the target random seeds, and obtain a combining function according to the mapping relationship of the labels; A label module, used to sequentially bring the labels of the basic excitation components into the combination function to obtain a random seed with the label output by the combination function; the random seed is selected from the random seed sequence according to the label output by the combination function; A combination module, used for sequentially combining the label-based excitation component having the combination function input and the random seed of the label output by the combination function to obtain a plurality of random excitation components; A random excitation module, used to obtain a plurality of the random excitation components and a label associated with each of the random excitation components; the random excitation components are obtained by respectively combining a preset basic excitation component and a random seed in a random seed sequence; the label associated with the random excitation component is obtained by combining the label of the basic excitation component and the label of the random seed, the label is used to mark the basic excitation component and the random seed corresponding to each random excitation component, and different random excitation components are associated with different labels; the number of the random excitation components is the same as the number of random seeds in the random seed sequence; A verification module, used to compile and run the random stimulus component during the verification of the design file of the system on chip by the verification platform, obtain a verification result, and record a label corresponding to the running random stimulus component when the verification result is a verification failure signal; The reproduction module is used to obtain the basic excitation component and the random seed sequence according to the recorded label, and reproduce the verification failure signal using the basic excitation component and the random seed sequence.

9. An electronic device, characterized in that: The method comprises a processor and a memory, wherein the memory stores a program or instruction that can be run on the processor, and when the program or instruction is executed by the processor, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A readable storage medium, characterized in that: When the instructions in the readable storage medium are executed by a processor of an electronic device, the electronic device is enabled to perform the method as claimed in any one of method claims 1 to 7.

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