Operation method of memory and memory
By receiving and sampled DBI, DM, DQ, and DQS signals in DDR SDRAM memory, control signals are generated to implement the DBI/DM function, solving the problem of large operating particles, and optimized power consumption and signal integrity.
Patent Information
- Application Number
- CN202411374767.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-29
- Publication Date
- 2025-01-28
AI Technical Summary
When the DBI/DM function is turned on, the operating granularity of the existing DDR SDRAM memory is relatively large, which affects the performance and power consumption optimization of the memory.
By receiving DBI, DM, DQ, and DQS signals, the DQS signal is used to sample, and the first sampling signal and the second sampling signal are exported alternately. , To realize the DBI/DM function while opening.
The DBI/DM function is implemented while opening, optimizing power consumption and signal integrity, and narrowing the operation particle size.
Smart Images
Figure CN119377141A_ABST
Abstract
Description
Technical Field
[0001] The present application generally relates to the field of electronic devices, and more particularly to a memory operating method and a memory. Background Art
[0002] Memory is the foundation of information technology. Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) is an SDRAM with double data transfer rate. It transmits data once during the rising and falling phases of the clock, that is, the data transmission speed is twice the system clock frequency. Due to the increased speed, its transmission performance is better than traditional SDRAM.
[0003] In addition, there is a dedicated pin on the DDR SDRAM particle to support the data mask (DM) function and the data bus inversion (DBI) function, usually named DM_n or DBI_n. During the write operation, the input signal DBI, the input data DQ and the selection signal DQS are synchronized, and the rising and falling edges of DQS correspond to valid data. However, with the diversification of memory types, DM / DBI cannot be turned on at the same time, which will affect the operation granularity of the memory. Therefore, how to reduce the operation granularity of DBI / DM has always been a problem. Summary of the invention
[0004] The purpose of the present application is to provide a memory operation method and a memory to solve the problem of DBI / DM operation granularity.
[0005] In a first aspect, the present application provides a memory operation method, the operation method comprising:
[0006] receiving a data bus inversion (DBI) signal, a data mask (DM) signal, an input data (DQ) signal, and a data strobe signal (DQS);
[0007] Sampling is performed according to the DQS signal, and a first sampling signal and a second sampling signal obtained by alternately sampling in one data sampling unit are output in parallel; and
[0008] According to a DBI / DM setting mode, at least one of a DBI control signal associated with the DBI signal and a DM control signal associated with the DM signal is selectively generated through at least one of the first sampling signal and the second sampling signal.
[0009] Optionally, the method also includes: sampling the input data signal according to the DQS signal, and outputting in parallel a first data signal and a second data signal obtained by alternately sampling in a data sampling unit, and making the first data signal and the second data signal each output write data according to at least one of the DBI control signal and the DM control signal.
[0010] Optionally, the steps of sampling according to the DQS signal and sampling the input data signal include sampling according to the rising edge and falling edge groups of the DQS signal to obtain the first sampling signal and the second sampling signal, and the data sampling unit is one byte.
[0011] Optionally, the step of setting the mode according to DBI / DM includes setting it through a mode register setting (MRS) and outputting a DBI enable signal or a DM enable signal to selectively generate at least one of the DBI control signal and the DM control signal through at least one of the first sampling signal and the second sampling signal.
[0012] Optionally, when the DBI / DM setting mode is set to DBI on and DM off, the first sampling signal and the second sampling signal are combined with the DBI signal to become the first DBI control signal and the second DBI control signal belonging to the DBI control signal, respectively, and the first DBI control signal and the second DBI control signal respectively control the output of the first data signal and the second data signal in units of one data sampling unit.
[0013] Optionally, when the DBI / DM setting mode is set to DM on and DBI off, at least one of the first sampling signal and the second sampling signal is combined with the DM signal to become the DM control signal, and the DM control signal controls the output of the first data signal and the second data signal, so that the input data signal is controlled by the DM signal in units of one or two data sampling units.
[0014] Optionally, when the DBI / DM setting mode is set to DBI on and DM on, one of the first sampling signal and the second sampling signal is combined with the DBI signal to become the first DBI control signal, and the other of the first sampling signal and the second sampling signal is combined with the DM signal to become the DM control signal, so that the input data signal is controlled by the DBI control signal and the DM control signal respectively in units of two data sampling units.
[0015] Optionally, when the data of the data sampling unit is controlled by the DBI control signal and the DM control signal, the DM control signal obtains priority control.
[0016] Optionally, the step of sampling according to the DQS signal includes sampling the DBI signal according to the DQS signal, and outputting in parallel the first sampling signal and the second sampling signal obtained by alternately sampling the DBI signal.
[0017] Optionally, the steps of sampling according to the DQS signal and sampling the input data signal further include performing double clock signal sampling after sampling according to the rising edge and falling edge groups of the DQS signal to produce the first sampling signal and the second sampling signal, as well as the first data signal and the second data signal.
[0018] In a second aspect, the present application provides a memory, the memory comprising:
[0019] An interface for receiving a data bus inversion (DBI) signal, a data mask (DM) signal, an input data (DQ) signal, and a data strobe signal (DQS);
[0020] A control circuit, the control circuit is used to execute the various operation methods as described above; and
[0021] A storage array, the storage array comprises storage units arranged in a matrix of multiple rows and columns, and is used to store the written data after the input data is controlled by the DBI control signal or the DM control signal.
[0022] Through the memory operation method and memory provided in the present application, a control algorithm for enabling DM / DBI at the same time is proposed, which can not only realize the simultaneous activation of DM / DBI functions, ensuring the optimization of power consumption and signal integrity while DM, but also reduce the operation granularity of DBI / DM. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.
[0024] Figure 1 is a functional module block diagram of a memory provided according to some embodiments of the present application;
[0025] Figure 2 is a schematic diagram of a storage array circuit of a memory provided according to some embodiments of the present application;
[0026] Figure 3is a schematic diagram of a DM / DBI operation flow of a memory provided according to some embodiments of the present application;
[0027] FIG. 4( a ) is a schematic diagram of a DM / DBI operation flow of a memory provided according to some embodiments of the present application;
[0028] FIG4( b ) is a schematic diagram of a data sampling unit provided according to some embodiments of the present application;
[0029] FIG4( c ) is a schematic diagram of data transmission control of a memory provided according to some embodiments of the present application;
[0030] Figure 5 is a functional module block diagram of a memory provided according to some embodiments of the present application;
[0031] Figure 6 A DM / DBI control timing diagram of input data provided according to some embodiments of the present application;
[0032] Figure 7 is a schematic block diagram of a control circuit provided according to some embodiments of the present application;
[0033] Figure 8 It is a functional schematic block diagram of a storage system provided according to some embodiments of the present application. DETAILED DESCRIPTION
[0034] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.
[0035] It should be understood that although the terms first, second, etc. may be used herein to describe various components, these components should not be limited to these terms. These terms are used to distinguish one component from another component. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component without departing from the scope of the present application.
[0036] It should be understood that when a component is said to be "on" or "connected" another component, it can be directly on or connected to another component, or there may be an intervening component. Other words used to describe the relationship between components should be interpreted in a similar manner.
[0037] As used herein, the term "layer" refers to a portion of a material including an area having a thickness. A layer may extend over the entire underlying or superstructure, or may have an extent that is less than the extent of the underlying or superstructure. In addition, a layer may be an area of a uniform or non-uniform continuous structure having a thickness that is less than the thickness of a continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive layers and a contact layer and one or more dielectric layers.
[0038] It should be noted that the illustrations provided in the embodiments of the present application are only used to illustrate the basic concept of the present application in a schematic manner. Although the illustrations only show components related to the present application and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout may also be more complicated.
[0039] This article uses Cartesian coordinates to represent directions, with the substrate as the reference, "Z" represents the first direction, which is the direction perpendicular to the substrate; "X" represents the second direction parallel to the substrate; "Y" represents the third direction parallel to the substrate and perpendicular to X.
[0040] First, please refer to Figure 1 , Figure 1 This is a functional schematic block diagram of a memory provided according to some embodiments of the present application. The memory 200 mainly includes a memory array 10, a peripheral circuit 20 for controlling the memory array 10, and an interface 30 for receiving various data and control signals.
[0041] like Figure 1 As shown, the peripheral circuit 20 is connected to the memory array 10, and the peripheral circuit 20 generally includes at least a row decoder 240, a word line voltage generator 211, a word line driver 212, a column decoder 250, a bit line driver 251, a bit line voltage generator 271, a reference current generator 261, a sensitive amplifier current comparator 262, and a logic control module 230 connected to the aforementioned devices for receiving operation instructions from the interface 30 and controlling the aforementioned devices.
[0042] The row decoder 240 receives the row address signal from the interface 30 and decodes the row address signal to select an addressed word line.
[0043] The word line driver 212 is connected to the plurality of word lines WL<0:m>, the word line voltage generator 211 and the row decoder 240. The word line driver 212 receives a row address selection signal and a word line driving voltage, and outputs the word line driving voltage to at least one word line WL<0:m> among the plurality of word lines WL<0:m> according to the row address selection signal. <m>At least one row of connected storage cells.
[0044] The bit line driver 251, the bit line voltage generator 271 and the column decoder 250 belong to the column driving circuit and are as shown in FIG. Figure 1 The bit line voltage generator 271 and the column decoder 250 are connected to the logic control module 230 to be controlled by the logic control module 230 .
[0045] The column decoder 250 receives the column address signal and decodes the column address signal to select the addressing bit line connected to the operation target memory cell. The bit line voltage generator 271 generates the clamping voltage required for each selected bit line and outputs the set clamping voltage to each corresponding selected bit line.
[0046] The bit line driver 251 is connected to a plurality of bit lines, a bit line voltage generator 271 and a column decoder 250. The bit line driver 251 receives a bit line voltage and a column address selection signal, and outputs a set clamped bit line voltage to at least one bit line BL<0:n> among the plurality of bit lines BL<0:n> according to the column address selection signal. <n>At least one column of memory cells is connected.
[0047] The peripheral circuit 20 further includes a sensitive amplifier current comparator 262, a reference current generator 261, a data latch (not shown), etc. The sensitive amplifier current comparator 262 is connected to the reference current generator 261 and a plurality of bit lines BL<0:n> and is connected to the data latch 223. The sensitive amplifier current comparator 262 is used to compare the read current with the reference current generated by the reference current generator 261 after receiving the read current, determine the data stored in the selected storage unit, and then store the data in the data latch 280, and output it to the data bus of the interface 30 through the input / output circuit 290 together with the data read from other bit lines.
[0048] Based on the structural design of the peripheral circuit 20 of the above-mentioned memory, the operation on the memory may include an erase operation, a read operation and a program operation, or a set and reset operation.
[0049] It should be understood that the storage cells of the storage array in the memory may be storage cells of various types of structures, such as capacitor storage cells of double data rate synchronous dynamic random access memory (DDR SDRAM), floating gate storage cells, nitride layer structure (ONO) storage cells, resistive memory cells (RRAM), phase change structure storage cells (PCM / PCRAM / SOM), etc. The present application does not limit this, but the present application is particularly suitable for phase change structure storage cells as DDR SDRAM, so the phase change structure storage cell (PCM) will be used as an example for illustration below, but it should be understood that it is not limited to this.
[0050] Please refer to Figure 2 As shown, Figure 2 The circuit diagram is an example of a memory array 10 as a memory provided according to some embodiments of the present application. The memory array 10 includes a plurality of memory cells 11 arranged in a multi-row and multi-column array, and word lines WLn and bit lines BLn respectively connecting the plurality of memory cells 11 in the plurality of rows and columns. Each row of memory cells includes a plurality of memory cells 11 arranged along a row direction X. Each column of memory cells includes a plurality of memory cells 11 arranged along a column direction (i.e., a second direction Y). For example, Figure 2 Only the memory cells of three rows WLn-1 to WLn+1 and three columns BLn-1 to BLn+1 are shown. In practice, the number of rows and columns of memory cells included in the memory depends on its storage capacity. Figure 2 The memory cell exemplified is a phase change memory cell 11, which includes an Ovonic Threshold Switch (OTS) 111 and a phase change memory cell (PCM storage cell) 112 connected in series between a word line WLn and a bit line BLn.
[0051] Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) is an SDRAM with double data transfer rate. It transmits data once during the rising and falling phases of the clock, that is, the data transmission speed is twice the system clock frequency. Due to the increased speed, its transmission performance is better than traditional SDRAM.
[0052] During a write operation of DDR SDRAM, Figure 1 As shown, the input signal DBI, the input data DQ and the data selection signal DQS are synchronized, and the rising and falling edges of DQS correspond to valid data. The memory 200 has a dedicated pin (pin) for supporting the data mask (DM) function and the data bus inversion (DBI) function, usually named DM_n or DBI_n.
[0053] Figure 3 A DM / DBI operation flow chart of a memory according to some embodiments of the present application is shown. Figure 3 As shown, during a DDR SDRAM write operation, the DM or DBI function is set to on or off through MRS (Mode Register Set), but not both at the same time.
[0054] The role of the DM function in a write operation is usually that when the DM_n of a given byte is sampled to a low level, the DRAM will mask the input write operation data; and when the DM_n of a given byte is sampled to a high level, the DRAM will not mask the input write operation data, but will write it into the storage unit. Figure 3 The two results at the bottom right. Since the data granularity is generally 4 bytes or 8 bytes, and DM corresponds to data in units of 1 byte, DM can support smaller granularity write operations while reducing power consumption.
[0055] The role of the DBI function in a write operation is that when the DBI_n of a given byte is sampled to a low level, the DRAM will invert the input write operation data. When the DBI_n of a given byte is sampled to a high level, the DRAM will not invert the input write operation data. Figure 3 The two results on the upper right side. Since the signal consumes energy only when it is pulled low, and when DBI is enabled, the number of bits pulled low does not exceed half of the total number of bits, while ensuring that fewer bits are switched between high and low levels, DBI can reduce power consumption and improve signal integrity.
[0056] However, since DDR SDRAM supports data writing in units of 8 bytes, the number of data bits is small. Therefore, when DM is turned on and DBI is turned off, the power consumption increase is smaller than when DBI is turned on. At the same time, the write operation granularity is smaller, and the number of unnecessary data bits accompanying each valid data is smaller. Therefore, when DBI is turned on and DM is turned off, the number of unnecessary data bits that are not masked is smaller, and the voltage amplification required for the write operation is smaller. Therefore, when DM / DBI are not turned on at the same time, the impact on DDR SDRAM performance is smaller.
[0057] In further research, the applicant found that since PCM only supports 16Bytes / 32Bytes write operations, the number of data bits is large, and the power consumption is greatly affected by turning DBI off and on during each write operation; at the same time, when DM is turned off, the number of unnecessary data bits that are not masked may be large, resulting in a large write voltage amplification. Therefore, in order to balance power consumption and write operation granularity, it is particularly necessary for PCM to be able to turn on DBI and DM at the same time.
[0058] After further research in this application, it is designed to sample the signal DBI by grouping the rising and falling edges of DQS to obtain the DBIR (DBI even Byte) and DBIF (DBI odd Byte) signals, and then control the opening and closing of the DM / DBI function through the DM / DBI enable signal configured by MRS, so that the DM / DBI functions can be turned on at the same time.
[0059] Therefore, according to a further embodiment of the present application, a memory operation method is provided, the operation method comprising:
[0060] receiving a data bus inversion (DBI) signal, a data mask (DM) signal, an input data (DQ) signal, and a data strobe signal (DQS);
[0061] Sampling is performed according to the DQS signal, and a first sampling signal and a second sampling signal obtained by alternately sampling in one data sampling unit are output in parallel; and
[0062] According to a DBI / DM setting mode, at least one of a DBI control signal associated with the DBI signal and a DM control signal associated with the DM signal is selectively generated through at least one of the first sampling signal and the second sampling signal.
[0063] Specifically, as shown in FIG4(a), after receiving the data bus inversion (DBI) signal DBI_n, the data mask (DM) signal DM_n, the input data (DQ) signal, and the data selection signal (DQS), the rising edge and the falling edge of the DQS signal are used as sampling time points, and grouping is performed according to the difference between the rising edge and the falling edge to obtain the first sampling signal DBIR and the second sampling signal DBIF output in parallel. Since the rising edge and the falling edge are alternately arranged, and as mentioned above, data is transmitted once in the rising period and the falling period of the clock, and DQS is synchronized with the clock signal, in this embodiment, one byte is used as a data sampling unit.
[0064] Therefore, as shown in FIG4(b), each DBIR / DBIF signal, i.e., the first / second sampling signal, is based on one byte and corresponds to the eight bytes (Byte0:Byte7) of the input data DQ alternately. However, it should be understood that, in this embodiment, although one byte is used as a data sampling unit, it is not limited thereto, and two bytes may also be used as a sampling unit.
[0065] After obtaining the first sampling signal and the second sampling signal, the first sampling signal and the second sampling signal will selectively generate at least one of a DBI control signal associated with the DBI signal and a DM control signal associated with the DM signal through at least one of the first sampling signal and the second sampling signal according to a DBI / DM setting mode.
[0066] Specifically, as shown in FIG4(a), since there are two sampling signals corresponding to the two requirements of DBI / DM, when DBI on / DM off is selected, both the first sampling signal DBIR and the second sampling signal DBIF can be set to control the on-state of DBI; when DBI off / DM on is selected, both the first sampling signal DBIR and the second sampling signal DBIF can be set to control the on-state of DM, or only one of the first sampling signal DBIR and the second sampling signal DBIF can be selected to control the on-state of DM; when DBI on / DM on is selected, one of the first sampling signal DBIR and the second sampling signal DBIF can be set to control the on-state of DBI, and the other of the first sampling signal DBIR and the second sampling signal DBIF can be set to control the on-state of DM.
[0067] In other words, the first sampling signal DBIR can be applicable to the scenario of DBI on / DM on, and the scenario of DBI on / DM off (that is, regardless of whether DM is on or off, it is used as a DBI control signal); the second sampling signal DBIF can also be applicable to the scenario of DBI on / DM off (because when DM is off, both sampling signals are used as DBI control signals), and can be applicable to the scenario of DM on / DBI on or off (that is, when DM is on, if DBI is off, at least one of the first sampling signal DBIR and the second sampling signal DBIF can be used as the DM control signal, and if DBI is on, they can be used as the DBI and DM control signals respectively together with the first sampling signal).
[0068] Therefore, the above possibilities are generally described here as selectively generating at least one of a DBI control signal associated with the DBI signal and a DM control signal associated with the DM signal through at least one of the first sampling signal and the second sampling signal according to the DBI / DM setting mode.
[0069] FIG4(c) is a schematic diagram of data transmission control of a memory provided according to some embodiments of the present application, which shows the various control methods and corresponding data transmission and control units described above in a table. As shown in FIG4(c), when the input data is Byte0 to Byte7, because the bytes are sampled at the rising edge and falling edge of each DQS signal, and each byte corresponds to a rising edge or a falling edge, a pair of first sampling signals DBIR0 and second sampling signals DBIF0 are generated for every two bytes.
[0070] In addition, when DM is off / DBI is on, since both the first sampling signal DBIR and the second sampling signal DBIF are used as DBI control signals, each sampling signal corresponds to one byte, so each DBI control signal can perform DBI control on each byte.
[0071] When DM is turned on / DBI is turned off, since only the second sampling signal DBIF is used as the DM control signal, each sampling signal corresponds to two bytes, for example, DBIF0 corresponds to Byte0 and Byte1, DBIF1 corresponds to Byte2 and Byte3, and so on, so each DM control signal can perform DM control on every two bytes. However, it should be understood that only the first sampling signal DBIR can be used as the DM control signal, or both the first sampling signal DBIR and the second sampling signal DBIF can be used as DM control signals (also referred to as the first DM control signal and the second DM control signal). In the latter example, since each sampling signal corresponds to a byte, each DM control signal can perform DM control on each byte. Therefore, in general, at least one of the first sampling signal and the second sampling signal can be used to combine the DM signal to become the DM control signal (even if each is referred to as the first DM control signal and the second DM control signal, they are collectively referred to as the DM control signal here), and the DM control signal controls the output of the first data signal and the second data signal, so that the input data signal is controlled by the DM signal in units of one or two data sampling units.
[0072] When DM is turned on / DBI is turned on, since the second sampling signal DBIF is used as the DM control signal, and the first sampling signal DBIR is used as the DBI control signal (the first sampling signal DBIR can also be used as the DM control signal, and the second sampling signal DBIF can be used as the DBI control signal), each sampling signal corresponds to two bytes, for example, DBIF0 corresponds to Byte0 and Byte1, DBIR0 also corresponds to Byte0 and Byte1, and so on. Therefore, each DM control signal or DBI control signal can perform DBI / DM control on every two bytes.
[0073] In some embodiments, the step of setting the mode according to DBI / DM includes setting through a mode register set (MRS) and outputting a DBI enable signal or a DM enable signal to control the first sampling signal and the second sampling signal to become at least one of the DBI signal and the DM signal.
[0074] Specifically, Figure 5 As shown, Figure 5 A functional module block diagram of a memory provided according to some embodiments of the present application is shown. Figure 5 In the embodiment, the memory 300 also includes the memory array 10, the peripheral circuit 21 and the interface 30. However, the peripheral circuit 21 in this embodiment includes the control circuit 215, and the control circuit 215 includes the sampling circuit 216 and the mode register 217.
[0075] As described above, the sampling circuit 216 is used to generate the first sampling signal DBIR and the second sampling signal DBIF. The control circuit 215 sets the first sampling signal DBIR and the second sampling signal DBIF to become the DBI control signal and / or the DM control signal according to the setting of the mode register 217.
[0076] Therefore, according to some embodiments of the present application, the present application provides a memory, wherein the memory includes:
[0077] An interface 30 for receiving a data bus inversion (DBI) signal, a data mask (DM) signal, an input data (DQ) signal, and a data strobe signal (DQS);
[0078] a control circuit 215, the control circuit comprising a sampling circuit 216, the sampling circuit 216 being used to perform sampling according to the DQS signal, and outputting in parallel a first sampling signal DBIR and a second sampling signal DBIF obtained by alternate sampling; and the control circuit 215 is further used to selectively generate at least one of a DBI control signal associated with the DBI signal and a DM control signal associated with the DM signal through at least one of the first sampling signal DBIR and the second sampling signal DBIF according to a DBI / DM setting mode; and
[0079] The storage array 10 includes storage cells arranged in a matrix of multiple rows and columns, and is used to store the written data after the input data is controlled by the DBI control signal or the DM control signal.
[0080] Through the aforementioned memory operation method and memory, not only can the DM / DBI functions be enabled at the same time, ensuring that power consumption and signal integrity can be optimized while DM is in effect, but the operation granularity of DBI / DM can also be reduced.
[0081] In a further embodiment, the method further includes: sampling the input data signal according to the DQS signal, and outputting in parallel a first data signal and a second data signal obtained by alternately sampling in a data sampling unit, and making the first data signal and the second data signal each output write data according to at least one of the DBI control signal and the DM control signal.
[0082] Specifically, Figure 6 As shown, Figure 6 A DM / DBI control timing diagram of input data provided according to some embodiments of the present application is shown. Figure 6 In the embodiment, the input data DQ is decomposed into a data sampling unit, that is, a byte, according to the rising edge and the falling edge of the DQS signal, and the first data signal DQR and the second data signal DQF are output in parallel by alternate group sampling. In addition, Figure 6 The waveforms of input data DQ, a data strobe signal DQS, and a DBI signal input into the memory as an input example are also shown.
[0083] exist Figure 6 In the figure, an example is shown of the waveforms of the DBI control signal and the DM control signal obtained by combining the DBI signal and the DM signal when the first sampling signal DBIR and the second sampling signal DBIF are used as DBI on / DM off, DBI off / DM on, and DBI on / DM on, respectively, as well as the controlled conditions of the first data signal DQR and the second data signal DQF obtained under the control of the DBI control signal and the DM control signal.
[0084] exist Figure 6 In the example of three DBI / DM being turned on or off, the controlled situation of each byte [00:15] in the first data signal DQR and the second data signal DQF is represented by different gray scales. For example, the byte controlled by DM is the darkest gray, the byte controlled by DBI is the medium gray, the byte controlled by both DBI and DM is represented by light gray, and the byte controlled by neither DBI / DM is represented by the lightest gray. For example, in the example of DBI being turned on / DM being turned off, bytes 02, 03, 04, 07, 08, 10, 11, and 12 are controlled by DBI; in the example of DBI being turned off / DM being turned on, bytes 02, 03, 06, 07, 10, and 11 are controlled by DM; in the example of DBI being turned on / DM being turned on, bytes 00, 01, 04, 05, 08, 09, 12, and 13 are controlled by DBI, bytes 02, 03, 06, and 07 are controlled by DM; and bytes 10 and 11 are controlled by both DBI and DM.
[0085] Therefore, according to the above description, it can be known that in some embodiments, the steps of sampling according to the DQS signal and sampling the input data signal DQ include grouping sampling according to the rising edge and the falling edge of the DQS signal, and the data sampling unit is one byte.
[0086] In some embodiments, when the DBI / DM setting mode is set to DBI on and DM off, the first sampling signal DBIR and the second sampling signal DBIF are combined with the DBI signal to become the first DBI control signal and the second DBI control signal belonging to the DBI control signal, respectively, and the first DBI control signal and the second DBI control signal respectively control the output of the first data signal DQR and the second data signal DQF in units of the data sampling unit.
[0087] In some embodiments, when the DBI / DM setting mode is set to DM on and DBI off, one of the first sampling signal DBIR and the second sampling signal DBIF is combined with the DM signal to become the DM control signal, and the DM control signal synchronously controls the output of the first data signal DQR and the second data signal DQF, so that the input data signal DQ is controlled by the DM signal in units of two data sampling units.
[0088] In the embodiment described in the previous paragraph, it can be understood that the first sampling signal DBIR and the second sampling signal DBIF can also be combined with the DM signal to become the first DM control signal and the second DM control signal (not shown), and the first DM control signal and the second DM control signal respectively control the output of the first data signal DQR and the second data signal DQF, so that the input data signal DQ is controlled by the DM control signal (including the first DM control signal and the second DM control signal) in units of the data sampling unit.
[0089] It should be explained here that, as mentioned above, there can be only one or two DM control signals, but for the sake of convenience of explanation, only one DM control signal is summarized here and expressed as at least one of the first sampling signal DBIR and the second sampling signal DBIF combined with the DM signal to become the DM control signal, and the DM control signal controls the output of the first data signal DQR and the second data signal DQF, so that the input data signal DQ is controlled by the DM signal in units of one or two data sampling units.
[0090] In some embodiments, when the DBI / DM setting mode is set to DBI on and DM on, the first sampling signal DBIR is combined with the DBI signal to become the first DBI control signal, and the second sampling signal DBIF is combined with the DM signal to become the DM control signal, so that the input data signal DQ is controlled by the DBI signal and the DM signal respectively in units of two data sampling units.
[0091] In the embodiment described in the previous paragraph, the second sampling signal DBIF can also be combined with the DBI signal to become the first DBI control signal, and the first sampling signal DBIR can be combined with the DM signal to become the DM control signal, so that the input data signal DQ is controlled by the DBI control signal and the DM control signal respectively in units of two data sampling units.
[0092] That is, in general, when the DBI / DM setting mode is set to DBI on and DM on, either the first sampling signal DBIR or the second sampling signal DBIF can be combined with the DBI signal to become the first DBI control signal, and the other of the first sampling signal DBIR and the second sampling signal DBIF can be combined with the DM signal to become the DM control signal.
[0093] In some embodiments, when the transmission data of the data sampling unit is controlled by the DBI control signal and the DM control signal at the same time, the DM control signal obtains priority control.
[0094] It can be understood that in some embodiments, the step of setting the mode according to DBI / DM includes setting through a mode register setting (MRS) and outputting a DBI enable signal or a DM enable signal to control at least one of the first sampling signal DBIR and the second sampling signal DBIF to become at least one of the DBI control signal and the DM control signal.
[0095] In some embodiments, the step of sampling according to the DQS signal includes sampling the DBI signal according to the DQS signal, and outputting in parallel the first sampling signal DBIR and the second sampling signal DBIF obtained by alternately sampling the DBI signal. It can be understood that the first sampling signal and the second sampling signal are not limited to sampling the DBI signal, and can also be obtained by directly sampling the rising edge and the falling edge of the DQS in groups, so the first and second sampling signals are not limited to sampling the DBI signal.
[0096] The following is further used to achieve Figure 5 The specific circuit of the control circuit function shown is explained.
[0097] like Figure 7 As shown, the control circuit 215 includes a sampling circuit 216, and the sampling circuit 216 includes a plurality of deserializers 216a, and the deserializers 216a are used to group and split the DBI signal into a first sampling signal DBIR and a second sampling signal DBIF through the rising edge and the falling edge of the DQS signal; and split the input signal DQ into a first data signal DQR and a second data signal DQF. The splitting method is as described above, with one byte as a data sampling unit.
[0098] In some embodiments, the control circuit 215 further includes double clock signal sampling. That is, through the double clock signal WT_CK_X2, the first sampling signal DBIR and the second sampling signal DBIF, as well as the first data signal DQR and the second data signal DQF are doubled to become DBIR_X2 and DBIF_X2, as well as DQR_X2 and DQF_X2. In this description, for the sake of simplicity, the description is omitted in a manner of omitting X2, so that regardless of whether there is double clock sampling, the first sampling signal and the second sampling signal, as well as the first data signal and the second data signal are all said to be generated.
[0099] The control circuit 215 also includes a part not shown in FIG. Figure 7 The mode register 217 is used to output a DM enable signal DM_en and a DBI enable signal DBI_en according to the setting. The DM enable signal DM_en and the DBI enable signal DBI_en control the distribution of the first sampling signal DBIR and the second sampling control signal DBIF according to their high level or low level.
[0100] like Figure 7 As shown, the control circuit 215 further includes a plurality of AND gates 215a for transmitting the first sampling signal DBIR and the second sampling signal DBIF to generate the first DBI control signal DBIR_DBI_n and the second DBI control signal DBIF_DBI_n according to the enable signal DBI_en set by the mode register 217. Figure 7 As shown, the second sampling signal DBIF is combined with the DM signal to generate the DM control signal DM_n. After being controlled by the DBI control signal, the first data signal DQR and the second data signal DQF are output as the first data write signal DQR_DBI and the second data write signal DQF_DBI through the multiplexer 215b.
[0101] Although a specific embodiment of the control circuit 215 is illustrated above, it should be understood that there may be a variety of circuits that achieve the aforementioned operation method, as long as the aforementioned functions can be achieved, and therefore the control circuit is not limited to the circuit illustrated here. For example, instead of directly sampling the DBI signal, the DQS signal may be deconstructed into a first sampling signal and a second sampling signal, and then, according to the settings of the DBI enable signal and the DM enable signal, the first sampling signal and the second sampling signal are respectively combined with the input DBI signal and / or the DM signal according to the settings, and the DBI control signal and the DM control signal are output.
[0102] As shown previously Figure 5 and Figure 7 From the functional block diagram of the memory circuit illustrated, it can be understood that in some embodiments, the sampling circuit 216 is also used to sample the input data signal DQ according to the DQS signal, and output in parallel the first data signal DQR and the second data signal DQF obtained by alternately sampling in one data sampling unit; and the control circuit 215 is also used to make the first data signal DQR and the second data signal DQF output the write data to the storage array 10 according to at least one of the DBI control signal and the DM control signal.
[0103] In some embodiments, the sampling circuit 216 is further configured to perform sampling according to the rising edge and falling edge groups of the DQS signal, and the data sampling unit is one byte.
[0104] In some embodiments, the control circuit 215 further includes a mode register 217 for outputting a DBI enable signal DBI_en or a DM enable signal DM_en according to a setting to control the first sampling signal DBIR and the second sampling signal DBIF to become at least one of the DBI control signal and the DM control signal.
[0105] In some embodiments, when the DBI / DM setting mode of the control circuit 215 is set to DBI on and DM off, the first sampling signal DBIR and the second sampling signal DBIF are combined with the DBI signal to become the first DBI control signal DBIR_DBI_n and the second DBI control signal DBIF_DBI_n belonging to the DBI control signal DBI_n, respectively, and the first DBI control signal and the second DBI control signal respectively control the output of the first data signal and the second data signal in units of one data sampling unit.
[0106] In some embodiments, when the DBI / DM setting mode of the control circuit 215 is set to DM on and DBI off, as described above, at least one of the first sampling signal DBIR and the second sampling signal DBIF is combined with the DM signal to become the DM control signal DM_n, and the DM control signal DM_n controls the output of the first data signal DQR and the second data signal DQF, so that the input data signal DQ is controlled by the DM signal in units of one or two data sampling units.
[0107] The reason why at least one of them is mentioned above is that in some embodiments, the first sampling signal DBIR and the second sampling signal DBIF can also be combined with the DM signal to become the first DM control signal and the second DM control signal (not shown), and the first DM control signal and the second DM control signal respectively control the output of the first data signal DQR and the second data signal DQF, so that the input data signal DQ is controlled by the DM signal in units of one data sampling unit.
[0108] In some embodiments, when the DBI / DM setting mode is set to DBI on and DM on, the control circuit 215 can, as described above, make either the first sampling signal DBIR or the second sampling signal DBIF combined with the DBI signal to become the first DBI control signal DBI_n, and make the other of the first sampling signal and the second sampling signal DBIF combined with the DM signal to become the DM control signal DM_n, so that the input data signal DQ is controlled by the DBI signal DBI_n and the DM signal DM_n respectively in units of two of the data sampling units.
[0109] Depend on Figure 7 It can be understood that in some embodiments, when the data of the data sampling unit is controlled by the DBI control signal and the DM control signal, the control circuit 215 obtains priority control by the DM control signal; and the sampling circuit 216 is used to sample the DBI signal and output in parallel the first sampling signal DBIR and the second sampling signal DBIF obtained by alternately sampling the DBI signal.
[0110] It should be noted that, in some embodiments, the DM signal and the DBI signal are input from the same PIN, that is, the information of both is contained in a common signal, which is represented by DBI in the figure. Therefore, in the input of a DM / DBI signal, different DBI control signals and DM control signals can be generated in conjunction with the actuation of the DBI enable signal DBI_en or the DM enable signal DM_en, and the DBI / DM mode setting of the mode register 217. Through the aforementioned memory 300, not only can the DM / DBI functions be enabled at the same time, ensuring that power consumption and signal integrity can be optimized while DM is in operation, but also the operation granularity of DBI / DM can be reduced.
[0111] Furthermore, according to some embodiments of the present application, Figure 8 As shown, a storage system 400 is also provided, and the storage system 400 includes the memory 300 described above; and
[0112] The controller 40 is electrically connected to the memory 300 and is used to control the memory 300 .
[0113] That is, the control circuit 215 in the memory 300 controls the settings of DMI and DM, and controls the DMI / DM function of the input data, and the operation methods described in the previous embodiments can be performed. Alternatively, the control circuit 215 described above can be set in the controller 40 to control the settings of DMI and DM, and control the DMI / DM function of the input data, and the operation methods described in the previous embodiments can be performed. Therefore, it should be understood that the memory described in this application can also be a storage system.
[0114] In some embodiments, the storage system may be implemented as a storage device such as a universal flash storage (UFS) device, a solid state drive (SSD), a multimedia card in the form of MMC, eMMC, RS-MMC and micro MMC, a secure digital card in the form of SD, mini SD and micro SD, a Personal Computer Memory Card International Association (PCMCIA) card type storage device, a peripheral component interconnect (PCI) type storage device, a high-speed PCI (PCI-E) type storage device, a compact flash (CF) card, a smart media card or a memory stick, etc.
[0115] The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technical personnel in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.< / n> < / m>
Claims
1. A method for operating a memory, characterized in that: The operation method comprises: receiving a data bus inversion (DBI) signal, a data mask (DM) signal, an input data (DQ) signal, and a data strobe signal (DQS); Sampling is performed according to the DQS signal, and a first sampling signal and a second sampling signal obtained by alternately sampling in one data sampling unit are output in parallel; and According to a DBI / DM setting mode, at least one of a DBI control signal associated with the DBI signal and a DM control signal associated with the DM signal is selectively generated through at least one of the first sampling signal and the second sampling signal.
2. The memory operation method according to claim 1, characterized in that: The method further comprises: The input data signal is sampled according to the DQS signal, and a first data signal and a second data signal obtained by alternately sampling in a data sampling unit are output in parallel, and the first data signal and the second data signal are each output as write data according to at least one of the DBI control signal and the DM control signal.
3. The memory operation method according to claim 2, characterized in that: The steps of sampling according to the DQS signal and sampling the input data signal include sampling according to the rising edge and falling edge groups of the DQS signal to obtain the first sampling signal and the second sampling signal, and the data sampling unit is one byte.
4. The memory operation method according to claim 2, characterized in that: The step of setting the mode according to DBI / DM includes setting through a mode register set (MRS) and outputting a DBI enable signal or a DM enable signal to selectively generate at least one of the DBI control signal and the DM control signal through at least one of the first sampling signal and the second sampling signal.
5. The memory operation method according to claim 2, characterized in that: When the DBI / DM setting mode is set to DBI on and DM off, the first sampling signal and the second sampling signal are combined with the DBI signal to become the first DBI control signal and the second DBI control signal belonging to the DBI control signal, respectively, and the first DBI control signal and the second DBI control signal respectively control the output of the first data signal and the second data signal in units of one data sampling unit.
6. The memory operation method according to claim 2, characterized in that: When the DBI / DM setting mode is set to DM on and DBI off, at least one of the first sampling signal and the second sampling signal is combined with the DM signal to become the DM control signal, and the DM control signal controls the output of the first data signal and the second data signal, so that the input data signal is controlled by the DM signal in units of one or two data sampling units.
7. The memory operation method according to claim 2, characterized in that: When the DBI / DM setting mode is set to DBI on and DM on, one of the first sampling signal and the second sampling signal is combined with the DBI signal to become the first DBI control signal, and the other of the first sampling signal and the second sampling signal is combined with the DM signal to become the DM control signal, so that the input data signal is controlled by the DBI control signal and the DM control signal respectively in units of two data sampling units.
8. The memory operation method according to claim 2, characterized in that: When the data of the data sampling unit is controlled by the DBI control signal and the DM control signal, the DM control signal obtains priority control.
9. The memory operation method according to claim 2, characterized in that: The step of sampling according to the DQS signal includes sampling the DBI signal according to the DQS signal, and outputting in parallel the first sampling signal and the second sampling signal obtained by alternately sampling the DBI signal.
10. The memory operation method according to claim 3, characterized in that: The steps of sampling according to the DQS signal and sampling the input data signal further include performing double clock signal sampling after sampling according to the rising edge and falling edge groups of the DQS signal to produce the first sampling signal and the second sampling signal, as well as the first data signal and the second data signal.
11. A memory, characterized in that: The memory comprises: An interface for receiving a data bus inversion (DBI) signal, a data mask (DM) signal, an input data (DQ) signal, and a data strobe signal (DQS); A control circuit, the control circuit being used to execute the operating method according to any one of claims 1 to 10; and A storage array, the storage array comprises storage units arranged in a matrix of multiple rows and columns, and is used to store the written data after the input data is controlled by the DBI control signal or the DM control signal.