Multi-interface adaptive switching system

Abstract

The invention discloses a multi-interface self-adaptive switching system, relates to the technical field of bus communication, and aims to realize bus communication and relay control through an FPGA (Field Programmable Gate Array), save software and hardware resources and improve the performance at the same time. When the interface of the processor cannot meet the resource requirement, the interface expansion is performed through the FPGA, and the functions of multi-path CAN bus, RS485 bus communication and the like can be realized. And interface switching of different buses such as CAN and RS485 can be realized only by clicking IO port output on an upper computer, so that the efficiency is greatly improved.

Description

Technical Field

[0001] The invention relates to the technical field of bus communication, and in particular to a CAN, RS485 and other multiple interface adaptive switching system based on FPGA. Background Art

[0002] With the rapid development of embedded system interconnection and communication, traditional RS232, RS422 and other buses are gradually restricted by the transmission distance, anti-interference ability, load capacity and transmission rate.

[0003] The CAN bus system is a multi-master bus system that realizes the transmission of large amounts of data between two nodes under the coordination of the bus controller. Since the CAN network messages are sent in a broadcast manner, that is, the data detected by all nodes are consistent, the CAN bus is very suitable for the transmission of control information and data information.

[0004] The CAN bus has an ultra-long transmission distance, with a theoretical upper limit of 10km. A single bus can carry 110 nodes without interfering with each other, and the high baud rate ensures the data transmission rate.

[0005] The RS485 interface supports one host to connect multiple slaves, which is a daisy chain connection, and different devices are distinguished by communication addresses.

[0006] The transmission signal of RS485 is a differential signal, which also brings many advantages in communication:

[0007] A. Strong anti-interference ability: Since the differential signal A / B is close to the routing, the interference noise is generally equal, and the difference is 0, that is, this noise has no effect on the logical meaning of the signal.

[0008] B. Strong signal judgment ability: The threshold judgment point of the receiving end is at the positive and negative intersection of the two signal lines, which is used as the point for judging the logic 0 / 1 jump (A voltage is greater than B voltage for logic "1", otherwise it is "0", and the voltage amplitude requirement of the signal is low.

[0009] However, there is no mature multi-interface CAN and RS485 adaptive switching solution at this stage. At the same time, most of the existing bus communication solutions require one control pin for one signal, which takes up a lot of resources; in addition, there may be errors in the timing of CPU controlling multiple signals, and the output signal synchronization is poor. Summary of the invention

[0010] In view of the above problems, the present invention provides a system for adaptively switching multiple interfaces for overcoming the above problems or at least partially solving the above problems.

[0011] The present invention provides the following scheme:

[0012] A multi-interface adaptive switching system, comprising:

[0013] FPGA device, wherein the FPGA device establishes a communication connection with the CPU via the Local Bus and the PCI-E standard;

[0014] A first bus transceiver, wherein the first bus transceiver is connected to the FPGA device;

[0015] A second bus transceiver, the second bus transceiver is connected to the FPGA device; the first bus transceiver and the second bus transceiver are used to implement transceiver communication of different types of communication buses;

[0016] A relay group, the relay group comprising a first relay and a second relay, the first relay is connected to the second relay and a first communication bus and a second communication bus, the second relay is connected to the first bus transceiver, the second bus transceiver and the first relay; the first relay and the second relay are respectively connected to the FPGA device through an IO corresponding interface;

[0017] The CPU is configured with a driver for realizing the transceiver functions of the different types of communication buses; the CPU is used to send a bus switching instruction to the FPGA device, so that the FPGA device sends the bus switching instruction to the first relay and the second relay through the IO port, the first relay is in the first bus conduction state by default, and the first relay and the second relay are switched from the initial state to the second bus conduction state after receiving the bus switching instruction;

[0018] In the initial state, the first relay connects the first bus transceiver to the first communication bus and the second relay is suspended, and when receiving an instruction to output the first bus, the second relay is closed;

[0019] When receiving the second bus output instruction, switching the first relay to convert the first bus to the second bus, and then closing the second relay; switching to the second bus output.

[0020] Preferably: the first bus transceiver includes a Glb2582 transceiver, and the first communication bus includes an RS485 communication bus; the second bus transceiver includes a Glb3053 transceiver, and the second communication bus includes a CAN communication bus.

[0021] Preferably: the driver comprises a CAN driver, and the CAN driver adopts a triple data buffer structure of a sending ringbuffer, a receiving ringbuffer and a user data ringbuffer.

[0022] Preferably: the CAN driver comprises a CAN initialization module, a CAN communication frame sending and receiving module, and a CAN communication frame packaging and unpacking module.

[0023] Preferably: the CAN initialization module is used to determine the frame format, frame type, data length of each frame, data and message identification code initialization format of the CAN communication frame, apply for the ringbuffer space for storing the received communication frame, and configure the CAN register;

[0024] The CAN communication frame sending and receiving module is used to complete the configuration of the communication frame and judge the transmission buffer state before the CAN communication frame is sent, and to judge the transmission completion state before the end of the sending, so as to ensure that the communication frame has been sent; each time the reception of the communication frame is completed, the receiving buffer is released by setting the command register, so as to ensure the normal transmission of the subsequent communication frame;

[0025] The CAN communication frame packaging and unpacking module is used to decompose the data from the user into CAN communication frames, send out each frame of CAN data by calling the CAN communication frame sending interface, assemble and splice the data parts from the CAN bus communication frame, and feed back the complete data to the user.

[0026] Preferably: the frame format includes an extended frame, the frame type includes a data frame, the data length of each frame includes 8 bytes, and the initialization format of the data and message identification code is 0.

[0027] Preferably: the driver includes an RS485 driver, and the RS485 driver is used to provide a baud rate and other parameter configuration interface function, a configurable receiving interrupt threshold, a timeout interrupt function, and a data receiving and sending function.

[0028] Preferably: the FPGA device is configured with a plurality of expandable interfaces for realizing the expansion function of multiple communication buses of different types.

[0029] Preferably: the CPU is further used to receive user-triggered switching information, and generate the bus switching instruction according to the switching information.

[0030] According to the specific embodiments provided by the present invention, the present invention discloses the following technical effects:

[0031] The embodiment of the present application provides a multi-interface adaptive switching system, which realizes bus communication and control of relays through FPGA, saves software and hardware resources, and improves performance. When the processor's own interface cannot meet the resource requirements, the interface expansion through FPGA can realize functions such as multi-channel CAN bus and RS485 bus communication. Only by clicking the IO port output on the host computer can the interface switching of different buses such as CAN and RS485 be realized, which greatly improves efficiency.

[0032] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0034] Figure 1 It is a framework diagram of a system for adaptively switching multiple interfaces provided by an embodiment of the present invention;

[0035] Figure 2 is a CAN communication block diagram provided by an embodiment of the present invention;

[0036] Figure 3 It is a RS485 communication block diagram provided by an embodiment of the present invention;

[0037] Figure 4 It is a block diagram of the CAN communication function module provided by an embodiment of the present invention;

[0038] Figure 5 is a CAN communication data flow diagram provided by an embodiment of the present invention;

[0039] Figure 6 is a CAN module communication flow chart provided by an embodiment of the present invention;

[0040] Figure 7 It is a block diagram of the RS485 communication function module provided by an embodiment of the present invention;

[0041] Figure 8 This is the RS485 communication function module workflow provided by the embodiment of the present invention;

[0042] Fig. 9 It is a bus switching principle diagram provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0043] The technical scheme in the embodiment of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiment of the present invention. Obviously, the described embodiment is only a part of the embodiment of the present invention, not all of the embodiments. Based on the embodiment of the present invention, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present invention.

[0044] See also Figure 1 , is a system for adaptively switching multiple interfaces provided by an embodiment of the present invention, such as Figure 1 As shown, the system may include:

[0045] An FPGA device, wherein the FPGA device establishes a communication connection with the CPU via a Local Bus and a PCI-E standard;

[0046] A first bus transceiver, wherein the first bus transceiver is connected to the FPGA device;

[0047] A second bus transceiver, the second bus transceiver is connected to the FPGA device; the first bus transceiver and the second bus transceiver are used to implement transceiver communication of different types of communication buses;

[0048] A relay group, the relay group comprising a first relay and a second relay, the first relay is connected to the second relay and a first communication bus and a second communication bus, the second relay is connected to the first bus transceiver, the second bus transceiver and the first relay; the first relay and the second relay are respectively connected to the FPGA device through corresponding interfaces;

[0049] Among them, the CPU is configured with a driver for realizing the transceiver functions of the different types of communication buses; the CPU is used to send a bus switching instruction to the FPGA device, so that the FPGA device sends the bus switching instruction to the first relay and the second relay through the IO port, the first relay defaults to the first bus conduction state, and the first relay and the second relay switch from the initial state to the second bus conduction state after receiving the bus switching instruction.

[0050] In the initial state, the first relay connects the first bus transceiver to the first communication bus and the second relay is suspended, and when receiving an instruction to output the first bus, the second relay is closed;

[0051] When receiving the second bus output instruction, switching the first relay to convert the first bus to the second bus, and then closing the second relay; switching to the second bus output.

[0052] In the initial state, the first relay connects the first bus transceiver to the first communication bus and the second relay is suspended. When an instruction to output the first bus is received, the second relay is closed. When an instruction to output the second bus is received, the first relay is switched to convert the first bus to the second bus, and then the second relay is closed. At this time, the output is the second bus.

[0053] The multiple interface adaptive switching system provided in the embodiment of the present application uses FPGA to control the output of different types of buses such as CAN and RS485, and has better performance. In terms of hardware, the FPGA controls the relay to perform adaptive switching of different bus interfaces such as CAN and RS485, and can use fewer pins to achieve more signal control, saving resources. PCIe is used between the CPU and FPGA to improve the data transmission speed and has scalability and compatibility.

[0054] The first communication bus and the second communication bus provided in the embodiment of the present application can determine their types according to the actual use scenario requirements, and configure the corresponding bus transceiver according to the bus type. For example, in one implementation, the embodiment of the present application can provide that the first bus transceiver includes a Glb2582 transceiver, and the first communication bus includes an RS485 communication bus; the second bus transceiver includes a Glb3053 transceiver, and the first communication bus includes a CAN communication bus. Through the above two transceivers, CAN and RS485 bus communications and switching functions can be realized. The corresponding first communication bus can be a CAN bus, and the second communication bus can be an RS485 bus.

[0055] Due to the demand for localization, imported chips need to be replaced in situ. Faced with an embedded system with tailorable functions, the embodiment of the present application provides a CAN bus and RS485 bus driver based on FPGA.

[0056] In a specific implementation, the driver includes a CAN driver, and the CAN driver adopts a triple data buffer structure of a sending ringbuffer, a receiving ringbuffer and a user data ringbuffer.

[0057] The CAN driver comprises a CAN initialization module, a CAN communication frame sending and receiving module, and a CAN communication frame packaging and unpacking module.

[0058] The CAN initialization module is used to determine the frame format, frame type, data length of each frame, data and message identification code initialization format of the CAN communication frame, apply for the ringbuffer space for storing the received communication frame, and configure the CAN register;

[0059] The CAN communication frame sending and receiving module is used to complete the configuration of the communication frame and judge the transmission buffer state before the CAN communication frame is sent, and to judge the transmission completion state before the end of the sending, so as to ensure that the communication frame has been sent; each time the reception of the communication frame is completed, the receiving buffer is released by setting the command register, so as to ensure the normal transmission of the subsequent communication frame;

[0060] The CAN communication frame packaging and unpacking module is used to decompose the data from the user into CAN communication frames, send out each frame of CAN data by calling the CAN communication frame sending interface, assemble and splice the data parts from the CAN bus communication frame, and feed back the complete data to the user.

[0061] The frame format includes an extended frame, the frame type includes a data frame, the data length of each frame includes 8 bytes, and the initialization format of the data and message identification code is 0.

[0062] The driver includes an RS485 driver, and the RS485 driver is used to provide a baud rate and other parameter configuration interface function, a configurable receiving interrupt threshold, a timeout interrupt function, and a data receiving and sending function.

[0063] In order to facilitate the expansion of the interface, the embodiment of the present application can also provide that the FPGA device is configured with several expandable interfaces for realizing the expansion function of multiple communication buses of different types.

[0064] In order to facilitate the determination of the bus switching timing, the embodiment of the present application may further provide that the CPU is also used to receive user-triggered switching information and generate the bus switching instruction according to the switching information.

[0065] The following describes in detail the system provided in the embodiment of the present application by taking the switching between the CAN bus and the RS485 bus as an example.

[0066] FPGA (Field Programmable Gate Array) is an integrated circuit chip that integrates a large number of programmable logic and storage units. It is flexible and programmable and can realize various digital logic functions.

[0067] FPGA technology can be used to realize the design of CAN bus and RS485 bus. Through the programmability of FPGA, the functions of CAN bus controller, interface circuit, etc. can be flexibly realized.

[0068] As an electrical interface, RS485 interface realizes the physical layer in the communication network. It has the advantages of high transmission rate, good noise resistance, long transmission distance and multi-station capability. Using FPGA for RS485 design can take advantage of the flexibility and programmability of FPGA to realize efficient and stable RS485 communication interface.

[0069] PCIe is used for data transmission between CPU and FPGA. PCIe is a high-speed serial computer expansion bus standard. It is a high-speed serial point-to-point dual-channel high-bandwidth transmission. The connected devices are allocated exclusive channel bandwidth and do not share bus bandwidth. PCIe exists in two forms: M.2 interface channel form and PCIe standard slot.

[0070] A. PCIe uses serial data packets (TLP) for transmission. Data and instructions at each layer are transmitted in the form of TLP packets, ensuring the integrity and reliability of data transmission.

[0071] B. PCIe uses differential LVDS serial transmission in data transmission. One PCIE channel is transmitted and received by two pairs of LVDS differential signal lines.

[0072] C. It adopts point-to-point serial connection. Compared with the shared parallel architecture of PCI bus, it can allocate independent channel resources to all devices in the system, fully guarantee the bandwidth of the equipment and improve the data transmission efficiency.

[0073] The FPGA and CPU communicate via PCIE and Local Bus, and the FPGA external Glb3053 transceiver communicates with the outside world via CAN (such as Figure 2 As shown), the FPGA external Glb2582 transceiver performs RS485 communication (as shown Figure 3 shown).

[0074] The CAN bus communication function is realized through FPGA, and the CAN communication frame can be correctly transmitted. To complete the complete data transmission, it is also necessary to unpack the data from the CPU and pack the CAN communication frames from other modules. Therefore, the design of the CAN driver consists of five parts: CAN initialization, CAN communication frame sending and receiving, and CAN communication frame packing and unpacking. Figure 4 As shown:

[0075] CAN initialization:

[0076] The frame format of the CAN communication frame is set to an extended frame, the frame type is set to a data frame, the data length of each frame is set to 8 bytes, and the data and message identification codes are initialized to 0. Initialization also requires the application of a ringbuffer space for storing received communication frames, which is used to store multiple groups of communication frames. The configuration of the CAN register mainly includes baud rate, interrupt enable, clock division, and output controller.

[0077] CAN communication frame sending and receiving:

[0078] Before sending the CAN communication frame, the configuration of the communication frame is completed and the status of the transmission buffer is judged. Before the end of sending, the transmission completion status is judged to ensure that the communication frame has been sent. Each time the reception of the communication frame is completed, the receiving buffer is released by setting the command register to ensure the normal transmission of subsequent communication frames.

[0079] Packaging and unpacking of CAN communication frames:

[0080] The unpacking of CAN communication frames decomposes the data from the user into CAN communication frames, and sends each frame of CAN data by calling the CAN communication frame sending interface. The packaging of CAN communication frames assembles and splices the data parts from the CAN bus communication frames, and feeds back the complete data to the user.

[0081] The CAN bus driver design uses a triple data buffer structure of send ringbuffer, receive ringbuffer and user data ringbuffer to ensure the correctness and integrity of the data sent and received by the user. The data flow diagram of CAN communication is as follows Figure 5 shown.

[0082] After the CAN module completes the CAN controller initialization and related parameter configuration, it waits for the receive interrupt. The outline of the workflow is as follows:

[0083] The FPGA is connected to the RS485 bus through an RS485 converter, which converts the level into a differential signal and provides a control signal for selecting the sending or receiving mode.

[0084] In RS485 communication networks, 485 transceivers are usually used to convert TTL levels and RS485 levels. The serial port controller in the node uses RX and TX signal lines to connect to the 485 transceiver, and the transceiver leads out the RS485 signal through differential lines.

[0085] TTL signals are generally used for transmission between the serial port controller and the transceiver, while differential signals are used for transmission between the transceiver and the bus.

[0086] When sending data, the TX signal of the serial port controller is converted into a differential signal by the transceiver and transmitted to the bus.

[0087] When receiving data, the transceiver converts the differential signal on the bus into a TTL signal and transmits it to the serial port controller through the RX pin.

[0088] The software provides RS485 communication function, baud rate and other parameter configuration interface functions, configurable receiving interrupt threshold, timeout interrupt function, and data receiving and sending functions. The RS485 communication function module consists of Figure 7 shown.

[0089] After the module completes the initialization of the serial port controller and the configuration of related parameters, it waits for the reception interrupt. The outline of the workflow is as follows: Figure 8 shown.

[0090] After FPGA realizes CAN and RS485 communication, FPGA controls the relay by controlling the IO port to realize the switching between CAN and RS485 buses. The bus switching design diagram is shown in Fig. 9 As shown in the figure, the switching control of CAN / RS485 can be realized by using two relays together. Relay 1 is selected as RS485 bus by default, and relay 2 is suspended by default. The switch control of the relay is realized by 5V TTL signal control, so that RS485 and CAN can be switched. When the 485 interface is needed, the relay keeps the initial default state; when the CAN interface is needed, click the corresponding IO port output on the host computer, and control relay 1 and relay 2 to close through the IO port, and the external output is switched to the CAN interface.

[0091] When the processor's own interface cannot meet the resource requirements, FPGA is used to expand the interface on the external memory bus interface to realize functions such as multi-channel CAN bus and RS485 bus communication. Figure 1 Shown: A block diagram of the implementation of CAN, RS485 multiple interface adaptive switching technology based on FPGA.

[0092] When the processor's own interface cannot meet the resource requirements, FPGA is used to expand the interface on the external memory bus interface to realize functions such as multi-channel CAN bus and RS485 bus communication.

[0093] In short, the multiple interface adaptive switching system provided by this application realizes bus communication and control of relays through FPGA, saves software and hardware resources, and improves performance at the same time. When the processor's own interface cannot meet resource requirements, the interface is expanded through FPGA, and functions such as multi-channel CAN bus and RS485 bus communication can be realized. Only by clicking the IO port output on the host computer, the interface switching of different buses such as CAN and RS485 can be realized, which greatly improves efficiency.

[0094] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0095] It can be known from the description of the above implementation methods that those skilled in the art can clearly understand that the present application can be implemented by means of software plus a necessary general hardware platform. Based on such an understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product can be stored in a storage medium such as ROM / RAM, a magnetic disk, an optical disk, etc., and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in the various embodiments of the present application or certain parts of the embodiments.

[0096] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can refer to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system or system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can refer to the partial description of the method embodiment. The system and system embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without creative work.

[0097] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims

1. A system for adaptively switching multiple interfaces, characterized in that: include: An FPGA device, wherein the FPGA device establishes a communication connection with the CPU via a Local Bus and a PCI-E standard; A first bus transceiver, wherein the first bus transceiver is connected to the FPGA device; A second bus transceiver, the second bus transceiver is connected to the FPGA device; the first bus transceiver and the second bus transceiver are used to implement transceiver communication of different types of communication buses; A relay group, the relay group comprising a first relay and a second relay, the first relay is connected to the second relay and a first communication bus and a second communication bus, the second relay is connected to the first bus transceiver, the second bus transceiver and the first relay; the first relay and the second relay are respectively connected to the FPGA device through an IO corresponding interface; The CPU is configured with a driver for realizing the transceiver functions of the different types of communication buses; the CPU is used to send a bus switching instruction to the FPGA device, so that the FPGA device sends the bus switching instruction to the first relay and the second relay through the IO port, the first relay is in the first bus conduction state by default, and the first relay and the second relay are switched from the initial state to the second bus conduction state after receiving the bus switching instruction; In the initial state, the first relay connects the first bus transceiver to the first communication bus and the second relay is suspended, and when receiving an instruction to output the first bus, the second relay is closed; When receiving the second bus output instruction, switching the first relay to convert the first bus to the second bus, and then closing the second relay; switching to the second bus output.

2. The multi-interface adaptive switching system according to claim 1, characterized in that: The first bus transceiver includes a Glb2582 transceiver, and the first communication bus includes an RS485 communication bus; the second bus transceiver includes a Glb3053 transceiver, and the second communication bus includes a CAN communication bus.

3. The multi-interface adaptive switching system according to claim 2, characterized in that: The driver comprises a CAN driver, and the CAN driver adopts a triple data buffer structure of a sending ringbuffer, a receiving ringbuffer and a user data ringbuffer.

4. The multi-interface adaptive switching system according to claim 3, characterized in that: The CAN driver comprises a CAN initialization module, a CAN communication frame sending and receiving module, and a CAN communication frame packaging and unpacking module.

5. The multi-interface adaptive switching system according to claim 4, characterized in that: The CAN initialization module is used to determine the frame format, frame type, data length of each frame, data and message identification code initialization format of the CAN communication frame, apply for the ringbuffer space for storing the received communication frame, and configure the CAN register; The CAN communication frame sending and receiving module is used to complete the configuration of the communication frame and judge the transmission buffer state before the CAN communication frame is sent, and to judge the transmission completion state before the end of the sending, so as to ensure that the communication frame has been sent; Each time the reception of a communication frame is completed, the receiving buffer is released by setting the command register to ensure the normal transmission of subsequent communication frames; The CAN communication frame packaging and unpacking module is used to decompose the data from the user into CAN communication frames, send out each frame of CAN data by calling the CAN communication frame sending interface, assemble and splice the data parts from the CAN bus communication frame, and feed back the complete data to the user.

6. The multi-interface adaptive switching system according to claim 5, characterized in that: The frame format includes an extended frame, the frame type includes a data frame, the data length of each frame includes 8 bytes, and the initialization format of the data and message identification code is 0.

7. The multi-interface adaptive switching system according to claim 2, characterized in that: The driver includes an RS485 driver, which is used to provide a baud rate and other parameter configuration interface function, a configurable receiving interrupt threshold, a timeout interrupt function, and a data receiving and sending function.

8. The multi-interface adaptive switching system according to claim 1, characterized in that: The FPGA device is configured with a number of expandable interfaces for realizing the expansion function of multiple communication buses of different types.

9. The multi-interface adaptive switching system according to claim 1, characterized in that: The CPU is further configured to receive user-triggered switching information and generate the bus switching instruction according to the switching information.

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