Data conversion circuit and computing device

Abstract

The invention discloses a data conversion circuit and computing equipment, and relates to the technical field of power consumption management. The computing device includes a plurality of memories, a data conversion circuit, and a processor. The data conversion circuit is used for obtaining the power of each memory by adopting an improved integrated circuit I3C protocol to obtain first power data; performing data conversion processing on the first power data to obtain second power data; and sending the second power data to the processor by adopting the first communication protocol. The computing equipment provided by the technical scheme of the invention can accurately read the power of each memory in the plurality of memories to obtain the first power data with relatively high precision and relatively strong anti-interference capability. Furthermore, when data conversion processing is carried out on the first power data, the data conversion processing is not easily influenced by factors such as noise and ground floating, high-precision second power data can be obtained, and the problem that the system performance is reduced due to the fact that the memory power is abnormal or lost is avoided.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of power consumption management technology, and in particular, to a data conversion circuit and a computing device. Background Art

[0002] Usually, the server can monitor the power of the memory through the central processing unit (CPU) to manage the power consumption according to the memory power and ensure the long-term stable operation of the system. Currently, for CPUs that do not support the Improved Inter Integrated Circuit (I3C) protocol, the power of the memory is mainly monitored by an external power sampling circuit.

[0003] However, due to factors such as environmental interference and ground plane floating, when monitoring the power of the memory through an external power sampling circuit, the CPU may not be able to obtain the memory power, or the obtained memory power may be inaccurate, or even anomalies may occur when obtaining the memory power, which will affect the system performance of the server. Summary of the invention

[0004] The embodiments of the present application provide a data conversion circuit and a computing device, which can effectively reduce the impact of factors such as environmental interference and ground plane floating on memory power, and ensure that the obtained memory power is relatively accurate.

[0005] The embodiment of the present application adopts the following technical solution:

[0006] In a first aspect, an embodiment of the present application provides a computing device, the computing device comprising a plurality of memories, a data conversion circuit and a processor; a first end of the data conversion circuit is coupled to each memory, and a second end of the data conversion circuit is coupled to the processor;

[0007] Data conversion circuit for:

[0008] The power of each memory is obtained by adopting the I3C protocol to obtain first power data;

[0009] Performing data conversion processing on the first power data to obtain second power data;

[0010] Sending second power data to the processor using the first communication protocol;

[0011] The first communication protocol is different from the I3C protocol.

[0012] Based on this solution, the power of each memory in multiple memories is obtained through a data conversion circuit, and the first power data can be obtained. Since the power of each memory is the digital power collected by the internal integrated circuit of the memory, it has high precision and strong anti-interference ability. Therefore, the first power data obtained has high precision and strong anti-interference ability. Furthermore, when the first power data is subjected to data conversion processing, it is not easily affected by factors such as noise and ground floating, and high-precision second power data can be obtained. The present application obtains the total power of multiple memories through a data conversion circuit, which can not only ensure that the obtained power is relatively accurate, but also avoid the problem of abnormality or loss when obtaining the total power of multiple memories, resulting in a decrease in system performance.

[0013] In a possible implementation, the data conversion circuit includes a first data converter and a power regulator; a first end of the first data converter is a first end of the data conversion circuit, a second end of the first data converter is coupled to a first end of the power regulator, and a second end of the power regulator is a second end of the data conversion circuit;

[0014] A first data converter is used to obtain the power of each memory by adopting the I3C protocol to obtain first power data; perform data conversion processing on the first power data to obtain gain data; and send the gain data to the power regulator by adopting the I2C protocol;

[0015] The power regulator is used to perform data conversion processing on the gain data to obtain second power data; and send the second power data to the processor using the first communication protocol.

[0016] Based on this solution, the power of each memory is obtained through the first data converter, and the obtained first power data is subjected to data conversion processing to obtain gain data. In this way, the first power data in the I3C protocol format can be converted into gain data in the I2C format that meets the input data format requirements of the power regulator through the first data converter, and the gain data corresponds to the power of each memory. Then, the gain data is subjected to data conversion processing by the power regulator, and the second power data in the first communication protocol format corresponding to the total power of multiple memories can be obtained. Thus, the processor can determine the total power of multiple memories based on the second power data. And when the first data converter and the power regulator are both inherent circuits or devices in the computing device, it is possible to avoid adding a power sampling circuit and save costs.

[0017] In another possible implementation, the first data converter is a baseboard management controller that supports both the I3C protocol and the I2C protocol.

[0018] Based on this solution, the first data converter can realize the mutual conversion between the data in the I3C protocol format and the data in the I2C protocol format, that is, it can ensure that the first power data is processed by data conversion to obtain the gain data.

[0019] In another possible implementation, the first data converter is specifically used to determine the total power of multiple memories based on the first power data; determine the gain coefficient based on the total power of multiple memories, the operating voltages of the multiple memories, and the equivalent voltage corresponding to the operating currents of the multiple memories; and generate gain data based on the gain coefficient.

[0020] Based on this solution, the first data converter can determine the total power of multiple memories based on the first power data, and then based on the total power of the memories, the working voltages of the multiple memories, and the equivalent voltage corresponding to the working currents of the multiple memories, it can determine the gain coefficient related to the total power of the memories, thereby ensuring that the generated gain data corresponds to the total power of the multiple memories.

[0021] In another possible implementation, the third terminal of the power regulator is coupled to the first voltage source, and the fourth terminal of the power regulator is coupled to the second voltage source; the power regulator is specifically used to determine the gain coefficient based on the gain data; and generate the second power data based on the gain coefficient, the first voltage corresponding to the first voltage source, and the second voltage corresponding to the second voltage source. The first voltage is the same as the operating voltage of the multiple memories, and the second voltage is the same as the equivalent voltage corresponding to the operating current of the multiple memories.

[0022] Based on this solution, since the first voltage is the same as the operating voltage of multiple memories, and the second voltage is the same as the equivalent voltage corresponding to the operating current of multiple memories, the power regulator can accurately determine the total power of multiple memories based on the gain coefficient, the first voltage and the second voltage in the gain data, and thus obtain second power data with higher accuracy.

[0023] In another possible implementation, the first data converter includes: a format converter and a second data converter; the first end of the format converter is the first end of the first data converter, the second end of the format converter is coupled to the first end of the second data converter; the second end of the second data converter is the second end of the first data converter;

[0024] A format converter, used for obtaining the power of each memory by adopting the I3C protocol to obtain first power data, performing data format conversion on the first power data to obtain third power data; and sending the third power data to the second data converter by adopting the I2C protocol;

[0025] The second data converter is used to perform data conversion processing on the third power data to obtain gain data; and use the I2C protocol to send the gain data to the power regulator.

[0026] Based on this solution, when the second data converter only supports the I2C protocol and cannot support both the I3C protocol and the I2C protocol, a format converter is set between the second data converter and the multiple memories. The power of each memory in the multiple memories is obtained through the format converter to obtain the first power data in the I3C protocol format, and the first power data in the I3C protocol format is converted into a data format to obtain the third power data in the I2C protocol format that can be processed by the second data converter. Thus, the gain data in the I2C protocol format can be obtained by performing data conversion processing on the third power data through the second data converter.

[0027] In yet another possible implementation, the second data converter is a baseboard management controller supporting the I2C protocol.

[0028] Based on this solution, the second data converter can process the third power data in the I2C protocol format to obtain gain data in the I2C protocol format.

[0029] In a second aspect, an embodiment of the present application further provides a data conversion circuit, the data conversion circuit comprising a first data converter and a power regulator; a first end of the first data converter is coupled to each of a plurality of memories in a computing device, a second end of the first data converter is coupled to a first end of the power regulator; a second end of the power regulator is coupled to a processor in the computing device;

[0030] A first data converter is used to obtain the power of each memory by adopting the I3C protocol to obtain first power data; perform data conversion processing on the first power data to obtain gain data, and send the gain data to the power regulator by adopting the I2C protocol;

[0031] The power regulator is used to perform data conversion processing on the gain data to obtain second power data; and use the first communication protocol to send the second power data to the processor; wherein the first communication protocol is different from the I3C protocol.

[0032] In a possible implementation, the first data converter includes a format converter and a second data converter. The first end of the format converter is the first end of the first data converter; the second end of the format converter is coupled to the first end of the second data converter; the second end of the second data converter is the second end of the first data converter;

[0033] A format converter, used for obtaining the power of each memory by adopting the I3C protocol to obtain first power data, performing data format conversion on the first power data to obtain third power data; and sending the third power data to the second data converter by adopting the I2C protocol;

[0034] The second data converter is used to perform data conversion processing on the third power data to obtain gain data.

[0035] In one possible implementation, the third terminal of the power regulator is coupled to the first voltage source, and the fourth terminal of the power regulator is coupled to the second voltage source; the power regulator is specifically used to: determine a gain coefficient based on gain data; generate second power data based on the gain coefficient, a first voltage corresponding to the first voltage source, and a second voltage corresponding to the second voltage source; wherein the first voltage is the same as the operating voltage of multiple memories, and the second voltage is the same as the equivalent voltage corresponding to the operating current of multiple memories.

[0036] In a third aspect, an embodiment of the present application further provides a chip, which includes the data conversion circuit of the second aspect mentioned above. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 is a schematic diagram of the structure of a computing device provided in an embodiment of the present application;

[0038] Figure 2 is a schematic diagram of the structure of another computing device provided in an embodiment of the present application;

[0039] Figure 3 is a structural diagram of another computing device provided in an embodiment of the present application;

[0040] Figure 4 is a structural schematic diagram of a data conversion circuit provided in an embodiment of the present application;

[0041] Figure 5 is a structural schematic diagram of another data conversion circuit provided in an embodiment of the present application;

[0042] Figure 6 It is a flowchart of a data conversion method provided in an embodiment of the present application;

[0043] Figure 7 It is a flowchart of another data conversion method provided in an embodiment of the present application;

[0044] Figure 8 It is a flowchart of another data conversion method provided in an embodiment of the present application;

[0045] Fig. 9 It is a flowchart of another data conversion method provided in an embodiment of the present application;

[0046] Fig.10 It is a flowchart of another data conversion method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0047] The technical solution in the embodiment of the present application will be described below in conjunction with the drawings in the embodiment of the present application. In order to facilitate the clear description of the technical solution in the embodiment of the present application, the first, second, etc. descriptions appearing in the embodiment of the present application are only used for illustration and distinction of the description objects, and there is no order, nor does it represent a special limitation on the number of devices in the embodiment of the present application, and cannot constitute any limitation on the embodiment of the present application.

[0048] In order to facilitate the understanding of this application, the terms involved in this application are now explained.

[0049] A computing device is an electronic device used to perform computing tasks. Computing devices may include personal computers, servers, embedded computers, and supercomputers, etc. In this application, a computing device is taken as an example for exemplary description. The server in this application may be an independent physical server, or a server cluster or distributed system consisting of multiple physical servers, or a cloud server that provides cloud services, cloud databases, cloud computing, cloud functions, cloud storage, cloud communications, middleware services, domain name services, security services, content delivery networks (Content Delivery Network, CDN), and basic cloud computing services such as large databases and artificial intelligence platforms. When the above-mentioned server is a server cluster consisting of multiple physical servers, or a distributed system, multiple physical servers can form a blockchain, and each physical server is a node on the blockchain. The physical type of the server may include a cabinet server, a rack server, a high-density server, a graphics processing unit (Graphic Processing Unit, GPU) server, a tower server, and may also be a blade server, an artificial intelligence (Artificial Intelligence, AI) server, etc. The embodiment of this application does not limit the type of server.

[0050] The baseboard management controller (Board Management Controller, BMC) is a controller in a computing device that provides management for the motherboard. As an independent processor embedded in a computing device, BMC can be used to monitor the software and hardware information, health status, and operating status of the computing device. It should be noted that BMC can also be called an integrated remote management port (Integrated Lights-Out, iLO), a remote control card (Integrated Dell Remote Access, IDRAC), hardware device management (Hardware Device Management, HDM), an integrated management module (Integrated Management Module, IMM), etc. The embodiment of the present application does not limit the name of BMC.

[0051] A voltage regulator module (VRM) is a hardware component in a computing device that converts the DC voltage provided by the power supply into a stable and adjustable voltage required by the components inside the server (especially high-performance components such as the CPU and memory). Through its internal circuit design and control mechanism, the VRM can dynamically adjust the output voltage according to the server load and processor requirements. The VRM's regulation capabilities ensure that the CPU and other high-performance components can operate under efficient and stable conditions.

[0052] The I3C protocol is a new serial communication interface standard based on a master-slave structure and is compatible with the Inter-Integrated Circuit (I2C) protocol. The I3C protocol is designed to address the limitations of the I2C bus and the Serial Peripheral Interface (SPI) in terms of low power consumption, high performance, and high integration, and is particularly suitable for the connection and communication between a variety of sensors and peripherals.

[0053] The I2C protocol is a simple, bidirectional, two-wire synchronous serial bus. The I2C protocol has the advantages of few pins, simple hardware implementation, strong scalability, and support for multiple masters.

[0054] The SVID (Serial Voltage Identification, SVID) protocol is a protocol used by the CPU to dynamically adjust the output voltage of the VRM power supply. It is mainly used in servers and personal computer systems. Through this SVID protocol, the CPU can dynamically adjust the output voltage of the VRM power supply in real time according to the current load conditions and performance requirements to achieve the purpose of optimizing system performance, reducing power consumption and extending hardware life.

[0055] The Advanced Configuration and Power Interface (ACPI) protocol is an operating system power management and hardware configuration interface that defines a hardware abstraction interface between the system firmware (BIOS or UEFI) and the operating system. It assigns power management almost entirely to BIOS control, greatly limiting the operating system's ability to control power consumption.

[0056] A computing device (e.g., a server) includes a plurality of dual-inline memory modules (DIMMs), which may also be referred to as memory sticks or memories. Each memory includes a microcontroller unit (MCU) and / or a power sampling circuit, and the digital power (a power value represented by a digital quantity) of the memory can be determined by the MCU and / or the power sampling circuit, and the digital power of the memory is stored in a power register of the memory.

[0057] Furthermore, when each memory supports the I3C protocol, if the CPU does not support the I3C protocol, the CPU cannot read the power of each memory from multiple memories, that is, the CPU cannot directly read the memory power. Therefore, for CPUs that do not support the I3C protocol, other solutions are needed to monitor the memory power.

[0058] The embodiment of the present application provides a computing device, which includes multiple memories, a processor, and a data conversion circuit coupled between the multiple memories and the processor. The data conversion circuit uses the I3C protocol to obtain the power of each memory, obtains the first power data including the power of each memory, performs data conversion processing on the first power data, obtains the second power data, and then uses the first communication protocol to send the second power data to the processor. Since the power of each memory obtained by the data conversion circuit is the digital power collected by the internal integrated circuit of the memory, it has high accuracy and strong anti-interference ability. Therefore, when the format conversion processing is performed on the obtained first power data, the influence of factors such as noise and ground floating can be effectively reduced, and high-precision second power data can be obtained, so as to avoid affecting the system performance of the server due to abnormality or loss of memory power.

[0059] Figure 1 Schematic diagram of a computing device provided in an embodiment of the present application. Figure 1 As shown, the computing device 10 includes a plurality of memories 101, a data conversion circuit 102, and a processor 103. A first end of the data conversion circuit 102 is coupled to each memory 101, and a second end of the data conversion circuit 102 is coupled to the processor 103. The data conversion circuit 102 is used to obtain the power of each memory 101 using the I3C protocol to obtain first power data; then perform data conversion processing on the first power data to obtain second power data; finally, use the first communication protocol to send the second power data to the processor 103. The first communication protocol is different from the I3C protocol.

[0060] Exemplarily, since each memory 101 in the plurality of memories 101 supports the I3C protocol, the data conversion circuit 102 also supports the I3C protocol. Therefore, the first end of the data conversion circuit 102 can be coupled to each memory 101 via the I3C bus to support the data conversion circuit 102 to obtain the power of each memory 101 using the I3C protocol.

[0061] The number of memories 101 in the multiple memories 101 can be any value greater than or equal to 1. The embodiment of the present application does not limit the number of memories 101 included in the multiple memories 101. However, due to the limitations of multiple factors such as memory capacity, number of slots, type and capacity of memory, heat dissipation, and user budget and performance requirements, the computing device 10 usually includes at most 8 memories. The embodiment of the present application takes the multiple memories 101 including 8 memories 101 as an example for illustrative description. It can be understood that Figure 1 In the figure, the multiple memories 101 including three memories 101 are taken as an example for illustrative illustration.

[0062] Each memory 101 may include an MCU and / or a power sampling circuit. The digital power of the memory 101 can be obtained through the MCU or the power sampling circuit, and the digital power of the memory 101 is stored in the power register of the memory 101. Therefore, the data conversion circuit 102 can obtain the stored digital power from the power register of each memory 101 to obtain the first power data.

[0063] Exemplarily, the data conversion circuit 102 may support both the I3C protocol and the first communication protocol. The processor 103 may support the first communication protocol. Therefore, the second end of the data conversion circuit 102 may be coupled to the processor 103 via the first communication bus.

[0064] The first communication protocol may be any other communication protocol except the I3C protocol. The first communication bus may be a bus that supports the first communication protocol. In some examples, the first communication protocol may be an SVID protocol, and the first communication bus may be an SVID bus. In other examples, the first communication protocol may be an ACPI protocol, and the first communication bus may be an ACPI bus. The embodiments of the present application do not limit the specific implementation of the first communication protocol and the first communication bus. The embodiments of the present application are exemplified by taking the first communication protocol as an SVID protocol and the first communication bus as an SVID bus.

[0065] Exemplarily, the processor 103 may be a CPU in the computing device 10 that supports the first communication protocol but does not support the I3C protocol. In some examples, the processor 103 may be a CPU in the computing device 10 that supports the SVID protocol but does not support the I3C protocol. In other examples, the processor 103 may be a CPU in the computing device 10 that supports the ACPI protocol but does not support the I3C protocol. The embodiment of the present application is exemplified by taking the processor 103 as a CPU that supports the SVID protocol but does not support the I3C protocol as an example.

[0066] The processor 103 may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof that do not support the I3C protocol in the computing device 10. The general-purpose processor may be a microprocessor or any conventional processor.

[0067] The data conversion circuit 102 may be any device or apparatus capable of implementing the above functions. In some examples, the data conversion circuit 102 may be a hardware component in the computing device 10. In other examples, the data conversion circuit 102 may be an FPGA or a programmable logic device (CPLD) chip provided in the computing device 10. The embodiment of the present application does not limit the specific implementation of the data conversion circuit 102. The embodiment of the present application takes the data conversion circuit 20 as a hardware component in the computing device 10 as an example for illustrative description. For example, the data conversion circuit 102 may be a VRM that supports both the I3C protocol and the first communication protocol.

[0068] The first power data may be power data in an I3C protocol format. In some examples, the first power data may include multiple memory power data in an I3C protocol format obtained by reading the power of each memory 101 in the multiple memories 101. In other words, the first power data may include multiple memory power data in an I3C protocol format. For example, if the multiple memories 101 include 8 memories 101, the first power data includes 8 memory power data in an I3C protocol format.

[0069] It can be understood that, in the memory power data in the I3C protocol format, the content of the data packet may include the read memory power, and the packet header and the packet tail may respectively include the first packet header and the first packet tail corresponding to the I3C protocol format.

[0070] The second power data may be power data in the format of the first communication protocol. In some examples, the first communication protocol is an SVID protocol. The second power data may be total memory power data in the SVID protocol format. In the total memory power data in the SVID protocol format, the content of the data packet may include the total power of multiple memories, and the header and the tail may respectively include a second header and a second tail corresponding to the SVID protocol format. The second header is different from the first header, and the second tail is different from the first tail.

[0071] The data conversion circuit 102 uses the I3C protocol to obtain the power of each memory and obtain the first power data, which may include: the data conversion circuit 102 uses the I3C protocol to send a power read request to each memory 101, and each memory 101 responds to the power read request, reads the digital power (memory power) stored in the power register, and converts the read memory power into memory power data in the I3C protocol format and returns it to the data conversion circuit 102.

[0072] The data conversion circuit 102 performs data conversion processing on the first power data to obtain the second power data, which may include: the data conversion circuit 102 performs preset operations and format conversion on each memory power data to obtain the second power data in the first communication protocol format, and uses the first communication protocol to send the second power data to the processor 103.

[0073] In the computing device provided by the embodiment of the present application, since the power of each memory in the multiple memories obtained by the data conversion circuit is the digital power collected by the internal integrated circuit of the memory, the accuracy is high and the anti-interference ability is strong, therefore, the accuracy of the first power data obtained is also high and the anti-interference ability is also strong. Furthermore, when the first power data is subjected to data conversion processing, it is not easily affected by factors such as noise and ground floating, and high-precision second power data can be obtained, which can not only ensure that the power of the multiple memories obtained is relatively accurate, but also avoid the problem of system performance degradation caused by abnormal or lost memory power.

[0074] In some embodiments, the data conversion circuit 102 may be a VRM that supports both the I3C protocol and the first communication protocol. If the VRM cannot support both the I3C protocol and the first communication protocol, but supports both the I2C protocol and the first communication protocol, then the data conversion circuit 102 may include a BMC that supports both the I3C protocol and the I2C protocol and a VRM that supports both the I2C protocol and the first communication protocol.

[0075] like Figure 2 As shown in the above Figure 1Based on the illustrated embodiment, the data conversion circuit 102 may include a first data converter 1021 and a power regulator 1022. The first end of the first data converter 1021 is the first end of the data conversion circuit 20 and is coupled to each memory 101 of the plurality of memories 101; the second end of the first data converter 1021 is coupled to the first end of the power regulator 1022, and the second end of the power regulator 1022 is the second end of the data conversion circuit 102 and is coupled to the processor 103.

[0076] Among them, the first data converter 1021 is used to obtain the power of each memory 101 in the multiple memories 101 using the I3C protocol to obtain first power data; perform data conversion processing on the first power data to obtain gain data; and use the I2C protocol to send the gain data to the power regulator 1022.

[0077] Exemplarily, the first data converter 1021 may be a hardware component in the computing device 10 that supports both the I2C protocol and the I3C protocol. That is, the first data converter 1021 can convert data in the I3C protocol format into data in the I2C protocol format, or convert data in the I2C protocol format into data in the I3C protocol format. In some examples, the first data converter 1021 may be a BMC that supports the I2C protocol and the I3C protocol. The embodiment of the present application is exemplified by taking the first data converter 1021 as a BMC as an example.

[0078] Exemplarily, since the first data conversion circuit 1021 and each memory 101 both support the I3C protocol, the first end of the first data converter 1021 can be coupled to each memory 101 via the I3C bus to support the first data conversion circuit 1021 to obtain power from each memory 101 using the I3C protocol.

[0079] The first data conversion circuit 1021 uses the I3C protocol to obtain the power of each memory 101, and the implementation method of obtaining the first power data is similar to the data conversion circuit 102 using the I3C protocol to obtain the power of each memory 101, and the implementation method of obtaining the first power data is similar, and the embodiments of the present application will not be repeated here.

[0080] The power regulator 1022 may be a hardware component in the computing device 10 that supports both the I2C protocol and the first communication protocol. That is, the power regulator 1022 can convert data in the I2C protocol format into data in the first communication protocol format, or convert data in the first communication protocol format into data in the I2C protocol format. In some examples, the power regulator 1022 may be a VRM that supports both the I2C protocol and the first communication protocol. The embodiment of the present application takes the power regulator 1022 as a VRM as an example for exemplary description.

[0081] In an embodiment of the present application, the first data converter 1021 is specifically used to determine the total power of multiple memories 101 based on the first power data; determine the gain coefficient based on the total power of multiple memories 101, the operating voltage of multiple memories 101 and the equivalent voltage corresponding to the operating current of multiple memories 101; and generate gain data based on the gain coefficient.

[0082] The total power of the multiple memories 101 may be the sum of the power of each memory 101 in the multiple memories 101. Exemplarily, the first data converter 1021 may include a first parsing module and an addition module. The first data converter 1021 determines the total power of the multiple memories 101 based on the first power data, which may include: the first data converter 1021 parses the power data of each memory in the first power data through the first parsing module to obtain the power of each memory 101. And the power of each memory 101 is added through the addition module to obtain the total power of the multiple memories 101.

[0083] Parsing each memory power data in the first power data through the first parsing module to obtain the power of each memory 101 may include: identifying the data packet content in each memory power data (removing the packet header and packet tail in each memory power data) through the first parsing module to obtain the power of each memory 101.

[0084] In an embodiment of the present application, the operating voltage of the multiple memories 101 may be the input voltage of the multiple memories 101, and may be recorded as Vin. The equivalent voltage corresponding to the operating current of the multiple memories 101 may be the voltage across the sampling resistor when a sampling resistor is connected in series between the working power supply corresponding to the input voltage Vin of the multiple memories 101 and the multiple memories 101, and may be recorded as Visys. In some examples, the size of Vin and Visys may be determined according to the actual hardware design of the multiple memories 101. For example, Vin may be 12V, and Visys may be 3.3V, and the embodiment of the present application does not limit the size of Vin and Visys. The embodiment of the present application is illustrative using Vin as 12V and Visys as 3.3V as an example.

[0085] Exemplarily, the first data converter 1021 may further include a first multiplication module and a division module. The first data converter 1021 determines the gain coefficient based on the total power of the multiple memories 101, the working voltages of the multiple memories 101, and the equivalent voltages corresponding to the working currents of the multiple memories 101, which may include: the first data converter 1021 calculates the product of the working voltages Vin of the multiple memories 101 and the equivalent voltages Visys corresponding to the working currents of the multiple memories 101 through the first multiplication module to obtain the voltage coefficient Vin*Visys; and then calculates the quotient of the total power of the multiple memories 101 and the voltage coefficient Vin*Visys through the division module to obtain the gain coefficient Gain. The calculation of the gain coefficient Gain can refer to the following formula (1).

[0086] Gain=Pdim / (Vin*Visys) (1);

[0087] Wherein, Pdim represents the total power of the multiple memories 101 ; Vin represents the operating voltage of the multiple memories 101 ; and Visys represents the equivalent voltage corresponding to the operating current of the multiple memories 101 .

[0088] In the embodiment of the present application, since the equivalent voltages corresponding to the working voltages of multiple memories and the working currents of multiple memories can accurately reflect the actual working conditions of multiple memories, the gain coefficient determined based on the total power of multiple memories, the working voltages of multiple memories and the equivalent voltages corresponding to the working currents of multiple memories can not only accurately reflect the actual working conditions of multiple memories, but also correspond to the total power of multiple memories.

[0089] The gain data may be data in the I2C protocol format. In the gain data in the I2C protocol format, the data packet content may include a gain coefficient, and the packet header and the packet tail may respectively include a third packet header and a third packet tail corresponding to the I2C protocol format. The third packet header may be different from the first packet header and the second packet header; the third packet tail may be different from the first packet tail and the second packet tail.

[0090] Exemplarily, the first data converter 1021 may further include a first encoding module. The first data converter 1021 generating gain data based on the gain coefficient may include: the first data converter 1021 encodes the gain coefficient through the first encoding module to obtain the gain data in the I2C protocol format.

[0091] Encoding the gain coefficient through the first encoding module to obtain the gain data in the I2C protocol format may include: using the gain coefficient as the content of the data packet through the first encoding module, and adding a third packet header and a third packet tail corresponding to the I2C protocol format to the gain coefficient to obtain the gain data in the I2C protocol format.

[0092] Exemplarily, since both the first data converter 1021 and the power regulator 1022 support the I2C protocol, the second end of the first data converter 1021 can be coupled to the first end of the power regulator 1022 via the I2C bus to support the power regulator 1022 to obtain gain data using the I2C protocol.

[0093] The power regulator 1022 is used to perform data conversion processing on the gain data to obtain second power data; and send the second power data to the processor 103 using the first communication protocol.

[0094] Exemplarily, the power regulator 1022 may further include a third terminal and a fourth terminal. The third terminal of the power regulator 1022 is coupled to the first voltage source Vcc1; the fourth terminal of the power regulator 1022 is coupled to the second voltage source Vcc2. The power regulator 1022 is specifically configured to determine a gain parameter coefficient based on the gain data, and generate second power data based on the gain parameter coefficient, a first voltage corresponding to the first voltage source, and a second voltage corresponding to the second voltage source.

[0095] For example, the power regulator 1022 may further include a second parsing module. The power regulator 2021022 determines the gain coefficient based on the gain data, which may include: the power regulator 1022 parses the gain data through the second parsing module to obtain the gain coefficient, and writes the gain coefficient into a corresponding gain register in the power regulator 1022.

[0096] The implementation method of parsing the gain data through the second parsing module to obtain the gain coefficient is similar to the implementation method of parsing the memory power data in the first power data through the first parsing module to obtain the power of each memory 101, and the embodiments of the present application will not be repeated here.

[0097] In the embodiment of the present application, based on the above formula (1), it can be known that in order to determine the total power of the multiple memories 101 based on the gain coefficient Gain, the power regulator 1022 needs to obtain the working voltage Vin of the multiple memories 101 and the equivalent voltage Visys corresponding to the working current of the multiple memories 101. Based on this and the hardware limitation of the power regulator 1022, the first voltage source Vcc1 and the second power source Vcc2 can be input to the third terminal of the power regulator 1022. The first voltage corresponding to the first voltage source Vcc1 is the same as the working voltage Vin of the multiple memories 101, and the second voltage corresponding to the second voltage source Vcc2 is the same as the equivalent voltage Visys corresponding to the working current of the multiple memories 101.

[0098] The power regulator 1022 generates second power data based on the gain coefficient, the first voltage corresponding to the first voltage source, and the second voltage corresponding to the second voltage source, which may include: the power regulator 1022 multiplies the gain coefficient, the first voltage corresponding to the first voltage source Vcc1, and the second voltage corresponding to the second voltage source Vcc2 to obtain the total power Pdim of the multiple memories 101, and encodes the total power Pdim of the multiple memories 101 to obtain the second power data in the pre-first signal protocol format.

[0099] In some examples, the power regulator 1022 may include a second multiplication module. The power regulator 1022 performs a multiplication operation on the gain coefficient, the first voltage corresponding to the first voltage source Vcc1, and the second voltage corresponding to the second voltage source Vcc2 to obtain the total power Pdim of the multiple memories 101, which may include: the power regulator 1022 calculates the product of the gain coefficient Gain, the first voltage corresponding to the first voltage source Vcc1, and the second voltage corresponding to the second voltage source Vcc2 through the second multiplication module to obtain the total power Pdim of the multiple memories 101.

[0100] Since the first voltage is the same as the operating voltage Vin of the multiple memories 101, and the second voltage is the same as the equivalent voltage Visys corresponding to the operating current of the multiple memories 101, the product of the gain coefficient Gain, the operating voltage Vin of the multiple memories 101 and the equivalent voltage Visys corresponding to the operating current of the multiple memories 101 can be determined as the total power Pdim of the multiple memories 101, and the calculation of the total power Pdim of the multiple memories 101 can refer to the following formula (2).

[0101] Pdim = Gain*Vin*Visys (2);

[0102] Exemplarily, taking the first communication protocol as the SVID protocol as an example, the power regulator 1022 may further include a second encoding module. The power regulator 1022 encodes the total power Pdim of the multiple memories 101 to obtain the second power data in the first communication protocol format, which may include: the power regulator 1022 encodes the total power Pdim of the multiple memories 101 through the second encoding module to obtain the second power data in the SVID protocol format.

[0103] The power regulator 1022 encodes the total power Pdim of the multiple memories 101 through the second encoding module to obtain the second power data in the SVID protocol format, which may include: the second encoding module uses the total power Pdim of the multiple memories 101 as the content of the data packet, and adds the second packet header and the second packet tail corresponding to the SVID protocol format to the total power Pdim of the multiple memories 101 to obtain the second power data in the SVID protocol format.

[0104] In the computing device provided by the embodiment of the present application, the power of each memory in the multiple memories is obtained through the first data converter, and the total power of the multiple memories is determined based on the obtained first power data in the I3C format, and the gain coefficient is determined based on the total power of the multiple memories, the working voltage of the multiple memories, and the equivalent voltage corresponding to the working current of the multiple memories. Therefore, based on the gain coefficient, the gain data in the I2C protocol format that meets the input data format requirements of the power regulator can be generated, and the gain data corresponds to the total power of the multiple memories. Then, the gain data is converted by the power regulator to obtain the second power data in the I2C protocol format corresponding to the total power of the multiple memories. Thus, the processor can determine the total power of the multiple memories based on the second power data. And when the first data converter and the power regulator are both inherent circuits or devices in the computing device, it is possible to avoid adding a power sampling circuit and save costs.

[0105] In some embodiments, the first data converter 1021 may be a BMC that supports both the I3C protocol and the I2C protocol. If the BMC cannot support both the I3C protocol and the I2C protocol, but supports the I2C protocol, the first data converter 1021 may include a format converter that supports both the I3C protocol and the I2C protocol and a BMC that only supports the I2C protocol.

[0106] like Figure 3 As shown in the above Figure 2 Based on the embodiment shown, the first data converter 1021 may include a format converter 301 and a second data converter 302. The first end of the format converter 301 is the first end of the first data converter 1021, and is coupled to each memory 101 of the plurality of memories 101; the second end of the format converter 301 is coupled to the first end of the second data converter 302; the second end of the second data converter 302 is the second end of the first data converter 1021, and is coupled to the first end of the power regulator 1022.

[0107] The format converter 301 is used to obtain the power of each memory 101 in the multiple memories 101 using the I3C protocol to obtain first power data, perform data format conversion on the first power data to obtain third power data; and use the I2C protocol to send the third power data to the second data converter 302.

[0108] Exemplarily, the format converter 301 may be a hardware component that supports both the I3C protocol and the I2C protocol. That is, the format converter 301 may convert data in the I3C protocol format into data in the I2C protocol format, or convert data in the I2C protocol format into data in the I3C protocol format.

[0109] Exemplarily, since the format converter 301 and multiple memories 101 support the I3C protocol, the first end of the format converter 301 can be coupled to each memory 101 via the I3C bus to support the format converter 301 to obtain power from each memory 101 via the I3C protocol.

[0110] The third power data may be power data in an I2C protocol format, and if the first power data includes a plurality of memory power data in an I3C protocol format, the third power data also includes the same number of memory power data in an I2C protocol format. It is understandable that the content (power) of the data packet in each memory power data in an I2C protocol format in the third power data is the same as the content (power) of the data packet in the corresponding memory power data in an I3C protocol format in the first power data.

[0111] The format converter 301 uses the I3C protocol to obtain the power of each memory 101 in the plurality of memories 101, and the implementation method of obtaining the first power data is the same as Figure 2 The first data converter 1021 uses the I3C protocol to obtain the power of each memory 101 in the multiple memories 101, and the implementation method of obtaining the first power data is similar, which will not be repeated in the embodiment of the present application.

[0112] Exemplarily, the format converter 301 performs data format conversion on the first power data to obtain third power data, which may include: performing data format conversion on each memory power data in the I3C protocol format in the first power data to obtain memory power data in the I2C protocol format, and determining each memory power data in the I2C protocol format as the third power data.

[0113] Performing data format conversion on each memory power data in the I3C protocol format in the first power data may include: retaining the content of the data packet in each memory power data in the I3C protocol format, converting the packet header from the first packet header to the third packet header, and converting the packet tail from the first packet tail to the third packet tail.

[0114] The second data converter 302 is used to perform data conversion processing on the third power data to obtain gain data; and send the gain data to the power regulator 1022 using the I2C protocol.

[0115] Exemplarily, the second data converter 302 may be a hardware component that only supports the I2C protocol. In some examples, the second data converter 302 may be a BMC that only supports the I2C protocol.

[0116] Since both the format converter 301 and the second data converter 302 support the I2C protocol, the second end of the format converter 301 can be coupled to the first end of the second data converter 302 via the I2C bus to support the second data converter 302 to obtain the third power data via the I2C protocol.

[0117] Similar to the implementation method in which the first data converter 1021 performs data conversion processing on the first power data to obtain gain data, the second data converter 302 performs data conversion processing on the third power data to obtain gain data, which may include: determining the total power of multiple memories 101 based on the third power data; determining a gain coefficient based on the total power of the multiple memories 101, the operating voltages of the multiple memories 101, and the equivalent voltage corresponding to the operating currents of the multiple memories 101; and generating gain data based on the gain coefficient.

[0118] The implementation method of determining the total power of the multiple memories 101 based on the third power data is similar to the implementation method of determining the total power of the multiple memories 101 based on the first power data. For details, see Figure 2 The description of the embodiment shown in the figure is omitted here.

[0119] In the computing device provided by the embodiment of the present application, when the second data converter only supports the I2C protocol and cannot support both the I3C protocol and the I2C protocol, a format converter is set between the second data converter and the multiple memories, and the power of each memory in the multiple memories is obtained through the format converter to obtain the first power data in the I3C protocol format, and the first power data in the I3C protocol format is format-converted to obtain the third power data in the I2C protocol format that can be processed by the second data converter. Thus, the gain data in the I2C protocol format can be obtained by performing data conversion processing on the third power data through the second data converter.

[0120] Based on the above embodiments, the present application also provides a data conversion circuit. Figure 4 Schematic diagram of a data conversion circuit provided by an embodiment of the present application. Figure 4 As shown, the data conversion circuit 40 includes a first data converter 401 and a power regulator 402; a first end of the first data converter 401 is coupled to each of a plurality of memories in a computing device, a second end of the first data converter 401 is coupled to a first end of the power regulator 402; a second end of the power regulator 402 is coupled to a processor in the computing device;

[0121] The first data converter 401 is used to obtain the power of each memory by using the I3C protocol to obtain first power data; perform data conversion processing on the first power data to obtain gain data, and send the gain data to the power regulator 402 by using the I2C protocol;

[0122] The power regulator 402 is used to perform data conversion processing on the gain data to obtain second power data; and send the second power data to the processor using a first communication protocol; wherein the first communication protocol is different from the I3C protocol.

[0123] In the embodiment of the present application, the first data converter 401 may correspond to Figure 2 The first data converter 1021 in the embodiment shown. The power regulator 402 may correspond to Figure 2 Power regulator 1022 in the illustrated embodiment.

[0124] like Figure 5 As shown in the above Figure 4 Based on the embodiment shown, the first data converter 401 may include a format converter 4011 and a second data converter 4012. The first end of the format converter 4011 is the first end of the first data converter 401; the second end of the format converter 4011 is coupled to the first end of the second data converter 4012; and the second end of the second data converter 4012 is the second end of the first data converter 401.

[0125] The format converter 4011 is used to obtain the power of each memory by adopting the I3C protocol to obtain the first power data, perform data format conversion on the first power data to obtain the third power data; and send the third power data to the second data converter 4012 by adopting the I2C protocol;

[0126] The second data converter 4012 is used to perform data conversion processing on the third power data to obtain gain data.

[0127] In the embodiment of the present application, the format converter 4011 may correspond to Figure 3 The format converter 301 in the illustrated embodiment. The second data converter 4012 may correspond to Figure 3 The second data converter 302 in the illustrated embodiment.

[0128] In some examples, continue to refer to Figure 4 As shown, the third terminal of the power regulator 402 is coupled to the first voltage source Vcc1, and the fourth terminal of the power regulator 402 is coupled to the second voltage source Vcc2; the power regulator 402 is specifically used to: determine the gain coefficient based on the gain data; generate the second power data based on the gain coefficient, the first voltage corresponding to the first voltage source and the second voltage corresponding to the second voltage source; wherein the first voltage is the same as the working voltage of multiple memories, and the second voltage is the same as the equivalent voltage corresponding to the working current of multiple memories.

[0129] Regarding a data conversion circuit in the above embodiment, the specific methods and corresponding beneficial effects of each circuit have been described in detail in the corresponding embodiment part of the computing device part. Please refer to the implementation method and beneficial technical effects of the above exemplary computing device part, and no further details will be given here.

[0130] Corresponding to the embodiment of the computing device 10, the present application also provides an embodiment of a data conversion method, which can be applied to the computing device 10 provided in any of the above embodiments. Figure 6 As shown, the data conversion method may include the following steps 601 to 603.

[0131] Step 601, using the I3C protocol to obtain the power of each memory in a plurality of memories, and obtain first power data.

[0132] Step 602: Perform data conversion processing on the first power data to obtain second power data.

[0133] Step 603: Send second power data to the processor using the first communication protocol.

[0134] In some embodiments, reference Figure 7 As shown in the above Figure 6 Based on the illustrated embodiment, step 602 may include the following steps 6021 and 6022 .

[0135] Step 6021, performing data conversion processing on the first power data to obtain gain data;

[0136] Step 6022: Perform data conversion processing on the gain data to obtain second power data.

[0137] In some embodiments, reference Figure 8 As shown in the above Figure 7 Based on the illustrated embodiment, step 6021 may include the following steps 801 to 803 .

[0138] Step 801: determine the total power of multiple memories based on first power data.

[0139] Step 802: determining a gain coefficient based on the total power of the multiple memories, the operating voltages of the multiple memories, and the equivalent voltages corresponding to the operating currents of the multiple memories.

[0140] Step 803: Generate gain data based on the gain coefficient.

[0141] In some embodiments, reference Fig. 9 As shown in the above Figure 7 Based on the illustrated embodiment, step 6022 may include the following steps 901 and 902 .

[0142] Step 901, determining a gain coefficient based on gain data.

[0143] Step 902: Generate second power data based on the gain coefficient, the first voltage, and the second voltage.

[0144] The first voltage is the same as the operating voltage of the multiple memories, and the second voltage is the same as the equivalent voltage corresponding to the operating current of the multiple memories.

[0145] In some embodiments, reference Fig.10 As shown in the above Figure 7 Based on the illustrated embodiment, step 6021 may include the following steps 1001 and 1002 .

[0146] Step 1001: convert the data format of the first power data to obtain third power data.

[0147] Step 1002: Perform data conversion processing on the third power data to obtain gain data.

[0148] Regarding a data conversion method in the above embodiment, the specific methods and corresponding beneficial effects of each step have been described in detail in the corresponding embodiment part of the computing device part. Please refer to the implementation method and beneficial technical effects of the above exemplary computing device part, and no further details will be given here.

[0149] In addition, an embodiment of the present application may also provide a chip, which may include the above-mentioned data conversion circuit.

[0150] The implementation methods described above are only specific implementation methods of the present application and are not intended to limit the scope of protection of the present application. Any modifications, equivalent substitutions, improvements, etc. made on the basis of the technical solution of the present application should be included in the scope of protection of the present application.

Claims

1. A computing device, characterized in that The computing device comprises a plurality of memories, a data conversion circuit and a processor; a first end of the data conversion circuit is coupled to each of the memories, and a second end of the data conversion circuit is coupled to the processor; The data conversion circuit is used for: Using an improved integrated circuit I3C protocol to obtain the power of each memory, and obtain first power data; Performing data conversion processing on the first power data to obtain second power data; The second power data is sent to the processor using a first communication protocol; wherein the first communication protocol is different from the I3C protocol.

2. The computing device according to claim 1, wherein: The data conversion circuit includes a first data converter and a power regulator; a first end of the first data converter is a first end of the data conversion circuit, a second end of the first data converter is coupled to a first end of the power regulator, and a second end of the power regulator is a second end of the data conversion circuit; The first data converter is used to obtain the power of each memory by adopting the I3C protocol to obtain the first power data; perform data conversion processing on the first power data to obtain gain data; and send the gain data to the power regulator by adopting the integrated circuit I2C protocol; The power regulator is used to perform data conversion processing on the gain data to obtain the second power data; and use the first communication protocol to send the second power data to the processor.

3. The computing device according to claim 2, characterized in that The first data converter is a baseboard management controller supporting the I3C protocol and the I2C protocol.

4. The computing device according to claim 2, wherein: The first data converter is specifically used for: Determining a total power of the plurality of memories based on the first power data; Determine a gain coefficient based on the total power of the multiple memories, the operating voltages of the multiple memories, and the equivalent voltages corresponding to the operating currents of the multiple memories; Based on the gain coefficient, the gain data is generated.

5. The computing device according to claim 2, wherein: The third terminal of the power regulator is coupled to the first voltage source, and the fourth terminal of the power regulator is coupled to the second voltage source; the power regulator is specifically used for: Based on the gain data, determining a gain coefficient; generating the second power data based on the gain coefficient, a first voltage corresponding to the first voltage source, and a second voltage corresponding to the second voltage source; The first voltage is the same as the operating voltage of the multiple memories, and the second voltage is the same as the equivalent voltage corresponding to the operating current of the multiple memories.

6. The computing device according to claim 2, wherein: The first data converter comprises: a format converter and a second data converter; the first end of the format converter is the first end of the first data converter, the second end of the format converter is coupled to the first end of the second data converter; the second end of the second data converter is the second end of the first data converter; The format converter is used to obtain the power of each memory by adopting the I3C protocol to obtain the first power data, perform data format conversion on the first power data to obtain third power data; and send the third power data to the second data converter by adopting the I2C protocol; The second data converter is used to perform data conversion processing on the third power data to obtain the gain data; and use the I2C protocol to send the gain data to the power regulator.

7. The computing device according to claim 6, characterized in that The second data converter is a baseboard management controller that supports the I2C protocol but does not support the I3C protocol.

8. A data conversion circuit, characterized in that: The data conversion circuit includes a first data converter and a power regulator; a first end of the first data converter is coupled to each memory of a plurality of memories in a computing device, a second end of the first data converter is coupled to a first end of the power regulator; a second end of the power regulator is coupled to a processor in the computing device; The first data converter is used to obtain the power of each memory by adopting the I3C protocol to obtain first power data; perform data conversion processing on the first power data to obtain gain data, and send the gain data to the power regulator by adopting the I2C protocol; The power regulator is used to perform data conversion processing on the gain data to obtain second power data; and use a first communication protocol to send the second power data to the processor; wherein the first communication protocol is different from the I3C protocol.

9. The data conversion circuit according to claim 8, characterized in that: The first data converter includes a format converter and a second data converter; the first end of the format converter is the first end of the first data converter; the second end of the format converter is coupled to the first end of the second data converter; the second end of the second data converter is the second end of the first data converter; The format converter is used to obtain the power of each memory by adopting the I3C protocol to obtain the first power data, perform data format conversion on the first power data to obtain third power data; and send the third power data to the second data converter by adopting the I2C protocol; The second data converter is used to perform data conversion processing on the third power data to obtain the gain data.

10. The data conversion circuit according to claim 8, characterized in that: The third terminal of the power regulator is coupled to the first voltage source, and the fourth terminal of the power regulator is coupled to the second voltage source; the power regulator is specifically used for: Based on the gain data, determining a gain coefficient; generating the second power data based on the gain coefficient, a first voltage corresponding to the first voltage source, and a second voltage corresponding to the second voltage source; The first voltage is the same as the operating voltage of the multiple memories, and the second voltage is the same as the equivalent voltage corresponding to the operating current of the multiple memories.

Images