Functional unit hot plug interface protection circuit based on MLVDS serial bus

Abstract

A functional unit hot plug interface protection circuit based on an MLVDS serial bus relates to the technical field of digital control, and comprises an MLVDS transceiver, a first protection unit, a first isolation chip, an IIC buffer, a second protection unit and a second isolation chip, the MLVDS transceiver is electrically connected with the first protection unit and the first isolation chip respectively, and the first isolation chip is electrically connected with the IIC buffer. The first protection unit is electrically connected with the MLVDS bus, and the first isolation chip is electrically connected with the FPGA chip of the functional unit; the IIC buffer is electrically connected with the second protection unit and the second isolation chip, the second protection unit is electrically connected with the IIC bus, and the second isolation chip is electrically connected with the FPGA chip of the functional unit; according to the circuit, in the hot plug process of the functional unit, the functional unit is protected, and communication between the functional unit and the MLVDS bus is not affected.

Description

Technical Field

[0001] The invention relates to the technical field of digital control, in particular to a functional unit hot-plug interface protection circuit based on an MLVDS serial bus. Background Art

[0002] The instrumentation and control digital platform refers to an integrated platform used in instrumentation and control systems. This platform uses digital means to improve the performance of the automation control system. On this platform, multiple functional modules or functional units can be integrated to achieve data collection, processing, control and other functions in the industrial production process. The integration method is to insert the board where the functional unit is located into the corresponding slot of the system platform;

[0003] During the use of the instrumentation and control digital platform, when a fault occurs and a functional unit needs to be replaced or a functional unit needs to be added according to functional requirements, the equipment is usually required to hot-swap the replaced or added functional unit while it is powered on, so as to avoid power outages of the equipment as much as possible; and after the functional unit is pulled out or inserted into the carrier board, it cannot cause damage to the hardware interface between itself and other functional units on the bus, and cannot interfere with the communication between the functional unit itself and other functional units on the bus. At the same time, after the functional unit is inserted, the main controller should be able to effectively identify the type of the inserted functional unit and the slot address of the functional unit, and complete the distribution of the configuration information of the inserted functional unit to ensure the stable operation of the system.

[0004] At present, connectors with long and short pins are usually used in digital instrumentation and control platforms to complete the hot-swap function. The long pin is used for the power pin, and the short pin is used for the signal line pin. When the functional unit is inserted into the backplane, the long pin is inserted into the backplane before the short pin to power the functional unit. When the backplane is unplugged, the long pin is unplugged after the short pin. The entire plug-in process maintains the stability of the voltage on the functional unit, effectively protects the hardware interface from damage, and realizes the hot-swap of the functional unit. However, this method has requirements for the selection of docking plug-ins, is not cost-effective, and is greatly affected by the randomness of the plug-in process. In particular, in the process of miniaturization and micro-miniaturization of equipment, this method is difficult to use in the actual functional unit interface protection process.

[0005] In addition, the MLVDS bus is a widely used communication technology that exchanges binary data through a multi-point differential bus. In the process of short-distance communication transmission, it has low power consumption and high communication rate. It adopts the form of differential communication, so it has excellent anti-interference characteristics and is widely used in equipment communication in the instrumentation and control digital platform. Although the MLVDS bus has great advantages in the communication rate of functional units, the traditional hot-swap processing mechanism is not very perfect. When the functional unit is unplugged or inserted, the main controller often cannot quickly identify the slot address and board type of the newly inserted functional unit, cannot protect the functional unit from being damaged by the instantaneous high-voltage shock caused by the plug-in process, and cannot avoid the inserted functional unit from affecting the existing communication on the bus.

[0006] Chinese patent (CN111949592B) discloses a hot-swap circuit device suitable for LVDS, which effectively avoids the possible risks of circuit overload and short circuit overcurrent by setting a connector circuit, a power supply static electricity and surge protection circuit, a signal static electricity and surge protection circuit, a power supply current limiting circuit, and an LVDS DC isolation and bias circuit, and realizes reliable live hot-swap of the LVDS circuit, and has the characteristics of simple circuit structure, high reliability, low power consumption, and extremely low cost;

[0007] However, since the communication rate of the MLVDS bus is faster and is somewhat different from that of the LVDS bus, the circuit device cannot achieve communication positioning for the hot plug action between the MLVDS bus and the functional unit;

[0008] Therefore, we propose a circuit structure that can protect the functional unit itself during the hot plugging process without affecting the communication between the functional unit and the MLVDS bus. Summary of the invention

[0009] In order to overcome the deficiencies in the background technology, the present invention discloses a functional unit hot-swap interface protection circuit based on an MLVDS serial bus.

[0010] In order to achieve the above-mentioned invention object, the present invention adopts the following technical scheme:

[0011] A functional unit hot-swap interface protection circuit based on an MLVDS serial bus, comprising an MLVDS transceiver, a first protection unit, a first isolation chip, an IIC buffer, a second protection unit and a second isolation chip, wherein the MLVDS transceiver is electrically connected to the first protection unit and the first isolation chip respectively, the first protection unit is electrically connected to the MLVDS bus, and the first isolation chip is electrically connected to an FPGA chip of the functional unit;

[0012] The IIC buffer is electrically connected to the second protection unit and the second isolation chip respectively, the second protection unit is electrically connected to the IIC bus, and the second isolation chip is electrically connected to the FPGA chip of the functional unit.

[0013] Preferably, the first protection unit includes a thermistor A, a thermistor B, a protection diode A, a protection diode B and a protection diode C, wherein one end of the thermistor A is electrically connected to the high signal end of the MLVDS bus, and the other end of the thermistor A is electrically connected to the protection diode A, the protection diode B and the MLVDS transceiver respectively;

[0014] One end of the thermistor B is electrically connected to the low-order signal end of the MLVDS bus, and the other end of the thermistor B is electrically connected to the protection diode B, the protection diode C and the MLVDS transceiver respectively;

[0015] And the protection diode A and the protection diode C are both grounded.

[0016] Preferably, the second protection unit comprises a thermistor C, a thermistor D, a protection diode D and a protection diode E, wherein one end of the thermistor C is electrically connected to the clock line of the IIC bus, and the other end of the thermistor C is electrically connected to the protection diode D and the IIC buffer respectively;

[0017] One end of the thermistor D is electrically connected to the data line of the IIC bus, and the other end of the thermistor D is electrically connected to the protection diode E and the IIC buffer respectively;

[0018] And the protection diode D and the protection diode E are both grounded.

[0019] Preferably, the MLVDS transceiver and the IIC buffer are both provided with a tri-state circuit.

[0020] Preferably, the FPGA chip includes a board type register, a unit slot register, a status register and a control register, wherein the board type register is used to store type information of the functional unit;

[0021] The unit slot register is used to store the slot information where the functional unit is located;

[0022] The status register is used to store various operating status information of the functional unit;

[0023] The control register is used to set the working parameters and control options of the functional unit.

[0024] Preferably, the board type register of the FPGA chip is electrically connected to a board type identification module (8), and the board type identification module is electrically connected to the IIC bus.

[0025] Preferably, the board type identification module includes resistors R81 to R88, power supply ISO_3V3 and power supply ISO_GND, wherein the first ends of resistors R81 to R84 are electrically connected to the power supply ISO_GND, and the first ends of resistors R85 to R88 are electrically connected to the power supply ISO_3V3;

[0026] The second end of the resistor R81 and the second end of the resistor R88 are both electrically connected to the Board_type0 signal;

[0027] The second end of the resistor R82 and the second end of the resistor R87 are both electrically connected to the Board_type1 signal;

[0028] The second end of the resistor R83 and the second end of the resistor R86 are both electrically connected to the Board_type2 signal;

[0029] A second end of the resistor R84 and a second end of the resistor R85 are both electrically connected to the Board_type3 signal.

[0030] Preferably, the unit slot register of the FPGA chip is electrically connected to a slot address identification module (9), and the slot address identification module is electrically connected to the IIC bus.

[0031] Preferably, the slot address identification module includes resistors R29 to R36, diodes D5 to D8, power supply ISO_3V3 and power supply ISO_GND, wherein the first ends of resistors R29 to R32 are electrically connected to power supply ISO_3V3, the first ends of resistors R33 to R36 are electrically connected to LOC_ADDR0 to LOC_ADDR4 signals respectively, and the first ends of diodes D5 to D8 are electrically connected to power supply ISO_GND;

[0032] The second ends of the resistor R32, the resistor R33 and the diode D8 are all electrically connected to the signal SEL_ID0;

[0033] The second ends of the resistor R31, the resistor R34 and the diode D7 are all electrically connected to the signal SEL_ID1;

[0034] The second ends of the resistor R30, the resistor R35 and the diode D6 are all electrically connected to the signal SEL_ID2;

[0035] The second ends of the resistor R29, the resistor R36 and the diode D5 are all electrically connected to the signal SEL_ID3.

[0036] Preferably, the diodes D5 to D8 are all of model ESDLC3V3D3B.

[0037] Due to the adoption of the above-mentioned technical solution, the present invention has the following beneficial effects:

[0038] The invention discloses a functional unit hot-swap interface protection circuit based on an MLVDS serial bus, which can effectively prevent the instantaneous high voltage generated during the hot-swap process of the functional unit from damaging the FPGA chip under the cooperation of the first and second protection units.

[0039] The MLVDS transceiver can ensure stable communication between the functional units and the MLVDS bus;

[0040] In addition, the use of the first and second isolation chips can effectively ensure that the communication circuit in the functional unit and the FPGA chip do not interfere with each other, thereby achieving electrical isolation of the communication signal;

[0041] In addition, through the cooperation of the board type identification module, the slot address identification module and the corresponding registers in the FPGA, the online board type and slot address of each slot can be obtained, and the inserted and removed functional units can be dynamically identified and managed. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 A structural schematic diagram of the present invention;

[0043] Figure 2 It is a schematic diagram of the connection structure between the functional unit and the main control unit;

[0044] Figure 3 It is a circuit diagram of the board type identification module;

[0045] Figure 4 This is a circuit diagram of the slot address identification module.

[0046] In the figure: 1. MLVDS transceiver; 2. first protection unit; 21. thermistor A; 22. thermistor B; 23. protection diode A; 24. protection diode B; 25. protection diode C; 3. first isolation chip; 4. IIC buffer; 5. second protection unit; 51. thermistor C; 52. thermistor D; 53. protection diode D; 54. protection diode E; 6. second isolation chip; 7. FPGA chip; 8. board type identification module; 9. slot address identification module. DETAILED DESCRIPTION

[0047] The technical solution of the present invention will be described below in conjunction with the drawings in the embodiments of the present invention. In the description, it should be understood that if there are terms such as "upper", "lower", "front", "back", "left", "right" and the like indicating directions or positional relationships, they are only corresponding to the drawings of the present invention, for the convenience of describing the present invention, and do not indicate or imply that the devices or components referred to must have a specific direction:

[0048] Embodiment 1 is:

[0049] Combined with Figure 1-2 The functional unit hot-swap interface protection circuit based on the MLVDS serial bus comprises an MLVDS transceiver 1, a first protection unit 2, a first isolation chip 3, an IIC buffer 4, a second protection unit 5 and a second isolation chip 6, wherein the MLVDS transceiver 1 is electrically connected to the first protection unit 2 and the first isolation chip 3 respectively, the first protection unit 2 is electrically connected to the MLVDS bus, and the first isolation chip 3 is electrically connected to the FPGA chip 7 of the functional unit;

[0050] The IIC buffer 4 is electrically connected to the second protection unit 5 and the second isolation chip 6 respectively, the second protection unit 5 is electrically connected to the IIC bus, and the second isolation chip 6 is electrically connected to the FPGA chip 7 of the functional unit;

[0051] Among them, the hot-swap process of the functional unit is the process of inserting the board where the functional unit is located into any slot on the system. Multiple slots in the system are respectively connected to the MLVDS bus, the IIC bus and the power management unit; after the board where the functional unit is located is inserted into the slot, the first protection unit 2 and the second protection unit 5 can initially block the current and voltage directly flowing to the functional unit, thereby preventing the voltage fluctuation from the slot input to the functional unit board from being large, causing damage to the components in the functional unit, and playing a protective role for the functional unit;

[0052] In addition, the FPGA chip 7 is responsible for processing the communication signals received by the functional unit from the MLVDS bus and the IIC bus. Therefore, the use of the first and second isolation chips 6 can effectively ensure that the communication circuit in the functional unit and the FPGA chip 7 do not interfere with each other, thereby realizing the electrical isolation of the communication signal. The communication circuit is composed of the MLVDS transceiver 1 and the IIC buffer 4.

[0053] In particular, the MLVDS transceiver 1 and the IIC buffer 4 are both provided with a tri-state circuit, which can effectively ensure that the functional unit card will not interfere with other functional units that are communicating with the MLVDS bus or the IIC bus during the insertion and removal process.

[0054] Embodiment 2 is:

[0055] Based on Example 1, the first protection unit 2 and the second protection unit 5 are further defined, the first protection unit 2 includes a thermistor A21, a thermistor B22, a protection diode A23, a protection diode B24 and a protection diode C25, wherein one end of the thermistor A21 is electrically connected to the high signal end of the MLVDS bus, and the other end of the thermistor A21 is electrically connected to the protection diode A23, the protection diode B24 and the MLVDS transceiver 1 respectively;

[0056] One end of the thermistor B22 is electrically connected to the low-order signal end of the MLVDS bus, and the other end of the thermistor B22 is electrically connected to the protection diode B24, the protection diode C25 and the MLVDS transceiver 1 respectively;

[0057] And the protection diode A23 and the protection diode C25 are both grounded.

[0058] In addition, the second protection unit 5 includes a thermistor C51, a thermistor D52, a protection diode D53 and a protection diode E54, wherein one end of the thermistor C51 is electrically connected to the clock line of the IIC bus, and the other end of the thermistor C51 is electrically connected to the protection diode D53 and the IIC buffer 4 respectively;

[0059] One end of the thermistor D52 is electrically connected to the data line of the IIC bus, and the other end of the thermistor D52 is electrically connected to the protection diode E54 and the IIC buffer 4 respectively;

[0060] And the protection diode D53 and the protection diode E54 are both grounded.

[0061] The thermistors of the two protection units are PCT thermistors, which means positive temperature coefficient thermistors. The characteristic of this type of thermistor is that the resistance value increases when the temperature rises; therefore, in the circuit, PTC thermistors help protect the circuit from the impact of instantaneous high voltage and current peaks that may occur during the plug-in and unplug process. When the board is inserted or unplugged, a momentary large current or voltage spike may be generated. The PTC thermistor can help discharge this energy and protect the corresponding MLVDS transceiver 1 and IIC buffer 4 from damage. This protection mechanism is crucial to ensure the stability and safety of the system during the hot plug-in process of the board;

[0062] The protection diodes in the first protection unit 2 and the second protection unit 5 are TVS diodes, which are used to protect the circuit from ESD and other transient voltage events. The working principle of the TVS diode is to use the avalanche breakdown effect. When the input voltage exceeds a predetermined threshold, the TVS diode quickly changes to a low impedance state, thereby transferring the overvoltage energy to the ground, protecting the subsequent circuit from damage.

[0063] When an ESD event occurs, each protection diode can respond quickly, clamping the excessive voltage to a safe level, preventing the ESD current from flowing through the MLVDS transceiver 1, thereby protecting the transceiver 1 from damage by the ESD event; in addition, in addition to ESD, the TVS diode can also protect the circuit from other transient voltage events, such as lightning strikes, voltage fluctuations during switching of the switching power supply, etc.; and, when the input voltage exceeds the normal range, the TVS diode can limit the voltage to a safe range, ensuring that the MLVDS transceiver 1 will not be subjected to excessive voltage shocks; and under normal working conditions, the leakage current of the TVS diode is very small and hardly affects the normal operation of the MLVDS transceiver 1.

[0064] It should be noted that the response time of TVS diodes is usually in the nanosecond level, which can respond to transient voltage events in a timely manner, and most TVS diodes are bidirectional and can protect against transient voltage events in both positive and negative directions.

[0065] Embodiment 3 is:

[0066] On the basis of Embodiment 1, the FPGA chip 7 is further limited to include a board type register, a unit slot register, a status register, and a control register, which can be programmed and configured to adapt to different application scenarios and functional requirements;

[0067] The board type register is used to store the type information of the functional unit;

[0068] The unit slot register is used to store the slot information where the functional unit is located;

[0069] The status register is used to store various operating status information of the functional unit, such as error status, working mode, etc., so that the main control unit in the system can monitor and manage each functional unit;

[0070] The control register is used to set the working parameters and control options of the functional unit, such as communication rate, power management, etc., allowing the behavior of adjusting the parameters of the functional unit like the main control;

[0071] These registers are interconnected through the logic inside the FPGA to form a transmission path for data and control signals. They are connected to external devices, such as the MLVDS communication interface unit and the slot address recognition unit, to receive and send data. They are also connected to other logic blocks inside the FPGA, such as the state machine and decoder, to work together to complete the system functions. By programming and configuring the FPGA, the functions and connection relationships of these registers can be flexibly defined and changed to meet different application requirements.

[0072] Embodiment 4 is:

[0073] Based on Example 3, combined with the attached Figure 3-4 , the board type identification module 8 and the slot address identification module 9 are further defined, wherein the board type register of the FPGA chip 7 is electrically connected to the board type identification module 8, and the board type identification module 8 is electrically connected to the IIC bus. When the board where the functional unit is located is inserted into the slot, the board type identification module 8 is connected to the slot through the IO pin used to identify the board type, and outputs the corresponding board type information to the FPGA, and then the FPGA chip 7 analyzes the board type information, obtains the specific board type and sends it to the register for storage, and finally the FPGA chip 7 outputs the board type information in the register from the IIC bus to the main control unit.

[0074] In addition, the board type identification module 8 includes resistors R81 to R88, a power supply ISO_3V3 and a power supply ISO_GND, wherein the first ends of the resistors R81 to R84 are electrically connected to the power supply ISO_GND, and the first ends of the resistors R85 to R88 are electrically connected to the power supply ISO_3V3;

[0075] The second end of the resistor R81 and the second end of the resistor R88 are both electrically connected to the Board_type0 signal;

[0076] The second end of the resistor R82 and the second end of the resistor R87 are both electrically connected to the Board_type1 signal;

[0077] The second end of the resistor R83 and the second end of the resistor R86 are both electrically connected to the Board_type2 signal;

[0078] The second end of the resistor R84 and the second end of the resistor R85 are both electrically connected to the Board_type3 signal;

[0079] Power supply ISO_3V3 and power supply ISO_GND are the power supply end and ground end of the isolated power supply, and are the power supply signals output from the system to the second protection circuit after the board where the functional unit is located is inserted into the slot;

[0080] After the isolated power supply signal is output to the resistor network composed of resistors R81 to R88, the connection status between the resistor networks will change, thereby generating different Board_type signal combinations. These signals are sent to the FPGA for analysis to determine the board type of the functional unit. The determined board type is sent to the board type register for storage;

[0081] It should be noted that resistors R81 to R88 are organized into a resistor network in the form of a two-row and four-column matrix. The specific steps of the resistor network are:

[0082] When the functional unit is not inserted, all Board_type signals are connected to ISO_3V3 and are high level.

[0083] When a functional unit is inserted, some resistors will be disconnected, so that the corresponding Board_type signal is connected to ISO_GND, showing a low level.

[0084] Based on the position of the disconnected resistor, the type of functional unit can be determined. For example, if Board_type0 and Board_type1 are pulled low, the board type is 0b0010.

[0085] By reading these Board_type signals, the main controller can know the type of the currently inserted board.

[0086] As needed, the unit slot register of the FPGA chip 7 is electrically connected to a slot address identification module 9, and the slot address identification module 9 is electrically connected to the IIC bus. After the board where the functional unit is located is inserted into the corresponding slot, the address identification module is plugged into the corresponding slot through the IO pin used to identify the slot information, and obtains the slot signal. The FPGA chip 7 analyzes the slot information according to the slot signal, and then stores it in the slot address register. Finally, the FPGA chip 7 outputs the slot information in the register from the IIC bus to the main control unit.

[0087] In addition, the slot address identification module 9 includes resistors R29-R36, diodes D5-D8, power supply ISO_3V3 and power supply ISO_GND, wherein the first ends of resistors R29-R32 are electrically connected to the power supply ISO_3V3, the first ends of resistors R33-R36 are electrically connected to LOC_ADDR0-LOC_ADDR4 signals respectively, and the first ends of diodes D5-D8 are electrically connected to the power supply ISO_GND;

[0088] The second ends of the resistor R32, the resistor R33 and the diode D8 are all electrically connected to the signal SEL_ID0;

[0089] The second ends of the resistor R31, the resistor R34 and the diode D7 are all electrically connected to the signal SEL_ID1;

[0090] The second ends of the resistor R30, the resistor R35 and the diode D6 are all electrically connected to the signal SEL_ID2;

[0091] The second ends of the resistor R29, the resistor R36 and the diode D5 are all electrically connected to the signal SEL_ID3.

[0092] Particularly, the diodes D5 to D8 are all of the ESDLC3V3D3B type.

[0093] As a specific example, the system's main control unit periodically sends query instructions through the IIC bus, which can effectively identify the type and slot address of the board currently inserted into the slot, so that the main control unit can dynamically manage the hot plugging of functional units in the system, and then correctly perform board initialization configuration and periodic data access.

[0094] The parts of the present invention that are not described in detail are prior art. It is obvious to those skilled in the art that the present invention is not limited to the details of the above-mentioned exemplary embodiments, and the present invention can be implemented in other specific forms without departing from the spirit or basic characteristics of the present invention; therefore, no matter from which point of view, the embodiments should be regarded as exemplary and non-restrictive. The scope of the present invention is limited by the appended claims rather than the above description. Therefore, it is intended to include all changes within the meaning and scope of the equivalent elements of the claims in the present invention, and any figure marks in the claims should not be regarded as limiting the claims involved.

Claims

1. A functional unit hot-swap interface protection circuit based on MLVDS serial bus, characterized in that: The invention comprises an MLVDS transceiver (1), a first protection unit (2), a first isolation chip (3), an IIC buffer (4), a second protection unit (5) and a second isolation chip (6), wherein the MLVDS transceiver (1) is electrically connected to the first protection unit (2) and the first isolation chip (3), respectively, the first protection unit (2) is electrically connected to the MLVDS bus, and the first isolation chip (3) is electrically connected to the FPGA chip (7) of the functional unit; The IIC buffer (4) is electrically connected to the second protection unit (5) and the second isolation chip (6) respectively; the second protection unit (5) is electrically connected to the IIC bus; and the second isolation chip (6) is electrically connected to the FPGA chip (7) of the functional unit.

2. The functional unit hot-swap interface protection circuit based on the MLVDS serial bus as claimed in claim 1, characterized in that: The first protection unit (2) comprises a thermistor A (21), a thermistor B (22), a protection diode A (23), a protection diode B (24) and a protection diode C (25), wherein one end of the thermistor A (21) is electrically connected to the high-order signal end of the MLVDS bus, and the other end of the thermistor A (21) is electrically connected to the protection diode A (23), the protection diode B (24) and the MLVDS transceiver (1) respectively; One end of the thermistor B (22) is electrically connected to the low-order signal end of the MLVDS bus, and the other end of the thermistor B (22) is electrically connected to the protection diode B (24), the protection diode C (25) and the MLVDS transceiver (1) respectively; And the protection diode A (23) and the protection diode C (25) are both grounded.

3. The functional unit hot-swap interface protection circuit based on the MLVDS serial bus as claimed in claim 1, characterized in that: The second protection unit (5) comprises a thermistor C (51), a thermistor D (52), a protection diode D (53) and a protection diode E (54), wherein one end of the thermistor C (51) is electrically connected to a clock line of the IIC bus, and the other end of the thermistor C (51) is electrically connected to the protection diode D (53) and the IIC buffer (4) respectively; One end of the thermistor D (52) is electrically connected to the data line of the IIC bus, and the other end of the thermistor D (52) is electrically connected to the protection diode E (54) and the IIC buffer (4) respectively; And the protection diode D (53) and the protection diode E (54) are both grounded.

4. The functional unit hot-swap interface protection circuit based on the MLVDS serial bus as claimed in claim 1, characterized in that: The MLVDS transceiver (1) and the IIC buffer (4) are both provided with a tri-state circuit.

5. The functional unit hot-swap interface protection circuit based on the MLVDS serial bus as claimed in claim 1, characterized in that: The FPGA chip (7) comprises a board type register, a unit slot register, a status register and a control register, wherein the board type register is used to store type information of the functional unit; The unit slot register is used to store the slot information where the functional unit is located; The status register is used to store various operating status information of the functional unit; The control register is used to set the working parameters and control options of the functional unit.

6. The functional unit hot-swap interface protection circuit based on the MLVDS serial bus as claimed in claim 5, characterized in that: The board type register of the FPGA chip (7) is electrically connected to a board type identification module (8), and the board type identification module (8) is electrically connected to the IIC bus.

7. The functional unit hot-swap interface protection circuit based on the MLVDS serial bus as claimed in claim 6, characterized in that: The board type identification module (8) comprises resistors R81-R88, a power supply ISO_3V3 and a power supply ISO_GND, wherein the first ends of the resistors R81-R84 are electrically connected to the power supply ISO_GND, and the first ends of the resistors R85-R88 are electrically connected to the power supply ISO_3V3; The second end of the resistor R81 and the second end of the resistor R88 are both electrically connected to the Board_type0 signal; The second end of the resistor R82 and the second end of the resistor R87 are both electrically connected to the Board_type1 signal; The second end of the resistor R83 and the second end of the resistor R86 are both electrically connected to the Board_type2 signal; A second end of the resistor R84 and a second end of the resistor R85 are both electrically connected to the Board_type3 signal.

8. The functional unit hot-swap interface protection circuit based on the MLVDS serial bus as claimed in claim 5, characterized in that: The unit slot register of the FPGA chip (7) is electrically connected to a slot address recognition module (9), and the slot address recognition module (9) is electrically connected to the IIC bus.

9. The functional unit hot-swap interface protection circuit based on the MLVDS serial bus as claimed in claim 8, characterized in that: The slot address identification module (9) comprises resistors R29-R36, diodes D5-D8, a power supply ISO_3V3 and a power supply ISO_GND, wherein the first ends of the resistors R29-R32 are electrically connected to the power supply ISO_3V3, the first ends of the resistors R33-R36 are electrically connected to the LOC_ADDR0-LOC_ADDR4 signals respectively, and the first ends of the diodes D5-D8 are electrically connected to the power supply ISO_GND; The second ends of the resistor R32, the resistor R33 and the diode D8 are all electrically connected to the signal SEL_ID0; The second ends of the resistor R31, the resistor R34 and the diode D7 are all electrically connected to the signal SEL_ID1; The second ends of the resistor R30, the resistor R35 and the diode D6 are all electrically connected to the signal SEL_ID2; The second ends of the resistor R29, the resistor R36 and the diode D5 are all electrically connected to the signal SEL_ID3.

10. The MLVDS serial bus-based functional unit hot-swap interface protection circuit according to claim 9, characterized in that: The diodes D5 to D8 are all of type ESDLC3V3D3B.

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