SPI communication system and SPI communication method
Through the SPI communication system, the SPI device drives the clock signal and data signal, and the problem of delay reading data and delay changes are solved, and higher SPI communication rates and the accuracy of data transmission are achieved.
Patent Information
- Application Number
- CN202411396783.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-08
- Publication Date
- 2025-01-28
AI Technical Summary
The existing SPI communication system has large delays and delay changes in the data reading stage, which causes the main SPI device to adjust the sampling points of the readback data to ensure accurate sampling, which in turn affects the data accuracy and communication rate.
By receiving the instruction clock signal and instruction data signal sent by the main SPI device from the SPI device during the instruction period, and sending the read clock signal and reading data signal to the main SPI device during the read data period, the main SPI device is based The read clock signal sent by the SPI device receives the data signal.
Because the read clock signal is driven by SPI device, the read clock signal and data signal can maintain a good fixed timing relationship at the/main SPI device side. Communication rate and accuracy of data transmission.
Smart Images
Figure CN119377156A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of communication technology, and in particular to an SPI communication system and an SPI communication method. Background Art
[0002] At present, in the communication between SPI (Serial Peripheral Interface) devices, in the master SPI device data reading stage, the master SPI sends a clock signal CLK, the slave SPI receives the clock signal CLK sent by the master, and then sends the read data to the data signal line according to the clock signal CLK beat, and the master SPI receives the read data returned by the slave SPI. During this period, a large delay will be generated. Due to the existence of these delays, originally at the slave SPI device end, the clock signal CLK and the data signal Dx timing are good (the CLK rising edge is at the center point of each group of bits Dx, where each group of bits may be 1bit, 2bit, 4bit, etc.), at the master SPI device end, the clock signal CLK and the data signal Dx timing have a great change relative to the signal at the sending end, resulting in the problem of large read data delay and delay variation, resulting in the SPI master device needing to adjust the sampling point of the readback data to ensure accurate sampling of the readback data and ensure data correctness. Summary of the invention
[0003] According to one aspect of the present disclosure, there is provided an SPI communication system, the SPI communication system comprising a master SPI device and a slave SPI device, wherein:
[0004] The slave SPI device is used to: receive the instruction clock signal and instruction data signal sent by the master SPI device in the instruction period to receive the read instruction; send the read clock signal and the read data signal to the master SPI device in the read data period;
[0005] The master SPI device is used to: send an instruction clock signal and a read instruction data signal to the slave SPI device in an instruction period; and receive the read data signal sent by the slave SPI device according to the read clock signal sent by the slave SPI device in a read data period.
[0006] In a possible implementation manner, the master SPI device is used to: send an instruction clock signal and a write instruction data signal to the slave SPI device during an instruction period; send a write clock signal and a write data signal to the slave SPI device during a write data period;
[0007] In a possible implementation, the slave SPI device is used to: receive an instruction clock signal and an instruction data signal sent by the master SPI device during an instruction period to receive a write instruction; and receive a write clock signal and a write data signal sent by the master SPI device during a write data period to receive write data.
[0008] In a possible implementation manner, a rising edge of the instruction clock signal corresponds to a middle position of the first instruction data signal, and a falling edge of the instruction clock signal corresponds to a middle position of the second instruction data signal, and the cycle repeats, wherein the second instruction data signal is a next instruction data signal adjacent to the first instruction data signal;
[0009] In a possible implementation manner, a rising edge of the write clock signal corresponds to a middle position of the first write data signal, and a falling edge of the write clock signal corresponds to a middle position of the second write data signal, and the cycle repeats, wherein the second write data signal is a next write data signal adjacent to the first write data signal;
[0010] In one possible implementation, the rising edge of the read clock signal corresponds to the middle position of the first read data signal, and the falling edge of the read clock signal corresponds to the middle position of the second read data signal, and so on, wherein the second read data signal is the next read data signal adjacent to the first read data signal.
[0011] In a possible implementation manner, the SPI transmitting end in the master SPI device and the slave SPI device is used for:
[0012] Set the clock period of the clock signal to 2T. Send the first data signal and the second data signal continuously in each clock period. T is a positive value. In each clock period:
[0013] At the beginning of the clock cycle, the first data signal is sent;
[0014] After T / 2, the rising edge of the clock signal is sent;
[0015] After T / 2, the second data signal is sent;
[0016] After T / 2, the falling edge of the clock signal is sent;
[0017] After T / 2, the next clock cycle begins.
[0018] In a possible implementation manner, the master SPI device and the slave SPI device are both chips.
[0019] According to another aspect of the embodiment of the present disclosure, the embodiment of the present disclosure further provides an SPI communication method, which is applied to an SPI communication system including a master SPI device and a slave SPI device, wherein the method comprises: using the slave SPI device to receive an instruction clock signal and an instruction data signal sent by the master SPI device in an instruction period to receive a read instruction; sending a read clock signal and a read data signal to the master SPI device in a read data period;
[0020] The master SPI device is used to send an instruction clock signal and a read instruction data signal to the slave SPI device during an instruction period; and a read data signal sent by the slave SPI device is received according to the read clock signal sent by the slave SPI device during a read data period.
[0021] In a possible implementation, the method further includes:
[0022] The master SPI device is used to send a command clock signal and a write command data signal to the slave SPI device during the command period; and send a write clock signal and a write data signal to the slave SPI device during the write data period;
[0023] The slave SPI device is used to receive the instruction clock signal and instruction data signal sent by the master SPI device in the instruction period to receive the write instruction; and to receive the write clock signal and write data signal sent by the master SPI device in the write data period to receive the write data.
[0024] In a possible implementation manner, a rising edge of the instruction clock signal corresponds to a middle position of the first instruction data signal, and a falling edge of the instruction clock signal corresponds to a middle position of the second instruction data signal, and the cycle repeats, wherein the second instruction data signal is a next instruction data signal adjacent to the first instruction data signal;
[0025] In a possible implementation manner, a rising edge of the write clock signal corresponds to a middle position of the first write data signal, and a falling edge of the write clock signal corresponds to a middle position of the second write data signal, and the cycle repeats, wherein the second write data signal is a next write data signal adjacent to the first write data signal;
[0026] In one possible implementation, the rising edge of the read clock signal corresponds to the middle position of the first read data signal, and the falling edge of the read clock signal corresponds to the middle position of the second read data signal, and so on, wherein the second read data signal is the next read data signal adjacent to the first read data signal.
[0027] In a possible implementation, the method further includes:
[0028] The following steps are performed using the SPI transmitter in the master SPI device and the slave SPI device:
[0029] Set the clock period of the clock signal to 2T. Send the first data signal and the second data signal continuously in each clock period. T is a positive value. In each clock period:
[0030] At the beginning of the clock cycle, the first data signal is sent;
[0031] After T / 2, the rising edge of the clock signal is sent;
[0032] After T / 2, the second data signal is sent;
[0033] After T / 2, the falling edge of the clock signal is sent;
[0034] After T / 2, the next clock cycle begins.
[0035] In a possible implementation manner, the master SPI device and the slave SPI device are both chips.
[0036] According to one aspect of the present disclosure, an electronic device is provided, comprising: a processor; and a memory for storing processor-executable instructions; wherein the processor is configured to call the instructions stored in the memory to execute the above method.
[0037] According to one aspect of the present disclosure, a computer-readable storage medium is provided, on which computer program instructions are stored, and the computer program instructions implement the above method when executed by a processor.
[0038] When receiving a read instruction from the master SPI device, the slave SPI device of the embodiment of the present disclosure sends a read clock signal and a read data signal, so that the master SPI device receives the read data signal according to the read clock signal. Since the read clock signal is driven by the slave SPI device, the read clock signal and the data signal can maintain a good fixed timing relationship at both the slave / master SPI device ends. The master SPI device uses the clock signal sent by the slave SPI device to easily and accurately sample the read data signal sent by the slave SPI device, thereby facilitating the improvement of the SPI communication rate.
[0039] It should be understood that the above general description and the following detailed description are exemplary and explanatory only and do not limit the present disclosure. Other features and aspects of the present disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0040] The drawings herein are incorporated into the specification and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and are used to illustrate the technical solutions of the present disclosure together with the specification.
[0041] Figure 1 A block diagram of an SPI communication system according to an embodiment of the present disclosure is shown.
[0042] Figure 2a A timing diagram of a master SPI device write operation according to an embodiment of the present disclosure is shown.
[0043] Figure 2b A timing diagram of a master SPI device read operation in the related art is shown.
[0044] Figure 3 A timing diagram of a master SPI device read operation according to an embodiment of the present disclosure is shown.
[0045] Figure 4 A schematic diagram of single data rate (SDR) SPI communication using SPI mode 0 as an example in the related art is shown.
[0046] Figure 5 A schematic diagram of SPI communication according to an embodiment of the present disclosure is shown.
[0047] Figure 6 A flow chart of an SPI communication method according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION
[0048] Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.
[0049] In the description of the present disclosure, it should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.
[0050] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present disclosure, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.
[0051] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.
[0052] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.
[0053] The term "and / or" herein is only a description of the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the term "at least one" herein represents any combination of at least two of any one or more of a plurality of. For example, including at least one of A, B, and C can represent including any one or more elements selected from the set consisting of A, B, and C.
[0054] In addition, in order to better illustrate the present disclosure, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present disclosure can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present disclosure.
[0055] See also Figure 1 , Figure 1 A block diagram of an SPI communication system according to an embodiment of the present disclosure is shown.
[0056] like Figure 1 As shown, the SPI communication system includes a master SPI device 10 and a slave SPI device 20, wherein:
[0057] The slave SPI device 20 is used to: receive the instruction clock signal and instruction data signal sent by the master SPI device 10 in the instruction period to receive the read instruction; send the read clock signal and the read data signal to the master SPI device 10 in the read data period;
[0058] The master SPI device 10 is used to: send an instruction clock signal and a read instruction data signal to the slave SPI device 20 during an instruction period; and receive the read data signal sent by the slave SPI device 20 according to the read clock signal sent by the slave SPI device 20 during a read data period.
[0059] The slave SPI device 20 of the embodiment of the present disclosure receives the instruction clock signal and the instruction data signal sent by the master SPI device 10 in the instruction period to receive the read instruction; sends the read clock signal and the read data signal to the master SPI device 10 in the read data period; the master SPI device receives the read data signal sent by the slave SPI device according to the read clock signal sent by the slave SPI device in the read data period. Since the read clock signal is driven by the slave SPI device 20, the read clock signal and the data signal can maintain a good fixed timing relationship at the slave / master SPI device end. The master SPI device 10 uses the clock signal sent by the slave SPI device 20 to easily and accurately sample the read data signal sent by the slave SPI device 20, which is convenient for improving the SPI communication rate, and the master SPI device 10 can improve the accuracy of the read data when receiving the read data signal.
[0060] The instruction period of the embodiment of the present disclosure may refer to the period when the master SPI device 10 sends an instruction clock signal and an instruction data signal, and the read data period may refer to the period when the slave SPI device 20 sends a read clock signal and a read data signal to the master SPI device 10. Correspondingly, it also includes a write data period when the master SPI device 10 sends a write clock signal and a write data signal to the slave SPI device 20. For the specific setting of the parameters of the write data period, the instruction period, and the read data period, those skilled in the art can set them according to actual conditions and needs, and the embodiment of the present disclosure is not limited to this.
[0061] In a possible implementation, the master SPI device 10 and the slave SPI device 20 can both be terminal devices or chips, and the terminal device implements corresponding functions by, for example, calling computer-readable instructions stored in a memory by a processing component. In one example, the chip or processing component includes, but is not limited to, a separate processor, or a discrete component, or a combination of a processor and a discrete component. The processor may include a controller having an execution instruction function in an electronic device, and the processor may be implemented in any appropriate manner, for example, by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components. Inside the processor, the executable instructions may be executed by hardware circuits such as logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers.
[0062] Exemplarily, the terminal device may be a user equipment (UE), a mobile device, a user terminal, a terminal, a handheld device, a computing device or a vehicle-mounted device, etc. Exemplarily, some examples of terminals are: a mobile phone, a tablet computer, a laptop computer, a PDA, a mobile Internet device (MID), a wearable device, a virtual reality (VR) device, an augmented reality (AR) device, a wireless terminal in industrial control (Industrial Control), a wireless terminal in self-driving, a wireless terminal in remote medical surgery, a wireless terminal in smart grid (Smart Grid), a wireless terminal in transportation safety (Transportation Safety), a wireless terminal in smart city (Smart City), a wireless terminal in smart home (Smart Home), a wireless terminal in Internet of Vehicles, etc. For example, the server may be a local server or a cloud server.
[0063] Exemplarily, SPI communication usually includes a chip select signal line (CS), a clock signal line (CLK), and several data signal lines (Dx). In order to speed up data transmission, the data signal lines are usually 2 (DUAL) or 4 (QUAD), or more. In order to distinguish between read / write, an operation can be divided into a command phase (Command Phase) in the first half and a data phase (DATA Phase) in the second half. In the related art, the command phase is when the master SPI device 10 sends a command (including (read / write) command, address, length and other information) to the slave SPI device 20. In the write data phase, the master SPI device 10 sends write data, and the slave SPI device 20 receives write data. All data signal lines are driven by the master SPI device 10 and never driven. In the read data phase, the slave SPI device 20 sends read data, and the master SPI device 10 receives read data, and all data lines are driven by the slave SPI device 20.
[0064] Table 1 shows the signal driving description of the write operation in the related art.
[0065] Table 1
[0066]
[0067] From Table 1, we can see that:
[0068] The master SPI device 10 drives the chip select signal line to send a chip select signal CS, and the slave SPI device 20 receives the chip select signal CS.
[0069] The master SPI device 10 drives the clock signal line to send the clock signal CLK, and the slave SPI device 20 receives the clock signal CLK.
[0070] Write instruction period: the master SPI device 10 drives the data signal line Dx to send a write instruction, and the slave SPI device 20 samples the data signal line Dx to receive the write instruction.
[0071] Data writing period: the master SPI device 10 drives the data signal line Dx to send write data, and the slave SPI device 20 samples the data signal line Dx to receive write data.
[0072] See also Figure 2a , Figure 2a FIG. 1 is a timing diagram of a write operation of the master SPI device 10 according to an embodiment of the present disclosure.
[0073] Depend on Figure 2a It can be seen that in the write operation, whether it is the write instruction period or the write data period, the data signal Dx is sent by the master and received by the slave (sent by the master SPI device 10 and received by the slave SPI device 20), the clock signal CLK delay (Delay1) and the data signal Dx delay (Delay2) are the same, and the timing relationship between the clock signal CLK and the data signal Dx is consistent in the master SPI device 10 / slave SPI device 20. For example Figure 2a The rising edge of the clock signal CLK is located exactly in the middle of each segment of the data signal Dx, which is convenient for the receiving end to receive data and also convenient for increasing the SPI communication rate.
[0074] Table 2 shows the signal driving description of the read operation in the related art.
[0075] Table 2
[0076]
[0077] From Table 2, we can see that:
[0078] The master SPI device 10 drives the chip select signal line to send a chip select signal CS, and the slave SPI device 20 receives the chip select signal CS.
[0079] The master SPI device 10 drives the clock signal line to send the clock signal CLK, and the slave SPI device 20 receives the clock signal CLK.
[0080] Read instruction period: the master SPI device 10 drives the data signal line Dx to send a read instruction, and the slave SPI device 20 samples the data signal line Dx to receive the read instruction.
[0081] Read conversion period (Turnaround Phase): the master SPI device 10 / slave SPI device 20 does not drive the data signal line Dx. During the conversion period, the data signal line Dx is driven by the master SPI device 10 and then converted to being driven by the slave SPI device 20. During the conversion period, the master SPI device 10 / slave SPI device 20 will not drive the data signal line Dx at the same time.
[0082] Data reading period: the slave SPI device 20 drives the data signal line Dx to send read data, and the master SPI device 10 samples the data signal line Dx to receive the read data.
[0083] See also Figure 2b , Figure 2b A timing diagram of a read operation of a master SPI device 10 in the related art is shown.
[0084] Depend on Figure 2b It can be seen that in the read operation, during the read instruction period, it is very convenient for the slave SPI device 20 to receive the read instruction. During the data read period, the master SPI device 10 sends out the clock signal CLK, and the slave SPI device 20 receives the clock signal CLK sent by the master (delay Delay1), and then sends out the read data to the data signal line Dx according to the clock signal CLK beat, and the master SPI device 10 receives the read data returned by the slave SPI device 20 (delay Delay2). Because of the existence of these delays, originally at the slave SPI device 20 end, the clock signal CLK and the data signal Dx timing were good (the rising edge of CLK was in the middle of each segment Dx), and at the master SPI device 10 end, the clock signal CLK and the data signal Dx timing have changed greatly relative to the sending end of the slave SPI device 20, and need to be debugged to find the stable middle point of the read data signal for sampling and receiving, to ensure that the received read data is correct.
[0085] In summary, in the related art, the master SPI device 10 drives the clock signal CLK, and the master SPI device 10 / slave SPI device 20 switches the driving data signal Dx according to the write / read data direction. The timing of the write operation is very good, but the read operation has the problems of large read data delay and delay variation:
[0086] The delay from the clock signal CLK of the master SPI device 10 to the master SPI device 10 receiving the read data Dx is relatively large;
[0087] The delay (Delay3) from the clock signal CLK of the master SPI device 10 to the master SPI device 10 receiving the read data Dx is the sum of the delay (Delay1) from the clock signal CLK of the master SPI device 10 to the slave SPI device 20 and the delay (Delay2) from the data signal Dx of the slave SPI device 20 to the master SPI device 10 (Delay3=Delay1+Delay2);
[0088] The delay from the clock signal CLK of the master SPI device 10 to the master SPI device 10 receiving the read data Dx is prone to change. For example, the delay will change significantly with changes in operating conditions such as operating temperature, and the delay will change due to differences in chip internal wiring and board-level routing. Of course, there are various reasons for the delay change, which are not listed here exhaustively.
[0089] In the case of large read data delay and delay variation, in order to receive read data accurately, it is necessary to debug each chip system to support a higher SPI rate as much as possible and adapt to various variation limits (such as high and low temperature), which is cumbersome to debug. And it is necessary to support various variation delay limits such as high and low temperature. Under the goal of pursuing the highest possible SPI rate (fast data transmission), only one relatively low rate can be selected to adapt to the variation limit and ensure the correct reception of data.
[0090] It can be seen that it is necessary to solve the above-mentioned problems of large read data delay and delay variation, which cause cumbersome debugging and rate limitation, so as to improve the efficiency and accuracy of SPI communication.
[0091] In view of this, an embodiment of the present disclosure proposes an SPI communication system. In the SPI communication system of the embodiment of the present disclosure, the slave SPI device 20 receives the instruction clock signal and the instruction data signal sent by the master SPI device 10 in the instruction period to receive the read instruction; sends the read clock signal and the read data signal to the master SPI device 10 in the read data period; the master SPI device receives the read data signal sent by the slave SPI device 20 according to the read clock signal sent by the slave SPI device 20 in the read data period. Since the read clock signal and the read data signal are both driven by the slave SPI device 20, the read clock signal and the read data signal can maintain a good fixed timing relationship at the slave / master SPI device end. The master SPI device 10 uses the read clock signal sent by the slave SPI device 20 to easily and accurately sample the read data signal sent by the slave SPI device 20, thereby facilitating the improvement of the SPI communication rate.
[0092] In the SPI communication system of the disclosed embodiment, the clock signal and the data signal are driven on the same side, that is, when the data transmitting end (master SPI device 10 / slave SPI device 20) drives the data signal, it is also responsible for driving the clock signal, rather than the master SPI device 10 driving the clock signal all the time. In the disclosed embodiment, the clock signal and the data signal are both driven by the data transmitting end, and the delays when transmitted to the data receiving end are the same (the routing is consistent, and the delay changes caused by the temperature and other working conditions are also the same). The timing relationship between the clock signal and the data signal determined at the transmitting end is also the same timing relationship determined at the receiving end. The data receiving end is convenient for receiving data, the receiving logic is simple, and each product does not need to do too much cumbersome debugging.
[0093] The embodiments of the present disclosure do not limit the specific implementation methods of the master SPI device 10 and the slave SPI device 20. For example, the master SPI device 10 and the slave SPI device 20 can both be chips. The SPI communication scheme of the embodiments of the present disclosure is used to implement SPI communication between chips, which can effectively improve the communication efficiency between chips.
[0094] See also Figure 3 , Figure 3 FIG. 1 is a timing diagram of a read operation of the master SPI device 10 according to an embodiment of the present disclosure.
[0095] Please refer to Table 3, which shows the signal driving description of the read operation of the embodiment of the present disclosure.
[0096] Table 3
[0097]
[0098] Exemplarily, as shown in Table 3, in each period of the read operation, the master SPI device 10 drives the chip select signal CS to send a chip select, and the slave SPI device 20 receives the chip select signal CS.
[0099] Exemplarily, as shown in Table 3, during the read instruction period: the master SPI device 10 drives the clock signal CLK to send the clock, and receives the clock signal CLK from the slave SPI device 20; the master SPI device 10 drives the data signal Dx to send a read instruction, and the slave SPI device 20 samples the data signal Dx to receive the read instruction; the timing relationship between the clock signal CLK and the data signal Dx received from the slave SPI device 20 is determined.
[0100] Exemplarily, as shown in Table 3, in the read conversion period (Turnaround Phase), the master SPI device 10 / slave SPI device 20 does not drive CLK / Dx, and in the conversion period CLK / Dx is driven by the master SPI device 10 and converted to being driven by the slave SPI device 20, and during the conversion period, the master SPI device 10 / slave SPI device 20 will not drive CLK / Dx at the same time.
[0101] Exemplarily, as shown in Table 3, during the data read period: the slave SPI device 20 drives the clock signal CLK to send the clock, and the master SPI device 10 receives the clock signal CLK; the slave SPI device 20 drives the data signal Dx to send the read data, and the master SPI device 10 samples the data signal Dx to receive the read data; the timing relationship between the clock signal CLK and the data signal Dx received by the master SPI device 10 is the same as the timing relationship between the clock signal CLK and the data signal Dx of the slave SPI device 20 at the transmitting end, and the rising edge of the clock signal CLK is exactly in the middle of the data signal Dx, so the receiving end master SPI device 10 (without special debugging) can easily, conveniently and accurately sample and receive the read data.
[0102] For example, Figure 3 It can be seen that in the read operation, during the read instruction period, the CLK / Dx timing relationship of the slave SPI device 20 receiving the read instruction is determined, and the CLK rising edge is exactly in the middle of each segment of data, which is convenient for reception. During the read data period, the CLK / Dx timing relationship of the master SPI receiving the read data is determined, and the CLK rising edge is exactly in the middle of each segment of data, which is convenient for reception.
[0103] According to the determined timing, the receiving and sending logic is designed, and it can work normally without tedious debugging. Moreover, the high and low temperature working conditions are the same, the delay changes of the clock signal CLK / data signal Dx are also the same, and the change limits are the same, so that a higher SPI communication rate can be supported.
[0104] In the above, the data sending end in the SPI communication system of the embodiment of the present disclosure is introduced as the slave SPI device 20. Of course, the master SPI device 10 can also be used as the data sending end. For example, in a possible implementation, the master SPI device 10 is used to: send an instruction clock signal and a write instruction data signal to the slave SPI device 20 in the instruction period; send a write clock signal and a write data signal to the slave SPI device 20 in the write data period; in a possible implementation, the slave SPI device 20 is used to: receive the instruction clock signal and the instruction data signal sent by the master SPI device 10 in the instruction period to receive the write instruction; receive the write clock signal and the write data signal sent by the master SPI device 10 in the write data period to receive the write data.
[0105] It should be noted that the manner in which the master SPI device 10 sends data as a data transmitter is described above and will not be elaborated here.
[0106] The disclosed embodiment proposes an SPI communication system. In the SPI communication system of the disclosed embodiment, the slave SPI device 20 sends a read clock signal and a read data signal when receiving a read instruction from the master SPI device 10, so that the master SPI device 10 receives the read data signal according to the read clock signal. Since the read clock signal is driven by the slave SPI device 20, the read clock signal and the data signal can maintain a good fixed timing relationship at the slave / master SPI device end. The master SPI device 10 uses the clock signal sent by the slave SPI device 20 to easily and accurately sample the read data signal sent by the slave SPI device 20, which is convenient for improving the SPI communication rate. By adopting the same-side driving of the clock signal and the data signal, that is, when the master SPI device 10 / slave SPI device 20 drives the data signal, it is also responsible for driving the clock signal, rather than the master SPI device 10 driving the clock signal all the time, compared with the method in which the clock signal is driven by the master SPI, the SPI working rate can be improved, the accuracy of data transmission can be improved, and the debugging difficulty can be reduced.
[0107] As an example, the same project was tested, and the SPI communication designed by the original scheme (both write and read operations were driven by the main SPI clock signal) was debugged to a stable SPI rate of 15MHz, and the debugging was cumbersome. However, using the scheme proposed in the embodiment of the present disclosure (using the clock signal and the data signal to drive on the same side), when other adjustments were the same, the SPI stable working rate of the scheme proposed in the embodiment of the present disclosure was 30MHz, and the debugging process was simpler.
[0108] See also Figure 4 , Figure 4 A schematic diagram of single data rate (SDR) SPI communication using SPI mode 0 as an example in the related art is shown.
[0109] like Figure 4 As shown, the data transmitter sends data to Dx at the falling edge of the clock signal (CLK), keeps the data unchanged at the rising edge of the clock signal (CLK), and sends the next data at the next falling edge of the clock signal (CLK). Data Dx remains stable for a whole clock (CLK) cycle between the two falling edges of the clock signal (CLK).
[0110] like Figure 4 As shown, the data receiving end samples and receives the Dx data at the rising edge of the clock signal (CLK). This sampling point is exactly the middle point where the data signal Dx remains stable for a whole clock (CLK) cycle, meeting the best setup time and hold time.
[0111] It can be seen that the shortcomings of SDR SPI communication are:
[0112] The rate of the clock CLK is twice the rate of the data Dx. Within a period in which the data Dx changes once (0 to 1 or 1 to 0), the clock CLK needs to change twice (once rising and once falling).
[0113] If the clock CLK and the PAD of the data Dx have the same driving capabilities, the maximum communication rate is limited by the communication (driving) capability of the clock CLK.
[0114] If the clock CLK is to be compatible with the data Dx rate, the PAD driving capability of the clock CLK needs to be increased, and the PAD area of the clock CLK needs to be increased. In addition, the clock CLK needs a rise / fall time, and the high and low levels need to be maintained for a period of time. Continuously increasing the PAD area and driving capability of the clock CLK does not linearly increase the communication rate of the clock CLK.
[0115] Therefore, in order to solve the problem that the rate of the clock CLK is twice the rate of the data Dx and the communication rate is limited by the communication capability of CLK, and to further improve the accuracy of SPI data transmission, the present invention discloses a DDR (Dual Data Rate) SPI communication technology that samples data on both the rising and falling edges of the clock signal CLK.
[0116] In a possible implementation manner, a rising edge of the instruction clock signal corresponds to a middle position of the first instruction data signal, and a falling edge of the instruction clock signal corresponds to a middle position of the second instruction data signal, and the cycle repeats, wherein the second instruction data signal is a next instruction data signal adjacent to the first instruction data signal;
[0117] In a possible implementation manner, a rising edge of the write clock signal corresponds to a middle position of the first write data signal, and a falling edge of the write clock signal corresponds to a middle position of the second write data signal, and the cycle repeats, wherein the second write data signal is a next write data signal adjacent to the first write data signal;
[0118] In one possible implementation, the rising edge of the read clock signal corresponds to the middle position of the first read data signal, and the falling edge of the read clock signal corresponds to the middle position of the second read data signal, and so on, wherein the second read data signal is the next read data signal adjacent to the first read data signal.
[0119] Exemplarily, the aforementioned “middle position” may be the center point of the data signal length (eg Figure 2a in the middle of the Dx data).
[0120] Exemplarily, the two (or two-beat) data signals corresponding to the same clock signal can be regarded as a pair of data signals, the middle position of the first data signal corresponds to the rising edge of the clock signal, and the middle position of the second data signal corresponds to the falling edge of the clock signal. As mentioned above, the first instruction data signal and the second instruction data signal can be regarded as a pair of instruction data signals, the first instruction data signal is the first instruction data signal of the pair of instruction data signals, and the second instruction data signal is the next adjacent instruction data signal of the first instruction data signal. Then the rising edge of the instruction clock signal corresponds to the middle position of the first instruction data signal, and the falling edge of the instruction clock signal corresponds to the middle position of the second instruction data signal, and so on.
[0121] In a possible implementation manner, the SPI transmitting end in the master SPI device 10 and the slave SPI device 20 is used for:
[0122] Set the clock period of the clock signal to 2T. Send the first data signal and the second data signal continuously in each clock period. T is a positive value. In each clock period:
[0123] At the beginning of the clock cycle, the first data signal is sent;
[0124] After T / 2, the rising edge of the clock signal is sent;
[0125] After T / 2, the second data signal is sent;
[0126] After T / 2, the falling edge of the clock signal is sent;
[0127] After T / 2, the next clock cycle begins.
[0128] See also Figure 5 , Figure 5 A schematic diagram of SPI communication according to an embodiment of the present disclosure is shown.
[0129] For example, Figure 5 As shown, the SPI transmitter (including the master SPI device 10 and the slave SPI device 20):
[0130] First send data to Dx, after T / 2, send the rising edge of clock CLK, after T / 2, send the next data to Dx, after T / 2, send the falling edge of clock CLK, clock CLK and data Dx keep T / 2. In this way, a cycle of 2 data is completed. Repeat this cycle and end after all data are transmitted.
[0131] In the cycle of these two data, the clock CLK and the data Dx change at the same frequency, and both change after maintaining for one T. The clock CLK and the data Dx are staggered by T / 2 to ensure that the SPI receiver has a good setup time (T / 2) and hold time (T / 2) when sampling the data Dx at the rising edge / falling edge of the clock CLK.
[0132] The SPI communication technology of DDR (Dual Data Rate) that samples data at both the rising and falling edges of the clock signal CLK in this embodiment of the present disclosure has the following advantages:
[0133] Compared with SDR communication, the change rate of the clock CLK is reduced to half.
[0134] The clock CLK and the data Dx change at the same frequency, and the communication capability is no longer limited by the clock CLK.
[0135] The clock CLK and data Dx can reuse the same PAD design, and there is no need to design the CLK PAD separately, and there is no need to blindly increase the clock CLK PAD area and driving capability.
[0136] The clock CLK and data Dx use the same PAD. Compared with SDR, the communication rate of DDR can be doubled (the actual application is also subject to other conditions).
[0137] As an example, the same project was tested, and the SPI communication of the SDR was designed with the original solution. The CLK and Dx reused the same PAD design, and the CLK rate of the SPI for stable debugging was 15MHz (corresponding to a single-line data communication rate of 15Mbps, a two-line data communication rate of 30Mbps, and a four-line data communication rate of 60Mbps).
[0138] According to the DDR technical solution of the embodiment of the present disclosure, when the PAD design of CLK and Dx remains unchanged, the CLK rate of the SPI for debugging stable operation is 15MHz (corresponding to a single-line data communication rate of 30Mbps, a two-line data communication rate of 60Mbps, and a four-line data communication rate of 120Mbps). It can be seen that the data communication rate has doubled.
[0139] See also Figure 6 , Figure 6 A flow chart of an SPI communication method according to an embodiment of the present disclosure is shown.
[0140] The method is applied to a SPI communication system including a master SPI device 10 and a slave SPI device 20 .
[0141] like Figure 6 As shown, the method includes:
[0142] Step S11, using the slave SPI device 20 to receive the instruction clock signal and instruction data signal sent by the master SPI device 10 in the instruction period to receive the read instruction; sending the read clock signal and the read data signal to the master SPI device 10 in the read data period;
[0143] Step S12, using the master SPI device 10 to send a command clock signal and a read command data signal to the slave SPI device 20 during the command period; receiving a read data signal sent by the slave SPI device 20 according to the read clock signal sent by the slave SPI device 20 during the read data period.
[0144] In the embodiment of the present disclosure, when the slave SPI device 20 receives the read instruction of the master SPI device 10 during the instruction period, it sends a read clock signal and a read data signal during the read data period, so that the master SPI device 10 receives the read data signal according to the read clock signal. Since the read clock signal is driven by the slave SPI device 20, the master SPI device 10 can improve the accuracy of the read data when receiving the read data signal, and the read clock signal and the data signal can maintain a good fixed timing relationship at the slave / master SPI device end. The master SPI device 10 uses the clock signal sent by the slave SPI device 20 to easily and accurately sample the read data signal sent by the slave SPI device 20, thereby facilitating the improvement of the SPI communication rate.
[0145] In a possible implementation, the method further includes: using the master SPI device 10 to send a command clock signal and a write command data signal to the slave SPI device 20 during a command period; sending a write clock signal and a write data signal to the slave SPI device 20 during a write data period;
[0146] In a possible implementation, the method further includes: using the slave SPI device 20 to receive an instruction clock signal and an instruction data signal sent by the master SPI device 10 during an instruction period to receive a write instruction; and receiving a write clock signal and a write data signal sent by the master SPI device 10 during a write data period to receive write data.
[0147] In a possible implementation manner, a rising edge of the instruction clock signal corresponds to a middle position of the first instruction data signal, and a falling edge of the instruction clock signal corresponds to a middle position of the second instruction data signal, and the cycle repeats, wherein the second instruction data signal is a next instruction data signal adjacent to the first instruction data signal;
[0148] In a possible implementation manner, a rising edge of the write clock signal corresponds to a middle position of the first write data signal, and a falling edge of the write clock signal corresponds to a middle position of the second write data signal, and the cycle repeats, wherein the second write data signal is a next write data signal adjacent to the first write data signal;
[0149] In one possible implementation, the rising edge of the read clock signal corresponds to the middle position of the first read data signal, and the falling edge of the read clock signal corresponds to the middle position of the second read data signal, and so on, wherein the second read data signal is the next read data signal adjacent to the first read data signal.
[0150] In a possible implementation, the method further includes:
[0151] The following steps are performed using the SPI transmitter in the master SPI device 10 and the slave SPI device 20:
[0152] Set the clock period of the clock signal to 2T. Send the first data signal and the second data signal continuously in each clock period. T is a positive value. In each clock period:
[0153] At the beginning of the clock cycle, the first data signal is sent;
[0154] After T / 2, the rising edge of the clock signal is sent;
[0155] After T / 2, the second data signal is sent;
[0156] After T / 2, the falling edge of the clock signal is sent;
[0157] After T / 2, the next clock cycle begins.
[0158] It can be understood that the above-mentioned various method embodiments mentioned in the present disclosure can be combined with each other to form a combined embodiment without violating the principle logic. Due to space limitations, the present disclosure will not repeat them. It can be understood by those skilled in the art that in the above-mentioned method of the specific implementation method, the specific execution order of each step should be determined according to its function and possible internal logic.
[0159] In some embodiments, the SPI communication method provided by the embodiments of the present disclosure corresponds to the aforementioned SPI communication system, and its specific implementation can refer to the description of the above method embodiment, which will not be repeated here for the sake of brevity.
[0160] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.
Claims
1. An SPI communication system, characterized in that: The SPI communication system comprises a master SPI device and a slave SPI device, wherein: The slave SPI device is used to: receive the instruction clock signal and instruction data signal sent by the master SPI device in the instruction period to receive the read instruction; send the read clock signal and the read data signal to the master SPI device in the read data period; The master SPI device is used to: send an instruction clock signal and a read instruction data signal to the slave SPI device in an instruction period; and receive a read data signal sent by the slave SPI device according to the read clock signal sent by the slave SPI device in a read data period.
2. The SPI communication system according to claim 1, characterized in that: The master SPI device is used to: send a command clock signal and a write command data signal to the slave SPI device during the command period; send a write clock signal and a write data signal to the slave SPI device during the write data period; The slave SPI device is used to: receive the instruction clock signal and the instruction data signal sent by the master SPI device during the instruction period to receive the write instruction; During the data writing period, a write clock signal and a write data signal sent by the master SPI device are received to receive write data.
3. The SPI communication system according to claim 2, characterized in that: The rising edge of the instruction clock signal corresponds to the middle position of the first instruction data signal, and the falling edge of the instruction clock signal corresponds to the middle position of the second instruction data signal, and the cycle repeats, wherein the second instruction data signal is the next instruction data signal adjacent to the first instruction data signal; The rising edge of the write clock signal corresponds to the middle position of the first write data signal, and the falling edge of the write clock signal corresponds to the middle position of the second write data signal, and the cycle repeats, wherein the second write data signal is the next write data signal adjacent to the first write data signal; The rising edge of the read clock signal corresponds to the middle position of the first read data signal, and the falling edge of the read clock signal corresponds to the middle position of the second read data signal, and the cycle repeats, wherein the second read data signal is the next read data signal adjacent to the first read data signal.
4. The SPI communication system according to claim 1, characterized in that: The SPI transmitting end in the master SPI device and the slave SPI device is used for: Set the clock period of the clock signal to 2T, send the first data signal and the second data signal continuously in each clock period, T is a positive value of time, wherein in each clock period: At the beginning of the clock cycle, the first data signal is sent; After T / 2, the rising edge of the clock signal is sent; After T / 2, the second data signal is sent; After T / 2, the falling edge of the clock signal is sent; After T / 2, the next clock cycle begins.
5. The SPI communication system according to claim 1, characterized in that: The master SPI device and the slave SPI device are both chips.
6. An SPI communication method, characterized in that: The method is applied to an SPI communication system including a master SPI device and a slave SPI device, wherein the method comprises: The slave SPI device receives the instruction clock signal and instruction data signal sent by the master SPI device in the instruction period to receive the read instruction; and sends the read clock signal and the read data signal to the master SPI device in the read data period; The master SPI device is used to send an instruction clock signal and a read instruction data signal to the slave SPI device during an instruction period; and a read data signal sent by the slave SPI device is received according to the read clock signal sent by the slave SPI device during a read data period.
7. The SPI communication method according to claim 6, characterized in that: The method further comprises: using the master SPI device to send a command clock signal and a write command data signal to the slave SPI device during a command period; sending a write clock signal and a write data signal to the slave SPI device during a write data period; The slave SPI device is used to receive the instruction clock signal and instruction data signal sent by the master SPI device in the instruction period to receive the write instruction; and to receive the write clock signal and write data signal sent by the master SPI device in the write data period to receive the write data.
8. The SPI communication method according to claim 7, characterized in that: The rising edge of the instruction clock signal corresponds to the middle position of the first instruction data signal, and the falling edge of the instruction clock signal corresponds to the middle position of the second instruction data signal, and the cycle repeats, wherein the second instruction data signal is the next instruction data signal adjacent to the first instruction data signal; The rising edge of the write clock signal corresponds to the middle position of the first write data signal, and the falling edge of the write clock signal corresponds to the middle position of the second write data signal, and the cycle repeats, wherein the second write data signal is the next write data signal adjacent to the first write data signal; The rising edge of the read clock signal corresponds to the middle position of the first read data signal, and the falling edge of the read clock signal corresponds to the middle position of the second read data signal, and the cycle repeats, wherein the second read data signal is the next read data signal adjacent to the first read data signal.
9. The SPI communication method according to claim 6, characterized in that: The method further comprises: The following steps are performed using the SPI transmitter in the master SPI device and the slave SPI device: Set the clock period of the clock signal to 2T, send the first data signal and the second data signal continuously in each clock period, T is a positive value of time, wherein in each clock period: At the beginning of the clock cycle, the first data signal is sent; After T / 2, the rising edge of the clock signal is sent; After T / 2, the second data signal is sent; After T / 2, the falling edge of the clock signal is sent; After T / 2, the next clock cycle begins.
10. The SPI communication method according to claim 6, characterized in that: The master SPI device and the slave SPI device are both chips.