A power network optimization method for enhancing chip reliability in strong magnetic pulse environments

Abstract

This application belongs to the field of chip power network technology. This application provides a power network optimization method to enhance chip reliability under strong magnetic pulse environments. Based on the chip's design conditions, this disclosure utilizes EDA tools to design the chip and obtain an initial power network. The method aims to make the initial power network form a closed loop as much as possible; to ensure that vias in different metal layers are on the same vertical line, transforming the open-loop structure into an L-shaped structure; to appropriately increase redundant metal lines while meeting power supply requirements; and to reduce the magnetic flux integration area through a multi-fold structure, thus obtaining the target power network. This expands the scope of improving the chip's resistance to magnetic interference, considers the influence of external magnetic fields on the chip power network, and provides a reliability optimization scheme for chip design under strong magnetic pulse environments.

Description

Technical Field

[0001] This disclosure relates to the field of chip power network technology, and in particular to a power network optimization method for enhancing chip reliability under strong magnetic pulse environments. Background Technology

[0002] With the rapid development of integrated circuits, feature sizes have shrunk from the micrometer level to the nanometer level. Researchers are repeatedly defying the claim that "Moore's Law no longer applies," giving rise to new transistor structures and integrated circuit architectures such as FinFET, GAAFET, and Chiplet. Feature sizes are moving towards the atomic level, and the integration density of integrated circuits is now vastly different. This dramatic increase in integration density brings a series of advantages, such as lower supply voltage, resulting in significantly reduced power consumption, and a surge in the number of transistors, leading to more powerful chips. However, increasingly complex integrated circuits will also face more complex reliability issues; for example, the electromagnetic environment is a major area of ​​reliability research.

[0003] Inside the chip, researchers primarily focus on EMI caused by rapid switching currents. In this regard, Wataru Ichimura et al. reduced EMI in 2014 by suppressing the Q factor of the PDN using variable in-line capacitors and resistors. Dongil Shin et al., in 2015, efficiently calculated the electromagnetic interference coefficient of the PDN using a cavity resonant circuit model. In 2021, Changjong Lee et al. optimized the design of the decoupling capacitor of the PDN based on deep reinforcement learning, suppressing EMI. In 2022, Jingook Kim's team proposed an automated reinforcement learning approach based on SPICE integration to address both EMI and power integrity issues.

[0004] Externally, due to the small size of the PDN (Power Distribution Network) on the chip, the potential fluctuations generated by a magnetic field pulse in a small loop are negligible according to Faraday's law of electromagnetic induction. Therefore, researchers often overlook the impact of external EMI (Electromagnetic Interference) on the PDN. However, in certain application environments, the strength and rate of change of the magnetic field are sufficient to cause fluctuations in the PDN's potential, leading to timing issues, logic errors, or even chip burnout. For example, in the military field, besides using electromagnetic interference to disrupt enemy control systems, electromagnetic pulses can be used to develop new weapons; electromagnetic coil guns or electromagnetic railguns both use electromagnetic force to launch projectiles. The principle is as follows... Figure 1 As shown. In such applications, transient current is often generated by capacitor discharge, which simultaneously induces a magnetic field. The topology of the discharge circuit is shown below. Figure 2As shown, the peak value of the magnetic field pulse generated during the discharge of a typical electromagnetic railgun can reach around 10T, with a frequency of approximately 10kHz-300MHz. In the civilian sector, some medical devices, such as MRI scanners, also generate high-frequency, high-intensity magnetic fields, while wireless local area networks (WiFi) generate high-frequency, low-intensity magnetic fields. Electromagnetic pulses are ubiquitous and diverse in both military and civilian applications. Understanding the characteristics of various electromagnetic pulses is crucial for designing electromagnetic interference (EMI) suppression chips.

[0005] Therefore, it is necessary to improve one or more of the problems existing in the above-mentioned related technical solutions.

[0006] It should be noted that this section is intended to provide background or context for the technical solutions of this disclosure as set forth in the claims. The description herein does not constitute an admission that it is prior art simply because it is included in this section. Summary of the Invention

[0007] To avoid the shortcomings of existing technologies, this invention provides a power network optimization method for enhancing chip reliability under strong magnetic pulse environments, thereby solving the problem in existing technologies where the influence of external severe magnetic fields on the chip power network is ignored due to the small area of ​​the chip power network.

[0008] According to a first aspect of the present disclosure, a power network optimization method for enhancing chip reliability under strong magnetic pulse environments is provided, the method comprising:

[0009] Based on the chip's design requirements, EDA tools are used to design the chip in order to obtain the initial power network;

[0010] Perform a first DRC check on the initial power network. If the check passes, select an optimization strategy to optimize the initial power network.

[0011] A second DRC check is performed on the optimized initial power network. If it passes, the target power network is obtained.

[0012] Furthermore, the optimization strategy includes:

[0013] Strategy 1: To make the loop formed by the power network itself tend to be closed;

[0014] Strategy 2: Add a preset number of redundant metal lines to the power network;

[0015] Strategy 3: The power network uses a multi-fold structure to reduce the integral area.

[0016] Furthermore, the step of selecting an optimization strategy to optimize the initial power network includes:

[0017] The initial power network is optimized using strategy one, strategy two, and strategy three in sequence.

[0018] Furthermore, the method also includes:

[0019] If the first DRC check fails, the initial power network is corrected according to the error information of the first DRC check;

[0020] Perform the first DRC check on the corrected initial power network.

[0021] Furthermore, the method also includes:

[0022] If the second DRC check fails, the optimized initial power network is corrected according to the error information of the second DRC check;

[0023] The second DRC check is performed on the corrected and optimized initial power network.

[0024] According to a second aspect of the present disclosure, a power network optimization device for enhancing chip reliability under strong magnetic pulse environments is provided, the device comprising:

[0025] The design module is used to design the chip based on the chip's design conditions using EDA tools to obtain the initial power network;

[0026] An optimization module is used to perform a first DRC check on the initial power network. If the check passes, an optimization strategy is selected to optimize the initial power network.

[0027] The output module is used to perform a second DRC check on the optimized initial power network. If the check passes, the target power network is obtained.

[0028] Furthermore, the device also includes:

[0029] The first correction module is configured to correct the initial power network according to the error information of the first DRC check if the first DRC check fails; and to perform the first DRC check on the corrected initial power network.

[0030] Furthermore, the device also includes:

[0031] The second correction module is used to correct the optimized initial power network according to the error information of the second DRC check if the second DRC check fails; and to perform the second DRC check on the corrected optimized initial power network.

[0032] According to a third aspect of the present disclosure, a computer-readable storage medium is provided, having a computer program stored thereon, which, when executed by a processor, implements the steps of the power network optimization method for enhancing chip reliability under strong magnetic pulse environments as described in any of the above embodiments.

[0033] According to a fourth aspect of the present disclosure, an electronic device is provided, comprising:

[0034] processor; and

[0035] Memory for storing the executable instructions of the processor;

[0036] The processor is configured to execute the steps of the power network optimization method for enhancing chip reliability under strong magnetic pulse environments described in any of the above embodiments by executing the executable instructions.

[0037] The technical solutions provided by the embodiments of this disclosure may include the following beneficial effects:

[0038] In the embodiments of this disclosure, the power network optimization method for enhancing chip reliability under strong magnetic pulse environments described above, on the one hand, uses EDA tools to design the chip based on its design conditions to obtain an initial power network. This involves maximizing the formation of closed loops within the initial power network; ensuring that vias in different metal layers are aligned on the same vertical line, transforming the open-loop structure into an L-shaped structure; appropriately increasing redundant metal lines while meeting power supply requirements; and reducing the magnetic flux integration area through a multi-fold structure to obtain the target power network. On the other hand, this expands the scope of improving the chip's resistance to magnetic interference, considers the influence of external magnetic fields on the chip's power network, and provides a reliability optimization scheme for chip design under strong magnetic pulse environments. Attached Figure Description

[0039] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0040] Figure 1 This diagram illustrates the principle of an electromagnetic railgun in the prior art.

[0041] Figure 2 The discharge circuit of an electromagnetic gun in the prior art is shown;

[0042] Figure 3 The diagram illustrates the steps of a power network optimization method for enhancing chip reliability under strong magnetic pulse environments, as shown in an exemplary embodiment of this disclosure.

[0043] Figure 4 A simplified model of parameters is shown in an exemplary embodiment of this disclosure;

[0044] Figure 5 This illustrates the potential fluctuations of the tree-like and ring-like structures in exemplary embodiments of this disclosure;

[0045] Figure 6 A tree structure diagram illustrating cases one and two in an exemplary embodiment of this disclosure is shown;

[0046] Figure 7 The potential fluctuations of the tree-like structure in cases one and two of the exemplary embodiments of this disclosure are shown;

[0047] Figure 8 This illustrates a single-fold structure of the power network in an exemplary embodiment of the present disclosure;

[0048] Figure 9 The integral region enclosed by the open-loop conductor and the magnetic field symmetry point in an exemplary embodiment of this disclosure is shown.

[0049] Figure 10 The diagram illustrates a three-fold structure of the power network in an exemplary embodiment of this disclosure;

[0050] Figure 11 The simulation results of the variation in the number of bends in the multi-fold structure in the exemplary embodiments of this disclosure are shown.

[0051] Figure 12 The following are power network models with different fold lengths in exemplary embodiments of this disclosure;

[0052] Figure 13 The simulation results of open-loop network structures with different crease lengths in exemplary embodiments of this disclosure are shown.

[0053] Figure 14 This illustrates potential fluctuations with different linewidths in exemplary embodiments of this disclosure;

[0054] Figure 15 This illustrates voltage fluctuations for different numbers of power supply lines (PDNs) in an exemplary embodiment of this disclosure;

[0055] Figure 16 This illustration shows a partial model of the Leon2 power network in an exemplary embodiment of this disclosure;

[0056] Figure 17 This illustrates the power supply path stripped from the Leon2 power network in an exemplary embodiment of this disclosure;

[0057] Figure 18 This illustrates a prototype line from input port to port 1 in an exemplary embodiment of this disclosure;

[0058] Figure 19 This illustrates an optimized route from input port to port 1 in an exemplary embodiment of this disclosure;

[0059] Figure 20 The simulation results before and after optimization of port 1 in an exemplary embodiment of this disclosure are shown;

[0060] Figure 21 A prototype circuit from input port to port 2 is shown in an exemplary embodiment of this disclosure;

[0061] Figure 22 An optimized circuit for input port to port 2 is shown in an exemplary embodiment of this disclosure;

[0062] Figure 23 The simulation results before and after port 2 optimization are shown in the exemplary embodiments of this disclosure;

[0063] Figure 24 A prototype circuit from input port to port 3 is shown in an exemplary embodiment of this disclosure;

[0064] Figure 25 An optimized circuit from input port to port 3 is shown in an exemplary embodiment of this disclosure;

[0065] Figure 26 The simulation results before and after port 3 optimization are shown in the exemplary embodiments of this disclosure;

[0066] Figure 27 A prototype circuit from input port to port 4 is shown in an exemplary embodiment of this disclosure;

[0067] Figure 28 An optimized circuit for input port to port 4 is shown in an exemplary embodiment of this disclosure;

[0068] Figure 29 The simulation results before and after optimization of port 4 in an exemplary embodiment of this disclosure are shown;

[0069] Figure 30 This illustrates the PDN model before optimization in an exemplary embodiment of this disclosure;

[0070] Figure 31 The potential fluctuations of the PDN model before optimization in the exemplary embodiments of this disclosure are shown;

[0071] Figure 32 This illustrates the optimized PDN model in an exemplary embodiment of the present disclosure;

[0072] Figure 33 The potential fluctuations of the optimized PDN model in the exemplary embodiments of this disclosure are shown;

[0073] Figure 34This illustrates a comparison of potential fluctuations at each test point before and after optimization in an exemplary embodiment of this disclosure.

[0074] Figure 35 This diagram illustrates a power network optimization apparatus for enhancing chip reliability under strong magnetic pulse environments, as shown in an exemplary embodiment of this disclosure. Detailed Implementation

[0075] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0076] Furthermore, the accompanying drawings are merely illustrative diagrams of embodiments of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities.

[0077] This example implementation provides a power network optimization method to enhance chip reliability under strong magnetic pulse environments. (See reference...) Figure 3 As shown, the power network optimization method for enhancing chip reliability under strong magnetic pulse environment may include steps S101 to S103.

[0078] Based on the chip's design requirements, EDA tools are used to design the chip in order to obtain the initial power network;

[0079] Perform a first DRC check on the initial power network. If the check passes, select an optimization strategy to optimize the initial power network.

[0080] A second DRC check is performed on the optimized initial power network. If it passes, the target power network is obtained.

[0081] The power network optimization method described above for enhancing chip reliability under strong magnetic pulse environments has two main aspects. First, based on the chip's design specifications, an initial power network is designed using EDA tools. This involves maximizing the formation of a closed loop within the initial power network; ensuring that vias in different metal layers are aligned on the same vertical line, transforming the open-loop structure into an L-shaped structure; appropriately increasing redundant metal lines while meeting power supply requirements; and reducing the magnetic flux integration area through a multi-fold structure to obtain the target power network. Second, this method expands the scope of improving the chip's resistance to magnetic interference, considering the impact of external magnetic fields on the chip's power network, and providing a reliability optimization scheme for chip design under strong magnetic pulse environments.

[0082] Below, we will refer to Figures 3 to 34 The steps of the power network optimization method for enhancing chip reliability under strong magnetic pulse environment described in this example embodiment will be explained in more detail.

[0083] In steps S101 to S103, when the back-end engineer begins the chip placement and routing work, in order to improve the chip's immunity to magnetic interference, the following design steps can be performed:

[0084] Fully understand the design specifications regarding line width, line spacing, and resource constraints.

[0085] Use EDA tools to complete the initial power network of the chip.

[0086] Perform a Design Rule (DRC) check on the power network results. If the DRC check passes, proceed to perform step-by-step optimization based on the power network initially completed by the EDA tool, using optimization strategies one, two, and three. If the DRC check fails, manually modify the power network according to the DRC error message.

[0087] Perform a DRC check on the optimized power network. If the DRC check passes, the power network is complete; if the DRC check fails, manually modify the power network based on the DRC error message.

[0088] In one specific embodiment, the simulation model of this application employs simplified models with different parameters for different simulation variables, such as... Figure 4 As shown. Stripes_length represents the length of the stripes, the entire model is a mesh structure, and Stripes_width represents the width of the stripes. The number of metal stripes in the model is also an important influencing factor discussed later; therefore, the number of metal stripes (Stripes_num) has also been parameterized. The blue and green stripes are located on the upper and lower layers respectively, connected by black vias.

[0089] In one specific embodiment, the multilayer metal network of the chip contains both ring structures (e.g., the top two layers of PDN and power supply lines connected together by vias) and tree structures (e.g., power supply lines connecting multiple layers of metal to functional units vias). This section simulates these two different structures by adding a background magnetic field.

[0090] The simulation model of the ring structure adopts a closed-loop structure with a line length of 1000um, a line width of 0.25um, and a number of lines of 4.

[0091] The tree-like simulation model uses an open-loop structure with 1000µm of lines, a line width of 0.25µm, and 4 lines.

[0092] In a ring structure, the load on the metal wire is small, so the induced ring current does not produce large potential fluctuations. In a tree structure, the changing magnetic field causes electrons to move in a specific direction, resulting in different potentials at different ends. Therefore, the rapid change in magnetic flux produces larger potential fluctuations in a tree structure.

[0093] After adding a background magnetic field, the potential fluctuations at different locations of the PDN are as follows: Figure 5 As shown, the potential fluctuation in a ring structure is approximately 30% of that in a tree structure. Therefore, when designing a PDN, different metal layers should be connected vias as much as possible to transform the tree structure into a ring structure.

[0094] Due to the different locations of vias, the power lines in the tree structure will form different structures. These different structures result in varying levels of immunity to magnetic fields in the PDN. The PDN is categorized below based on the location of the vias, as follows: Figure 6 (a) Case (i.e., Case 1) and Figure 6 (b) Case 2 (i.e., case 2) is simulated for electromagnetic interference resistance. Figure 6 (a) The four metal wires in the structure form an open loop structure because the vias are not on the same vertical line. Figure 6 (b) In the structure, the vias connecting the four metal wires are located on the same vertical line, forming an L-shaped structure. Metal wire 3 is located directly below wire 1, and metal wire 4 is located directly below wire 2. The simulation results are as follows: Figure 7 As shown.

[0095] from Figure 7 The simulation results show that Figure 6 (b) The potential fluctuation of the structure is reduced to Figure 6(a) The structure is 50% larger, resulting in stronger anti-interference capabilities. This is mainly because the pulsed magnetic field generates a vortex electric field in space, causing electrons in the conductor to move directionally within the electric field, thus creating a potential difference. Figure 6 (a) The distance the electron travels in the structure is Figure 6 (b) The structure is twice the size of the electrons, therefore the potential difference generated by the work done by the electrons is also twice the size. In addition, Figure 6 (a) The open-loop structure with the most layers can easily form a multi-turn coil structure, which increases the number of turns of the magnetic induction coil, thereby causing the induced electromotive force to be superimposed. Figure 6 (b) The L-shaped structure breaks the spiral structure of the multi-layer open-loop structure, and the multi-layer metal will naturally not have the effect of the coil turns superimposed, thus greatly reducing the potential fluctuation.

[0096] A more in-depth discussion reveals that different multi-fold structures can be formed between two fixed potential test points when the tree structure is in case two. The following simulation analysis will focus on the number and length of the folds.

[0097] The simulation model of the multi-fold structure uses a fixed potential reference point and test point, and the outermost line has a length of 1000um and a line width of 0.25um.

[0098] Regarding the number of folded edges

[0099] In the layout design of chip power networks, from point A to point B of the next layer, most of the routing structures automatically generated by EDA software are as follows: Figure 8 The circuit model shown.

[0100] Magnetic fields have symmetrical properties, which can be mainly divided into two types: axial symmetry and point symmetry. Among them, point symmetry means that the magnetic field has symmetrical properties at a certain point in space, that is, any straight line or plane passing through that point cuts the spatial magnetic field, and the two sides of the cut spatial magnetic field have absolutely identical magnetic field properties. Using Maxwell's explicit solution, a time-varying homogeneous magnetic field was constructed, and the statement that the induced voltage of the open-loop circuit depends on the symmetrical point that generates the magnetic field was proved by derivation of Gauss's law, Lorentz gauge, and delayed potential. Furthermore, the formula for the induced voltage of the open-loop wire under a uniform time-varying magnetic field was simply summarized by Maxwell's equations (1):

[0101] (1)

[0102] in, The area enclosed by the conductor and the symmetrical point is as follows Figure 9 As shown.

[0103] The area enclosed here can be obtained from equation (2):

[0104] (2)

[0105] To minimize voltage fluctuations in the on-chip power network under the influence of electromagnetic pulses, the integral region enclosed by the symmetrical points of the open-loop circuit and the electromagnetic field should be minimized, thereby minimizing the potential difference fluctuations across the open-loop wires. Therefore, based on this theory, this paper derives a three-fold structure from the default single-fold structure in computers, also from point A to point B, as follows: Figure 10 As shown.

[0106] To accurately compare the differences between the single-fold and three-fold power network structures, the physical models of both are configured with the same parameters: an open-loop structure with a line length of 492 μm and a line width of 8 μm. In the three-fold structure, the area enclosed by the open-loop line from point A to point B and the symmetrical point of the magnetic field is reduced by nearly half compared to the single-fold structure. The simulation results are as follows: Figure 11 As shown.

[0107] The simulation results show that the voltage fluctuation extreme value of the single-fold loop structure is 0.1435V, while the voltage fluctuation extreme value of the three-fold structure is 0.0717V.

[0108] from Figure 11 Simulation results show that the potential difference fluctuation of the three-fold structure is reduced to 50% of that of the single-fold structure, resulting in stronger electromagnetic compatibility performance. This is mainly because the integrated area enclosed by the conductor and the magnetic field symmetry point in the three-fold structure is almost half the size of that enclosed by the single-fold structure. Therefore, when calculating the open-loop induced voltage, the induced voltage of the three-fold structure is almost half that of the single-fold structure, and the resulting voltage fluctuation is also almost halved. From this, we can conclude that the number of folds in a multi-fold structure in a power network affects the voltage fluctuation of the power network under a pulsed magnetic field. The fluctuating voltage increases with the increase of the number of folds, and the reduction is approximately 50.0% when the area enclosed by the open-loop power line structure and the magnetic field symmetry point is halved.

[0109] Regarding the folded length

[0110] Similarly, in the study of induced voltage in open-loop power lines, reducing the integral area enclosed by the open-loop power line path and the magnetic field symmetry point can reduce voltage fluctuations caused by high-power electromagnetic pulses. There are two ways to reduce the integral area enclosed by the open-loop power line path and the magnetic field symmetry point. One is to increase the number of bends so that the open-loop power line path is closer to the magnetic field symmetry point. This method has been verified in simulation experiments verifying the impact of the number of bends on electromagnetic interference. However, this method cannot be infinitely extended to five-fold, seven-fold, nine-fold, etc., because the on-chip power network has certain space constraints and cost limitations. Blindly increasing the number of bends not only wastes the scarce space resources of the on-chip power network but also increases manufacturing difficulty and cost. Therefore, another way to reduce the integral area enclosed by the open-loop power line path and the magnetic field symmetry point is to change the bend length. For example... Figure 12 As shown.

[0111] The left side shows an open-loop network structure with a three-fold edge length of 246μm, and the right side shows a loop network structure with a three-fold edge length of 123μm. A physical model of this circuit was created using CAD modeling software. The material was set to copper, the model line length was 492μm, and the model line width and height were 8μm. The number of folds was determined to be three, and the edge lengths were modified to 246μm and 123μm respectively. The model was then imported into finite element simulation software. In a low-frequency simulation environment, the finite-time domain algorithm was used to solve for the potential difference fluctuations between the ports, resulting in the following... Figure 13 The simulation results are shown.

[0112] The voltage fluctuation extreme value of a three-fold loop network structure with a side length of 246μm is 0.0717V, and the voltage fluctuation extreme value of a three-fold loop network structure with a side length of 123μm is 0.0179V. From... Figure 13 As can be seen, the potential difference fluctuation of the power network structure with a 246μm three-fold side length is much greater than that of the power network structure with a 123μm three-fold side length. This is mainly because the integral area enclosed by the open-loop power line path and the magnetic field symmetry point of the 123μm three-fold side length structure is much smaller than that enclosed by the open-loop power line path and the magnetic field symmetry point of the 246μm three-fold side length structure. Therefore, when calculating the induced voltage in the open-loop circuit, the voltage fluctuation extreme value of the power network structure with a 246μm three-fold side length will be much greater than that of the power network structure with a 123μm three-fold side length.

[0113] Therefore, when participating in the optimization design of power networks, the length of the bends in the multi-fold structure should be fully considered to minimize the integral area enclosed by the open-loop power line path and the magnetic field symmetry point. However, this optimization differs from the optimization scheme of increasing the number of bends in the multi-fold structure. Under the same number of bends, there will be a minimum voltage fluctuation. In other words, this optimization strategy cannot theoretically perfectly cancel the voltage fluctuations caused by electromagnetic pulses to the power network, while increasing the number of bends can theoretically make the voltage fluctuations almost 0V.

[0114] In one specific embodiment, a background magnetic field is added to models with line widths of 0.25µm, 0.50µm, and 0.75µm, and the potential fluctuations are as follows: Figure 14 As shown, as the linewidth increases, the maximum potential fluctuation of the power supply network remains similar, but the rate of potential decrease gradually decreases, and the effect of increasing the linewidth on the ability to resist magnetic interference gradually decreases. When the linewidth increases to 0.75 μm, the linewidth no longer affects the potential fluctuation of the power supply network under a pulsed magnetic field.

[0115] Analysis of the simulation results reveals that regardless of the metal linewidth, the maximum potential induced by the pulsed magnetic field does not differ significantly. Therefore, linewidth is not the primary factor affecting the anti-magnetic interference capability of PDN.

[0116] In one specific embodiment, tree-structured PDN structures with 4, 8, 12, and 16 lines were simulated. The simulation results are as follows: Figure 15 As shown, the simulation results show that the more lines there are, the smaller the potential fluctuation caused by the pulsed magnetic field. Furthermore, the potential fluctuation decreases by 50% for every doubling of the number of lines.

[0117] Excess lines will create redundant loops in the metal network. A single metal line may belong to multiple loops of different areas simultaneously. The direction of the same pulsed magnetic field will produce electric fields with the same rotation direction in different loops, but on the same shared metal line, they will produce electric fields with different directions. These electric fields in different directions will cancel each other out. This is why the more lines there are, the smaller the potential fluctuations become.

[0118] Therefore, when designing a practical chip power supply network, some redundant metal strips can be added appropriately, provided that the chip area allows, while meeting the module's power supply requirements.

[0119] In one specific embodiment, a local model of the on-chip power network based on LEON2 is used, such as... Figure 16As shown. Referring to the parameters of its physical model, several typical power line paths were extracted from the power network structure of the Leon2 chip, forming a four-layer, seven-port power network prototype. The prototype power network model was set with a linewidth of 8μm and a border length of 492μm, as shown below. Figure 17 As shown. The model is made of copper.

[0120] Based on the simulation analysis results above, path optimization for the four ports of this power supply path to resist strong magnetic pulse interference is performed.

[0121] Port 1 optimization strategy and its optimization efficiency

[0122] like Figure 18 As shown, the line marked in red is the prototype line from the input port to port 1.

[0123] Based on the optimized scheme verified above, two additional bends were added to the basic circuit of port one, improving the original single-fold structure into a three-fold structure. This reduces the integral area enclosed by the magnetic field symmetry point and the open-loop power supply line, theoretically reducing the voltage fluctuation range between ports under high-power electromagnetic pulses. Its specific structure is as follows... Figure 19 As shown.

[0124] Importing the two circuit models above into finite element simulation software for electromagnetic simulation yields the following results: Figure 20 The simulation results are shown.

[0125] In the simulation experiment, the maximum inter-port voltage fluctuation of the original model of port 1 was 0.0372V, while the maximum inter-port voltage fluctuation after optimization was 0.0175V, and the optimization efficiency was 52.9%.

[0126] Port 2 optimization strategy and its optimization efficiency

[0127] like Figure 21 As shown, the part marked in red is the prototype circuit of port 2 before optimization.

[0128] Based on the optimization scheme verified in Chapter 3, two additional bends were added to the basic circuit of port 2, and the planar area covered by the entire circuit in space was reduced. This reduced the integral area enclosed by the magnetic field symmetry point and the power supply line, thereby reducing the voltage fluctuation range induced by the magnetic field in the open-loop circuit. The specific optimization scheme is as follows: Figure 22 As shown.

[0129] Importing the two circuit models above into finite element simulation software for electromagnetic simulation yields the following results: Figure 23 The simulation results are shown.

[0130] In the simulation experiment, the maximum inter-port voltage fluctuation of the original model of port 2 was 0.108V, while the maximum inter-port voltage fluctuation after optimization was 0.0329V, and the optimization efficiency was 69.5%.

[0131] Port 3 optimization strategy and its optimization efficiency

[0132] like Figure 24 As shown, the part marked in red is the prototype circuit of port 3 before optimization.

[0133] Based on the verified optimization scheme above, four additional bends were added to the basic circuit of port 3. Furthermore, the circuit from the input port to port 3 is shared with the circuit from the input port to port 2, reducing the overall space occupied by the power network, improving space utilization, and decreasing the integral path formed between the magnetic field symmetry point and the open-loop power line, thereby reducing potential difference fluctuations between ports. The specific circuit is as follows... Figure 25 As shown.

[0134] Importing the two circuit models above into finite element simulation software for electromagnetic simulation yields the following results: Figure 26 The simulation results are shown.

[0135] In the simulation experiment, the maximum inter-port voltage fluctuation of the original model of port 3 was 0.0681V, while the maximum inter-port voltage fluctuation after optimization was 0.0071V, and the optimization efficiency was 89.5%.

[0136] Port 4 optimization strategy and its optimization efficiency

[0137] like Figure 27 As shown, the part marked in red is the prototype circuit of port 4 before optimization.

[0138] Based on the verified optimization scheme above, two additional bends were added to the basic circuit of port 4, and the planar area covered by the entire circuit in space was reduced. This reduced the integral area enclosed by the magnetic field symmetry point and the power supply line, thereby reducing the voltage fluctuation range induced by the magnetic field in the open-loop circuit. The specific optimization scheme is as follows: Figure 28 As shown.

[0139] Importing the two circuit models above into finite element simulation software for electromagnetic simulation yields the following results: Figure 28 The simulation results are shown.

[0140] In the simulation experiment, the maximum inter-port voltage fluctuation of the original model of port 4 was 0.1435 V, while the maximum inter-port voltage fluctuation after optimization was 0.0780 V, and the optimization efficiency was 45.6%.

[0141] In one specific embodiment, by modeling the local PDN of the SMIC 130nm-based Leon2 processor ( Figure 30 The model used here is the PDN model before optimization. This model has a maximum line length of 20µm and a minimum linewidth of 0.3µm, and consists of 5 metal layers. Compared to the area of ​​the abstract model selected in the previous simulation, the area of ​​the small portion of the actual PDN model chosen here is nearly 2500 times smaller. Therefore, the induced potential in the simulation results is also much smaller, decreasing from the mV level to µV. The comparison is made before and after optimization of the same model, not for different models. Therefore, using a local model does not affect the verification results of the optimization strategy, and the local model significantly speeds up the simulation and reduces the simulation load on the software. Figure 30 Five randomly selected potential fluctuation monitoring points are marked in the figure. A background magnetic field is added to the model, and the simulation results are as follows. Figure 31 As shown.

[0142] Through comprehensive simulation analysis, the minimum linewidth of the model was modified, unnecessary lines were reduced, and via positions were changed, thereby altering the network structure. The optimized model is shown below. Figure 32 As shown. The simulation results after adding a background magnetic field to the optimized model are as follows. Figure 33 As shown.

[0143] Comparing the models before and after optimization, Figure 32 The red modules represent the parts added to the simulation results based on the original model. The optimization strategies here mainly include:

[0144] 1. Add vias at appropriate locations to connect different layers of metal wires into a loop;

[0145] 2. Appropriately increase redundant metal wires.

[0146] Figure 34 To compare the maximum potential fluctuations at each monitoring point before and after optimization, the potential fluctuations at monitoring points 1, 3, and 4 all showed significant reductions after optimization. The potential fluctuation at monitoring point 1 dropped directly to near 0V after optimization, the potential fluctuation at monitoring point 3 decreased by 90%, and the potential fluctuation at monitoring point 4 decreased by 50%. The lack of significant changes at monitoring points 2 and 5 is mainly because the optimization location did not cover the entire model. When optimizing only a single power supply node, it inevitably affects the potential fluctuations of other nodes in the entire power network. Considering all power supply nodes comprehensively requires extensive simulation calculations and result predictions; perhaps introducing machine learning methods is a good idea. Current optimization strategy research mainly focuses on the potential fluctuations of a single node, pre-evaluating the voltage fluctuation tolerance threshold of each module, and selecting paths with lower voltage fluctuation tolerance thresholds for focused optimization, which also provides direction for future research.

[0147] The power network optimization method described above for enhancing chip reliability under strong magnetic pulse environments has two main aspects. First, based on the chip's design specifications, an initial power network is designed using EDA tools. This involves maximizing the formation of a closed loop within the initial power network; ensuring that vias in different metal layers are aligned on the same vertical line, transforming the open-loop structure into an L-shaped structure; appropriately increasing redundant metal lines while meeting power supply requirements; and reducing the magnetic flux integration area through a multi-fold structure to obtain the target power network. Second, this method expands the scope of improving the chip's resistance to magnetic interference, considering the impact of external magnetic fields on the chip's power network, and providing a reliability optimization scheme for chip design under strong magnetic pulse environments.

[0148] It should be noted that although the steps of the method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that these steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or a step may be broken down into multiple steps. Furthermore, it is readily understood that these steps may be executed synchronously or asynchronously, for example, in multiple modules / processes / threads.

[0149] Furthermore, this example embodiment also provides a power network optimization device for enhancing chip reliability under strong magnetic pulse environments. (See reference...) Figure 35 As shown, the device 100 may include a design module 101, an optimization module 102, and an output module 103. Wherein:

[0150] Design module 101 is used to design the chip based on the chip's design conditions using EDA tools to obtain the initial power network;

[0151] The optimization module 102 is used to perform a first DRC check on the initial power network. If the check passes, an optimization strategy is selected to optimize the initial power network.

[0152] The output module 103 is used to perform a second DRC check on the optimized initial power network. If the check passes, the target power network is obtained.

[0153] Regarding the apparatus in the above embodiments, the specific manner in which each module performs its operation has been described in detail in the embodiments related to the method, and will not be elaborated upon here.

[0154] It should be noted that although several modules or units for the device used to perform actions have been mentioned in the detailed description above, this division is not mandatory. In fact, according to embodiments of this disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units. Components shown as modules or units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this disclosure according to actual needs. Those skilled in the art can understand and implement this without any inventive effort.

[0155] In exemplary embodiments of this disclosure, a computer-readable storage medium is also provided, having stored thereon a computer program that, when executed by a processor, can implement the steps of the power network optimization method for enhancing chip reliability under strong magnetic pulse environments described in any of the above embodiments. In some possible embodiments, various aspects of the invention can also be implemented as a program product comprising program code that, when run on a terminal device, causes the terminal device to perform the steps of the various exemplary embodiments of the invention described in the section on the power network optimization method for enhancing chip reliability under strong magnetic pulse environments described in this specification.

[0156] In exemplary embodiments of this disclosure, an electronic device is also provided, which may include a processor and a memory for storing executable instructions of the processor. The processor is configured to perform the steps of the power network optimization method for enhancing chip reliability under strong magnetic pulse environments described in any of the above embodiments by executing the executable instructions.

[0157] Those skilled in the art will understand that various aspects of the present invention can be implemented as systems, methods, or program products. Therefore, various aspects of the present invention can be specifically implemented in the following forms: entirely in hardware, entirely in software (including firmware, microcode, etc.), or in a combination of hardware and software, collectively referred to herein as “circuit,” “module,” or “system.”

Claims

1. A power network optimization method for enhancing chip reliability under strong magnetic pulse environments, characterized in that, The method includes: Based on the chip's design specifications, EDA tools are used to design the chip to obtain its initial power network. Within the chip's multi-layered metal network, there are both ring and tree structures. The initial power network of the top two layers, along with the power supply lines connected between the multi-layered metals via vias, forms a tree structure. The power supply lines connecting the multi-layered metals to the functional units via vias form a ring structure. The initial power network connects different layers of metal through vias, transforming the tree structure into a ring structure. The vias are positioned so that the vias connecting the four metal lines in the initial power network structure are on the same vertical line, forming an L-shaped structure. The initial power network undergoes a first DRC check. If it passes, the initial power network is optimized sequentially using strategies one, two, and three. The optimization strategies include: Strategy one: making the loops formed by the power network itself tend to be closed; Strategy two: adding a preset number of redundant metal lines to the power network; Strategy three: using a multi-fold structure in the power network to reduce the integral area, wherein the number of folds is increased in the multi-fold structure. If the initial DRC check fails, the initial power network is corrected based on the error information from the first DRC check; the corrected initial power network then undergoes the first DRC check. A second DRC check is performed on the optimized initial power network. If it passes, the target power network is obtained; if it fails, the optimized initial power network is corrected according to the error information of the second DRC check. The corrected optimized initial power network is then subjected to the second DRC check.

2. A power network optimization device for enhancing chip reliability under strong magnetic pulse environments, characterized in that, The device includes: The design module is used to design the chip based on the chip's design conditions using EDA tools to obtain the initial power network. Within the chip's multi-layered metal network, there are both ring and tree structures. The initial power network of the top two layers and the power supply lines connected between the multi-layered metals by vias form a ring structure. The power supply lines ultimately connected to the functional units after the multi-layered metals are connected by vias also form a ring structure. The initial power network connects different layers of metal through vias, transforming the tree structure into a ring structure. The vias are positioned so that the vias connecting the four metal lines in the initial power network structure are on the same vertical line, forming an L-shaped structure. An optimization module is used to perform a first DRC check on the initial power network. If the check passes, the initial power network is optimized sequentially using strategies one, two, and three. The optimization strategies include: strategy one: making the loops formed by the power network itself tend to be closed; strategy two: adding a preset number of redundant metal lines to the power network; strategy three: using a multi-fold structure in the power network to reduce the integral area. If the check fails, the initial power network is corrected based on the error information from the first DRC check; and the corrected initial power network is then subjected to the first DRC check. The output module is used to perform a second DRC check on the optimized initial power network. If the check passes, the target power network is obtained; if the check fails, the optimized initial power network is corrected according to the error information of the second DRC check; and the corrected optimized initial power network is then subjected to the second DRC check.

3. A computer-readable storage medium having a computer program stored thereon, characterized in that, When executed by the processor, the program implements the steps of the power network optimization method for enhancing chip reliability under strong magnetic pulse environment as described in claim 1.

4. An electronic device, characterized in that, include: processor; as well as Memory for storing the executable instructions of the processor; The processor is configured to execute the steps of the power network optimization method for enhancing chip reliability under strong magnetic pulse environments as described in claim 1 by executing the executable instructions.

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