Complier unit layout port information checking method, computer equipment and storage medium

Abstract

The invention relates to a Complier unit layout port information checking method, computer equipment and a storage medium. The method comprises the steps that a to-be-checked unit layout top layer is acquired; adding first number information to all the pin labels without suffixes in the port information as suffixes; responding to the situation that the first wiring boundary does not exist in the top layer of the unit layout, and outputting prompt information; outputting prompt information in response to the situation that the hierarchy type is rectangular and is a pin metal hierarchy and the coordinates are not located in the first wiring boundary; outputting prompt information in response to the condition that the coordinate of the pin label is not located in the coordinate range of the pin metal layer; outputting prompt information in response to the fact that the serial number information of the pin tag does not correspond to the hierarchical information; and outputting prompt information in response to the fact that the edge of the pin tag does not coincide with the edge of the first wiring boundary. According to the method, the Complier unit layout port information is automatically checked by using the computer program, so that the checking efficiency of the unit layout can be greatly improved.

Description

Technical Field

[0001] The present application relates to integrated circuit design verification, and in particular to a method for checking port information of a compiler unit layout, and also to a computer device and a computer-readable storage medium. Background Art

[0002] In order to shorten the design cycle and reduce the design cost, designers began to use memory compilers (also known as memory compilers) to perform layout for memories such as SRAM (static random access memory) and ROM (read-only memory), changing the way of customizing the layout design of a single capacity. This method facilitates the rapid and efficient generation of memory IPs of various storage capacities. For the layout layout of the memory compiler, it is necessary to prepare the unit layout (leaf cells) that meet certain requirements in advance.

[0003] After the compiler unit layout is drawn according to certain requirements, on the one hand, it will check the splicing problems between unit layouts to avoid DRC problems, and on the other hand, it needs to check the port information, which includes pin metal (pin metal layer) and pin label (pin label). Checking the port information is very important because the correctness of the port information will affect the splicing process of the storage compiler for the Memory IP.

[0004] At present, the port information is generally checked manually, that is, manually opening the cell layout and checking whether the top cell of the cell layout meets the standards according to the requirements. Since each cell layout may have up to dozens of port information, and a set of compiler library cell layouts is large, even up to hundreds; these cell layouts are manually checked, which is time-consuming, cumbersome, and even leads to problems of inspection omissions. Summary of the invention

[0005] Based on this, it is necessary to provide an efficient method for checking the port information of the compiler unit layout.

[0006] A method for checking port information of a compiler unit layout, comprising: obtaining a top layer of a unit layout to be checked, the top layer of the unit layout including port information; adding first numbering information as a suffix to all pin labels without suffixes in the port information; in response to the absence of a first wiring boundary in the top layer of the unit layout, outputting corresponding prompt information; in response to the layer type being a rectangle and being a pin metal layer, and the coordinates not being within the first wiring boundary, outputting corresponding prompt information; in response to the numbering information of the pin label not corresponding to its layer information, outputting corresponding prompt information; in response to the coordinates of the pin label not being within the coordinate range of the corresponding pin metal layer, outputting corresponding prompt information; in response to the coordinates of the pin label not being at the edge of the first wiring boundary, outputting corresponding prompt information; wherein, some or all of the steps of the method are executed using a computer program.

[0007] The above-mentioned method for checking the port information of the compiler unit layout uses a program to automatically check the port information of the compiler unit layout, which can greatly improve the inspection efficiency of the unit layout.

[0008] In one of the embodiments, the method further includes: in response to the presence of layer types other than rectangles and labels in the top layer of the unit layout, outputting corresponding prompt information.

[0009] In one of the embodiments, in response to the numbering information of the pin label not corresponding to its hierarchical information, after the step of outputting corresponding prompt information, the step further includes: removing the suffix added in the step of adding the first numbering information as a suffix.

[0010] In one of the embodiments, in response to the absence of the first wiring boundary in the top layer of the unit layout, the step of outputting corresponding prompt information includes: there is only one wiring boundary with a hierarchy type of rectangle and located at the origin in the top layer of the unit layout.

[0011] In one of the embodiments, the method further includes: in response to the layer whose layer type is a rectangle being not a pin metal layer, outputting corresponding prompt information.

[0012] In one embodiment, in the step of outputting corresponding prompt information in response to the layer type being a rectangle and being a pin metal layer, and the coordinates not being within the first wiring boundary, the output prompt information includes coordinates that are outside the first wiring boundary, the layer type is a rectangle and is a pin metal layer.

[0013] In one embodiment, in response to the numbering information of the pin label not corresponding to its hierarchical information, in the step of outputting corresponding prompt information, the output prompt information includes the coordinates of the pin label not corresponding to its hierarchical information.

[0014] In one of the embodiments, in response to the coordinates of the pin label not being within the coordinate range of the corresponding pin metal layer, in the step of outputting corresponding prompt information, the output prompt information includes the coordinates of the pin label not being within the coordinate range of the corresponding pin metal layer.

[0015] In one embodiment, in the step of outputting corresponding prompt information in response to the coordinates of the pin label not being located at the edge of the first wiring boundary, the output prompt information includes the coordinates of the pin label whose coordinates are not located at the edge of the first wiring boundary.

[0016] In one of the embodiments, in the step of outputting corresponding prompt information in response to the presence of layer types other than rectangles and labels in the top layer of the unit layout, the output prompt information includes coordinates of the layers other than rectangles and labels.

[0017] In one of the embodiments, in the step of outputting corresponding prompt information in response to the layer whose layer type is a rectangle being not a pin metal layer, the output prompt information includes the coordinates of the layer whose layer type is a rectangle being not a pin metal layer.

[0018] In one embodiment, the pin label without a suffix is ​​a label of an internal port.

[0019] In one embodiment, the execution using a computer program is executed using a program written in a skill language.

[0020] It is also necessary to provide a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, the steps in the method of any of the above embodiments are implemented.

[0021] It is also necessary to provide a computer device, including a memory and a processor, wherein a computer program is stored in the memory, and when the processor executes the computer program, the steps in the method described in any of the above embodiments are implemented.

[0022] It is also necessary to provide a computer program product, comprising a computer program, which, when executed by a processor, implements the steps of the method described in any of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to better describe and illustrate the embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more drawings. The additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the embodiments and / or examples currently described, and the best modes of these inventions currently understood.

[0024] Figure 1 It is a schematic diagram of an exemplary Memeory IP composed of various unit layouts;

[0025] Figure 2 is a schematic diagram of a unit layout with an external port at the lower boundary;

[0026] Figure 3 It is a flowchart of a method for checking the layout port information of a compiler unit in one embodiment of the present application. DETAILED DESCRIPTION

[0027] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0029] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0030] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0031] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present invention. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0032] The present application provides a method for automatically checking the port information of the compiler unit layout. By running the program, the specification requirements of the unit layout port information are checked one by one. It can automatically check where the unit layout is unqualified, and can accurately locate the position of the erroneous port information in the unit layout through coordinate prompts, greatly improving the efficiency of unit layout inspection and modification.

[0033] The compiler unit layout needs to be drawn according to certain requirements. Figure 1 It is a schematic diagram of the Memeory IP composed of various unit layouts. There are internal ports and external ports in the unit layout. The external port refers to the port located at the boundary of the Memory IP after the Memory IP is assembled, so it can be connected externally; the internal port refers to the port located inside the Memory IP after the unit layout is assembled into the Memory IP, so it cannot be connected externally. Figure 2 It is a schematic diagram of a cell layout with an external port at the lower boundary. The cell layout Cell A contains a prBoundary (wiring boundary) layer of the level type rectangle (rectangle) located at the origin (i.e. Figure 2The pin metal of the port has a shape type of rectangle and is located on the edge of prBoundary. Figure 2 The pin label is located on the pin metal. Figure 2 In order to make the pin label name clear, the pin label name and the corresponding pin metal are slightly offset. Since the internal port only needs one layer of metal to pin out, there is no need to add suffix information to the pin label name, such as Figure 2 Pin1, PinC, etc. in the figure; however, the external port needs to use multiple layers of metal to produce the pin, and each layer of metal needs to be labeled, so the pin label name needs to be suffixed with corresponding "_a1", "_a2", "_a3", etc. according to the metal layer, for example Figure 2 PinA_a1, PinA_a2, PinA_a3, PinB_a1, PinB_a2, PinB_a3 in . Figure 2 The external port in the device uses three layers of metal pins. There is "PinA_a1" on metal 1, "PinA_a2" on metal 2, and "PinA_a3" on metal 3. These three layers of metal and the three pin labels are also overlapped. Figure 2 The overlapping of PinA_a1, PinA_a2, and PinA_a3 causes the text to overlap, and the overlapping of PinB_a1, PinB_a2, and PinB_a3 causes the text to overlap. The standardization of the port information requirements of Cell A is particularly important. Its correctness is directly related to whether it can be normally recognized by the storage compiler, which in turn affects the storage compiler's ability to splice Memory IP ( Figure 1 ) can the splicing process proceed normally.

[0034] Figure 3 : is a flow chart of a method for checking port information of a compiler unit layout in an embodiment of the present application, comprising the following steps:

[0035] S310, obtaining the top layer of the cell layout to be checked.

[0036] The top level of the unit layout includes port information, which includes pin metal (pin metal level) and pinlable (pin label). Each pin lable should correspond to a pin metal. The pin lable's hierarchical information has the same fields as the corresponding pin metal. For example, if the pin metal is A1, the corresponding pin lable's hierarchical information must be A1text.

[0037] S320, add a suffix to the pin label without a suffix.

[0038] For all pin labels without suffixes in the port information, add the first number information corresponding to the pin label hierarchical information as the suffix in the label name. Since the internal port at the top level of the unit layout only needs one layer of metal to be pinned out, there is no suffix information in the label name of the pin label corresponding to the internal port. In step S320, the layout interface of the unit layout is opened, and the first number information is added as a suffix to the label name of the pin label without a suffix (that is, the pin label of the internal port), thereby unifying the format of the pin label. For example, for a pin label named VSS (when the hierarchical information is A1text), after adding the suffix of the corresponding hierarchical information, the resulting pin label name is VSS_a1.

[0039] S330, determining whether the first wiring boundary exists on the top layer of the obtained cell layout, and if not, reporting an error prompt.

[0040] In one embodiment of the present application, step S330 is to determine whether there is one and only one prBoundary layer at the top level of the unit layout whose layer type (ShapeType) is rectangle and located at the origin (that is, the coordinates are (0, 0)). Only when the judgment result is yes, continue to check the port information at the top level of the unit layout, otherwise an error prompt is given.

[0041] If the judgment result of step S330 is "yes", then the subsequent checks are performed using different judgment logics according to whether the layer type (ShapeType) of each layer in the top layer of the cell layout is rectangle or label. Figure 3 When the level type of a certain level is rectangle, execute step S342, and when the level type is label, execute step S352.

[0042] In one embodiment of the present application, if there is a layer type other than rectangle and label (such as Path, Polygon, etc.) in the top layer of the unit layout, an error message is given.

[0043] S342, determine whether the layer is pin metal, if so, execute step S344, otherwise, report an error prompt.

[0044] If a layer is a rectangle but not a pin metal, an error message will be displayed.

[0045] S344, determining whether the pin metal is located within the first wiring boundary, and if a part of the pin metal structure or the entire pin metal is located outside the first wiring boundary, an error message is given.

[0046] Steps S342 and S344 are to determine whether the layer with layer type of rectangle is pin metal, if not, an error message is given; if so, coordinate calculation is performed to determine whether part of its structure is outside prBoundary, if so, an error message is given.

[0047] It can be understood that step S342 and step S344 must be executed once for each level of the rectangle.

[0048] In another embodiment of the present application, after step S330, for a layer whose layer type is rectangle, it can be simplified to give an error message if the layer is pin metal and the coordinates are not within the prBoundary (ie, part of the structure of the pin metal is or is entirely outside the prBoundary).

[0049] S352, determine whether the numbering information of the pin label corresponds to its hierarchical information, if so, execute step S354, otherwise, report an error.

[0050] Check whether the numbering information of the pin label corresponds to the hierarchical information of the pin label. Assuming that the hierarchical information of a pin label is A1text (i.e., the pin label adopts the A1text hierarchy), if the numbering information of the pin label is a2, it means that it does not correspond and an error message is given; if the numbering information of the pin label is a1, it means that it corresponds to the hierarchical information of the pin label.

[0051] S354, determine whether the coordinates of the pin label are within the coordinate range of the corresponding pin metal, if so, execute step S356, otherwise, report an error prompt.

[0052] The hierarchical information of the pin label corresponds to the pin metal. For example, if the hierarchical information of the pin label is A1text, the corresponding pin metal is the A1 layer. In the unit layout, the pin metal is a rectangle, and its coordinate range can be determined based on its two diagonals (such as the lower left corner and the upper right corner of the rectangle). The coordinates of the pin label are coordinate points. Through coordinate comparison, if the coordinates of the pin label are not within the coordinate range of the corresponding pin metal, an error prompt will be given.

[0053] S356, determine whether the coordinates of the pin label are located at the edge of the first wiring boundary, if so, execute step S356, otherwise, report an error prompt.

[0054] By calculating the coordinates, it is determined whether the pin label is at the edge of prBoundary. If the pin label is at the edge of prBoundary, according to step S344, the pin metal will not be outside the prBoundary under normal circumstances, and since the pin label is inside the pin metal, the pin label is at the edge of prBoundary, which means that the corresponding pin metal is also adjacent to the prBoundary.

[0055] It can be understood that for each label level, step S352, step S354 and step S356 must be executed once.

[0056] S360, remove the suffix added in the pin label.

[0057] The suffix added in step S320 is removed.

[0058] In the above-mentioned method for checking the port information of the compiler unit layout, at least some steps are automatically performed using a computer program, and the automatic checking of the port information of the compiler unit layout can greatly improve the inspection efficiency of the unit layout.

[0059] In one embodiment of the present application, when there are layer types other than rectangle and label in the layer at the top level of the unit layout, the output error prompt includes the coordinates of the abnormal layer. In one embodiment of the present application, the error prompt output by step S342 includes the coordinates of the layer whose layer type is rectangle but not pin metal. In one embodiment of the present application, the error prompt output by step S344 includes the coordinates of the pin metal outside the prBoundary. In one embodiment of the present application, the error prompt output by step S352 includes the coordinates of the pin label whose numbering information does not correspond to the layer information. In one embodiment of the present application, the error prompt output by step S354 includes the coordinates of the pin label that is not within the coordinate range of the corresponding pin metal. In one embodiment of the present application, the error prompt output by step S356 includes the coordinates of the pin label whose coordinates are not at the edge of prBoundary.

[0060] In one embodiment of the present application, before step S360, a step of summarizing the error information prompted during the above inspection process is also included. The summarized error information can clearly indicate which unqualified elements exist in the port information of the unit layout, as well as the specific coordinates of the unqualified places. Engineers can modify the port information of the unit layout based on the summarized error information.

[0061] In one embodiment of the present application, if the aforementioned computer program for checking the port information of the Complier unit layout provided by the present application fails to run successfully, log information is generated. When the program fails to read the layout data, the program will fail to run successfully (for example, when the layout data is missing, the program will fail to run successfully). The log information can also assist engineers in modifying the Complier unit layout.

[0062] In one embodiment of the present application, the aforementioned computer program for checking the layout port information of the compiler unit can be written in a skill language.

[0063] It should be understood that, although the various steps in the flowchart of the present application are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowchart of the present application may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0064] Those of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in the present application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory or optical memory, etc. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM).

[0065] The present application also provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps in the method described in any of the above embodiments are implemented.

[0066] The present application also provides a computer device, including a memory and a processor, wherein a computer program is stored in the memory, and when the processor executes the computer program, the steps in the method described in any of the above embodiments are implemented.

[0067] The present application also provides a computer program product, including a computer program, which implements the steps of the method described in any of the above embodiments when executed by a processor.

[0068] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0069] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0070] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A method for checking port information of a compiler unit layout, comprising: Obtaining a top layer of a unit layout to be checked, wherein the top layer of the unit layout includes port information; For all pin labels without a suffix in the port information, add the first number information as a suffix; In response to the absence of a first wiring boundary in the top layer of the cell layout, outputting corresponding prompt information; In response to the layer type being a rectangle and being a pin metal layer, and the coordinates not being within the first wiring boundary, outputting corresponding prompt information; In response to the numbering information of the pin label not corresponding to its hierarchical information, outputting corresponding prompt information; In response to the coordinates of the pin label not being within the coordinate range of the corresponding pin metal layer, outputting corresponding prompt information; In response to the coordinates of the pin label not being located at the edge of the first wiring boundary, outputting corresponding prompt information; Part or all of the steps of the method are executed using a computer program.

2. The method for checking the port information of the compiler unit layout according to claim 1, characterized in that: Also includes: In response to the presence of layer types other than rectangles and labels in the top layer of the unit layout, corresponding prompt information is output.

3. The method for checking the port information of the compiler unit layout according to claim 1, characterized in that: After the step of outputting corresponding prompt information in response to the numbering information of the pin label not corresponding to its hierarchical information, the method further includes: removing the suffix added in the step of adding the first numbering information as a suffix.

4. The method for checking the port information of the compiler unit layout according to claim 1, characterized in that: In response to the absence of the first wiring boundary in the top layer of the unit layout, the step of outputting corresponding prompt information includes: there is only one wiring boundary with a layer type of rectangle and located at the origin in the top layer of the unit layout.

5. The method for checking the layout port information of a compiler unit according to claim 2, characterized in that: Also includes: In response to the layer whose layer type is a rectangle being not a pin metal layer, corresponding prompt information is output.

6. The method for checking the port information of the compiler unit layout according to claim 5, characterized in that: In the step of outputting corresponding prompt information in response to the layer type being a rectangle and being a pin metal layer, and the coordinates not being located within the first wiring boundary, the output prompt information includes coordinates that are located outside the first wiring boundary, the layer type is a rectangle and is a pin metal layer; and / or In response to the numbering information of the pin label not corresponding to its hierarchical information, in the step of outputting corresponding prompt information, the output prompt information includes the coordinates of the pin label not corresponding to its hierarchical information; and / or In response to the coordinates of the pin label not being within the coordinate range of the corresponding pin metal layer, in the step of outputting corresponding prompt information, the output prompt information includes the coordinates of the pin label not being within the coordinate range of the corresponding pin metal layer; and / or In the step of outputting corresponding prompt information in response to the coordinates of the pin label not being located at the edge of the first wiring boundary, the output prompt information includes the coordinates of the pin label whose coordinates are not located at the edge of the first wiring boundary; and / or In the step of outputting corresponding prompt information in response to the presence of layer types other than rectangles and labels in the top layer of the unit layout, the output prompt information includes coordinates of the layers other than rectangles and labels; and / or In the step of outputting corresponding prompt information in response to the layer whose layer type is a rectangle being not a pin metal layer, the output prompt information includes the coordinates of the layer whose layer type is a rectangle and which is not a pin metal layer.

7. The method for checking the port information of the compiler unit layout according to claim 1, characterized in that: The pin labels without a suffix are the labels of the internal ports.

8. The method for checking the port information of the compiler unit layout according to claim 1, characterized in that: The execution using a computer program refers to execution using a program written in a skill language.

9. A computer device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps in the method according to any one of claims 1 to 8 when executing the computer program.

10. A computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps in the method according to any one of claims 1 to 8.

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