Verification environment generation method, verification environment generation device, function verification method and function verification system

Abstract

The invention relates to the technical field of pre-silicon verification, and discloses a verification environment generation method and device and a function verification method and system.The method comprises the steps that a target configuration file suitable for a to-be-tested chip model is read, and the target configuration file comprises field information; the field information is at least used for representing hierarchical information and a UPF file path of a target power domain module which is currently in an enabled state in the at least one power domain module; according to the target configuration file, generating environment configuration data of a to-be-tested chip model at least comprising UPF loading information and power supply information of a target power domain module; and according to the UPF loading information, loading the UPF file under the UPF file path into a target power domain module represented by the hierarchical information, and configuring a power supply for the target power domain module based on the power supply information to generate a verification environment for the to-be-tested chip model. According to the technical scheme provided by one or more embodiments, the verification environment can be automatically generated.

Description

Technical Field

[0001] The present application relates to the field of pre-silicon verification technology, and in particular to a verification environment generation method, device, function verification method and system. Background Art

[0002] With the continuous development of chip design, the low-power design of chips has always attracted much attention. Pre-silicon simulation verification of the low-power design of chips has become an urgent need for low-power design. Pre-silicon simulation verification of low-power design usually requires the construction of a verification environment.

[0003] By verifying the chip's functionality through a verification environment, it is possible to promptly discover the chip's design and functional defects in the early stages of verification, and to promptly modify the chip to match the defects, which is beneficial to improving chip design efficiency. However, the verification environment that is built needs to meet verification requirements for different configurations.

[0004] Currently, changes in verification requirements for different configurations or different levels of environments mostly require manual operations, such as manually loading UPF files adapted to different verification environments and rebuilding different verification environments to respond to changes in chip design and verification changes. This method cannot avoid errors in the environment construction process, and the verification efficiency for multi-level and multi-requirement verification objects is greatly reduced. In view of this, how to automatically generate a verification environment to meet the verification requirements adapted to different configurations has become a research direction for low-power design. Summary of the invention

[0005] The present application provides a method, device, function verification method and system for generating a verification environment, which can automatically generate a verification environment to meet verification requirements adapted to different configurations.

[0006] In a first aspect, the present application provides a method for generating a verification environment, the method being applied to a chip model to be tested, the chip model to be tested including at least one power domain module, the method comprising: reading a target configuration file applicable to the chip model to be tested, the target configuration file including a specified number of field information, the specified number of field information being at least used to characterize the hierarchical information and UPF file path of a target power domain module that is currently enabled in the at least one power domain module; generating environment configuration data for the chip model to be tested according to the target configuration file, the environment configuration data including at least UPF loading information and power supply information of the target power domain module; loading the UPF file under the UPF file path into the target power domain module represented by the hierarchical information according to the UPF loading information, and configuring power for the target power domain module based on the power supply information, so as to generate a verification environment for the chip model to be tested.

[0007] The technical solution provided by this embodiment of the present application is for a chip model to be tested including at least one power domain module, the target configuration file of the chip model to be tested is read, the power domain module in the enabled state represented in the target configuration file is determined as the target power domain module to be verified, and the environment configuration data of the chip model to be tested is generated according to the hierarchical structure information and UPF file path of the target power domain module represented in the target configuration file. Based on the generated environment configuration data, the UPF file is obtained under the UPF file path and loaded into the target power domain module, and the power supply is configured for the target power domain module, so as to generate a verification environment for the chip model to be tested. It can be seen that the technical solution provided by this embodiment of the present application does not need to manually determine and load the UPF file of the target power domain module, but can automatically analyze the information represented by the target configuration file and obtain the required UPF file, so as to complete the generation of the verification environment. This process reduces human errors, and when verifying different power domain modules, the relevant information represented in the target configuration file will change accordingly, and the new verification environment can be automatically generated based on the changed target configuration file, thereby improving the efficiency and accuracy of the verification environment generation, thereby ensuring the smooth progress of chip verification.

[0008] In a possible implementation, the target configuration file is generated in the following manner: obtaining the hierarchical information of each power domain module in the chip model to be tested, and obtaining the UPF file path of each power domain module; for any power domain module, determining whether the power domain module is set to an enabled state during the current verification process, and determining the enabled state information of the power domain module based on the hierarchical information, UPF file path and enabled state information of the power domain module; generating configuration entries of the power domain module based on the configuration entries of each power domain module in the chip model to be tested, generating the target configuration file of the chip model to be tested.

[0009] The technical solution provided in this embodiment of the present application generates configuration items of each power domain module by acquiring the hierarchical information, UPF file path and enable status information of each power domain module, and generates a target configuration file of the chip model to be tested based on the configuration items of each power domain module. By automatically generating the target configuration file, the generation efficiency of the UPF environment can be greatly improved.

[0010] In one possible implementation, based on the judgment result, determining the enable status information of the power domain module includes: if the power domain module is set to an enabled state during the current verification process, setting the enable status information of the power domain module to a first value; if the power domain module is set to a disabled state during the current verification process, setting the enable status information of the power domain module to a second value; wherein the first value and the second value are different values.

[0011] The technical solution provided in this embodiment of the present application expresses the enable status information of each power domain module through different numerical values, dynamically changes whether the power domain module is in an enabled state, and adjusts the target configuration file, thereby improving the generation efficiency of the UPF file.

[0012] In a possible implementation, generating environmental configuration data of the chip model to be tested according to the target configuration file includes: associating the hierarchical information and UPF file path of the target power domain module, and generating UPF loading information of the target power domain module based on the association result; reading the UPF file under the UPF file path, and identifying the power supply information of the target power domain module from the UPF file; and writing the UPF loading information and power supply information of the target power domain module into the environmental configuration data of the chip model to be tested.

[0013] In a possible implementation, the environment configuration data also includes preset compilation options; wherein, when the verification environment is first generated, the preset compilation options are integrated into the verification environment generated for the first time, and if the verification environment generated for the first time undergoes version iteration, the preset compilation options are retained in the verification environment after the version iteration.

[0014] The technical solution provided in this implementation mode of the present application obtains UPF loading information and power supply information by automatically parsing the target configuration file, thereby providing a convenient basis for the subsequent generation environment.

[0015] In a possible implementation, in the process of generating the environmental configuration data of the chip model to be tested, the method further includes: if the target configuration file cannot be obtained, generating an error message indicating that the target configuration file is missing; if there is no UPF file under the UPF file path, generating an error message indicating that the UPF file is missing; if there is no power supply information in the UPF file under the UPF file path, generating an error message indicating that the power supply information is missing.

[0016] The technical solution provided in this implementation mode of the present application can report errors for abnormal situations during the process of generating environment configuration data, avoiding the need to wait until the environment is compiled to report errors, which would cause delays in progress, and saving debugging time for environment compilation.

[0017] In one possible implementation, configuring power for the target power domain module based on the power supply information includes: if the chip model to be tested includes a first target power domain module and a second target power domain module in an enabled state, and the first target power domain module is located at an upper level of the second target power domain module, after configuring power for the first target power domain module based on the power supply information of the first target power domain module, then configuring power for the second target power domain module based on the power supply information of the second target power domain module.

[0018] The technical solution provided in this implementation of the present application determines the power distribution order of the power domain modules in a nested relationship, ensures that the power domain modules in a nested relationship can be powered on and off normally, and thus ensures that the verification environment can be smoothly generated.

[0019] In a possible implementation, the hierarchical relationship between the first target power domain module and the second target power domain module is determined by respective hierarchical information of the first target power domain module and the second target power domain module, wherein the hierarchical information of the first target power domain module is included in the hierarchical information of the second target power domain module.

[0020] The technical solution provided in this embodiment of the present application can quickly identify the nested relationship between different power domain modules through hierarchical information, thereby improving the efficiency of power configuration.

[0021] In a possible implementation, after generating a verification environment for the chip model to be tested, the method further includes: if a version iteration occurs in the verification environment, reading the target configuration file after the version iteration, and regenerating the environment configuration data based on the target configuration file after the version iteration; based on the regenerated environment configuration data, loading the UPF file and performing power configuration on the target power domain module that is currently in an enabled state to regenerate the verification environment.

[0022] The technical solution provided in this implementation mode of the present application only requires dynamic adjustment of the target configuration file when the verification project changes, and the subsequent process is automated, thereby greatly improving the convenience of environment generation during version iteration.

[0023] The second aspect of the present application provides a device for generating a verification environment, the device comprising: a configuration file reading unit, used to read a target configuration file applicable to a chip model to be tested, the target configuration file comprising a specified number of field information, the specified number of field information being used at least to characterize the hierarchical information and UPF file path of a target power domain module that is currently enabled in at least one power domain module of the chip model to be tested; a configuration data generating unit, used to generate environmental configuration data of the chip model to be tested according to the target configuration file, the environmental configuration data comprising at least UPF loading information and power supply information of the target power domain module; a verification environment generating unit, used to load the UPF file under the UPF file path into the target power domain module represented by the hierarchical information according to the UPF loading information, and configure power for the target power domain module based on the power supply information, so as to generate a verification environment for the chip model to be tested.

[0024] A third aspect of the present application provides a functional verification method, which is applied to a chip model to be tested, wherein the chip model to be tested includes at least one power domain module, and the method includes: reading a target configuration file applicable to the chip model to be tested, and generating environmental configuration data of the chip model to be tested according to the target configuration file; wherein the target configuration file is at least used to characterize the hierarchical information and UPF file path of a target power domain module that is currently enabled in the at least one power domain module, and the environmental configuration data includes at least UPF loading information and power supply information of the target power domain module; according to the UPF loading information, loading the UPF file under the UPF file path into the target power domain module represented by the hierarchical information, and configuring power for the target power domain module based on the power supply information to generate a verification environment for the chip model to be tested; compiling the generated verification environment, and after completing the environment compilation, sending an excitation signal to the target power domain module through the driver component of the target power domain module to perform functional verification on the target power domain module.

[0025] A functional verification method provided in the third aspect of the present application can automatically analyze the information represented by the target configuration file and obtain the required UPF file through the aforementioned verification environment generation method, thereby completing the generation of the verification environment. On this basis, by compiling the generated verification environment and providing corresponding stimulus signals, the overall process of functional verification can be realized, thereby improving the overall efficiency of functional verification.

[0026] The fourth aspect of the present application provides a function verification system, which includes a verification environment generating device and a function verification device, wherein: the verification environment generating device is used to read a target configuration file applicable to the chip model to be tested, and generate environment configuration data of the chip model to be tested according to the target configuration file; wherein the target configuration file is at least used to characterize the hierarchical information and UPF file path of the target power domain module that is currently in an enabled state in the at least one power domain module, and the environment configuration data at least includes UPF loading information and power supply information of the target power domain module; according to the UPF loading information, the UPF file under the UPF file path is loaded into the target power domain module represented by the hierarchical information, and the power supply is configured for the target power domain module based on the power supply information, so as to generate a verification environment for the chip model to be tested; the function verification device is used to compile the generated verification environment, and after completing the environment compilation, send an excitation signal to the target power domain module through the driver component of the target power domain module, so as to perform functional verification on the target power domain module. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0028] Figure 1 A step diagram of a method for generating a verification environment provided in an embodiment of the present application; Figure 2 A schematic diagram of the composition of configuration items of a target configuration file provided by one embodiment of the present application; Figure 3 A schematic diagram of a configuration for generating a verification environment provided by an embodiment of the present application; Figure 4 A schematic diagram of a process for generating a verification environment provided by an embodiment of the present application; Figure 5 A configuration diagram for generating an IP-level based verification environment provided by an embodiment of the present application; Figure 6 A configuration diagram for generating a SOC-level verification environment provided by an embodiment of the present application; Figure 7 A schematic diagram of the structure of a verification environment generation device provided by an embodiment of the present application; Figure 8A schematic diagram of the steps of a function verification method provided by an embodiment of the present application; Fig. 9 A schematic diagram of the structure of a function verification system provided by an embodiment of the present application; Fig.10 A schematic diagram of the structure of a verification environment generation device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0029] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0030] In addition, the descriptions involving "first", "second", etc. in this application are for descriptive purposes only and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the embodiments of the present application, unless otherwise specified, "multiple" means two or more. In addition, the use of "based on" or "according to" means openness and inclusiveness, because the process, steps, calculations or other actions "based on" or "according to" one or more of the conditions or values ​​can be based on additional conditions or beyond the described values ​​in practice.

[0031] With the continuous development of the chip industry, the requirements for low-power chip design are becoming more and more stringent. Pre-silicon simulation verification of low-power design is an urgent need for low-power verification of IP (Intellectual Property) or SoC (System on a Chip). By setting up a verification environment and building a virtual power network, it is possible to discover design defects and functional defects of the chip in the early stage of verification, which is conducive to the rapid modification and regression verification of the chip. However, for the increasingly detailed verification scale division of low-power design, verification projects with different configurations need to be verified.

[0032] In the related technologies, most of them currently need to introduce manual operations, manually load UPF (Unified Power Format) files adapted to different verification environments, and re-build the corresponding different verification environments at the top level of verification to respond to changes brought about by chip design and verification changes. This method has poor compatibility with verification requirements of different configurations, and cannot meet the adaptation of verification environments of different levels and configurations, resulting in a long time for setting up the initial environment each time verification is performed, resulting in reduced verification efficiency. In addition, if an error message appears in the generated verification environment, it is usually reported after the environment is compiled, and the verification environment needs to be modified and recompiled, which will also lead to reduced verification efficiency and extended verification cycle.

[0033] In view of this, the present application provides one or more implementations, providing a method, device and apparatus for generating a verification environment, which can automatically generate a verification environment to adapt to verification requirements of different configurations.

[0034] See also Figure 1 , the present application provides a method for generating a verification environment, the method is applied to a chip model to be tested, the chip model to be tested includes at least one power domain module, wherein the chip model to be tested may have different architectures based on different verification scenarios. For example, in an IP-level verification scenario, the chip model to be tested may include a verified power domain module; and in a SoC-level verification scenario, the chip model to be tested may include a plurality of different power domain modules, and these power domain modules may be connected in a preset manner, thereby jointly realizing system-level chip functions. In this embodiment, the chip model to be tested may be a chip model built in a simulation environment, and a corresponding verification environment may be established for one or more power domain modules in the chip model to be tested, so as to further perform functional verification in the established verification environment. Specifically, the method may include the following multiple steps: S11: Read a target configuration file applicable to the chip model to be tested, wherein the target configuration file includes a specified number of field information, and the specified number of field information is at least used to characterize the hierarchical information and UPF file path of the target power domain module that is currently enabled in at least one power domain module.

[0035] In this embodiment, the target configuration file may be a file generated in a fixed format. Generally speaking, the target configuration file may include a specified number of field information. Through the specified number of field information, multiple parameters of the power domain module in the chip model to be tested can be characterized. Specifically, the chip model to be tested includes at least one power domain module, and the power domain module is the area inside the chip model to be tested that distributes and manages power. For different verification scenarios, the power domain modules that need to be functionally verified in the chip model to be tested may also be different. For example, in an IP-level verification scenario, usually only one power domain module in the chip model to be tested will be functionally verified. In a SoC-level verification scenario, usually each power domain module in the chip model to be tested will be functionally verified. In this embodiment, the target power domain module may be one or more power domain modules to be verified.

[0036] In this embodiment, the target configuration file can be represented by a CSV (Comma-Separated Values, plain text file) format. In the CSV file, a specified number of field information may be included, and the field information at least includes information representing the hierarchical path of the target power domain module and information about the UPF file path. Among them, the specified number of field information may be three field information, for example: an enable field representing the enable state of the power domain module, an inst_path field representing the instantiation hierarchical information of the power domain module, and an upf_file field representing the UPF file path of the power domain module. Of course, as the verification scenario changes, the target configuration file may also contain more or less field information. The present application does not limit the number of field information contained in the target configuration file. Those skilled in the art, after understanding the essence of the technical solution of the present application, may simply deform and transform the number of field information in the target configuration file, or even the composition of the field information, but the content after deformation and transformation should still fall within the scope of protection of the present application.

[0037] In this embodiment, the target configuration file can be automatically generated based on certain rules. For example, according to the preset information of the chip model to be tested, a target configuration file including the configuration items of the power domain module can be automatically generated. Specifically, the preset information of the chip model to be tested is the hierarchical information, UPF file path and enable status information of each power domain module in the chip model to be tested. Among them, for the determination of the enable status information of each power domain module, it is necessary to determine whether the power domain module is set to an enabled state during the current verification process for any power domain module, and determine the enable status information of the power domain module based on the judgment result. Specifically, if the power domain module is set to an enabled state during the current verification process, the enable status information of the power domain module is set to a first value, such as 1, and if the power domain module is set to a non-enabled state during the current verification process, the enable status information of the power domain module is set to a second value, such as 0. The technical solution provided by this embodiment of the present application expresses the enable status information of each power domain module by different numerical values ​​to adjust the target configuration file, thereby improving the generation efficiency of the UPF file.

[0038] In this embodiment, the configuration parameters of a power domain module can be described together by enabling status information, hierarchy information and UPF file path. In view of this, enabling status information, hierarchy information and UPF file path can constitute a configuration entry of a power domain module. In the target configuration file, configuration entries of multiple power domain modules can be included, but the values ​​represented by the enabling status information in the configuration entry will be different depending on the verification scenario. The technical solution provided in this embodiment of the present application can greatly improve the generation efficiency of the UPF environment by generating a target configuration file.

[0039] In one embodiment, see Figure 2 The configuration entries specifically include enable field entries, inst_path field entries and upf_file field entries. Specifically, the enable field entry is used to represent the enable status information of all power domain modules, the inst_path field entry is used to represent the hierarchical information corresponding to all power domain modules, and the upf_file field entry is used to represent the UPF file path corresponding to all power domain modules. Among them, the power domain module with enable being 1 is the target power domain module that needs to generate a verification environment, and the power domain module with enable being 0 is the power domain module that does not need to generate a verification environment.

[0040] For example, the module identifier of power domain module A is dutA, and the corresponding enable value is 1, indicating that power domain module A is in an enabled state and is the target power domain module for which a verification environment needs to be generated; upf_file is DUT / A / duta.upf, indicating that the UPF file path of power domain module A is DUT / A / duta.upf. The inst_path corresponding to power domain module A is test_top.dutA, indicating the hierarchical information of power domain module A. If the inst_path corresponding to power domain module B is test_top.dutA.dutB, it means that power domain module A is the upper-level module of power domain module B.

[0041] S13: Generate environmental configuration data of the chip model to be tested according to the target configuration file, wherein the environmental configuration data at least includes UPF loading information and power supply information of the target power domain module.

[0042] In this embodiment, based on the target configuration file obtained in S11, the field information contained in the target configuration file is read to generate the environment configuration data of the chip model to be tested. Among them, the environment configuration data at least includes the UPF loading information and the power supply information of the target power domain module. Specifically, the hierarchical information and UPF file path of the target power domain module in the configuration entry of the target configuration file are read. First, the hierarchical information and UPF file path of the target power domain module are associated, and the UPF loading information of the target power domain module is generated based on the association result. Then, the UPF file under the UPF file path of the target power domain module is read, and the power supply information of the target power domain module is identified from the UPF file, and the UPF loading information and power supply information of the target power domain module are written into the environment configuration data of the chip model to be tested. Subsequently, according to the environment configuration data, the verification environment of the target power domain module can be generated. The technical solution provided by this embodiment of the present application automatically parses the target configuration file to obtain the UPF loading information and power supply information, which provides a convenient basis for the subsequent generation of the environment.

[0043] It should be noted that the above-mentioned environment configuration data also includes preset compilation options, which include common instructions required to generate a simulation verification environment, such as instructions for specifying compilation principles, error reporting and other information: '-lps_relax_1801', '-lps_log_verboselps.log', '-lps_verbose5'. When the verification environment is generated for the first time, the preset compilation options are integrated into the verification environment generated for the first time, and if the verification environment generated for the first time undergoes version iteration, that is, the verification project sends changes and the verification environment needs to be regenerated, then the preset compilation options are still retained in the verification environment generated after the version iteration. In addition, the preset compilation options also include the load instruction for loading the UPF file.

[0044] For example, please refer to Figure 3 , the csv file is the target configuration file of the chip model to be tested, which includes the enable field entry, inst_path field entry and upf_file field entry, which are used to characterize the hierarchical information, UPF file path and enable status information corresponding to each power domain module. CPU (Central Processing Unit), GPU (Graphics Processing Unit), DEVICES (peripheral devices), DDR (Double Data Rate SDRAM), scp (system control processor) are multiple power domain modules contained in the chip model to be tested. Run the CSV file to automatically generate the environmental configuration data of the chip model to be tested, including load*.upf, Supply VDD / VSS and preset compilation options. Among them, load*.upf is the UPF loading information of the target power domain module, and Supply VDD / VSS is the power supply information of the target power domain module.

[0045] S15: According to the UPF loading information, the UPF file under the UPF file path is loaded into the target power domain module represented by the hierarchical information, and power is configured for the target power domain module based on the power supply information to generate a verification environment for the chip model to be tested.

[0046] In this embodiment, the UPF loading information, power supply information and preset compilation options obtained in S13 are placed in the simulation directory, and the verification environment is generated according to the current environment structure. According to the UPF loading information obtained in S13, the UPF file under the UPF file path of the target power domain module is loaded into the target power domain module represented by the hierarchical information in the target configuration file through the load instruction, and the load instruction can be stored in the compilation option file. Among them, the compilation option file can be a file for storing various compilation options and execution instructions. Generally speaking, the compilation option file can be loaded into the verification environment generated for the first time, and when the verification environment is changed later, the compilation option file does not need to be overwritten and loaded. In practical applications, the compilation options and execution instructions in the compilation option file can be the options and instructions required by the verification environment during normal operation, so as to ensure that the verification environment can operate normally. At the same time, according to the power supply information obtained in S13, in addition to the power supply value for the target power domain module, the corresponding power supply instruction will also be carried. For example, the power supply information can include power supply instructions of supply on or supply off, and can also include specific power supply values ​​of VDD and VSS.

[0047] In addition, in the present embodiment, if an abnormal situation occurs during the process of generating the environment configuration data in step S13, an error may be reported in the S13 stage. Specifically, if the target configuration file cannot be obtained, an error message "csv error" is generated to indicate the missing target configuration file, and the key information log (KeyLogInformation, key log information) of "csv error" is printed in the current running window, for example: '"xxx.csv" no such file or directory.'; if there is no UPF file under the UPF file path, an error message "upf_fileerror" is generated to indicate the missing UPF file, and the key information log of "upf_fileerror" is printed in the current running window, for example: '"xxx" is NOT aupffile, plzcheck.'; if there is no power supply information in the UPF file under the UPF file path, an error message "VDD / VSS error" is generated to indicate the missing power supply information, and the key information log of "VDD / VSS error" is printed in the current running window, for example: '"xxx" do not include VDD and VSS.'. The above error information is displayed through the simulation log so that the chip model to be tested can be checked in time to make correct adjustments to the target configuration file. The technical solution provided by this embodiment of the present application can report errors for abnormal situations during the process of generating environmental configuration data, avoiding the need to wait until the environment is compiled to report errors, thereby delaying the progress and saving debugging time for environmental compilation.

[0048] In one embodiment, if there are multiple target power domain modules in a nested relationship, the power supply is configured for the target power domain modules in sequence. Specifically, if the first target power domain module and the second target power domain module are both in an enabled state, and the first target power domain module is at the upper level of the second target power domain module, it is necessary to first power on the first target power domain module, and then power on the second target power domain module. The technical solution provided in this embodiment of the present application determines the power distribution order of the power domain modules in a nested relationship, ensures that the power domain modules in a nested relationship can be powered on and off normally, and thus ensures that the verification environment can be smoothly generated.

[0049] In one embodiment, the hierarchical relationship between the target power domain modules is determined according to their respective hierarchical information. Specifically, if the first target power domain module is at the upper level of the second target power domain module, the hierarchical information of the first target power domain module is included in the hierarchical information of the second target power domain module. For example: power domain module A is at the upper level of power domain module B, the inst_path corresponding to power domain module A is test_top.dutA, and the inst_path corresponding to power domain module B is test_top.dutA.dutB. It can be concluded that the path of power domain module A is included in the path of power domain module B, which means that power domain module A is the upper level module of power domain module B. In the process of power configuration for power domain module A and power domain module B, it is necessary to distribute power to power domain module A first, and then to power domain module B. The technical solution provided by this embodiment of the present application can quickly identify the nested relationship between different power domain modules through hierarchical information, thereby improving the efficiency of power configuration.

[0050] In one embodiment, after the verification environment is generated by the chip model to be tested, when the verification project changes, the verification environment needs to be regenerated. If the verification environment undergoes version iteration, the target configuration file after the version iteration is read, and the environment configuration data is regenerated based on the target configuration file after the version iteration, and according to the regenerated environment configuration data, the target power domain module currently in the enabled state is loaded with UPF files and power configuration to regenerate the verification environment. Specifically, if the verification environment is regenerated for different verification levels of the same project or verification versions of different verification requirements of the same verification level, it is only necessary to modify the information corresponding to the enable field in the corresponding target configuration file, and the generation of a new verification environment can be automatically realized later. If the verification environment is regenerated for different verification levels of different projects or verification versions of verification requirements, it is only necessary to modify the information corresponding to the enable field, inst_path field and upf_file field in the target configuration file, and the generation of a new verification environment can be automatically realized later. The technical solution provided by this embodiment of the present application only needs to dynamically adjust the target configuration file when the verification project changes, and the subsequent process automation is realized, thereby greatly improving the convenience of environment generation during version iteration.

[0051] For example, see Figure 4 The present application provides an embodiment of a method for generating a verification environment using the above-mentioned method. Figure 4 The steps are executed: In this embodiment, a basic verification environment structure is first constructed, such as an IP-level verification environment (module-level verification environment) or a SOC-level verification environment (system-level verification environment), and the UPF environment is automatically constructed based on the above basic verification environment structure. First, according to the division of the independent power domain modules by the current chip model to be tested, the enable state, UPF file path and hierarchical information of each power domain module corresponding to each power domain module are obtained, and a CSV file is generated as a target configuration file according to the above three configuration items, wherein the CSV file includes three types of field information: enable field information, inst_path field information, and upf_file field information, and multiple script files that can generate a verification environment are generated according to the CSV file, such as test.upf, upf_chip_tb.v, upf.flist (the prefix names of .upf files, .v files, and .flist files can be changed as needed), and the above three script files are placed in the verification environment simulation directory to generate the verification environment. Among them, test.upf contains UPF loading information, and the UPF loading information is loaded into the corresponding power domain module through the loading instruction in upf.flist, upf_chip_tb.v contains power supply information VDD / VSS, and the power supply information VDD / VSS is loaded into the corresponding power domain module through the supply on / off instruction provided in upf_chip_tb.v (supplyon / off is determined by VDD / VSS, if the power supply information is VDD, it corresponds to the supply on instruction, if the power supply information is VSS, it corresponds to the supply off instruction), upf.flist is the aforementioned compilation option file, which at least includes the preset compilation options generated for simulation verification and the load instruction for loading the UPF loading information. Among them, the preset compilation options are some options provided according to the IEEE 1801 (official IEEE standard name of the UPF standard) rules that can be used to specify compilation principles, error messages and other information during the UPF simulation process, such as: '-lps_relax_1801', '-lps_log_verboselps.log', '-lps_verbose5', etc. During the verification environment generation process, if an error message appears in the print log, the three field information corresponding to the above-mentioned power domain module is adjusted in time according to the error message, and the verification environment is rebuilt. After the verification environment of this verification project is generated, if other verification projects or verification levels need to generate a new verification environment, it is only necessary to modify the three field information accordingly according to the requirements of the CSV file, and re-output the CSV file to perform the same verification environment generation process as the above process.

[0052] It should be noted that the file identifier of the script file *.upf for generating the verification environment should be consistent with the name load*upf corresponding to the load instruction in upf.flist for loading UPF loading information. For example, the load instruction corresponding to test.upf should be 'load*test.upf'.

[0053] In one embodiment, see Figure 5 , automatically build the verification environment based on the IP-level environment structure. Specifically, the IP-level environment structure is often used to build a verification environment in which the chip model to be tested contains only one target power domain module. The information of the target power domain module of the chip model to be tested can be determined through the testcase module, and the three configuration items of the target power domain module are obtained. A CSV file is generated through the compiler module, and the CSV file is run to generate three script files that can generate the verification environment: test.upf, upf_chip_tb.v, and upf.flist. The load instruction 'load*test.upf' of test.upf is written into the upf.flist file and the load instruction is executed. The power supply is configured for the target power domain module according to the supply on / off instruction in upf_chip_tb.v. Put the above three script files into the simulation running directory to generate the verification environment.

[0054] In one embodiment, see Figure 6, automatically build the verification environment based on the SOC-level verification environment. Specifically, the SOC-level verification environment is often used to build a verification environment in which the chip model to be tested contains multiple target power domain modules, wherein the chip model to be tested contains two target power domain modules with nested levels, and the first target power domain module is located at the upper level of the second target power domain module. Similarly, obtain the three configuration items of the chip model to be tested, and generate a CSV file through the compiler module, run the CSV file to generate three script files that can generate the verification environment: test.upf, upf_chip_tb.v, upf.flist, write the load instruction 'load*test.upf' of test.upf into the upf.flist file and execute the load instruction, and configure the power supply for the target power domain module according to the supply on / off instruction in upf_chip_tb.v. Put the above three script files into the simulation running directory to generate the verification environment. Among them, when configuring power for the target power domain module according to the supply on / off instruction in upf_chip_tb.v, the target power domain modules are configured in sequence according to the hierarchical relationship, that is, the supply on / off instruction is executed on the first target power domain module first, and then the supply on / off instruction is executed on the second target power domain module.

[0055] In view of the technical solutions provided by one or more of the above embodiments, a method for generating a verification environment provided by the present application is for a chip model to be tested including at least one power domain module, reads a target configuration file of the chip model to be tested, determines the power domain module in the enabled state represented in the target configuration file as the target power domain module to be verified, and generates the environment configuration data of the chip model to be tested according to the hierarchical structure information and UPF file path of the target power domain module represented in the target configuration file. Based on the generated environment configuration data, the UPF file is obtained under the UPF file path and loaded into the target power domain module, and the power supply is configured for the target power domain module, so as to generate a verification environment for the chip model to be tested. It can be seen that through the technical solutions provided by one or more embodiments of the present application, there is no need to manually determine and load the UPF file of the target power domain module, but the information represented by the target configuration file can be automatically analyzed and the required UPF file can be obtained, thereby completing the generation of the verification environment. This process reduces human errors, and when different power domain modules are verified, the relevant information represented in the target configuration file will change accordingly, and the new verification environment can be automatically generated based on the changed target configuration file, thereby improving the efficiency and accuracy of the verification environment generation, thereby ensuring the smooth progress of chip verification.

[0056] See also Figure 7The present application provides a device for generating a verification environment, the device comprising: A configuration file reading unit 101 is used to read a target configuration file applicable to the chip model to be tested, wherein the target configuration file includes a specified number of field information, and the specified number of field information is at least used to characterize the hierarchical information and UPF file path of a target power domain module that is currently in an enabled state in at least one power domain module of the chip model to be tested; a configuration data generating unit 103 is used to generate environmental configuration data of the chip model to be tested according to the target configuration file, wherein the environmental configuration data includes at least UPF loading information and power supply information of the target power domain module; a verification environment generating unit 105 is used to load the UPF file under the UPF file path into the target power domain module represented by the hierarchical information according to the UPF loading information, and configure power for the target power domain module based on the power supply information, so as to generate a verification environment for the chip model to be tested.

[0057] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiment of a method for generating a verification environment, and will not be repeated here.

[0058] The configuration file reading unit 101 is specifically used to describe the configuration parameters of a power domain module through enable status information, hierarchy information and UPF file path, and constitute a configuration entry of a power domain module, which configuration entry includes the enable status information, hierarchy information and UPF file path of each of the above-mentioned power domain modules.

[0059] The configuration data generation unit 103 is specifically used to read the field information contained in the target configuration file and generate the environment configuration data of the chip model to be tested. The environment configuration data at least includes the UPF loading information and the power supply information of the target power domain module. Specifically, the hierarchical information and UPF file path of the target power domain module in the configuration entry of the target configuration file are read. First, the hierarchical information and UPF file path of the target power domain module are associated, and the UPF loading information of the target power domain module is generated based on the association result. Then, the UPF file under the UPF file path of the target power domain module is read, and the power supply information of the target power domain module is identified from the UPF file, and the UPF loading information and power supply information of the target power domain module are written into the environment configuration data of the chip model to be tested.

[0060] The verification environment generation unit 105 is specifically used to place the obtained UPF loading information, power supply information and preset compilation options in the simulation directory, and generate the verification environment according to the current environment structure. According to the obtained UPF loading information, the UPF file under the UPF file path of the target power domain module is loaded into the target power domain module represented by the hierarchical information in the target configuration file through the load instruction, and the verification environment is generated for the chip model to be tested.

[0061] In addition, please refer to Figure 8 The present application also provides a function verification method, which may include the following steps: S21: Read a target configuration file applicable to the chip model to be tested, and generate environmental configuration data of the chip model to be tested based on the target configuration file; wherein the target configuration file is at least used to characterize the hierarchical information and UPF file path of the target power domain module that is currently enabled in the at least one power domain module, and the environmental configuration data includes at least the UPF loading information and power supply information of the target power domain module.

[0062] S23: According to the UPF loading information, the UPF file under the UPF file path is loaded into the target power domain module represented by the hierarchical information, and power is configured for the target power domain module based on the power supply information to generate a verification environment for the chip model to be tested.

[0063] S25: Compile the generated verification environment, and after completing the environment compilation, send an excitation signal to the target power domain module through the driving component of the target power domain module to perform functional verification on the target power domain module.

[0064] In this embodiment, after the verification environment is generated, the generated verification environment is compiled to perform functional verification of the target power domain module. Specifically, after the verification environment is compiled, a driving instruction is sent to the driving component, wherein the driving component can be an upstream driving component or a downstream driving component, generating different excitation signals, the driving component receives the driving instruction, and transmits the excitation signal to the power domain module to be tested to complete the verification according to different requirements. It should be noted that if the generated verification environment undergoes version iteration, there is no need to re-adapt the excitation signal, and the environment configuration data can be directly called to generate a new verification environment.

[0065] In this embodiment, the environment configuration data also includes a compilation option file, the compilation option file includes a UPF loading instruction, and the file identifier contained in the UPF loading instruction is consistent with the file identifier in the UPF loading information, so that the UPF file under the UPF file path is loaded into the target power domain module represented by the hierarchical information through the UPF loading instruction. The compilation option file also includes preset compilation options; when the verification environment is first generated, the preset compilation options are integrated into the verification environment generated for the first time, and if the verification environment generated for the first time undergoes version iteration, the preset compilation options are retained in the verification environment after the version iteration.

[0066] It can be seen that the execution process of steps S21 to S23 in this embodiment is similar to the description in the previous embodiment, so this embodiment mainly further explains step S25. For the specific implementation of steps S21 to S23, please refer to the description in the previous embodiment. In addition, this application also provides two implementations of applying the above-mentioned function verification method: In one implementation, please refer to Figure 5 , when the functional verification method applies the verification environment generated based on the IP-level verification environment, the functional verification is performed in the following manner: obtain the three configuration items of the target power domain module, and generate a CSV file through the compiler module, run the CSV file to generate three script files that can generate the verification environment: test.upf, upf_chip_tb.v, upf.flist, write the load instruction 'load*test.upf' of test.upf into the upf.flist file and execute the load instruction, configure the power supply for the target power domain module according to the supply on / off instruction in upf_chip_tb.v, put the above three script files into the simulation running directory, and generate the verification environment. Compile the generated verification environment, send the drive instruction to the drive component, complete the compilation of the environment and generate the excitation signal according to the demand, the excitation signal is transmitted to the DUT unit of the module to be tested and the DUT unit is functionally verified. Optionally, a driving instruction is sent to the upstream driving component master to perform functional verification on the DUT unit; or a driving instruction is sent to the downstream driving component slave to perform functional verification on the DUT unit; or a driving instruction is sent to the upstream driving component master to perform functional verification on the DUT unit and pass the verification result to the downstream driving component.

[0067] In one embodiment, see Figure 6, when the functional verification method applies the verification environment generated based on the SOC-level verification environment, the functional verification is performed in the following manner: obtain three configuration entries containing the information of each target power domain module, and generate a CSV file through the compiler module, run the CSV file to generate script files: test.upf, upf_chip_tb.v, upf.flist, write the load instruction 'load*test.upf' of test.upf into the upf.flist file and execute the load instruction, configure the power supply for each target power domain module according to the supply on / off instruction in upf_chip_tb.v, wherein the power is distributed one by one according to the hierarchical information of each target power domain module, and the above three script files are placed in the simulation running directory to generate the verification environment. Compile the generated verification environment. Take cluster as the first target power domain module and core as the second target power domain module as an example, wherein core is the next level power domain module of cluster. Specifically, when the core completes site selection and performs addressing, it can generate an excitation signal representing the addressing request, and then the excitation signal is transmitted to the noc through the cluster. At this time, the function verification of the core can be performed on the system.

[0068] See also Fig. 9 The present application provides a function verification system, the function verification system comprising a verification environment generating device 301 and a function verification device 303, wherein: A verification environment generating device 301 is used to read a target configuration file applicable to the chip model to be tested, and generate environment configuration data of the chip model to be tested according to the target configuration file; wherein the target configuration file is at least used to characterize the hierarchical information and UPF file path of the target power domain module that is currently enabled in the at least one power domain module, and the environment configuration data at least includes UPF loading information and power supply information of the target power domain module; according to the UPF loading information, the UPF file under the UPF file path is loaded into the target power domain module represented by the hierarchical information, and the power supply is configured for the target power domain module based on the power supply information, so as to generate a verification environment for the chip model to be tested; The function verification device 303 is used to compile the generated verification environment, and after completing the environment compilation, send an excitation signal to the target power domain module through the driving component of the target power domain module to perform function verification on the target power domain module.

[0069] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiment of a functional verification method, which will not be repeated here.

[0070] See also Fig.10 The present application also provides a verification environment generation device, the generation device includes a processor and a memory, the memory is used to store a computer program, when the computer program is executed by the processor, the verification environment generation method in any of the aforementioned embodiments is implemented.

[0071] In one embodiment, the above-mentioned generating device may include one or more processors (or processing circuits) configured to implement the above method, a memory and a computer program stored in the memory, for implementing any of the above methods. Among them, the processor can be selected as: CPU (Central Processing Unit, Central Processing Unit), GPU (Graphics Processing Unit, Graphics Processing Unit), NPU (Neural Network Processing Unit, Neural Network Processing Unit), TPU (Tensor Processing Unit, Tensor Processing Unit), DPU (Deep Learning Processing Unit, Deep Learning Processor), microprocessor, DSP (Digital Signal Processor, Digital Signal Processor), ASIC (Application Specific Integrated Circuit, Application Specific Integrated Circuit), FPGA (Field Programmable Gate Array, Field Programmable Gate Array), or a combination of at least two of these processor forms. The memory stores instructions that can be executed by at least one processor, and the types of the at least one processor may be different, for example, including CPU and FPGA, CPU and artificial intelligence processor, CPU and GPU, etc. The computer program can be written in Python language, and can also be written in other programming languages, including but not limited to Python, Perl, Tcl.

[0072] In one embodiment, the processor is a circuit with signal processing capability. In one implementation, the processor may be a circuit with instruction reading and execution capability, such as a CPU, microprocessor, GPU, or DSP. In another implementation, the processor may implement certain functions through the logical relationship of a hardware circuit, and the logical relationship of the hardware circuit may be fixed or reconfigurable, such as a hardware circuit implemented by an ASIC or PLD, such as an FPGA. In a reconfigurable hardware circuit, the process of the processor loading a configuration document to implement the hardware circuit configuration may be understood as the process of the processor loading instructions to implement the functions of some or all of the above units. In addition, it may also be a hardware circuit designed for artificial intelligence, which may be understood as an ASIC, such as an NPU, TPU, DPU, etc.

[0073] Some embodiments of the present application provide a verification environment generation method, device, function verification method and system, which reads the field information of the target configuration file, outputs a script file for generating the verification environment, compiles the script file, and automatically generates a verification environment for functional verification of the power domain module to be verified of the chip model to be tested. In addition, the error information generated in the environment construction can be output to the simulation log in a timely manner, so as to readjust the target configuration file of the environment construction to form a positive feedback.

[0074] Therefore, this solution does not need to repeatedly build the environment manually. It can automatically generate a verification environment based on the configuration content of the CSV file to meet the verification requirements adapted to different configurations for chip verification.

[0075] The embodiment of the present application also provides a computer-readable storage medium. The above method according to the embodiment of the present application can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium through a network download, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the above embodiment is implemented.

[0076] The embodiment of the present application provides a computer program product, which includes computer instructions, which are stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device executes the method of any embodiment of the present application.

[0077] Although the embodiments of the present application are described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present application, and such modifications and variations are all within the scope defined by the appended claims.

[0078] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0079] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0080] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0081] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0082] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0083] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0084] The above is only an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

[0085] Although the embodiments of the present application have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present application, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A method for generating a verification environment, characterized in that: The method is applied to a chip model to be tested, wherein the chip model to be tested includes at least one power domain module, and the method includes: Reading a target configuration file applicable to the chip model to be tested, wherein the target configuration file includes a specified number of field information, and the specified number of field information is at least used to characterize the hierarchical information and UPF file path of the target power domain module that is currently enabled in the at least one power domain module; Generate environmental configuration data of the chip model to be tested according to the target configuration file, wherein the environmental configuration data at least includes UPF loading information and power supply information of the target power domain module; According to the UPF loading information, the UPF file under the UPF file path is loaded into the target power domain module represented by the hierarchical information, and the power supply is configured for the target power domain module based on the power supply information to generate a verification environment for the chip model to be tested.

2. The method according to claim 1, characterized in that The target configuration file is generated in the following manner: Obtaining the respective hierarchical information of each power domain module in the chip model to be tested, and obtaining the respective UPF file path of each power domain module; For any power domain module, determine whether the power domain module is set to an enabled state during the current verification process, and determine the enable state information of the power domain module based on the determination result; Generate configuration entries of the power domain module based on the hierarchical information, UPF file path and enable status information of the power domain module; A target configuration file of the chip model to be tested is generated according to the configuration items of each power domain module in the chip model to be tested.

3. The method according to claim 2, characterized in that Based on the judgment result, determining the enabling state information of the power domain module includes: If the power domain module is set to an enabled state during the current verification process, setting the enable state information of the power domain module to a first value; If the power domain module is set to a disabled state during the current verification process, setting the enable state information of the power domain module to a second value; The first value and the second value are different values.

4. The method according to claim 1, characterized in that Generating the environment configuration data of the chip model to be tested according to the target configuration file includes: Associating the hierarchical information and UPF file path of the target power domain module, and generating UPF loading information of the target power domain module based on the association result; Read the UPF file under the UPF file path, and identify the power supply information of the target power domain module from the UPF file; The UPF loading information and power supply information of the target power domain module are written into the environment configuration data of the chip model to be tested.

5. The method according to claim 1 or 4, characterized in that: The environment configuration data also includes preset compilation options; wherein, when the verification environment is first generated, the preset compilation options are integrated into the verification environment generated for the first time, and if the verification environment generated for the first time undergoes version iteration, the preset compilation options are retained in the verification environment after the version iteration.

6. The method according to claim 1, characterized in that In the process of generating the environmental configuration data of the chip model to be tested, the method further includes: If the target configuration file cannot be obtained, generating an error message indicating that the target configuration file is missing; If there is no UPF file in the UPF file path, an error message indicating that the UPF file is missing is generated; If the power supply information does not exist in the UPF file under the UPF file path, an error message indicating that the power supply information is missing is generated.

7. The method according to claim 1, characterized in that Configuring power for the target power domain module based on the power supply information includes: If the chip model to be tested includes a first target power domain module and a second target power domain module in an enabled state, and the first target power domain module is located at an upper level of the second target power domain module, after configuring power for the first target power domain module based on the power supply information of the first target power domain module, then configuring power for the second target power domain module based on the power supply information of the second target power domain module.

8. The method according to claim 7, characterized in that The hierarchical relationship between the first target power domain module and the second target power domain module is determined by the hierarchical information of the first target power domain module and the second target power domain module respectively, wherein the hierarchical information of the first target power domain module is included in the hierarchical information of the second target power domain module.

9. The method according to claim 1, characterized in that: After generating a verification environment for the chip model to be tested, the method further includes: If the verification environment undergoes version iteration, read the target configuration file after the version iteration, and regenerate the environment configuration data based on the target configuration file after the version iteration; According to the regenerated environment configuration data, the UPF file is loaded and the power configuration is performed on the target power domain module that is currently in the enabled state to regenerate the verification environment.

10. A device for generating a verification environment, characterized in that: The device comprises: A configuration file reading unit, used to read a target configuration file applicable to the chip model to be tested, wherein the target configuration file includes a specified number of field information, and the specified number of field information is used at least to characterize the hierarchical information and UPF file path of a target power domain module currently in an enabled state in at least one power domain module of the chip model to be tested; A configuration data generating unit, configured to generate environment configuration data of the chip model to be tested according to the target configuration file, wherein the environment configuration data at least includes UPF loading information and power supply information of the target power domain module; A verification environment generating unit is used to load the UPF file under the UPF file path into the target power domain module represented by the hierarchical information according to the UPF loading information, and configure power for the target power domain module based on the power supply information to generate a verification environment for the chip model to be tested.

11. A function verification method, characterized in that: The method is applied to a chip model to be tested, wherein the chip model to be tested includes at least one power domain module, and the method includes: Read a target configuration file applicable to the chip model to be tested, and generate environment configuration data of the chip model to be tested according to the target configuration file; wherein the target configuration file is at least used to characterize the hierarchical information and UPF file path of the target power domain module currently in the enabled state in the at least one power domain module, and the environment configuration data at least includes UPF loading information and power supply information of the target power domain module; According to the UPF loading information, the UPF file under the UPF file path is loaded into the target power domain module represented by the hierarchical information, and the power supply is configured for the target power domain module based on the power supply information to generate a verification environment for the chip model to be tested; The generated verification environment is compiled, and after the environment compilation is completed, an excitation signal is sent to the target power domain module through a driving component of the target power domain module to perform functional verification on the target power domain module.

12. The method according to claim 11, characterized in that If the generated verification environment undergoes version iteration, the stimulus signal is reused in the verification environment after the version iteration.

13. The method according to claim 11, characterized in that The environment configuration data also includes a compilation option file, which includes a UPF loading instruction. The file identifier contained in the UPF loading instruction is consistent with the file identifier in the UPF loading information, so that the UPF file under the UPF file path is loaded into the target power domain module represented by the hierarchical information through the UPF loading instruction.

14. The method according to claim 13, characterized in that The compilation option file also includes preset compilation options; wherein, when the verification environment is first generated, the preset compilation options are integrated into the verification environment generated for the first time, and if the verification environment generated for the first time undergoes version iteration, the preset compilation options are retained in the verification environment after the version iteration.

15. A function verification system, characterized in that: The function verification system comprises a verification environment generating device and a function verification device, wherein: The verification environment generating device is used to read a target configuration file applicable to the chip model to be tested, and generate environment configuration data of the chip model to be tested according to the target configuration file; wherein the target configuration file is at least used to characterize the hierarchical information and UPF file path of the target power domain module currently in the enabled state in the at least one power domain module, and the environment configuration data at least includes the UPF loading information and power supply information of the target power domain module; according to the UPF loading information, the UPF file under the UPF file path is loaded into the target power domain module represented by the hierarchical information, and the power supply is configured for the target power domain module based on the power supply information, so as to generate a verification environment for the chip model to be tested; The functional verification device is used to compile the generated verification environment, and after completing the environment compilation, send an excitation signal to the target power domain module through the driving component of the target power domain module to perform functional verification on the target power domain module.

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