High-density circuit board and method based on electroplating solar etching process

Abstract

The invention relates to the technical field of high-density circuit boards, and particularly discloses a high-density circuit board and method based on an electroplating solar etching process, and the method comprises the steps: obtaining a circuit pattern image collected by an industrial camera, extracting a circuit pattern design image from a database, and then carrying out the calculation of the circuit pattern design image; the method comprises the following steps: respectively carrying out feature extraction on a circuit pattern image and a circuit pattern design image by adopting an image analysis and processing technology based on deep learning, and carrying out significant interactive fusion to obtain circuit pattern detection-design significant sparse interactive fusion features; and based on the circuit pattern detection-design significant sparse interactive fusion features, automatically detecting whether the circuit pattern has defects or not. Therefore, through the automatic image processing technology, the defects on the circuit board can be identified and detected more intelligently, and the detection efficiency and accuracy can be improved.

Description

Technical Field

[0001] The present application relates to the technical field of high-density circuit boards, and more specifically, to a high-density circuit board and method based on an electroplating erosion process. Background Art

[0002] In the electronics industry, as electronic products develop towards miniaturization and high performance, the requirements for printed circuit boards (PCBs) are becoming higher and higher. Traditional PCB manufacturing technology can no longer meet the needs of modern electronic devices for higher density, smaller size and more complex functions. Therefore, the development of new manufacturing technologies has become an inevitable trend.

[0003] The traditional PCB manufacturing method mainly relies on the subtractive process, that is, first covering the entire substrate with a layer of copper foil, then transferring the circuit pattern to the copper foil through photolithography, and then using chemical etching liquid to remove the unnecessary copper foil part, leaving the circuit pattern. However, this method has some problems when manufacturing high-density circuit boards: since the etching accuracy is affected by the chemical etching liquid and the resolution of photolithography technology, it is difficult to achieve very fine line widths. A large amount of copper material is removed during the etching process, resulting in a waste of resources. In addition, the etching solution contains harmful substances, and improper handling will cause environmental pollution.

[0004] Therefore, an optimized high-density circuit board manufacturing solution is desired. Summary of the invention

[0005] The present application provides a high-density circuit board and method based on electroplating eclipse process, which can more intelligently identify and detect defects on the circuit board through automated image processing technology, thereby helping to improve detection efficiency and accuracy. At the same time, the use of deep learning models can learn and identify multiple types of defects, which can improve the generalization ability of detection application scenarios, thereby reducing the possibility of misjudgment and missed detection. In other words, this method can adapt to different types of circuit boards and complex pattern designs, and improve the flexibility and adaptability of detection.

[0006] In a first aspect, a method for a high-density circuit board based on an electroplating eclipse process is provided, comprising: Providing a substrate, wherein the material of the substrate is FR-4 epoxy glass fiber board; Covering the substrate with a copper layer, and coating a photosensitive dry film on the copper layer; Using an exposure device to transfer a preset circuit pattern onto the photosensitive dry film to obtain a circuit board substrate after exposure treatment; Performing a development process on the circuit board substrate after the exposure process to remove the unexposed portion of the photosensitive dry film to obtain a circuit board substrate after the development process; Electroplating the circuit board substrate after the development process to obtain a circuit board substrate after the electroplating process; Removing all the remaining photosensitive dry film and the copper layer below the photosensitive dry film to obtain a circuit board substrate after stripping; Performing surface treatment on the circuit board substrate after the stripping treatment to obtain a circuit board substrate after the surface treatment; The circuit board substrate after the surface treatment is subjected to drilling treatment to obtain a high-density circuit board based on the electroplating erosion process.

[0007] In a possible implementation, performing a development process on the circuit board substrate after the exposure process to remove the photosensitive dry film at the unexposed portion to obtain the circuit board substrate after the development process, comprising: Acquire a circuit pattern image captured by an industrial camera; extracting a circuit pattern design image from a database; Performing circuit pattern feature extraction on the circuit pattern image and the circuit pattern design image to obtain a circuit pattern detection feature map and a circuit pattern design feature map; The circuit pattern detection feature map and the circuit pattern design feature map are significantly interactively fused to obtain a circuit pattern detection-design significant sparse interactive fusion feature, including: performing kernel correlation sparse masking on the circuit pattern detection feature map and the circuit pattern design feature map to obtain a circuit pattern detection-design kernel feature correlation sparse weight matrix; performing position-by-position correlation interactive fusion on the circuit pattern detection feature map and the circuit pattern design feature map to obtain a circuit pattern detection-design position-by-position interactive fusion feature map; based on the circuit pattern detection-design kernel feature correlation sparse weight matrix, performing feature significant sparse modulation on the circuit pattern detection-design position-by-position interactive fusion feature map to obtain a circuit pattern detection-design significant sparse interactive fusion feature map as the circuit pattern detection-design significant sparse interactive fusion feature; Based on the circuit pattern detection-design significant sparse interactive fusion features, the recognition result of the circuit pattern image is determined.

[0008] In a possible implementation, performing circuit pattern feature extraction on the circuit pattern image and the circuit pattern design image to obtain a circuit pattern detection feature map and a circuit pattern design feature map includes: The circuit pattern image and the circuit pattern design image are input into a circuit pattern twin detection model including a first circuit pattern image feature extractor and a second circuit pattern image feature extractor to obtain the circuit pattern detection feature map and the circuit pattern design feature map.

[0009] In a possible implementation, performing kernel correlation sparse masking on the circuit pattern detection feature map and the circuit pattern design feature map to obtain a circuit pattern detection-design kernel feature correlation sparse weight matrix includes: Inputting the circuit pattern detection feature map and the circuit pattern design feature map into a kernel feature distillation network to obtain a circuit pattern detection kernel feature vector and a circuit pattern design kernel feature vector respectively; Performing global correlation coding on the circuit pattern detection kernel feature vector and the circuit pattern design kernel feature vector to obtain a global coding matrix between circuit pattern detection-design kernel features; The circuit pattern detection-design kernel feature global encoding matrix is ​​input into a sparse mask unit to obtain the circuit pattern detection-design kernel feature associated sparse weight matrix.

[0010] In a second aspect, a high-density circuit board based on electroplating eclipse process is provided, and the high-density circuit board based on electroplating eclipse process is manufactured by the method for a high-density circuit board based on electroplating eclipse process described in the first aspect.

[0011] The present application provides a high-density circuit board and method based on electroplating eclipse process, which obtains a circuit pattern image collected by an industrial camera, and extracts a circuit pattern design image from a database, then uses image analysis and processing technology based on deep learning to extract features of the circuit pattern image and the circuit pattern design image respectively and perform significant interactive fusion to obtain circuit pattern detection-design significant sparse interactive fusion features, and finally, based on the circuit pattern detection-design significant sparse interactive fusion features to automatically detect whether the circuit pattern has defects. In this way, through automated image processing technology, defects on circuit boards can be identified and detected more intelligently, thereby helping to improve detection efficiency and accuracy. At the same time, the use of a deep learning model can learn and identify multiple types of defects, which can improve the generalization ability of detection application scenarios, thereby reducing the possibility of misjudgment and missed detection. In other words, this method can adapt to different types of circuit boards and complex pattern designs, and improve the flexibility and adaptability of detection. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings of the embodiments of the present application are briefly introduced below. Obviously, the drawings described below only relate to some embodiments of the present application, and are not intended to limit the present application.

[0013] Figure 1 It is a schematic flow chart of a method for high-density circuit board based on electroplating erosion process according to an embodiment of the present application.

[0014] Figure 2In the method for high-density circuit boards based on electroplating etch process in an embodiment of the present application, a schematic flow chart of developing the circuit board substrate after exposure to remove the photosensitive dry film in the unexposed portion to obtain the circuit board substrate after development is provided.

[0015] Figure 3 In the method for high-density circuit boards based on electroplating etch process according to an embodiment of the present application, the circuit board substrate after exposure is developed to remove the photosensitive dry film of the unexposed portion to obtain a data flow diagram of the circuit board substrate after development.

[0016] Figure 4 In the method for high-density circuit boards based on electroplating eclipse process in an embodiment of the present application, the circuit pattern detection feature map and the circuit pattern design feature map are significantly interactively fused to obtain a schematic flow chart of circuit pattern detection-design significant sparse interactive fusion features.

[0017] Figure 5 In the method for high-density circuit boards based on electroplating eclipse process of an embodiment of the present application, a schematic flowchart of performing kernel correlation sparse masking on the circuit pattern detection feature map and the circuit pattern design feature map to obtain a circuit pattern detection-design kernel feature correlation sparse weight matrix. DETAILED DESCRIPTION

[0018] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, not all embodiments. Based on the embodiments of the present application, all other embodiments obtained by ordinary technicians in this field without creative work also fall within the scope of protection of the present application.

[0019] Traditional printed circuit board (PCB) manufacturing technology mainly uses a subtractive method, which involves laying a layer of copper foil on the entire substrate, then using photolithography to transfer the circuit design pattern, and using chemical etchants to dissolve the copper foil in non-essential areas to form the circuit. However, when this technology is applied to the manufacture of high-density circuit boards, several challenges are encountered. On the one hand, due to the characteristics of chemical etchants and the resolution limitations that can be achieved by photolithography, it becomes quite difficult to achieve extremely fine lines. On the other hand, a large amount of unnecessary copper is removed during the etching process, which not only causes a waste of raw materials, but also increases production costs.

[0020] Based on this, the present application proposes a method for high-density circuit boards based on electroplating etch technology, which combines the advantages of electroplating technology and fine etching technology, and can accurately control the width and spacing of circuit lines, thereby achieving higher wiring density. Specifically, Figure 1Schematic flow chart of a method for high-density circuit board based on electroplating erosion process according to an embodiment of the present application. Figure 1 As shown, the method for high-density circuit boards based on electroplating eclipse process includes: S1, providing a substrate, the material of the substrate is FR-4 epoxy glass fiber board; S2, covering a copper layer on the substrate, and coating a photosensitive dry film on the copper layer; S3, using an exposure device to transfer a preset circuit pattern to the photosensitive dry film to obtain a circuit board substrate after exposure; S4, developing the circuit board substrate after exposure to remove the photosensitive dry film of the unexposed part to obtain the circuit board substrate after development; S5, electroplating the circuit board substrate after development to obtain the circuit board substrate after electroplating; S6, removing all the remaining photosensitive dry film and the copper layer under the photosensitive dry film to obtain the circuit board substrate after stripping; S7, surface treating the circuit board substrate after stripping to obtain the circuit board substrate after surface treatment; S8, drilling the circuit board substrate after surface treatment to obtain the high-density circuit board based on electroplating eclipse process.

[0021] In the above-mentioned method for high-density circuit boards based on electroplating eclipse process, S1 provides a substrate, and the material of the substrate is FR-4 epoxy glass fiber board. It should be understood that FR-4 epoxy glass fiber board is a common PCB (printed circuit board) substrate, which has good electrical insulation performance, high mechanical strength, stable thermal expansion coefficient, good heat resistance and flame retardancy. These characteristics make FR-4 an ideal choice for making multi-layer PCBs, especially for electronic devices that require high reliability, FR-4 substrates can provide a stable working environment. Optionally, in one embodiment of the present application, S1 includes: first selecting FR-4 epoxy glass fiber board as the substrate material, because its good electrical properties and mechanical strength are suitable for making high-density circuit boards. According to the design size of the circuit board, use a precision cutting tool to cut the FR-4 board into the required size. In this process, it is necessary to pay attention to maintaining the accuracy of the size. Before officially starting the production of the circuit board, the surface of the FR-4 substrate needs to be pre-treated. It usually includes cleaning the surface to remove pollutants such as grease and dust, and performing micro-etching to make the surface slightly rough to increase the adhesion between the copper layer and the substrate.

[0022] In the above-mentioned method of high-density circuit board based on electroplating etch process, S2 covers a copper layer on the substrate and coats a photosensitive dry film on the copper layer. It should be understood that the role of the copper layer is to provide a conductive layer on the substrate to facilitate the subsequent formation of circuit patterns. The photosensitive dry film is a medium for transferring the circuit pattern to the copper layer. After the circuit pattern is transferred to the photosensitive dry film by photolithography, the unexposed part can be removed by development treatment to expose the copper layer below. In this way, a predetermined circuit pattern can be formed on the copper layer. Optionally, in one embodiment of the present application, S2 includes: depositing a copper layer on the substrate by vacuum evaporation, sputtering or electroplating. The thickness of the copper layer is generally in the range of 1 to 20 microns. Afterwards, a photosensitive dry film is coated on the surface of the copper layer. This is usually done by heating the dry film to soften it and then pressing it on the copper layer to ensure close contact between the dry film and the copper layer to avoid bubbles or wrinkles.

[0023] In the above-mentioned method of high-density circuit board based on electroplating erosion process, the S3 uses an exposure device to transfer the preset circuit pattern to the photosensitive dry film to obtain the circuit board substrate after exposure. It should be understood that by precisely controlling the exposure conditions, the photosensitive dry film can undergo chemical changes under ultraviolet light or other forms of radiation, so that the blocked part (i.e., the part of the future circuit) and the unblocked part (the part to be removed) are distinguished, laying the foundation for the next step of development treatment. Optionally, in one embodiment of the present application, the S3 includes: first, a mask corresponding to the desired circuit pattern needs to be prepared. The mask is usually a transparent substrate with opaque parts on it, which correspond to the unwanted areas on the circuit board. Align the mask with the circuit board substrate and ensure that there is no movement or deviation between the two. This step is very important because any misalignment will cause pattern errors on the circuit board. Use an exposure device to irradiate ultraviolet light or other light sources onto the photosensitive dry film. At this time, the mask will block part of the light, and only the light that passes through the transparent part of the mask can reach the photosensitive dry film, causing it to undergo chemical changes. The exposure time needs to be adjusted according to the light intensity and the characteristics of the photosensitive dry film to ensure that the photosensitive dry film can be properly photosensitized and cured, so that the circuit pattern can be correctly retained during development.

[0024] In the above-mentioned method for high-density circuit boards based on electroplating erosion process, the S4 is to perform a development process on the circuit board substrate after the exposure process to remove the unexposed part of the photosensitive dry film to obtain the circuit board substrate after the development process. It should be understood that the purpose of the development process is to remove the photosensitive dry film that is not cured by light during the exposure process, expose the copper layer below, and prepare for the subsequent electroplating process. Through the development process, only those parts of the photosensitive dry film that are blocked by the mask during the exposure process will be retained to form a negative image of the circuit pattern. This step is crucial to ensure the accuracy and integrity of the circuit pattern. Any minor defects may cause circuit malfunction and affect the performance and reliability of the final product. Optionally, in one embodiment of the present application, the S4 includes: the developer is a solution that can dissolve the unexposed photosensitive dry film, usually containing alkaline components. The circuit board substrate after the exposure process is placed in the developer to ensure that the entire surface is covered by the liquid. According to the type of photosensitive dry film and the concentration of the developer, the appropriate development time is controlled. Too long a time may lead to over-development, and too short a time may lead to incomplete development. After the development is completed, the circuit board needs to be thoroughly rinsed with clean water to remove the residual developer and dissolved photosensitive dry film. Finally, the circuit pattern after development is strictly inspected for defects.

[0025] In the above-mentioned method of high-density circuit board based on electroplating erosion process, the S5, electroplating the circuit board substrate after the development treatment to obtain the circuit board substrate after the electroplating treatment. It should be understood that the role of electroplating is to add an additional metal layer on the existing copper layer to increase conductivity, wear resistance and prevent corrosion. In this step, a metal plating layer will only be formed on the copper layer portion that is not covered by the photosensitive dry film, and the portion covered by the photosensitive dry film will not be electroplated, so that the desired circuit pattern can be formed. Optionally, in one embodiment of the present application, the S5 includes: ensuring that the circuit board substrate after the development treatment has been thoroughly cleaned and all residues that may affect the quality of electroplating are removed. According to the required plating material, the electroplating solution is prepared. Commonly used plating materials include copper, nickel, gold, etc., and the corresponding electroplating solution formulas for different materials will also be different. The circuit board substrate is placed in the electroplating tank as a cathode, and the anode material (usually pure copper or other required plating material) is inserted into the electroplating tank. After power is turned on, the metal ions in the electroplating solution will be deposited on the exposed copper layer of the circuit board substrate under the action of the electric field, forming a uniform metal coating. During the electroplating process, it is necessary to monitor parameters such as current density, electroplating time, temperature and pH value of the electroplating solution to ensure the quality of the coating. After the electroplating is completed, the circuit board substrate is removed and washed with clean water to remove the residual electroplating solution, and then dried.

[0026] In the above-mentioned method for high-density circuit boards based on electroplating erosion process, the S6 removes all the residual photosensitive dry film and the copper layer located below the photosensitive dry film to obtain the circuit board substrate after stripping treatment. It should be understood that the main purpose of the stripping treatment is to remove the photosensitive dry film and copper layer that are no longer needed, and only retain the circuit pattern formed by the electroplating treatment. This step is crucial to ensure the clarity and accuracy of the circuit pattern finally formed on the circuit board, because it directly determines the functionality and reliability of the circuit. Optionally, in one embodiment of the present application, the S6 includes: first, ensure that the circuit board substrate after the electroplating treatment has been thoroughly cleaned to remove any dust or impurities that may exist. Soak the circuit board substrate in a special stripping liquid or solvent to soften and remove the residual photosensitive dry film. The selection of the stripping liquid should be determined according to the chemical properties of the photosensitive dry film to ensure that the photosensitive dry film can be effectively dissolved without damaging the circuit board substrate. After the photosensitive dry film is removed, further treatment is required to remove the copper layer not covered by the photosensitive dry film. Chemical etching is usually used to dissolve the exposed copper layer through an etching solution (such as ferric chloride solution). The choice of etching solution depends on the material of the copper layer, and the etching time needs to be controlled to prevent over-etching. After etching, the circuit board substrate needs to be thoroughly cleaned to remove residual etching solution and dried. Subsequently, the circuit board substrate is visually inspected to ensure that the circuit pattern is intact and there is no excess residue or etching marks.

[0027] In the above-mentioned method of high-density circuit board based on electroplating eclipse process, the S7 is to perform surface treatment on the circuit board substrate after stripping treatment to obtain the circuit board substrate after surface treatment. It should be understood that the main function of surface treatment is to improve the reliability and functionality of the circuit board. Through surface treatment, the oxidation resistance and corrosion resistance of the circuit board surface can be increased, the weldability can be improved, the circuit board can be ensured to work normally in various environments, and the service life of the circuit board can be extended. In addition, the surface treatment can also make the circuit board surface easier to weld components in the subsequent assembly process, thereby improving production efficiency. Optionally, in one embodiment of the present application, the S7 includes: firstly, thoroughly cleaning the circuit board substrate after stripping treatment to remove impurities, grease, etc. that may remain on the surface to ensure that the surface is clean. According to the requirements of the surface treatment, pretreatment, such as micro-etching, may be required to increase the surface roughness and enhance the adhesion of the subsequent coating. Different surface treatment processes are selected according to the needs, such as organic protective coating (OSP), chemical nickel / immersion gold (ENIG), hot air leveling (HASL), etc. If a liquid coating is used in the surface treatment process, it is necessary to perform curing or drying treatment to ensure that the coating is firmly attached to the surface of the circuit board. Finally, the quality of the circuit board substrate after surface treatment is checked to ensure that the surface treatment achieves the expected effect.

[0028] In the above-mentioned method for a high-density circuit board based on an electroplating eclipse process, the S8 is to perform a drilling process on the circuit board substrate after the surface treatment to obtain a high-density circuit board based on an electroplating eclipse process. It should be understood that the main function of the drilling process is to form through holes and blind holes for connecting circuit traces between different layers to achieve electrical connection of a multi-layer circuit board. These holes can not only be used to pass through pins or pads, but also can be used as channels for signal transmission or power supply in a multi-layer circuit board. In addition, drilling can also be used to locate and fix components on a circuit board. Optionally, in one embodiment of the present application, the S8 includes: first, it is necessary to accurately locate the circuit board substrate according to the design drawing of the circuit board and mark the location where the hole needs to be drilled. Use a CNC drilling machine (CNC) or a laser drilling device to drill holes in the circuit board substrate. For precision high-density circuit boards, laser drilling technology may be required to achieve a small diameter aperture. After the drilling is completed, the hole wall needs to be processed, such as deburring, cleaning the residue in the hole, etc., to ensure the smoothness and cleanliness of the hole wall. For holes that require electrical connection (such as through holes), hole metallization is required, that is, a layer of metal (usually copper) is deposited on the hole wall to ensure conductivity in the hole. Finally, the drilled holes need to be inspected to ensure that parameters such as hole diameter, position and depth meet the design requirements. Through the above steps, a high-density circuit board after drilling is finally obtained, completing the manufacture of high-density circuit boards based on electroplating eclipse process.

[0029] Furthermore, it is important to ensure the accuracy and integrity of the circuit pattern during the manufacturing process of high-density printed circuit boards (HDI). In particular, when the circuit board substrate after exposure is subjected to development treatment to remove the photosensitive dry film of the unexposed part and obtain the circuit board substrate after development treatment, it is necessary to strictly check whether the circuit pattern has defects. This is because any tiny defect may cause circuit malfunction and affect the performance and reliability of the final product. However, in the prior art, traditional detection methods have certain limitations and shortcomings. For example, traditional circuit board detection usually relies on manual visual inspection. Although this method is intuitive and simple, it has the following problems in actual operation: manual inspection is slow, especially when facing mass production, it is impossible to complete the inspection work quickly. The inspection results are easily affected by personal experience and fatigue, resulting in unstable inspection results, which are prone to misjudgment or missed inspection. For another example, X-ray detection can penetrate materials and can also be used to check defects inside circuit boards in the prior art. However, this method also has its shortcomings: it usually needs to be inspected sample by sample, the inspection speed is slow, and it is not suitable for mass production environments.

[0030] Accordingly, when the circuit board substrate after the exposure treatment is developed to remove the photosensitive dry film of the unexposed part to obtain the circuit board substrate after the development treatment, the technical concept of the present application is to obtain the circuit pattern image collected by the industrial camera, and extract the circuit pattern design image from the database, and then use the image analysis and processing technology based on deep learning to extract features of the circuit pattern image and the circuit pattern design image respectively and perform significant interactive fusion to obtain the circuit pattern detection-design significant sparse interactive fusion feature, and finally, based on the circuit pattern detection-design significant sparse interactive fusion feature to automatically detect whether the circuit pattern has defects. In this way, through the automated image processing technology, the defects on the circuit board can be more intelligently identified and detected, which helps to improve the detection efficiency and accuracy. At the same time, the use of a deep learning model can learn and identify multiple types of defects, which can improve the generalization ability of the detection application scenario, thereby reducing the possibility of misjudgment and missed detection. In other words, this method can adapt to different types of circuit boards and complex pattern designs, and improve the flexibility and adaptability of detection.

[0031] Figure 2 In the method for high-density circuit boards based on electroplating etch process in an embodiment of the present application, a schematic flow chart of developing the circuit board substrate after exposure to remove the photosensitive dry film in the unexposed portion to obtain the circuit board substrate after development is provided. Figure 3 In the method of high-density circuit board based on electroplating etch process of the embodiment of the present application, the circuit board substrate after exposure is subjected to development treatment to remove the photosensitive dry film of the unexposed part to obtain the data flow diagram of the circuit board substrate after development treatment. Figure 2 and Figure 3 As shown, the circuit board substrate after the exposure treatment is developed to remove the photosensitive dry film of the unexposed part to obtain the circuit board substrate after the development treatment, including: S41, acquiring a circuit pattern image collected by an industrial camera; S42, extracting a circuit pattern design image from a database; S43, performing circuit pattern feature extraction on the circuit pattern image and the circuit pattern design image to obtain a circuit pattern detection feature map and a circuit pattern design feature map; S44, performing significant interactive fusion on the circuit pattern detection feature map and the circuit pattern design feature map to obtain a circuit pattern detection-design significant sparse interactive fusion feature; S45, determining the recognition result of the circuit pattern image based on the circuit pattern detection-design significant sparse interactive fusion feature.

[0032] In the above-mentioned method for high-density circuit boards based on electroplating eclipse process, the S41 obtains the circuit pattern image captured by the industrial camera. It should be understood that the industrial camera can quickly and accurately capture the image of the circuit board and provide raw data for subsequent automated detection. Compared with manual detection, this method can not only greatly improve the detection speed, but also significantly improve the accuracy of detection. At the same time, the images captured by the industrial camera can record the status of the circuit board in real time, which can be archived as an important record of quality control, so as to facilitate tracing the root cause of the problem or conducting statistical analysis in the future.

[0033] In the above-mentioned method for high-density circuit boards based on electroplating eclipse technology, the S42 extracts a circuit pattern design image from a database. It should be understood that, considering that the circuit pattern design image is a design blueprint in the circuit board manufacturing process, it contains all the design information such as wires, pads, vias, etc. on the circuit board. Therefore, in the technical solution of the present application, the circuit pattern design image is extracted from the database, and the circuit pattern design image is used as an important benchmark for combined analysis with the actually collected circuit pattern image. Specifically, the circuit pattern design image provides the morphological standard that the circuit board should have, so that the system can more easily identify defects.

[0034] In the above-mentioned method for high-density circuit boards based on electroplating eclipse process, the S43 performs circuit pattern feature extraction on the circuit pattern image and the circuit pattern design image to obtain a circuit pattern detection feature map and a circuit pattern design feature map. It should be understood that in order to capture and extract key circuit pattern feature information to improve the accuracy of subsequent defect detection, in the technical solution of the present application, the circuit pattern image and the circuit pattern design image are respectively input into a circuit pattern twin detection model including a first circuit pattern image feature extractor and a second circuit pattern image feature extractor to obtain a circuit pattern detection feature map and a circuit pattern design feature map. It is worth mentioning that the circuit pattern twin detection model can effectively extract and compare the features of the two images by sharing the same feature extraction network. Specifically, the two branches in the twin detection model share the same weights, which means that they perform the same feature extraction on the input image. This shared weight mechanism ensures consistent feature extraction for different input images. By comparing the features of the two images, the twin network can better identify the difference. In circuit board detection, the difference between the actual image and the design image is exactly the focus that needs to be paid attention to. In particular, in a specific example of the present application, the first circuit pattern image feature extractor and the second circuit pattern image feature extractor use a hole convolutional neural network model with the same network structure.

[0035] Optionally, in one embodiment of the present application, circuit pattern features are extracted from the circuit pattern image and the circuit pattern design image to obtain a circuit pattern detection feature map and a circuit pattern design feature map, including: inputting the circuit pattern image and the circuit pattern design image into a circuit pattern twin detection model comprising a first circuit pattern image feature extractor and a second circuit pattern image feature extractor to obtain the circuit pattern detection feature map and the circuit pattern design feature map.

[0036] In the above-mentioned method for high-density circuit boards based on electroplating eclipse process, the S44 performs significant interactive fusion on the circuit pattern detection feature map and the circuit pattern design feature map to obtain circuit pattern detection-design significant sparse interactive fusion features. It should be understood that considering that the circuit pattern design feature map is used to describe key information in circuit board design, including but not limited to design details such as the position of circuit components, the direction of circuits, and the size of pads, it provides an overall description of the circuit pattern design, including component layout and line direction characteristics. The circuit pattern detection feature map reflects the physical layout on the actual circuit board, including the position of circuit components, the direction of circuits, the size of pads, and other information during the actual manufacturing process. There is a mutual correlation and influence between the two feature maps. Specifically, if the circuit pattern design feature map indicates that there are specific layout requirements in the design (such as component position, line direction, etc.), then in the circuit pattern detection feature map, those features that reflect the actual manufacturing situation become particularly important. Therefore, in order to perform feature selection and optimization on the circuit pattern detection feature map based on the circuit pattern design feature map, in the technical solution of the present application, the circuit pattern detection feature map and the circuit pattern design feature map are significantly interactively fused to obtain a circuit pattern detection-design significantly sparse interactively fused feature map as a circuit pattern detection-design significantly sparse interactively fused feature.

[0037] Optionally, in one embodiment of the present application, Figure 4 In the method for high-density circuit boards based on electroplating eclipse process of the embodiment of the present application, the circuit pattern detection feature map and the circuit pattern design feature map are significantly interactively fused to obtain circuit pattern detection-design significant sparse interactive fusion features. Figure 4As shown, the circuit pattern detection feature map and the circuit pattern design feature map are significantly interactively fused to obtain a circuit pattern detection-design significantly sparse interactive fusion feature, including: S441, kernel correlation sparse masking is performed on the circuit pattern detection feature map and the circuit pattern design feature map to obtain a circuit pattern detection-design kernel feature correlation sparse weight matrix; S442, position-by-position correlation interactive fusion is performed on the circuit pattern detection feature map and the circuit pattern design feature map to obtain a circuit pattern detection-design position-by-position interactive fusion feature map; S443, based on the circuit pattern detection-design kernel feature correlation sparse weight matrix, feature significant sparse modulation is performed on the circuit pattern detection-design position-by-position interactive fusion feature map to obtain a circuit pattern detection-design significantly sparse interactive fusion feature map as the circuit pattern detection-design significantly sparse interactive fusion feature.

[0038] Optionally, in one embodiment of the present application, Figure 5 In the method for high-density circuit boards based on electroplating eclipse process of the embodiment of the present application, a schematic flow chart of performing kernel correlation sparse masking on the circuit pattern detection feature map and the circuit pattern design feature map to obtain a circuit pattern detection-design kernel feature correlation sparse weight matrix. Figure 5 As shown, the circuit pattern detection feature map and the circuit pattern design feature map are subjected to kernel correlation sparse masking to obtain a circuit pattern detection-design kernel feature correlation sparse weight matrix, including: S4411, inputting the circuit pattern detection feature map and the circuit pattern design feature map into a kernel feature distillation network respectively to obtain a circuit pattern detection kernel feature vector and a circuit pattern design kernel feature vector; S4412, performing global correlation coding on the circuit pattern detection kernel feature vector and the circuit pattern design kernel feature vector to obtain a circuit pattern detection-design kernel feature correlation global coding matrix; S4413, inputting the circuit pattern detection-design kernel feature correlation global coding matrix into a sparse masking unit to obtain the circuit pattern detection-design kernel feature correlation sparse weight matrix.

[0039] Optionally, in one embodiment of the present application, the circuit pattern detection feature map and the circuit pattern design feature map are respectively input into a kernel feature distillation network to obtain a circuit pattern detection kernel feature vector and a circuit pattern design kernel feature vector, including: performing feature decoupling on the circuit pattern detection feature map to obtain a set of circuit pattern detection decoupling feature vectors; calculating feature difference identification of each circuit pattern detection decoupling feature vector in the set of circuit pattern detection decoupling feature vectors relative to other circuit pattern detection decoupling feature vectors to obtain a circuit pattern detection decoupling feature difference representation vector; normalizing the circuit pattern detection decoupling feature difference representation vector to obtain a circuit pattern detection decoupling feature difference weight representation vector; using each eigenvalue of the circuit pattern detection decoupling feature difference weight representation vector as a weighted weight, weighted fusion of the set of circuit pattern detection decoupling feature vectors to obtain a circuit pattern detection kernel feature vector.

[0040] Optionally, in one embodiment of the present application, the feature difference identification of each circuit pattern detection decoupling feature vector in the set of the circuit pattern detection decoupling feature vector relative to other circuit pattern detection decoupling feature vectors is calculated to obtain a circuit pattern detection decoupling feature difference representation vector, including: subtracting each circuit pattern detection decoupling feature vector in the set of the circuit pattern detection decoupling feature vector from other circuit pattern detection decoupling feature vectors by position to obtain a set of subtracted circuit pattern detection decoupling feature vectors, calculating a norm of each subtracted circuit pattern detection decoupling feature vector in the set of the subtracted circuit pattern detection decoupling feature vectors, accumulating and summing them, and then dividing them by the number of vectors in the set of the circuit pattern detection decoupling feature vectors minus one to obtain each eigenvalue of the circuit pattern detection decoupling feature difference representation vector. Here, it should be understood that the circuit pattern design feature map is input into the kernel feature distillation network to obtain the circuit pattern design kernel feature vector, and this data processing process can refer to the above-mentioned method for processing the circuit pattern detection feature map.

[0041] Optionally, in one embodiment of the present application, the circuit pattern detection decoupling feature difference representation vector is normalized to obtain a circuit pattern detection decoupling feature difference weight representation vector, including: calculating the natural exponential function value of each eigenvalue in the circuit pattern detection decoupling feature difference representation vector to obtain a circuit pattern detection decoupling feature difference index representation vector; accumulating and summing each eigenvalue in the circuit pattern detection decoupling feature difference index representation vector to obtain a difference index sum value; and dividing each eigenvalue in the circuit pattern detection decoupling feature difference index representation vector by the difference index sum value to obtain the circuit pattern detection decoupling feature difference weight representation vector.

[0042] Optionally, in one embodiment of the present application, the circuit pattern detection kernel feature vector and the circuit pattern design kernel feature vector are globally correlated and encoded to obtain a global coding matrix between circuit pattern detection and design kernel features, including: multiplying the circuit pattern detection kernel feature vector with the transposed vector of the circuit pattern design kernel feature vector to obtain the global coding matrix between circuit pattern detection and design kernel features.

[0043] Optionally, in one embodiment of the present application, the circuit pattern detection-design kernel feature global coding matrix is ​​input into a sparse mask unit to obtain a circuit pattern detection-design kernel feature correlation sparse weight matrix, including: determining a first threshold, and taking twice the first threshold as a second threshold; comparing each eigenvalue of the circuit pattern detection-design kernel feature global coding matrix with the first threshold and the second threshold respectively, and scaling each eigenvalue of the compared circuit pattern detection-design kernel feature global coding matrix to obtain the circuit pattern detection-design kernel feature correlation sparse weight matrix.

[0044] Optionally, in one embodiment of the present application, each eigenvalue of the global coding matrix between the circuit pattern detection-design kernel features is compared with the first threshold and the second threshold respectively, and each eigenvalue of the global coding matrix between the circuit pattern detection-design kernel features after comparison is scaled to obtain a circuit pattern detection-design kernel feature correlation sparse weight matrix, including: in response to the eigenvalue of the global coding matrix between the circuit pattern detection-design kernel features being greater than the second threshold, the eigenvalue of the global coding matrix between the circuit pattern detection-design kernel features is amplified by three times; in response to the eigenvalue of the global coding matrix between the circuit pattern detection-design kernel features being greater than the first threshold and less than the second threshold, the eigenvalue of the global coding matrix between the circuit pattern detection-design kernel features remains unchanged; in response to the eigenvalue of the global coding matrix between the circuit pattern detection-design kernel features being less than the first threshold, the eigenvalue of the global coding matrix between the circuit pattern detection-design kernel features is reduced by three times.

[0045] Optionally, in one embodiment of the present application, the circuit pattern detection feature map and the circuit pattern design feature map are correlated and interactively fused position by position to obtain a circuit pattern detection-design position by position interactive fusion feature map, including: multiplying the circuit pattern detection feature map and the circuit pattern design feature map position by position to obtain the circuit pattern detection-design position by position interactive fusion feature map.

[0046] Optionally, in one embodiment of the present application, the circuit pattern detection-design position-by-position interactive fusion feature map is subjected to feature significant sparse modulation to obtain a circuit pattern detection-design significant sparse interactive fusion feature map as a circuit pattern detection-design significant sparse interactive fusion feature, including: multiplying each feature matrix of the circuit pattern detection-design position-by-position interactive fusion feature map along the channel dimension with the associated sparse weight matrix between the circuit pattern detection-design kernel features to obtain the circuit pattern detection-design significant sparse interactive fusion feature map.

[0047] In summary, in the embodiment of the present application, the circuit pattern detection feature map and the circuit pattern design feature map are significantly interactively fused using the following significant interactive fusion formula to obtain a circuit pattern detection-design significant sparse interactive fusion feature, wherein the significant interactive fusion formula is:

[0048]

[0049]

[0050]

[0051]

[0052]

[0053]

[0054] in, represents the circuit pattern detection feature map, Represents the circuit pattern design feature diagram, represents the kernel feature distillation network, represents the input feature map of the kernel feature distillation network, represents the feature graph decoupling operation, represents the set of decoupled eigenvectors, , , , , denote the first, second, and third decoupled eigenvectors in the set. , and decoupled eigenvectors, represents the number of vectors in the set of decoupled eigenvectors, represents the one-norm of the calculated vector, represents the number of vectors in the set of decoupled eigenvectors minus one, represents the first The eigenvalues ​​at the positions, represents the output kernel feature vector of the kernel feature distillation network, represents the circuit pattern detection kernel feature vector, represents the circuit pattern design kernel feature vector, represents the transpose of a vector, represents the global encoding matrix between circuit pattern detection-design kernel features, Represents each eigenvalue in the global encoding matrix between circuit pattern detection-design kernel features, represents matrix multiplication, represents a sparse mask operation, represents the first threshold, represents the sparse weight matrix of the correlation between circuit pattern detection-design kernel features, represents the position-by-position point product, Represents the circuit pattern detection-design position-by-position interactive fusion feature map, Representing circuit pattern detection-design sparse interaction fusion feature map.

[0055] Specifically, the data processing flow for significantly interactively fusing the circuit pattern detection feature graph and the circuit pattern design feature graph includes first inputting the circuit pattern detection feature graph and the circuit pattern design feature graph into a kernel feature distillation network to obtain a circuit pattern detection kernel feature vector and a circuit pattern design kernel feature vector. The kernel feature distillation network utilizes the powerful representation ability of neural networks, which not only reduces redundant information but also improves the expressiveness and robustness of features. It obtains a circuit pattern detection kernel feature vector and a circuit pattern design kernel feature vector by identifying and enhancing feature attributes that can best distinguish or describe the essence of data. The circuit pattern detection kernel feature vector and the circuit pattern design kernel feature vector retain the core attribute information of the original data (i.e., the circuit pattern detection feature graph and the circuit pattern design feature graph).

[0056] Next, the circuit pattern detection kernel feature vector and the circuit pattern design kernel feature vector are globally associated and encoded to obtain a circuit pattern detection-design kernel feature global encoding matrix. That is, the two kernel feature vectors are processed by global association encoding technology to construct a circuit pattern detection-design kernel feature global encoding matrix that can reflect the strength and pattern of the relationship between the two. The circuit pattern detection-design kernel feature global encoding matrix is ​​essentially a high-order feature matrix, in which the element values ​​reflect the degree of correlation between each feature dimension, which helps to discover potential data patterns and provides a solid foundation for the subsequent sparsification, ensuring that only the most relevant feature interactions are retained for further processing. Then, the circuit pattern detection-design kernel feature global encoding matrix is ​​input into a sparse mask unit to obtain a circuit pattern detection-design kernel feature correlation sparse weight matrix. That is, the sparsity principle is introduced to filter out less important connections or weights, while highlighting those parts that are most critical to the overall information transfer. The result of this is the formation of a circuit pattern detection-design kernel feature correlation sparse weight matrix, which effectively condenses the key information flow paths in the original data.

[0057] At the same time, on another data processing link, the circuit pattern detection feature map and the circuit pattern design feature map are input into the position-by-position association interaction to obtain the circuit pattern detection-design position-by-position interaction fusion feature map. This step directly acts on the two feature maps initially provided. This step focuses on the feature interaction at the local detail level, and realizes the information exchange and integration at each corresponding position across the feature maps through the position-by-position association interaction, and finally forms the circuit pattern detection-design position-by-position interaction fusion feature map.

[0058] Finally, based on the correlation sparse weight matrix between the circuit pattern detection-design kernel features, the circuit pattern detection-design position-by-position interactive fusion feature map is subjected to feature significant sparse modulation to obtain the circuit pattern detection-design significant sparse interactive fusion feature map. The final stage involves modulating the circuit pattern detection-design position-by-position interactive fusion feature map based on the previously generated correlation sparse weight matrix. This modulation process adjusts the contribution of each part according to the importance level indicated by the weight matrix, so that the adjusted result, i.e., the circuit pattern detection-design significant sparse interactive fusion feature map, can better reflect the most representative and relevant feature combination in the original input.

[0059] In the above-mentioned method for high-density circuit boards based on electroplating eclipse process, the S45 determines the recognition result of the circuit pattern image based on the circuit pattern detection-design significant sparse interactive fusion features. Optionally, in one embodiment of the present application, the recognition result of the circuit pattern image is determined based on the circuit pattern detection-design significant sparse interactive fusion feature map, including: inputting the circuit pattern detection-design significant sparse interactive fusion feature map into a classifier-based defect identifier to obtain the recognition result, and the recognition result is used to indicate whether the circuit pattern has defects. That is, the circuit pattern detection-design significant sparse interactive fusion features after significant interactive fusion are used for classification processing to automatically determine whether the circuit pattern has defects. In this way, through automated image processing technology, defects on the circuit board can be accurately detected, and detection efficiency and accuracy can be improved.

[0060] Preferably, inputting the circuit pattern detection-design significant sparse interaction fusion feature map into a classifier-based defect identifier to obtain an identification result comprises: Determine a circuit pattern detection-design significant sparse interaction fusion probability value obtained by inputting the circuit pattern detection-design significant sparse interaction fusion feature map into a classifier-based defect identifier, wherein the circuit pattern detection-design significant sparse interaction fusion probability value indicates a probability that a circuit pattern has a defect; Expanding the circuit pattern detection-design significant sparse interactive fusion feature map into a circuit pattern detection-design significant sparse interactive fusion feature vector; Calculate the product of the first circuit pattern detection-design significant sparse interactive fusion feature value of the circuit pattern detection-design significant sparse interactive fusion feature vector and the circuit pattern detection-design significant sparse interactive fusion probability value to obtain a first circuit pattern detection-design significant sparse interactive fusion feature probability product; Calculate the product of a second circuit pattern detection-design significant sparse interactive fusion feature value of the circuit pattern detection-design significant sparse interactive fusion feature vector and a difference between one and the circuit pattern detection-design significant sparse interactive fusion probability value to obtain a second circuit pattern detection-design significant sparse interactive fusion feature inverse probability product; Calculate the quotient of the first circuit pattern detection-design significant sparse interaction fusion feature value divided by the difference between one and the circuit pattern detection-design significant sparse interaction fusion probability value to obtain a first circuit pattern detection-design significant sparse interaction fusion feature inverse probability quotient; Calculating the quotient of the second circuit pattern detection-design significant sparse interaction fusion feature value and the circuit pattern detection-design significant sparse interaction fusion probability value to obtain a second circuit pattern detection-design significant sparse interaction fusion feature probability quotient; After adding the first circuit pattern detection-design significant sparse interaction fusion feature probability product and the second circuit pattern detection-design significant sparse interaction fusion feature inverse probability product, subtract the difference between the first circuit pattern detection-design significant sparse interaction fusion feature inverse probability quotient and the second circuit pattern detection-design significant sparse interaction fusion feature probability quotient to obtain a circuit pattern detection-design significant sparse interaction fusion correction feature value; For each first circuit pattern detection-design significant sparse interactive fusion feature value and second circuit pattern detection-design significant sparse interactive fusion feature value of the circuit pattern detection-design significant sparse interactive fusion feature vector, matrix multiplying a circuit pattern detection-design significant sparse interactive fusion correction feature matrix composed of the circuit pattern detection-design significant sparse interactive fusion correction feature values ​​with the circuit pattern detection-design significant sparse interactive fusion feature vector to obtain a corrected circuit pattern detection-design significant sparse interactive fusion feature vector; The corrected circuit pattern detection-design significant sparse interaction fusion feature vector is input into a classifier-based defect identifier to obtain an identification result.

[0061] Wherein, the circuit pattern detection-design significant sparse interactive fusion feature vector The correction process is expressed as:

[0062]

[0063]

[0064] in, is the circuit pattern detection-design significant sparse interaction fusion probability value, A circuit pattern detection-design significant sparse interactive fusion feature vector representing the circuit pattern detection-design significant sparse interactive fusion feature map expanded, and respectively represent the first circuit pattern detection-design significant sparse interactive fusion feature value and the second circuit pattern detection-design significant sparse interactive fusion feature value of the circuit pattern detection-design significant sparse interactive fusion feature vector, Represents the eigenvalue corresponding to and Circuit pattern detection - Design of significant sparse interactive fusion correction eigenvalues, represents a circuit pattern detection-design significant sparse interactive fusion correction feature matrix composed of the circuit pattern detection-design significant sparse interactive fusion correction feature values, represents matrix multiplication, Representation of corrected circuit pattern detection-design by significantly sparse interaction fusion feature vector.

[0065] That is, when the circuit pattern detection feature map and the circuit pattern design feature map respectively represent the twin image semantic features of the circuit pattern image and the circuit pattern design image, when performing significant interaction fusion encoding based on kernel-related sparse masks on them, the circuit pattern detection-design significant sparse interaction fusion feature map will also cause feature significance joint interaction diversity due to differences in image semantic kernel expression patterns, affecting the iterative consistency of the classification mapping and reducing the accuracy of the classification results.

[0066] Therefore, the present application targets the region-boundary integral relationship of the high-dimensional feature manifold of the circuit pattern detection-design significant sparse interactive fusion feature graph, and approximates the simply connected region representation of the high-dimensional manifold of the feature set of the circuit pattern detection-design significant sparse interactive fusion feature graph composed of eigenvalue pairs by defining the overall probability distribution of the feature set of the circuit pattern detection-design significant sparse interactive fusion feature graph as a manifold constraint boundary, so as to avoid the ambiguity in the mapping of the diversified feature representation of the circuit pattern detection-design significant sparse interactive fusion feature graph to the local manifold representation in the high-dimensional feature class convergence space, improve the execution iteration consistency of each local feature distribution in the mapping task, so as to improve the feature classification convergence effect and improve the accuracy of the recognition results obtained by the classifier-based defect identifier.

[0067] In summary, according to the method of high-density circuit boards based on electroplating eclipse process in the embodiment of the present application, a circuit pattern image collected by an industrial camera is obtained, and a circuit pattern design image is extracted from a database. Then, image analysis and processing technology based on deep learning is used to extract features of the circuit pattern image and the circuit pattern design image respectively and perform significant interactive fusion to obtain circuit pattern detection-design significant sparse interactive fusion features. Finally, based on the circuit pattern detection-design significant sparse interactive fusion features, the circuit pattern is automatically detected to see if there are defects. In this way, through automated image processing technology, defects on circuit boards can be more intelligently identified and detected, thereby helping to improve detection efficiency and accuracy. At the same time, the use of a deep learning model can learn and identify multiple types of defects, which can improve the generalization ability of detection application scenarios, thereby reducing the possibility of misjudgment and missed detection. In other words, this method can adapt to different types of circuit boards and complex pattern designs, and improve the flexibility and adaptability of detection.

[0068] Specifically, a high-density circuit board based on electroplating eclipse process is also provided, and the high-density circuit board based on electroplating eclipse process is manufactured by the aforementioned method for manufacturing a high-density circuit board based on electroplating eclipse process.

[0069] The basic principle of the present invention is described above in conjunction with specific embodiments. However, it should be pointed out that the advantages, strengths, effects, etc. mentioned in the present invention are only examples and not limitations, and it cannot be considered that these advantages, strengths, effects, etc. must be possessed by each embodiment of the present invention. In addition, the specific details of the above embodiments are only for the purpose of illustration and facilitation of understanding, rather than limitation, and the above details do not limit the present invention to being implemented by adopting the above specific details.

[0070] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, please refer to the relevant description of other embodiments. In the several embodiments provided by the present invention, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the module division is only a logical function division, and there may be other division methods in actual implementation. The modules described as separate components may or may not be physically separated, and the components displayed as modules may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment.

[0071] In addition, each functional module in each embodiment of the present invention may be integrated into one processing unit, each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of hardware plus software functional modules.

[0072] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference to a figure in a claim should not be considered as limiting the claim to which it relates.

[0073] In addition, it is obvious that the word "comprising" does not exclude other units or steps, and the singular does not exclude the plural. Multiple units stated in the device claim can also be implemented by one unit through software or hardware.

[0074] Finally, it should be noted that the above description has been given for the purpose of illustration and description. In addition, the above embodiments are only used to illustrate the technical solution of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that the technical solution of the present invention can be modified or replaced by equivalents without departing from the spirit and scope of the technical solution of the present invention.

Claims

1. A method for high-density circuit boards based on electroplating eclipse technology, characterized in that: include: Providing a substrate, wherein the material of the substrate is FR-4 epoxy glass fiber board; Covering the substrate with a copper layer, and coating a photosensitive dry film on the copper layer; Using an exposure device to transfer a preset circuit pattern onto the photosensitive dry film to obtain a circuit board substrate after exposure treatment; Performing a development process on the circuit board substrate after the exposure process to remove the unexposed portion of the photosensitive dry film to obtain a circuit board substrate after the development process; Electroplating the circuit board substrate after the development process to obtain a circuit board substrate after the electroplating process; Removing all the remaining photosensitive dry film and the copper layer below the photosensitive dry film to obtain a circuit board substrate after stripping; Performing surface treatment on the circuit board substrate after the stripping treatment to obtain a circuit board substrate after the surface treatment; The circuit board substrate after the surface treatment is subjected to drilling treatment to obtain a high-density circuit board based on the electroplating erosion process.

2. The method for high-density circuit board based on electroplating eclipse process according to claim 1, characterized in that: Performing a development process on the circuit board substrate after the exposure process to remove the photosensitive dry film at the unexposed portion to obtain the circuit board substrate after the development process, comprising: Acquire a circuit pattern image captured by an industrial camera; extracting a circuit pattern design image from a database; Performing circuit pattern feature extraction on the circuit pattern image and the circuit pattern design image to obtain a circuit pattern detection feature map and a circuit pattern design feature map; The circuit pattern detection feature map and the circuit pattern design feature map are significantly interactively fused to obtain a circuit pattern detection-design significant sparse interactive fusion feature, including: performing kernel correlation sparse masking on the circuit pattern detection feature map and the circuit pattern design feature map to obtain a circuit pattern detection-design kernel feature correlation sparse weight matrix; performing position-by-position correlation interactive fusion on the circuit pattern detection feature map and the circuit pattern design feature map to obtain a circuit pattern detection-design position-by-position interactive fusion feature map; based on the circuit pattern detection-design kernel feature correlation sparse weight matrix, performing feature significant sparse modulation on the circuit pattern detection-design position-by-position interactive fusion feature map to obtain a circuit pattern detection-design significant sparse interactive fusion feature map as the circuit pattern detection-design significant sparse interactive fusion feature; Based on the circuit pattern detection-design significant sparse interactive fusion features, the recognition result of the circuit pattern image is determined.

3. The method for high-density circuit board based on electroplating eclipse process according to claim 2, characterized in that: Extracting circuit pattern features from the circuit pattern image and the circuit pattern design image to obtain a circuit pattern detection feature map and a circuit pattern design feature map, including: The circuit pattern image and the circuit pattern design image are input into a circuit pattern twin detection model including a first circuit pattern image feature extractor and a second circuit pattern image feature extractor to obtain the circuit pattern detection feature map and the circuit pattern design feature map.

4. The method for high-density circuit board based on electroplating eclipse process according to claim 3, characterized in that: Performing kernel correlation sparse masking on the circuit pattern detection feature map and the circuit pattern design feature map to obtain a circuit pattern detection-design kernel feature correlation sparse weight matrix, including: Inputting the circuit pattern detection feature map and the circuit pattern design feature map into a kernel feature distillation network respectively to obtain a circuit pattern detection kernel feature vector and a circuit pattern design kernel feature vector; Performing global correlation coding on the circuit pattern detection kernel feature vector and the circuit pattern design kernel feature vector to obtain a global coding matrix between circuit pattern detection-design kernel features; The circuit pattern detection-design kernel feature global encoding matrix is ​​input into a sparse mask unit to obtain the circuit pattern detection-design kernel feature associated sparse weight matrix.

5. The method for high-density circuit board based on electroplating eclipse process according to claim 4, characterized in that: Inputting the circuit pattern detection feature map and the circuit pattern design feature map into a kernel feature distillation network respectively to obtain a circuit pattern detection kernel feature vector and a circuit pattern design kernel feature vector, comprising: Performing feature decoupling on the circuit pattern detection feature map to obtain a set of circuit pattern detection decoupling feature vectors; Calculating feature difference identification of each circuit pattern detection decoupling feature vector in the set of circuit pattern detection decoupling feature vectors relative to other circuit pattern detection decoupling feature vectors to obtain a circuit pattern detection decoupling feature difference representation vector; Normalizing the circuit pattern detection decoupling feature difference representation vector to obtain a circuit pattern detection decoupling feature difference weight representation vector; Each eigenvalue of the circuit pattern detection decoupling feature difference weight representation vector is used as a weighted weight, and a set of the circuit pattern detection decoupling feature vectors is weightedly fused to obtain a circuit pattern detection kernel feature vector.

6. The method for high-density circuit board based on electroplating eclipse process according to claim 5, characterized in that: Normalizing the circuit pattern detection decoupling feature difference representation vector to obtain a circuit pattern detection decoupling feature difference weight representation vector, including: Calculating the natural exponential function value of each characteristic value in the circuit pattern detection decoupling characteristic difference representation vector to obtain the circuit pattern detection decoupling characteristic difference index representation vector; Accumulating and summing each characteristic value in the circuit pattern detection decoupling characteristic difference index representation vector to obtain a difference index sum value; Each characteristic value in the circuit pattern detection decoupling feature difference index representation vector is divided by the difference index sum value to obtain the circuit pattern detection decoupling feature difference weight representation vector.

7. The method for high-density circuit board based on electroplating eclipse process according to claim 6, characterized in that: The circuit pattern detection-design kernel feature global encoding matrix is ​​input into a sparse mask unit to obtain a circuit pattern detection-design kernel feature correlation sparse weight matrix, including: Determine a first threshold, and use twice the first threshold as a second threshold; Each eigenvalue of the global coding matrix between the circuit pattern detection-design kernel features is compared with the first threshold and the second threshold respectively, and each eigenvalue of the global coding matrix between the circuit pattern detection-design kernel features after comparison is scaled to obtain the circuit pattern detection-design kernel feature correlation sparse weight matrix.

8. The method for high-density circuit board based on electroplating eclipse process according to claim 7, characterized in that: Comparing each eigenvalue of the circuit pattern detection-design kernel feature global coding matrix with the first threshold and the second threshold respectively, and scaling each eigenvalue of the compared circuit pattern detection-design kernel feature global coding matrix to obtain a circuit pattern detection-design kernel feature correlation sparse weight matrix, including: In response to the eigenvalue of the circuit pattern detection-design kernel feature inter-global coding matrix being greater than a second threshold, amplifying the eigenvalue of the circuit pattern detection-design kernel feature inter-global coding matrix by three times; In response to the eigenvalue of the circuit pattern detection-design kernel feature global coding matrix being greater than a first threshold and less than a second threshold, the eigenvalue of the circuit pattern detection-design kernel feature global coding matrix is ​​kept unchanged; In response to the eigenvalue of the circuit pattern detection-design kernel feature-to-feature global coding matrix being less than a first threshold, the eigenvalue of the circuit pattern detection-design kernel feature-to-feature global coding matrix is ​​reduced by three times.

9. The method for high-density circuit board based on electroplating eclipse process according to claim 8, characterized in that: Based on the circuit pattern detection-design significant sparse interactive fusion feature map, a recognition result of the circuit pattern image is determined, including: The circuit pattern detection-design significant sparse interaction fusion feature map is input into a classifier-based defect identifier to obtain the identification result, and the identification result is used to indicate whether the circuit pattern has a defect.

10. A high-density circuit board based on electroplating eclipse process, characterized in that: The high-density circuit board based on the electroplating eclipse process is manufactured by the method for producing a high-density circuit board based on the electroplating eclipse process as described in any one of claims 1-9.

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