Gate drive circuit and display panel

Abstract

The invention discloses a gate drive circuit and a display panel, and the gate drive circuit is controlled by one of a fourth node, the output end of a second output module or the first node of a next-stage shift register. The voltage regulation module can stabilize or reduce the grid potential of the second transistor through the low voltage signal, and then the potential of the second grid driving signal can be maintained at the high potential or the pulse amplitude.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a gate drive circuit and a display panel. Background Art

[0002] In a display panel, a gate driving circuit is usually used to provide corresponding gate driving signals for different transistors. The stability of the gate driving signal is particularly critical to the working stability of the transistor.

[0003] However, the jump of the corresponding signal potential in the gate driving circuit is likely to affect the potential stability of the internal node, and the potential stability of the internal node will further affect the stability of the gate driving signal. Summary of the invention

[0004] The present application provides a gate driving circuit and a display panel to alleviate the technical problem of low potential stability of a gate driving signal.

[0005] In a first aspect, the present application provides a gate drive circuit, which includes multiple shift registers, and the shift register includes a level transmission signal selection module, a pull-up control module, a first filter module, a second filter module, a first inversion module, a first output module, a second output module and a voltage regulation module. The level transmission signal selection module is electrically connected between the first wiring and the first node; the pull-up control module controls the potential of the second node according to the potential of the first node and the potential of the first clock signal; the first filter module is electrically connected between the second node and the third node, and the control end of the first filter module is connected to the reset signal; the second filter module is electrically connected between the first filter module and the third node, and the control end of the second filter module is connected to the filter control signal; the first inversion module is connected between the second node and the third node. The first output module outputs a first gate drive signal according to the potential of the third node and the potential of the fourth node; the second output module includes a first P-channel transistor and a second N-channel transistor, the first electrode of the first transistor is electrically connected to the first high potential line, the second electrode of the first transistor is electrically connected to the first electrode of the second transistor to output the second gate drive signal, the second electrode of the second transistor is connected to the first low potential signal, and the second node is electrically connected to the gate of the first transistor and the gate of the second transistor; one end of the voltage regulating module is connected to the low voltage signal, the other end of the voltage regulating module is connected to the gate of the second transistor, and the control end of the voltage regulating module is electrically connected to the fourth node, the output end of the second output module or one of the first nodes of the next stage shift register.

[0006] In the second aspect, the present application provides a display panel, which includes a pixel circuit and a gate driving circuit in at least one of the above-mentioned embodiments, the pixel circuit includes a write transistor for controlling the input of a data signal and a compensation transistor for controlling the input of the data signal to the gate of the driving transistor; the output end of the first output module is electrically connected to the gate of the write transistor, and the output end of the second output module is electrically connected to the gate of the compensation transistor.

[0007] The gate drive circuit and display panel provided in the present application, under the control of one of the fourth node, the output end of the second output module or the first node of the next-stage shift register, the voltage regulation module can stabilize or reduce the gate potential of the second transistor through a low voltage signal, so that the second transistor is stabilized or better in the cut-off state to reduce leakage current, and then the potential of the second gate drive signal can be maintained at a high potential or pulse amplitude, thereby improving the potential stability of the gate drive signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0009] Figure 1 It is a structural schematic diagram of a pixel circuit in the related art.

[0010] Figure 2 for Figure 1 A timing diagram of the pixel circuit.

[0011] Figure 3 It is a schematic diagram of the first structure of a gate drive circuit in the related art.

[0012] Figure 4 for Figure 3 The timing diagram of the gate drive circuit shown.

[0013] Figure 5 for Figure 3 The gate drive circuit shown in Figure 4 Schematic diagram of the first stage of the process.

[0014] Figure 6 for Figure 3 The gate drive circuit shown in Figure 4 Schematic diagram of the second stage of the status.

[0015] Figure 7 for Figure 3 The gate drive circuit shown in Figure 4 Schematic diagram of the third stage of the status.

[0016] Figure 8 for Figure 3 The gate drive circuit shown in Figure 4 Schematic diagram of the fourth stage of the status.

[0017] Fig. 9 for Figure 3 The gate drive circuit shown in Figure 4 Schematic diagram of the fifth stage of the status.

[0018] Fig.10 for Figure 3 The gate drive circuit shown in Figure 4 Schematic diagram of the sixth stage of the status.

[0019] Fig.11 for Figure 3 The gate drive circuit shown in Figure 4 Schematic diagram of the seventh stage of the state.

[0020] Fig.12 for Figure 3 The gate drive circuit shown in Figure 4 Schematic diagram of the eighth stage of the state.

[0021] Fig.13 for Figure 3 The gate drive circuit shown in Figure 4 Schematic diagram of the ninth stage of the process.

[0022] Fig.14 for Figure 3 The gate drive circuit shown in Figure 4 Schematic diagram of the status of the tenth stage.

[0023] Fig.15 for Figure 3 The gate drive circuit shown in Figure 4 Schematic diagram of the status of the eleventh stage.

[0024] Fig.16 for Figure 3 The gate drive circuit shown in Figure 4 Schematic diagram of the status of the twelfth stage.

[0025] Fig.17 for Figure 3 The gate drive circuit shown in Figure 4 Schematic diagram of the status of the thirteenth stage.

[0026] Fig.18 for Figure 3 The gate drive circuit shown in Figure 4 Schematic diagram of the status of the fourteenth stage.

[0027] Fig.19 for Figure 3 The gate drive circuit shown in Figure 4 Schematic diagram of the status of the fifteenth stage.

[0028] Fig. 20 It is a second structural schematic diagram of a gate driving circuit in the related art.

[0029] Fig.21 for Fig. 20 The timing diagram of the gate drive circuit shown.

[0030] Fig. 22 for Fig. 20 The gate drive circuit shown in Fig.21 Schematic diagram of the first stage of the state.

[0031] Fig.23 for Fig. 20 The gate drive circuit shown in Fig.21 Schematic diagram of the second stage of the status.

[0032] Fig.24 for Fig. 20 The gate drive circuit shown in Fig.21 Schematic diagram of the third stage of the status.

[0033] Fig.25 for Fig. 20 The gate drive circuit shown in Fig.21 Schematic diagram of the fourth stage of the status.

[0034] Fig.26 for Fig. 20 The gate drive circuit shown in Fig.21 Schematic diagram of the fifth stage of the status.

[0035] Fig. 27 for Fig. 20 The gate drive circuit shown in Fig.21 Schematic diagram of the sixth stage of the status.

[0036] Fig.28 for Fig. 20 The gate drive circuit shown in Fig.21 Schematic diagram of the seventh stage of the state.

[0037] Fig.29 for Fig. 20 The gate drive circuit shown in Fig.21 Schematic diagram of the eighth stage of the process.

[0038] Fig.30 A timing diagram of the generation of the Nth level negative pulse gate drive signal provided in an embodiment of the present application.

[0039] Fig.31 for Figure 3 or Fig. 20 The timing diagram of some nodes in the gate drive circuit is shown.

[0040] Fig.32 A first structural schematic diagram of a gate drive circuit provided in an embodiment of the present application.

[0041] Fig.33 A second structural schematic diagram of the gate drive circuit provided in an embodiment of the present application.

[0042] Fig.34 for Fig.32 , Fig.33 The timing diagram of the gate drive circuit shown.

[0043] Fig.35 for Fig.32 The gate drive circuit shown in Fig.34 Schematic diagram of the first stage of the state.

[0044] Fig.36 for Fig.32 The gate drive circuit shown in Fig.34 Schematic diagram of the second stage of the status.

[0045] Fig.37 for Fig.32 The gate drive circuit shown in Fig.34 Schematic diagram of the third stage of the status.

[0046] Fig.38 for Fig.32 The gate drive circuit shown in Fig.34 Schematic diagram of the fourth stage of the status.

[0047] Fig.39 for Fig.32 The gate drive circuit shown in Fig.34 Schematic diagram of the fifth stage of the status.

[0048] Fig.40 for Fig.32 The gate drive circuit shown in Fig.34 Schematic diagram of the sixth stage of the status.

[0049] Fig.41 for Fig.32 The gate drive circuit shown in Fig.34 Schematic diagram of the seventh stage of the state.

[0050] Fig.42 for Fig.32 The gate drive circuit shown in Fig.34 Schematic diagram of the eighth stage of the process.

[0051] Fig.43 for Fig.32 The gate drive circuit shown in Fig.34 Schematic diagram of the ninth stage of the process.

[0052] Fig.44 for Fig.32 The gate drive circuit shown in Fig.34 Schematic diagram of the status of the tenth stage.

[0053] Fig.45 for Fig.32 The gate drive circuit shown in Fig.34 Schematic diagram of the status of the eleventh stage.

[0054] Fig.46 for Fig.32 The gate drive circuit shown in Fig.34 Schematic diagram of the status of the twelfth stage.

[0055] Fig.47 for Fig.32 The gate drive circuit shown in Fig.34 Schematic diagram of the status of the thirteenth stage.

[0056] Fig.48 for Fig.32 The gate drive circuit shown in Fig.34 Schematic diagram of the status of the fourteenth stage.

[0057] Fig.49 for Fig.32 The gate drive circuit shown in Fig.34 Schematic diagram of the status of the fifteenth stage.

[0058] Fig.50 This is a third structural schematic diagram of the gate driving circuit provided in this embodiment.

[0059] Fig.51 for Fig.50 The timing diagram of the gate drive circuit shown.

[0060] Fig.52 for Fig.50 The gate drive circuit shown in Fig.51 Schematic diagram of the first stage of the process.

[0061] Fig.53 for Fig.50 The gate drive circuit shown in Fig.51 Schematic diagram of the second stage of the status.

[0062] Fig.54 for Fig.50 The gate drive circuit shown in Fig.51 Schematic diagram of the third stage of the status.

[0063] Fig.55 for Fig.50 The gate drive circuit shown in Fig.51 Schematic diagram of the fourth stage of the status.

[0064] Fig.56 for Fig.50 The gate drive circuit shown in Fig.51 Schematic diagram of the fifth stage of the status.

[0065] Fig.57 for Fig.50 The gate drive circuit shown in Fig.51 Schematic diagram of the sixth stage of the status.

[0066] Fig.58 for Fig.50 The gate drive circuit shown in Fig.51 Schematic diagram of the seventh stage of the state.

[0067] Fig.59 for Fig.50 The gate drive circuit shown in Fig.51 Schematic diagram of the eighth stage of the state.

[0068] Fig.60 for Figure 3 or Fig. 20 Schematic diagram of the cascade structure between shift registers in the gate drive circuit shown.

[0069] Fig.61 A schematic diagram of the structure of a display panel provided in an embodiment of the present application.

[0070] Fig.62 A schematic diagram of the structure of a pixel circuit provided in an embodiment of the present application.

[0071] Fig.63 for Fig.62 A timing diagram of the pixel circuit. DETAILED DESCRIPTION

[0072] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0073] In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance or implicitly indicating the number of technical features indicated. Therefore, the features specified as "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present invention, "multiple" means two or more, unless otherwise clearly and specifically defined.

[0074] In the gate drive circuit in the invention application with application number 202310191137.9, the N-th level negative pulse gate drive signal Pout[N] has one negative pulse in one frame. The N-th level positive pulse gate drive signal Nout[N] has two positive pulses in one frame, and the pulse widths of the two positive pulses must be equal and both have a width of 2H. This limits the width of the positive pulse of the N-th level positive pulse gate drive signal Nout[N] to remain consistent and cannot be changed, so that when the width of the positive pulse of the N-th level positive pulse gate drive signal Nout[N] is greater than 2H, the number of negative pulses of the N-th level negative pulse gate drive signal Pout[N] in one frame will increase.

[0075] Therefore, this will limit Figure 1 The pixel circuit shown is in accordance with Figure 2 Specifically, Figure 1 The pixel circuit shown may include at least one of a write transistor T2P, a drive transistor T1P, a first light emission control transistor T5P, a second light emission control transistor T6P, a first initialization transistor T4P, a second initialization transistor T7P, a third initialization transistor T8P, a compensation transistor T3P, a light emitting device D1, a storage capacitor Cst, and a bootstrap capacitor CbOst.

[0076] The first power line is electrically connected to the first electrode of the first light-emitting control transistor T5P and one end of the storage capacitor Cst, the second electrode of the first light-emitting control transistor T5P is electrically connected to the first electrode of the driving transistor T1P and the first electrode of the writing transistor T2P, the second electrode of the driving transistor T1P is electrically connected to the first electrode of the compensation transistor T3P and the first electrode of the second light-emitting control transistor T6P, the second electrode of the second light-emitting control transistor T6P is electrically connected to the first electrode of the second initialization transistor T7P and the anode of the light-emitting device D1, and the cathode of the light-emitting device D1 is electrically connected to the second power line.

[0077] The light emission control line is electrically connected to the gate of the first light emission control transistor T5P and the gate of the second light emission control transistor T6P.

[0078] The second electrode of the write transistor T2P is electrically connected to the data line, the gate of the write transistor T2P is electrically connected to one end of the bootstrap capacitor CbOst, and is connected to the Nth level negative pulse gate drive signal Pout[N]. The second electrode of the second initialization transistor T7P is electrically connected to the second initialization line, and the gate of the second initialization transistor T7P is connected to the gate drive signal Pscan2.

[0079] The second electrode of the compensation transistor T3P is electrically connected to the gate of the driving transistor T1P, and the gate of the compensation transistor T3P is connected to the Nth stage positive pulse gate driving signal Nout[N].

[0080] The gate of the driving transistor T1P is electrically connected to the other end of the storage capacitor Cst, the other end of the bootstrap capacitor CbOst, and the first electrode of the first initialization transistor T4P.

[0081] The second electrode of the first initialization transistor T4P is electrically connected to the first initialization line, and the gate of the first initialization transistor T4P is connected to the N-1th stage positive pulse gate driving signal Nout[N-1].

[0082] A first electrode of the third initialization transistor T8P is electrically connected to a first electrode of the driving transistor T1P, a second electrode of the third initialization transistor T8P is electrically connected to a third initialization line, and a gate of the third initialization transistor T8P and a gate of the second initialization transistor T7P share a gate driving signal Pscan2.

[0083] It should be noted that the second initialization line may also be replaced by the first initialization line, which can reduce one wiring required for the pixel circuit and is beneficial to increase the density of the pixel circuit in the display panel.

[0084] In the present application, the first electrode may be one of the source electrode and the drain electrode, and the second electrode may be the other of the source electrode and the drain electrode. For example, when the first electrode is the source electrode, the second electrode is the drain electrode; or when the first electrode is the drain electrode, the second electrode is the source electrode.

[0085] Among them, the first power line is used to transmit the positive power signal VDD, the second power line is used to transmit the negative power signal VSS, and the potential of the positive power signal VDD is higher than the potential of the negative power signal VSS. The data line is used to transmit the data signal Data. The light control line is used to transmit the light control signal EM. The first initialization line is used to transmit the first initialization signal Vi1. The second initialization line is used to transmit the second initialization signal. The third initialization line is used to transmit the third initialization signal Vi3. The first gate drive line is used to transmit the Nth level negative pulse gate drive signal Pout[N]. The second gate drive line connected to the shift register of different levels is used to transmit the N-1th level positive pulse gate drive signal Nout[N-1] and the Nth level positive pulse gate drive signal Nout[N] respectively.

[0086] As can be seen from the above, in the gate drive circuit shown in the invention application with application number 202310191137.9, the principle of generating a negative pulse in one frame of the Nth level negative pulse gate drive signal Pout[N] is formed by filtering out the first pulse of the start control signal STV or the NYth level positive pulse gate drive signal Nout[NY] through the second pulse of the reset signal RST. Therefore, the widths of the two positive pulses of the start control signal STV or the NYth level positive pulse gate drive signal Nout[NY] must be equal.

[0087] exist Figure 1 In the pixel circuit shown in the figure, in order to realize the synchronous conduction of the compensation transistor T3P and the first initialization transistor T4P, the pulse of the N-1th level positive pulse gate drive signal Nout[N-1] and the pulse of the Nth level positive pulse gate drive signal Nout[N] need to partially overlap, which is also Figure 1 The reason why the first initialization transistor T4P in the pixel circuit shown must be connected to the N-1th stage positive pulse gate driving signal Nout[N-1].

[0088] Furthermore, in order to complete the transmission of the third initialization signal Vi3 via node A and node B to node Q in sequence to reset the potentials of node A, node B, and node Q, the third initialization transistor T8P and the compensation transistor T3P need to be turned on synchronously, which requires the pulse of the gate drive signal Pscan2 to partially overlap with the pulse of the Nth level positive pulse gate drive signal Nout[N].

[0089] And for Figure 1 The pixel circuit shown can continue to use the gate drive signal Pscan2 with a pulse width of only 1H, which requires adjustment Figure 2 The driving timing of the pixel circuit shown in FIG. Figure 1 The gate drive circuit shown is improved.

[0090] In this context, in order to alleviate the technical problem that the pulse of the gate driving signal is difficult to meet the requirements in terms of time and width, this embodiment provides a gate driving circuit, see Figures 3 to 30 ,like Figure 3 , Fig. 20 As shown, the gate driving circuit includes a plurality of shift registers, and the shift register includes at least one of a stage transmission signal selection module 10 , a pull-up control module 20 , a first filtering module 30 , a second filtering module 80 and a first output module 46 .

[0091] The stage transmission signal selection module 10 is electrically connected between the first node O / O[N] and the start control line and the NYth stage positive pulse gate driving line, where Y is an integer greater than or equal to 2.

[0092] The pull-up control module 20 controls the potential of the second node K according to the potential of the first node O / O[N] and the potential of the first clock signal.

[0093] The first filter module 30 is electrically connected between the middle node and one of the second node K or the third node Q. The control end of the first filter module 30 is electrically connected to the NXth stage positive pulse gate drive line, where X is an integer greater than or equal to 2.

[0094] The second filter module 80 is electrically connected between the middle node and the other of the second node K or the third node Q, and the control end of the second filter module 80 is electrically connected to the N-2th stage positive pulse gate drive line.

[0095] The first output module 46 is electrically connected to the third node Q, the fourth node P, and the Nth stage negative pulse gate driving line.

[0096] It can be understood that the gate drive circuit provided in this embodiment filters out the first part of the second pulse that appears later than the second node K in a frame through the first filter module 30, and filters out the second part of the first pulse that appears first and the second pulse that appears later than the second node K in a frame through the second filter module 80. The first part of the fixed width in the first pulse can be retained, and then the first output module 46 can be controlled to output the gate drive signal of the pulse with the fixed width at the corresponding time. After such improvement, it can be suitable for the driving requirements of the back end.

[0097] In one embodiment, the shift register further includes a first inversion module 50 and a second output module 70. The first inversion module 50 is electrically connected between the second node K and the fourth node P; the second output module 70 is electrically connected to the second node K and the Nth level positive pulse gate drive line.

[0098] It is understandable that after Figure 3 , Fig. 20 After the improvement, since the first filtering module 30 can filter out the first part of the second pulse that appears later in a frame at the second node K, and the second filtering module 80 can filter out the second part of the first pulse that appears first and the second pulse that appears later in a frame at the second node K, the first part of the fixed width in the first pulse can be retained, and then the first output module 46 is controlled to output the gate drive signal with the fixed width pulse at the corresponding time, the pulse width of the Nth level positive pulse gate drive signal Nout[N] provided by the second output module 70 will not affect the pulse width of the Nth level negative pulse gate drive signal Pout[N], therefore, the two pulse widths of the Nth level positive pulse gate drive signal Nout[N] in a frame can not only be modulated to a width greater than 2H, but also can be modulated separately without keeping the two pulse widths equal. This provides support for the improvement of the driving timing of the pixel circuit.

[0099] In one embodiment, if Figure 3 , Fig. 20As shown, the first filtering module 30 includes a first filtering transistor T11 and a first capacitor C2, one of the source or the drain of the first filtering transistor T11 is electrically connected to the second node K, the other of the source or the drain of the first filtering transistor T11 is electrically connected to the intermediate node, and the gate of the first filtering transistor T11 is electrically connected to the NXth level positive pulse gate drive line; one end of the first capacitor C2 is electrically connected to the gate of the first filtering transistor T11, and the other end of the first capacitor C2 is electrically connected to the other of the source or the drain of the first filtering transistor T11.

[0100] It needs to be explained that if Fig.30 As shown, the first filtering module 30 is used to filter out the first part of the second pulse that appears after the second node K in one frame.

[0101] In one embodiment, if Figure 3 , Fig. 20 As shown, the second filtering module 80 includes a second filtering transistor T8, one of the source or drain of the second filtering transistor T8 is electrically connected to the intermediate node, the other of the source or drain of the second filtering transistor T8 is electrically connected to the third node Q, and the gate of the first filtering transistor T11 is electrically connected to the N-2th level positive pulse gate drive line.

[0102] It needs to be explained that if Fig.30 As shown, the second filtering module 80 is used to filter out the latter part of the first pulse that appears first and the latter part of the second pulse that appears later at the second node K in a frame.

[0103] It can be seen from this that the first filtering module 30 and the second filtering module 80 are used to filter out the second pulse and retain the first part of the first pulse with a fixed width.

[0104] In one embodiment, if Fig. 20 As shown, the shift register further includes an isolation module 75, which is connected in series between the second node K and the input end of the second output module 70, and a control end of the isolation module 75 is connected to the first clock signal.

[0105] It should be noted that the isolation module 75 is used to reduce the coupling of the pulse amplitude of the Nth level negative pulse gate drive signal Pout[N] to the pulse amplitude of the Nth level positive pulse gate drive signal Nout[N], thereby stabilizing the high potential of the Nth level positive pulse gate drive signal Nout[N].

[0106] In one embodiment, if Fig. 20As shown, the isolation module 75 includes a sixth transistor T14, one of the source or the drain of the sixth transistor T14 is electrically connected to the second node K, the other of the source or the drain of the sixth transistor T14 is electrically connected to the input end of the second output module 70, the gate of the sixth transistor T14 is connected to the first clock signal, and the sixth transistor T14 is a P-channel thin film transistor.

[0107] It should be noted that the sixth transistor T14 can reduce the coupling of the pulse amplitude of the Nth level negative pulse gate drive signal Pout[N] to the pulse amplitude of the Nth level positive pulse gate drive signal Nout[N], thereby stabilizing the high potential of the Nth level positive pulse gate drive signal Nout[N].

[0108] In other embodiments, the isolation module 75 may further include a transistor connected in series between the gate of the sixth transistor T14 and the node N.

[0109] Among them, the input end of the level transmission signal selection module 10 is electrically connected to the starting control line or the NYth level positive pulse gate drive line, wherein N is an integer greater than or equal to 1, and Y is an integer greater than or equal to 1.

[0110] The input end of the pull-up control module 20 is electrically connected to the output end of the stage transmission signal selection module 10 , and the control end of the pull-up control module 20 is electrically connected to the first clock line.

[0111] An input end of the first filter module 30 is electrically connected to an output end of the pull-up control module 20 , and a control end of the first filter module 30 is electrically connected to a reset line.

[0112] The control end of the pull-up module 40 is electrically connected to the output end of the first filter module 30, the input end of the pull-up module 40 is electrically connected to the second clock line, and the output end of the pull-up module 40 is electrically connected to the Nth level negative pulse gate drive line. The input end of the first inversion module 50 is electrically connected to the output end of the pull-up control module 20.

[0113] The control end of the pull-down module 60 is electrically connected to the output end of the first inverting module 50 , the input end of the pull-down module 60 is electrically connected to the high potential line, and the output end of the pull-down module 60 is electrically connected to the Nth stage negative pulse gate driving line.

[0114] In one embodiment, the first output module 46 includes a pull-up module 40 and a pull-down module 60 .

[0115] It should be noted that the first wiring can be a starting control line or a NY-th level positive pulse gate drive line; wherein when NY is less than or equal to 0, the first wiring is a starting control line. The N-th level positive pulse gate drive line, i.e., the second gate control line, is used to transmit the N-th level positive pulse gate drive signal Nout[N], i.e., the second gate drive signal. The N-th level negative pulse gate drive line, i.e., the first gate control line, is used to transmit the N-th level negative pulse gate drive signal Pout[N], i.e., the first gate drive signal.

[0116] In one embodiment, the first filtering module 30 includes a first filtering transistor T11 and a first capacitor C2, one of the source or the drain of the first filtering transistor T11 is electrically connected to the second node K, the other of the source or the drain of the first filtering transistor T11 is electrically connected to the third node Q, and the gate of the first filtering transistor T11 is connected to the reset signal RST; one end of the first capacitor C2 is electrically connected to the gate of the first filtering transistor T11, and the other end of the first capacitor C2 is electrically connected to the other of the source or the drain of the first filtering transistor T11.

[0117] A ratio of a channel width of the first filter transistor T11 to a channel length of the first filter transistor T11 is greater than or equal to 0.5 and less than or equal to 1.5.

[0118] It should be noted that this embodiment is conducive to ensuring the output stability of the Nth level negative pulse gate drive signal Pout[N], and avoids the coupling pull-down phenomenon before the negative pulse arrives.

[0119] In one embodiment, the pull-up module 40 includes a pull-up transistor T6 and a second capacitor C1, the gate of the pull-up transistor T6 is electrically connected to one of the source or drain of the first filter transistor T11, one of the source or drain of the pull-up transistor T6 is electrically connected to the second clock line, and the other of the source or drain of the pull-up transistor T6 is electrically connected to the Nth level negative pulse gate drive line; one end of the second capacitor C1 is electrically connected to the gate of the pull-up transistor T6, and the other end of the second capacitor C1 is electrically connected to the other of the source or drain of the pull-up transistor T6; wherein, the ratio of the capacity of the first capacitor C2 to the second capacitor C1 is greater than or equal to 0.5.

[0120] It should be noted that the design of the capacity ratio of the first capacitor C2 to the second capacitor C1 in this embodiment is conducive to further ensuring the output stability of the Nth level negative pulse gate drive signal Pout[N] and avoiding the coupling pull-down phenomenon before the negative pulse arrives.

[0121] Specifically, the capacity of the first capacitor C2 may be greater than or equal to 50 fF. The capacity of the second capacitor C1 may be greater than or equal to 100 fF.

[0122] The ratio of the channel width of the pull-up transistor T6 to the channel length of the pull-up transistor T6 is greater than 30:1, which is conducive to further ensuring the output stability of the Nth level negative pulse gate drive signal Pout[N]. The pull-up transistor T6 can be a P-channel thin film transistor.

[0123] In one embodiment, the level transmission signal selection module 10 includes a transistor T13 and a transistor T12, one of the source or the drain of the transistor T13 is electrically connected to the low potential line, the other of the source or the drain of the transistor T13 is electrically connected to the input end of the pull-up control module 20, the first gate of the transistor T13 is electrically connected to the start control line or the NYth level positive pulse gate drive line, the first gate of the transistor T13 is electrically connected to the second gate of the transistor T13, and the transistor T13 is an N-channel thin film transistor; one of the source or the drain of the transistor T12 is electrically connected to the high potential line, the other of the source or the drain of the transistor T12 is electrically connected to the other of the source or the drain of the transistor T13, the gate of the transistor T12 is electrically connected to the first gate of the transistor T13, and the transistor T12 is a P-channel thin film transistor.

[0124] It should be noted that the level transfer signal selection module 10 in this embodiment not only has an inverting effect objectively, that is, the potentials of the input signal and the output signal are opposite at the same time, but also plays a role in making the Nth level positive pulse gate drive signal Nout[N] serve as the level transfer signal between the shift registers. Otherwise, level transfer cannot be achieved between the shift registers, which will cause the gate drive circuit to be unable to normally provide the corresponding gate drive signal.

[0125] The ratio of the channel width of the transistor T13 to the channel length of the transistor T13 is greater than 2: 1. The ratio of the channel width of the transistor T12 to the channel length of the transistor T12 is in the range of 0.5:1 to 3:1.

[0126] The high potential line is used to transmit a high potential signal VGH, which can control the N-channel thin film transistor to be turned on or the P-channel thin film transistor to be turned off. The low potential line is used to transmit a low potential signal VGL, which can control the P-channel thin film transistor to be turned on or the N-channel thin film transistor to be turned off.

[0127] In one embodiment, the pull-up control module 20 includes a pull-up control transistor T2, one of the source or the drain of the pull-up control transistor T2 is electrically connected to the output end of the stage transmission signal selection module 10, the other of the source or the drain of the pull-up control transistor T2 is electrically connected to the input end of the first filtering module 30, and the gate of the pull-up control transistor T2 is electrically connected to the first clock line.

[0128] It should be noted that the pull-up control transistor T2 may be a P-channel thin film transistor. The ratio of the channel width of the pull-up control transistor T2 to the channel length of the pull-up control transistor T2 is in the range of 0.5:1 to 3:1.

[0129] In one embodiment, the first inversion module 50 includes a fourth transistor T3 and a fifth transistor T1, one of the source or the drain of the fourth transistor T3 is electrically connected to the high potential line, the other of the source or the drain of the fourth transistor T3 is electrically connected to one of the source or the drain of the fifth transistor T1 and the control end of the pull-down module 60, the other of the source or the drain of the fifth transistor T1 is electrically connected to the low potential line, and the output end of the pull-up control module 20 is electrically connected to the gate of the fourth transistor T3, the first gate of the fifth transistor T1, and the second gate of the fifth transistor T1.

[0130] It should be noted that the fourth transistor T3 is a P-channel thin film transistor and the fifth transistor T1 is a dual-gate N-channel thin film transistor, which can improve the dynamic performance of the fourth transistor T3 and the fifth transistor T1, and further improve the dynamic performance of the first inverter module 50.

[0131] The ratio of the channel width of the fourth transistor T3 to the channel length of the fourth transistor T3 is in the range of 0.5:1 to 3:1. The ratio of the channel width of the fifth transistor T1 to the channel length of the fifth transistor T1 is greater than or equal to 2:1.

[0132] In one embodiment, the pull-down module 60 includes a pull-down transistor T7, one of the source or the drain of the pull-down transistor T7 is electrically connected to the high potential line, the other of the source or the drain of the pull-down transistor T7 is electrically connected to the Nth level negative pulse gate drive line, and the gate of the pull-down transistor T7 is electrically connected to the output end of the first inversion module 50, i.e., the fourth node P.

[0133] It should be noted that the pull-down transistor T7 can be a P-channel thin film transistor. Under the joint action of the pull-down module 60 and the pull-up module 40, the required Nth level negative pulse gate driving signal Pout[N] can be modulated.

[0134] The ratio of the channel width of the pull-down transistor T7 to the channel length of the pull-down transistor T7 is greater than or equal to 30:1.

[0135] The second output module 70 includes a transistor T9 and a transistor T10, one of the source or the drain of the transistor T9 is electrically connected to the high potential line, the other of the source or the drain of the transistor T9 is electrically connected to one of the source or the drain of the transistor T10 and the Nth level positive pulse scanning line, the other of the source or the drain of the transistor T10 is electrically connected to the low potential line, and the output end of the pull-up control module 20 is electrically connected to the gate of the transistor T9, the first gate of the transistor T10 and the second gate of the transistor T10.

[0136] It should be noted that the transistor T9 is a P-channel thin film transistor and the transistor T10 is a dual-gate N-channel thin film transistor, which can improve the dynamic performance of the transistors T9 and T10, and further improve the dynamic performance of the second output module 70.

[0137] The ratio of the channel width of the first transistor T9 to the channel length of the first transistor T9 is greater than or equal to 30:1. The ratio of the channel width of the second transistor T10 to the channel length of the second transistor T10 is greater than or equal to 30:1.

[0138] In one embodiment, the second filter module 80 includes a second filter transistor T8, one of the source or drain of the second filter transistor T8 is electrically connected to the output end of the first filter module 30, the other of the source or drain of the second filter transistor T8 is electrically connected to the control end of the pull-up module 40, and the gate of the second filter transistor T8 is connected to the filter control signal RST2.

[0139] It should be noted that the second filter transistor T8 can be a P-channel thin film transistor; it can also be an N-channel thin film transistor.

[0140] The ratio of the channel width of the second filter transistor T8 to the channel length of the second filter transistor T8 may be in the range of 0.5:1 to 3:1.

[0141] In one embodiment, the N-th stage shift register also includes a feedback module 90, which includes a transistor T4 and a transistor T5, one of the source or the drain of the transistor T4 is electrically connected to the output end of the pull-up control module 20, the gate of the transistor T4 is electrically connected to the second clock line, the other of the source or the drain of the transistor T4 is electrically connected to one of the source or the drain of the transistor T5, the other of the source or the drain of the transistor T5 is electrically connected to the high potential line, and the gate of the transistor T5 is electrically connected to the output end of the first inversion module 50.

[0142] The ratio of the channel width of the transistor T4 to the channel length of the transistor T4 is in the range of 0.5:1 to 3:1. The ratio of the channel width of the transistor T5 to the channel length of the transistor T5 is in the range of 0.5:1 to 3:1.

[0143] It should be noted that the feedback module 90 can maintain the second node K at a high potential based on the potential of the fourth node P and the potential of the second clock line. That is, when the fourth node P is at a low potential and the second clock signal CK is at a low potential, the high potential line can control the potential of the second node K to the potential of the high potential signal VGH.

[0144] It should be noted that the Nth level positive pulse gate drive line is used to transmit the Nth level positive pulse gate drive signal Nout[N]. The Nth level negative pulse gate drive line is used to transmit the Nth level negative pulse gate drive signal Pout[N]. The first clock line is used to transmit the first clock signal XCK. The second clock line is used to transmit the second clock signal CK. The start control line is used to transmit the start control signal STV. The NYth level positive pulse gate drive line is used to transmit the NYth level positive pulse gate drive signal Nout[NY]. The NXth level positive pulse gate drive line is used to transmit the NXth level positive pulse gate drive signal Nout[NX]. The reset line is used to transmit the reset signal RST.

[0145] Figure 3 The operation process of the shift register shown in one frame may include the following: Figure 4 The following stages are shown:

[0146] Stage 1 S1: Figure 4 , Figure 5 As shown, the start control signal STV, the reset signal RST, the second clock signal CK, and the N-2th level positive pulse gate drive signal Nout[N-2] are all at a low potential, the first clock signal XCK is at a high potential, the first node O / O[N], the second node K, the middle node W and the third node Q are all at a high potential, the fourth node P is at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a low potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0147] Stage 2 S2: Figure 4 , Figure 6As shown, the start control signal STV, the reset signal RST, the first clock signal XCK, and the N-2th level positive pulse gate drive signal Nout[N-2] are all at a low potential, the second clock signal CK is at a high potential, the first node O / O[N], the second node K, the middle node W and the third node Q are all at a high potential, the fourth node P is at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a low potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0148] Stage 3 S3: Figure 4 , Figure 7 As shown, the start control signal STV, the second clock signal CK, and the N-2th level positive pulse gate drive signal Nout[N-2] are all at a low potential, the reset signal RST and the first clock signal XCK are at a high potential, the first node O / O[N], the second node K, the middle node W and the third node Q are all at a high potential, the fourth node P is at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a low potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0149] Stage 4 S4: Figure 4 , Figure 8 As shown, the start control signal STV, the first clock signal XCK, and the N-2th level positive pulse gate drive signal Nout[N-2] are all at a low potential, the reset signal RST and the second clock signal CK are at a high potential, the first node O / O[N], the second node K, the middle node W and the third node Q are all at a high potential, the fourth node P is at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a low potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0150] Stage 5 S5: Figure 4 , Fig. 9 As shown, the second clock signal CK is at a low potential, the start control signal STV, the reset signal RST, the first clock signal XCK, and the N-2th level positive pulse gate drive signal Nout[N-2] are at a high potential, the second node K, the middle node W and the third node Q are all at a high potential, the first node O / O[N] and the fourth node P are at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a low potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0151] Stage 6 S6: Figure 4 , Fig.10As shown, the first clock signal XCK is at a low potential, the start control signal STV, the reset signal RST, the second clock signal CK, and the N-2th level positive pulse gate drive signal Nout[N-2] are at a high potential, the middle node W, the fourth node P and the third node Q are all at a high potential, the second node K and the first node O / O[N] are at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a high potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0152] Stage 7 S7: Figure 4 , Fig.11 As shown, the reset signal RST and the second clock signal CK are at a low potential, the start control signal STV, the first clock signal XCK, and the N-2th level positive pulse gate drive signal Nout[N-2] are at a high potential, the fourth node P and the third node Q are both at a high potential, the middle node W, the second node K, and the first node O / O[N] are at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a high potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0153] Stage 8 S8: Figure 4 , Fig.12 As shown, the reset signal RST and the first clock signal XCK are at a low potential, the start control signal STV, the second clock signal CK, and the N-2th level positive pulse gate drive signal Nout[N-2] are at a high potential, the fourth node P and the third node Q are both at a high potential, the middle node W, the second node K, and the first node O / O[N] are at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a high potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0154] Stage 9 S9: Figure 4 , Fig.13 As shown, the second clock signal CK and the N-2th level positive pulse gate drive signal Nout[N-2] are at a low potential, the reset signal RST, the start control signal STV, and the first clock signal XCK are at a high potential, the intermediate node W, the first node O / O[N], the fourth node P and the third node Q are all at a high potential, the second node K is at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a high potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0155] Stage 10: Figure 4 , Fig.14As shown, the start control signal STV, the first clock signal XCK, and the N-2th level positive pulse gate drive signal Nout[N-2] are at a low potential, the reset signal RST and the second clock signal CK are at a high potential, the second node K, the middle node W, the first node O / O[N] and the third node Q are all at a high potential, the fourth node P is at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a low potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0156] Stage 11 S11: Figure 4 , Fig.15 As shown, the reset signal RST and the N-2th level positive pulse gate drive signal Nout[N-2] are at a low potential, the start control signal STV, the first clock signal XCK, and the second clock signal CK are at a high potential, the fourth node P and the third node Q are both at a high potential, the second node K, the middle node W, and the first node O / O[N] are at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a high potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0157] Stage 12 S12: Figure 4 , Fig.16 As shown, the second clock signal CK, the start control signal STV, the reset signal RST, and the N-2th level positive pulse gate drive signal Nout[N-2] are at a low potential, the first clock signal XCK is at a high potential, the fourth node P and the first node O / O[N] are both at a high potential, the third node Q, the second node K, and the middle node W are at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a high potential, and the Nth level negative pulse gate drive signal Pout[N] is at a low potential.

[0158] Stage 13 S13: Figure 4 , Fig.17 As shown, the first clock signal XCK, the start control signal STV, the reset signal RST, and the N-2th level positive pulse gate drive signal Nout[N-2] are at a low potential, the second clock signal CK is at a high potential, the second node K, the middle node W, the third node Q, and the first node O / O[N] are all at a high potential, the fourth node P is at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a low potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0159] Stage 14: Figure 4 , Fig.18As shown, the second clock signal CK, the start control signal STV, the reset signal RST, and the N-2th level positive pulse gate drive signal Nout[N-2] are at a low potential, the first clock signal XCK is at a high potential, the second node K, the middle node W, the third node Q, and the first node O / O[N] are all at a high potential, the fourth node P is at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a low potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0160] Stage 15: Figure 4 , Fig.19 As shown, the first clock signal XCK, the start control signal STV, the reset signal RST, and the N-2th level positive pulse gate drive signal Nout[N-2] are at a low potential, the second clock signal CK is at a high potential, the second node K, the middle node W, the third node Q, and the first node O / O[N] are all at a high potential, the fourth node P is at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a low potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0161] It needs to be explained that Figures 5 to 19 The “cross” in the figure indicates that the transistor covered by it is in the cut-off state, and the transistor not covered by the “cross” is in the on state. Figures 5 to 19 The dashed arrow in the figure shows the direction of current flow.

[0162] Fig. 20 The operation process of the shift register shown in one frame may include the following: Fig.21 The following stages are shown:

[0163] Stage 1 S1: Fig.21 , Fig. 22 As shown, the start control signal STV and the second clock signal CK are both at low potential, the first clock signal XCK is at high potential, the node N is at high potential, the fourth node P is at low potential, and the Nth level positive pulse gate drive signal Nout[N] is at low potential.

[0164] Stage 2 S2: Fig.21 , Fig.23 As shown, the start control signal STV and the first clock signal XCK are at a low potential, the second clock signal CK is at a high potential, the node N is at a high potential, the fourth node P is at a low potential, and the Nth level positive pulse gate drive signal Nout[N] is at a low potential.

[0165] Stage 3 S3: Fig.21 , Fig.24As shown, the second clock signal CK is at a low potential, the start control signal STV and the first clock signal XCK are at a high potential, the node N is at a high potential, the fourth node P is at a low potential, and the Nth level positive pulse gate drive signal Nout[N] is at a low potential.

[0166] Stage 4 S4: Fig.21 , Fig.25 As shown, the first clock signal XCK is at a low potential, the start control signal STV and the second clock signal CK are at a high potential, the fourth node P is at a high potential, the node N is at a low potential, and the Nth level positive pulse gate drive signal Nout[N] is at a high potential.

[0167] Stage 5 S5: Fig.21 , Fig.26 As shown, the second clock signal CK is at a low potential, the start control signal STV and the first clock signal XCK are at a high potential, the fourth node P is at a high potential, the node N is at a low potential, and the Nth level positive pulse gate drive signal Nout[N] is at a high potential.

[0168] Stage 6 S6: Fig.21 , Fig. 27 As shown, the first clock signal XCK is at a low potential, the start control signal STV and the second clock signal CK are at a high potential, the fourth node P is at a high potential, the node N is at a low potential, and the Nth level positive pulse gate drive signal Nout[N] is at a high potential.

[0169] Stage 7 S7: Fig.21 , Fig.28 As shown, the start control signal STV and the second clock signal CK are at a low potential, the first clock signal XCK is at a high potential, the fourth node P is at a high potential, the node N is at a low potential, and the Nth level positive pulse gate drive signal Nout[N] is at a high potential.

[0170] Stage 8 S8: Fig.21 , Fig.29 As shown, the start control signal STV and the first clock signal XCK are at a low potential, the second clock signal CK is at a high potential, the node N is at a high potential, the fourth node P is at a low potential, and the Nth level positive pulse gate drive signal Nout[N] switches from a high potential to a low potential.

[0171] It should be noted that Figure 22 to Figure 29 The “cross” in the figure indicates that the transistor covered by it is in the cut-off state, and the transistor not covered by the “cross” is in the on state. Figure 22 to Figure 29 The dashed arrow in the figure shows the direction of current flow.

[0172] Based on the above, Fig.30The negative pulse generation process of the Nth level negative pulse gate drive signal Pout[N] is shown. For the sake of clear description, the two pulses from right to left in the same signal are called the first pulse and the second pulse. The second node K transmits the first pulse and the second pulse in one frame. The high potential of the first part of the two pulses of the N-2th level positive pulse gate drive signal Nout[N-2] controls the second filter module 80 to filter out the latter part of the first pulse and the latter part of the second pulse output by the second node K; the high potential of the latter part of the first pulse of the reset signal RST controls the first filter module 30 to filter out the first part of the second pulse output by the second node K. At this point, the width of the second pulse of the intermediate node W has also narrowed; the second pulse output by the second node K is completely filtered out, and only the first part of the first pulse output by the second node K forms a negative pulse at the third node Q. The negative pulse of the third node Q opens the pull-up module 40, forming a negative pulse of the Nth level negative pulse gate drive signal Pout[N] with a fixed width.

[0173] See also Fig.31 , Fig.31 The second node K of the gate driving circuit shown in the figure is affected by the voltage jump of the first clock signal XCK and / or the second clock signal CK, and the potential between the second node K and the fifth node N is in a linkage relationship. Therefore, the potential of the second node K and the potential of the fifth node N will fluctuate significantly in the high and low level stages (such as Fig.31 burrs or spikes as shown).

[0174] like Fig.31 As shown, in particular, the potential of the fifth node N is significantly affected by the bootstrap coupling of the first gate drive signal in the low level stage, causing the second gate drive signal, i.e., the Nth level positive pulse gate drive signal Nout[N], to have an obvious depression phenomenon in the high level stage (such as Fig.31 This not only reduces the potential stability of the second gate driving signal, but also causes the consistency between the second gate driving signals transmitted in the display panel to decrease, thereby affecting the uniformity of the display.

[0175] Based on this, this embodiment provides a gate driving circuit, see Figure 32 to Figure 59 ,like Fig.32 , Fig.33 ,as well as Fig.50 As shown, the gate drive circuit includes multiple shift registers, and the shift registers include at least one of a stage transmission signal selection module 10, a pull-up control module 20, a first filter module 30, a second filter module 80, a first inversion module 50, a first output module 46, a second output module 70 and a voltage regulation module 71.

[0176] The stage-transmission signal selection module 10 is electrically connected between the first wiring and the first node O / O[N].

[0177] The pull-up control module 20 controls the potential of the second node K according to the potential of the first node O / O[N] and the potential of the first clock signal XCK.

[0178] The first filter module 30 is electrically connected between the second node K and the third node Q, and a control terminal of the first filter module 30 is connected to a reset signal RST.

[0179] The second filter module 80 is electrically connected between the first filter module 30 and the third node Q, and a control end of the second filter module 80 is connected to a filter control signal RST2.

[0180] The first inversion module 50 is connected between the second node K and the fourth node P.

[0181] The first output module 46 outputs a first gate driving signal according to the potential of the third node Q and the potential of the fourth node P.

[0182] The second output module 70 includes a P-channel first transistor T9 and an N-channel second transistor T10, the first electrode of the first transistor T9 is electrically connected to the first high potential line, the second electrode of the first transistor T9 is electrically connected to the first electrode of the second transistor T10 to output a second gate drive signal, the second electrode of the second transistor T10 is connected to the first low potential signal, and the second node K is electrically connected to the gate of the first transistor T9 and the gate of the second transistor T10.

[0183] One end of the voltage regulating module 71 is connected to the low voltage signal, the other end of the voltage regulating module 71 is connected to the gate of the second transistor T10, and the control end of the voltage regulating module 71 is electrically connected to the fourth node P, the output end of the second output module 70 or the first node of the next stage shift register, i.e., O[n+1].

[0184] It can be understood that the gate drive circuit provided in this embodiment can stabilize or reduce the gate potential of the second transistor T10 through a low voltage signal by the voltage regulation module 71 under the control of one of the fourth node P, the output end of the second output module 70 or the first node O[n+1] of the next-stage shift register, so that the second transistor T10 is stabilized or better in the cut-off state to reduce the leakage current, and then the potential of the second gate drive signal can be maintained at a high potential or pulse amplitude, thereby improving the potential stability of the gate drive signal.

[0185] It should be noted that the filtering control signal RST2 may be the N-2th level positive pulse gate driving signal Nout[N-2], and positive pulse gate driving signals of other levels may also be selected according to filtering needs.

[0186] It should be noted that, in one embodiment, the voltage regulating module 71 is used to stabilize or reduce the low potential of the second node K. Alternatively, in another embodiment, the voltage regulating module 71 is also used to stabilize or reduce the gate potential of the second transistor T10 during the positive pulse of the second gate driving signal.

[0187] In one embodiment, the voltage regulating module 71 includes a third transistor T15, a first electrode of the third transistor T15 is connected to a low voltage signal, a second electrode of the third transistor T15 is electrically connected to a gate of the second transistor T10, and a gate of the third transistor T15 is electrically connected to a fourth node P, an output end of the second output module 70, or a first node of a next-stage shift register, i.e., O[n+1].

[0188] It should be noted that the third transistor T15 can stabilize or reduce the gate potential of the second transistor T10 during the duration of the positive pulse of the second gate drive signal, so that the second transistor T10 is stable or better in the cut-off state to reduce leakage current, and then the potential of the second gate drive signal can be maintained at a high potential or pulse amplitude, thereby improving the potential stability of the gate drive signal.

[0189] In one embodiment, if Fig.32 As shown, the gate of the third transistor T15 is electrically connected to the fourth node P and one of the output terminals of the second output module 70, the low voltage signal is a first low potential signal, and the channel type of the third transistor T15 is the same as the channel type of the second transistor T10.

[0190] In this embodiment, the low voltage signal and the first low potential signal are both the signal NVGL.

[0191] It should be noted that, since the low voltage signal is a first low potential signal, the second transistor T10 and the third transistor T15 in this embodiment can share the same low potential line, which can save the number of wiring required for the gate drive circuit. The channel type of the third transistor T15 is the same as the channel type of the second transistor T10, and the third transistor T15 can be turned on when the second transistor T10 is in the off state to further reduce the gate potential of the second transistor T10.

[0192] In one embodiment, if Fig.33 As shown, the gate of the third transistor T15 is electrically connected to the fourth node P and one of the output terminals of the second output module 70, the channel type of the third transistor T15 is the same as the channel type of the second transistor T10, and the potential of the low voltage signal is lower than the potential of the first low potential signal.

[0193] In this embodiment, the first low potential signal is the signal NVGL, and the low voltage signal is the signal NVGL2.

[0194] It should be noted that the channel type of the third transistor T15 is the same as the channel type of the second transistor T10, and when the second transistor T10 is in the off state, the signal NVGL2 can be transmitted to the gate of the second transistor T10 through the third transistor T15, which can further reduce the gate potential of the second transistor T10 compared to the signal NVGL, thereby reducing the leakage current of the second transistor T10. In this way, the stability of the low potential of the second node K and the low potential of the middle node W can be improved.

[0195] In one embodiment, the difference between the potential of the signal NVGL and the potential of the signal NVGL2 is greater than or equal to 2V.

[0196] It should be noted that this embodiment can not only reduce the leakage current of the second transistor T10, but also adjust the threshold voltage of the second transistor T10 to shift toward the positive direction, thereby increasing the range of the threshold voltage of the second transistor T10.

[0197] In one embodiment, if Fig.35 As shown, the first inversion module 50 includes a P-channel fourth transistor T3 and an N-channel fifth transistor T1, the first electrode of the fourth transistor T3 is electrically connected to the second high potential line, the second electrode of the fourth transistor T3 is electrically connected to the fourth node P, and the gate of the fourth transistor T3 is electrically connected to the second node K; the first electrode of the fifth transistor T1 is electrically connected to the fourth node P, the second electrode of the fifth transistor T1 is connected to the second low potential signal, and the gate of the fifth transistor T1 is electrically connected to the second node K; wherein the potential of the second low potential signal is lower than the potential of the low voltage signal.

[0198] In this embodiment, the second low potential signal is the signal PVGL, and the low voltage signal is the signal NVGL.

[0199] It should be noted that, when the fifth transistor T1 is turned on, the gate-source voltage difference of the third transistor T15 can be made less than zero, which can effectively ensure the stability of the third transistor T15 under the dual 85.

[0200] In one embodiment, the second transistor T10 is a dual-gate transistor, and the first gate of the second transistor T10 is electrically connected to the second node K and the second gate of the second transistor T10; the third transistor T15 is a dual-gate transistor, and the first gate of the third transistor T15 is electrically connected to the fourth node P and the second gate of the third transistor T15.

[0201] It should be noted that the second transistor T10 and the third transistor T15 are double-gate transistors, which can not only reduce the drift of the threshold voltage but also improve the control accuracy.

[0202] In one embodiment, if Fig.50 As shown, the gate of the third transistor T15 is electrically connected to the first node O[n+1] of the next stage shift register, the low voltage signal is a first low potential signal, and the channel type of the third transistor T15 is different from the channel type of the second transistor T10; the shift register also includes a sixth transistor T14, the first electrode of the sixth transistor T14 is electrically connected to the second node K, the second electrode of the sixth transistor T14 is electrically connected to the gate of the first transistor T9, the gate of the sixth transistor is connected to the first clock signal XCK, and the channel type of the sixth transistor is the same as the channel type of the first transistor T9.

[0203] In this embodiment, the low voltage signal and the first low potential signal are both the signal VGL.

[0204] It should be noted that the first node of the next-stage shift register, namely O[n+1], is used as the signal source of the gate of the third transistor T15, the potential of O[n+1] is inverse to the potential of the fourth node P, and the waveform of O[n+1] is substantially the same as the waveform of the fifth node N. Therefore, by controlling the P-channel third transistor T15 using O[n+1], the potential of the fifth node N can be continuously and sufficiently pulled down, so that the voltage of the fifth node N reaches the target potential of VGL-Vth. In addition, the leakage current of the second transistor T10 can also be reduced, and the stability of the high potential provided by the second output module 70 can be improved.

[0205] Wherein, VGL is the potential of the low potential signal, and Vth is the threshold voltage of the second transistor T10.

[0206] Fig.32 , Fig.33 ,as well as Fig.50 The other structural parts, working principles, etc. of the gate driving circuit shown can also refer to the description of the aforementioned gate driving circuit.

[0207] Fig.34 for Fig.32 , Fig.33 The timing diagram of the gate drive circuit shown.

[0208] Fig.32 , Fig.33 The operation process of the shift register shown in one frame may include the following: Fig.34 The following stages are shown:

[0209] Stage 1 S1: Fig.34 , Fig.35As shown, the start control signal STV, the reset signal RST, the second clock signal CK, and the N-2th level positive pulse gate drive signal Nout[N-2] are all at a low potential, the first clock signal XCK is at a high potential, the first node O / O[N], the second node K, the middle node W and the third node Q are all at a high potential, the fourth node P is at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a low potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0210] Stage 2 S2: Fig.34 , Fig.36 As shown, the start control signal STV, the reset signal RST, the first clock signal XCK, and the N-2th level positive pulse gate drive signal Nout[N-2] are all at a low potential, the second clock signal CK is at a high potential, the first node O / O[N], the second node K, the middle node W and the third node Q are all at a high potential, the fourth node P is at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a low potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0211] Stage 3 S3: Fig.34 , Fig.37 As shown, the start control signal STV, the second clock signal CK, and the N-2th level positive pulse gate drive signal Nout[N-2] are all at a low potential, the reset signal RST and the first clock signal XCK are at a high potential, the first node O / O[N], the second node K, the middle node W and the third node Q are all at a high potential, the fourth node P is at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a low potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0212] Stage 4 S4: Fig.34 , Fig.38 As shown, the start control signal STV, the first clock signal XCK, and the N-2th level positive pulse gate drive signal Nout[N-2] are all at a low potential, the reset signal RST and the second clock signal CK are at a high potential, the first node O / O[N], the second node K, the middle node W and the third node Q are all at a high potential, the fourth node P is at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a low potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0213] Stage 5 S5: Fig.34 , Fig.39As shown, the second clock signal CK is at a low potential, the start control signal STV, the reset signal RST, the first clock signal XCK, and the N-2th level positive pulse gate drive signal Nout[N-2] are at a high potential, the second node K, the middle node W and the third node Q are all at a high potential, the first node O / O[N] and the fourth node P are at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a low potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0214] Stage 6 S6: Fig.34 , Fig.40 As shown, the first clock signal XCK is at a low potential, the start control signal STV, the reset signal RST, the second clock signal CK, and the N-2th level positive pulse gate drive signal Nout[N-2] are at a high potential, the middle node W, the fourth node P and the third node Q are all at a high potential, the second node K and the first node O / O[N] are at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a high potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0215] Stage 7 S7: Fig.34 , Fig.41 As shown, the reset signal RST and the second clock signal CK are at a low potential, the start control signal STV, the first clock signal XCK, and the N-2th level positive pulse gate drive signal Nout[N-2] are at a high potential, the fourth node P and the third node Q are both at a high potential, the middle node W, the second node K, and the first node O / O[N] are at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a high potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0216] Stage 8 S8: Fig.34 , Fig.42 As shown, the reset signal RST and the first clock signal XCK are at a low potential, the start control signal STV, the second clock signal CK, and the N-2th level positive pulse gate drive signal Nout[N-2] are at a high potential, the fourth node P and the third node Q are both at a high potential, the middle node W, the second node K, and the first node O / O[N] are at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a high potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0217] Stage 9 S9: Fig.34 , Fig.43As shown, the second clock signal CK and the N-2th level positive pulse gate drive signal Nout[N-2] are at a low potential, the reset signal RST, the start control signal STV, and the first clock signal XCK are at a high potential, the intermediate node W, the first node O / O[N], the fourth node P and the third node Q are all at a high potential, the second node K is at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a high potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0218] Stage 10: Fig.34 , Fig.44 As shown, the start control signal STV, the first clock signal XCK, and the N-2th level positive pulse gate drive signal Nout[N-2] are at a low potential, the reset signal RST and the second clock signal CK are at a high potential, the second node K, the middle node W, the first node O / O[N] and the third node Q are all at a high potential, the fourth node P is at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a low potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0219] Stage 11 S11: Fig.34 , Fig.45 As shown, the reset signal RST and the N-2th level positive pulse gate drive signal Nout[N-2] are at a low potential, the start control signal STV, the first clock signal XCK, and the second clock signal CK are at a high potential, the fourth node P and the third node Q are both at a high potential, the second node K, the middle node W, and the first node O / O[N] are at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a high potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0220] Stage 12 S12: Fig.34 , Fig.46 As shown, the second clock signal CK, the start control signal STV, the reset signal RST, and the N-2th level positive pulse gate drive signal Nout[N-2] are at a low potential, the first clock signal XCK is at a high potential, the fourth node P and the first node O / O[N] are both at a high potential, the third node Q, the second node K, and the middle node W are at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a high potential, and the Nth level negative pulse gate drive signal Pout[N] is at a low potential.

[0221] Stage 13 S13: Fig.34 , Fig.47As shown, the first clock signal XCK, the start control signal STV, the reset signal RST, and the N-2th level positive pulse gate drive signal Nout[N-2] are at a low potential, the second clock signal CK is at a high potential, the second node K, the middle node W, the third node Q, and the first node O / O[N] are all at a high potential, the fourth node P is at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a low potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0222] Stage 14: Fig.34 , Fig.48 As shown, the second clock signal CK, the start control signal STV, the reset signal RST, and the N-2th level positive pulse gate drive signal Nout[N-2] are at a low potential, the first clock signal XCK is at a high potential, the second node K, the middle node W, the third node Q, and the first node O / O[N] are all at a high potential, the fourth node P is at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a low potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0223] Stage 15: Fig.34 , Fig.49 As shown, the first clock signal XCK, the start control signal STV, the reset signal RST, and the N-2th level positive pulse gate drive signal Nout[N-2] are at a low potential, the second clock signal CK is at a high potential, the second node K, the middle node W, the third node Q, and the first node O / O[N] are all at a high potential, the fourth node P is at a low potential, the Nth level positive pulse gate drive signal Nout[N] is at a low potential, and the Nth level negative pulse gate drive signal Pout[N] is at a high potential.

[0224] It should be noted that Figures 35 to 49 The “cross” in the figure indicates that the transistor covered by it is in the cut-off state, and the transistor not covered by the “cross” is in the on state. Figures 35 to 49 The dashed arrow in the figure shows the direction of current flow.

[0225] Among them, in one frame, the gate drive circuit includes a stage S100 and a stage S200, and the above-mentioned first stage S1 to the fifteenth stage S15 belong to the stage S100, in which the pulses of each first gate drive signal and each second gate drive signal will be output; and in the stage S200, the pulses of each first gate drive signal and each second gate drive signal are not needed. Therefore, keeping at least one of the first clock signal XCK and the second clock signal CK at a low potential can reduce the potential flip frequency of at least one of the first clock signal XCK and the second clock signal CK, thereby reducing power consumption.

[0226] Fig.50 The operation process of the shift register shown in one frame may include the following: Fig.51 The following stages are shown:

[0227] Stage 1 S1: Fig.51 , Fig.52 As shown, the start control signal STV and the second clock signal CK are both at low potential, the first clock signal XCK is at high potential, the node N is at high potential, the fourth node P is at low potential, and the Nth level positive pulse gate drive signal Nout[N] is at low potential.

[0228] Stage 2 S2: Fig.51 , Fig.53 As shown, the start control signal STV and the first clock signal XCK are at a low potential, the second clock signal CK is at a high potential, the node N is at a high potential, the fourth node P is at a low potential, and the Nth level positive pulse gate drive signal Nout[N] is at a low potential.

[0229] Stage 3 S3: Fig.51 , Fig.54 As shown, the second clock signal CK is at a low potential, the start control signal STV and the first clock signal XCK are at a high potential, the node N is at a high potential, the fourth node P is at a low potential, and the Nth level positive pulse gate drive signal Nout[N] is at a low potential.

[0230] Stage 4 S4: Fig.51 , Fig.55 As shown, the first clock signal XCK is at a low potential, the start control signal STV and the second clock signal CK are at a high potential, the fourth node P is at a high potential, the node N is at a low potential, and the Nth level positive pulse gate drive signal Nout[N] is at a high potential.

[0231] Stage 5 S5: Fig.51 , Fig.56As shown, the second clock signal CK is at a low potential, the start control signal STV and the first clock signal XCK are at a high potential, the fourth node P is at a high potential, the node N is at a low potential, and the Nth level positive pulse gate drive signal Nout[N] is at a high potential.

[0232] Stage 6 S6: Fig.51 , Fig.57 As shown, the first clock signal XCK is at a low potential, the start control signal STV and the second clock signal CK are at a high potential, the fourth node P is at a high potential, the node N is at a low potential, and the Nth level positive pulse gate drive signal Nout[N] is at a high potential.

[0233] Stage 7 S7: Fig.51 , Fig.58 As shown, the start control signal STV and the second clock signal CK are at a low potential, the first clock signal XCK is at a high potential, the fourth node P is at a high potential, the node N is at a low potential, and the Nth level positive pulse gate drive signal Nout[N] is at a high potential.

[0234] Stage 8 S8: Fig.51 , Fig.59 As shown, the start control signal STV and the first clock signal XCK are at a low potential, the second clock signal CK is at a high potential, the node N is at a high potential, the fourth node P is at a low potential, and the Nth level positive pulse gate drive signal Nout[N] switches from a high potential to a low potential.

[0235] It needs to be explained that Figure 52 to Figure 9 The “cross” in the figure indicates that the transistor covered by it is in the cut-off state, and the transistor not covered by the “cross” is in the on state. Figure 52 to Figure 9 The dashed arrow in the figure shows the direction of current flow.

[0236] Fig.60 for Figure 3 , Fig. 20 , Fig.32 , Fig.33 or Fig.50 The schematic diagram of the structure of cascading different shift registers in the gate driving circuit shown in the figure, wherein the first-stage shift register, the second-stage shift register, the third-stage shift register, the Nth-stage shift register, and the N+1th-stage shift register are arranged in sequence from top to bottom. Each shift register works according to the first clock signal XCK and the second clock signal CK respectively.

[0237] Among them, the control end of the first filter module 30 and the control end of the second filter module 80 in the first-stage shift register are both connected to the low potential signal VGL, and the input end (IN) of the first-stage shift register connected to the start control line is connected to the start control signal STV. The first-stage shift register outputs the corresponding first-stage negative pulse gate drive signal Pout[1] and first-stage positive pulse gate drive signal Nout[1]. The first-stage negative pulse gate drive signal Pout[1] and the first-stage positive pulse gate drive signal Nout[1] are used to drive dummy pixels (Dummy) or are suspended.

[0238] The control end of the first filter module 30 and the control end of the second filter module 80 in the second-stage shift register are both connected to the low potential signal VGL, and the start control line connected to the second-stage shift register is connected to the cascade signal, i.e., the first-stage positive pulse gate drive signal Nout[1]. The second-stage shift register outputs the corresponding second-stage negative pulse gate drive signal Pout[2] and second-stage positive pulse gate drive signal Nout[2]. The second-stage negative pulse gate drive signal Pout[2] and second-stage positive pulse gate drive signal Nout[2] are used to drive dummy pixels (Dummy) or are left hanging.

[0239] The control end of the first filter module 30 and the control end of the second filter module 80 in the third-stage shift register are both connected to the low potential signal VGL, and the start control line connected to the third-stage shift register is connected to the cascade signal, i.e., the second-stage positive pulse gate drive signal Nout[2]. The third-stage shift register outputs the corresponding third-stage negative pulse gate drive signal Pout[3] and third-stage positive pulse gate drive signal Nout[3]. The third-stage negative pulse gate drive signal Pout[3] and the third-stage positive pulse gate drive signal Nout[3] are used to drive dummy pixels (Dummy) or are left floating.

[0240] The same logic can be applied to other control terminals, until the control terminals of the first filter module 30 and the second filter module 80 in the Nth stage shift register are connected to the NXth stage positive pulse gate drive signal Nout[NX] and the N-2th stage positive pulse gate drive signal Nout[N-2] respectively, and the starting control line connected to the Nth stage shift register is connected to the cascade signal, i.e., the N-1th stage positive pulse gate drive signal Nout[N-1]. The Nth stage shift register outputs the corresponding Nth stage negative pulse gate drive signal Pout[N] and the Nth stage positive pulse gate drive signal Nout[N]. The Nth stage negative pulse gate drive signal Pout[N] and the Nth stage positive pulse gate drive signal Nout[N] are used to drive the first row of pixel circuits (Pixel).

[0241] The control end of the first filter module 30 and the control end of the second filter module 80 in the N+1-th shift register are respectively connected to the N-X+1-th positive pulse gate drive signal Nout[N-X+1] and the N-1-th positive pulse gate drive signal Nout[N-1], and the starting control line connected to the N+1-th shift register is connected to the cascade signal, that is, the N-th positive pulse gate drive signal Nout[N]. The N+1-th shift register outputs the corresponding N+1-th negative pulse gate drive signal Pout[N+1] and the N+1-th positive pulse gate drive signal Nout[N+1]. The N+1-th negative pulse gate drive signal Pout[N+1] and the N+1-th positive pulse gate drive signal Nout[N+1] are used to drive the second row of pixel circuits (Pixel).

[0242] The same can be said for other subsequent shift registers. It should be noted that, since the output ends of some shift registers are connected to virtual pixels or are suspended, the output ends of the Nth-stage shift register are not connected to the Nth-row pixel circuit, but the number of rows of connected pixel circuits needs to be determined according to the number of shift registers connected to virtual pixels or suspended. For example, if the 1st to 3rd-stage shift registers are connected to virtual pixels, then the output ends of the Nth-stage shift register are connected to the N-3rd-row pixel circuit.

[0243] The same can be applied to other subsequent shift registers.

[0244] Fig.61 The display panel shown includes pixel circuits (Pixel) distributed in an array in the display area, Fig.32 The display panel shown includes pixel circuits (Pixel) distributed in an array in the display area, a first gate driving circuit 151 providing a light-emitting control signal EM, a fourth gate driving circuit 154 providing a gate driving signal Pscan2, a second gate driving circuit 152 providing an N-th level negative pulse gate driving signal Pout[N] and a gate driving signal Nscan, and a third gate driving circuit 153 providing an N-th level negative pulse gate driving signal Pout[N] and a gate driving signal Nscan.

[0245] The first gate driving circuit 151 may be located on the left side of the display area. The output end of each shift register in the first gate driving circuit 151 provides a light emitting control signal EM to two adjacent rows of pixel circuits through a corresponding light emitting control line, which is a unilateral drive.

[0246] The fourth gate driving circuit 154 may be located on the right side of the display area. The output end of each shift register in the fourth gate driving circuit 154 provides a gate driving signal Pscan2 to a row of pixel circuits through a corresponding gate driving line, which belongs to unilateral driving.

[0247] The second gate driving circuit 152 is located between the first gate driving circuit 151 and the display area. The third gate driving circuit 153 is located between the fourth gate driving circuit 154 and the display area. A scanning line for transmitting the Nth level negative pulse gate driving signal Pout[N] is electrically connected to the output end of a shift register in the second gate driving circuit 152, the output end of a shift register in the third gate driving circuit 153, and a row of pixel circuits, and a gate driving line for transmitting the gate driving signal Nscan is electrically connected to the output end of a shift register in the second gate driving circuit 152, the output end of a shift register in the third gate driving circuit 153, and a row of pixel circuits, which belongs to bilateral driving.

[0248] The second gate drive circuit 152 and the third gate drive circuit 153 can both adopt Figure 3 , Fig. 20 The gate driving circuit shown in the figure. The gate driving signal Nscan may include the Nth level positive pulse gate driving signal Nout[N] and the N-3th level positive pulse gate driving signal Nout[N-3].

[0249] because Figure 1 The gate of the first initialization transistor T4P in the pixel circuit shown in the figure has a necessary reason to be connected to the N-1th level positive pulse gate drive signal Nout[N-1], Fig.33 After the gate of the write transistor T2P in the pixel circuit shown is connected to the Nth level negative pulse gate drive signal Pout[N] and the gate of the compensation transistor T3P is connected to the Nth level positive pulse gate drive signal Nout[N], not only can the gate of the third initialization transistor T8P continue to use the existing gate drive signal Pscan2 (no need to improve the fourth gate drive circuit 154), but the gate of the first initialization transistor T4P can also be replaced with the N-3th level positive pulse gate drive signal Nout[N-3].

[0250] After that, Fig.62 The pixel circuit shown can work not only in one frame Fig.63 In addition to the existing stage P12, an additional stage P11 can be added. In this stage P11, the three-terminal (Q, A, B) potential of the driving transistor T1P can be reset by synchronously turning on the first initialization transistor T4P and the compensation transistor T3P to reduce the drift of the threshold voltage of the driving transistor T1P, thereby improving the flicker under different refresh frequencies.

[0251] In one of the embodiments, the present embodiment provides a display panel, which includes the gate driving circuit and the pixel circuit in at least one of the above embodiments.

[0252] It can be understood that since the display panel provided in this embodiment includes the gate driving circuit of at least one of the above-mentioned embodiments, the voltage regulating module 71 can also stabilize or reduce the gate potential of the second transistor T10 through a low voltage signal under the control of one of the fourth node P, the output end of the second output module 70 or the first node O[n+1] of the next-stage shift register, so that the second transistor T10 is stabilized or better in the cut-off state to reduce the leakage current, and the potential of the second gate driving signal can be maintained at a high potential or pulse amplitude, thereby improving the potential stability of the gate driving signal.

[0253] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0254] The gate drive circuit and display panel provided in the embodiments of the present application are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A gate drive circuit, characterized in that: The gate driving circuit includes a plurality of shift registers, and the shift registers include: a level transmission signal selection module, the level transmission signal selection module being electrically connected between the first wiring and the first node; A pull-up control module, wherein the pull-up control module controls the potential of the second node according to the potential of the first node and the potential of the first clock signal; A first filtering module, wherein the first filtering module is electrically connected between the second node and the third node, and a control terminal of the first filtering module is connected to a reset signal; A second filtering module, the second filtering module is electrically connected between the first filtering module and the third node, and a control end of the second filtering module is connected to a filtering control signal; A first inverting module, wherein the first inverting module is connected between the second node and a fourth node; a first output module, wherein the first output module outputs a first gate driving signal according to the potential of the third node and the potential of the fourth node; a second output module, the second output module comprising a first P-channel transistor and a second N-channel transistor, a first electrode of the first transistor being electrically connected to a first high potential line, a second electrode of the first transistor being electrically connected to a first electrode of the second transistor to output a second gate drive signal, a second electrode of the second transistor being connected to a first low potential signal, and the second node being electrically connected to a gate of the first transistor and a gate of the second transistor; and A voltage regulating module, one end of which is connected to a low voltage signal, the other end of which is connected to the gate of the second transistor, and the control end of which is electrically connected to the fourth node, the output end of the second output module, or the first node of the next-stage shift register.

2. The gate driving circuit according to claim 1, characterized in that: The voltage regulating module includes a third transistor, a first electrode of the third transistor is connected to the low voltage signal, a second electrode of the third transistor is electrically connected to the gate of the second transistor, and the gate of the third transistor is electrically connected to the fourth node, the output end of the second output module or one of the first nodes of the next-stage shift register.

3. The gate driving circuit according to claim 2, characterized in that: The gate of the third transistor is electrically connected to the fourth node and one of the output terminals of the second output module, the low voltage signal is the first low potential signal, and the channel type of the third transistor is the same as the channel type of the second transistor.

4. The gate driving circuit according to claim 2, characterized in that: The gate of the third transistor is electrically connected to the fourth node and one of the output terminals of the second output module, the channel type of the third transistor is the same as the channel type of the second transistor, and the potential of the low voltage signal is lower than the potential of the first low potential signal.

5. The gate driving circuit according to claim 4, characterized in that: A difference between a potential of the first low potential signal and a potential of the low voltage signal is greater than or equal to 2V.

6. The gate driving circuit according to claim 4, characterized in that: The first inversion module comprises: a fourth P-channel transistor, wherein a first electrode of the fourth transistor is electrically connected to the second high potential line, a second electrode of the fourth transistor is electrically connected to the fourth node, and a gate of the fourth transistor is electrically connected to the second node; an N-channel fifth transistor, wherein a first electrode of the fifth transistor is electrically connected to the fourth node, a second electrode of the fifth transistor is connected to a second low potential signal, and a gate of the fifth transistor is electrically connected to the second node; The potential of the second low potential signal is lower than the potential of the low voltage signal.

7. The gate drive circuit according to any one of claims 1 to 6, characterized in that: The second transistor is a dual-gate transistor, and a first gate of the second transistor is electrically connected to the second node and a second gate of the second transistor; The third transistor is a double-gate transistor, and a first gate of the third transistor is electrically connected to the fourth node and a second gate of the third transistor.

8. The gate driving circuit according to claim 2, characterized in that: The gate of the third transistor is electrically connected to the first node of the next-stage shift register, the low voltage signal is the first low potential signal, and the channel type of the third transistor is different from the channel type of the second transistor; The shift register also includes a sixth transistor, a first electrode of the sixth transistor is electrically connected to the second node, a second electrode of the sixth transistor is electrically connected to the gate of the first transistor, the gate of the sixth transistor is connected to the first clock signal, and a channel type of the sixth transistor is the same as that of the first transistor.

9. The gate driving circuit according to claim 8, characterized in that: The voltage regulating module is used to stabilize or reduce the low potential of the second node.

10. The gate driving circuit according to claim 9, characterized in that: The voltage regulating module is further used for stabilizing or reducing the gate potential of the second transistor during the duration of the positive pulse of the second gate driving signal.

11. The gate driving circuit according to claim 1, characterized in that: In one frame, when the gate driving circuit completes outputting each pulse of the first gate driving signal and each pulse of the second gate driving signal, the first clock signal is maintained at a low potential.

12. The gate driving circuit according to claim 11, characterized in that: The first output module outputs the connected second clock signal as the first gate drive signal according to the potential of the third node; when the pulse output of each of the first gate drive signal and each of the second gate drive signal of the gate drive circuit is completed, the second clock signal is maintained at a low potential.

13. A display panel, characterized in that: The display panel comprises: a pixel circuit including a write transistor for controlling input of a data signal and a compensation transistor for controlling input of the data signal to a gate of a drive transistor; and According to the gate drive circuit as described in any one of claims 1 to 12, the output end of the first output module is electrically connected to the gate of the write transistor, and the output end of the second output module is electrically connected to the gate of the compensation transistor.

Images