Full-swing input type sensitive amplifier, module and chip

Abstract

The invention belongs to the field of integrated circuits, and particularly relates to a full-swing input type sensitive amplifier, a module and a chip. The full-swing input type sensitive amplifier comprises an output circuit, a pre-charging circuit, a self-adaptive gating circuit and an offset suppression circuit. The output circuit adopts an inverted cross-coupled latch circuit, and latch nodes Q and QB serve as output nodes of quantization results; a pre-charge routing enable signal SAEN controls start and is used to pull up the output node to equipotential before comparison. The self-adaptive gating circuit provides two discharge paths which are respectively regulated and controlled by an NMOS tube and a PMOS tube for each output node, and the corresponding discharge paths are adaptively gated according to input signals with different swing amplitudes, so that the comparison of the two full-swing input signals is realized. And the offset suppression circuit is used for balancing the potential at the corresponding position in the discharge path in the reset stage. According to the invention, the problems of limited comparison range and overhigh offset voltage of a latch type sensitive amplifier are solved.

Description

Technical Field

[0001] The invention belongs to the field of integrated circuits, and in particular relates to a full-swing input type sensitive amplifier, a module and a chip. Background Art

[0002] With the popularity of wearable devices and the continuous reduction of key dimensions of CMOS process, the integration of chips is constantly improving, and the demand for large-capacity and high-density memory chips is increasing. However, large-capacity and high-density memory arrays will mount more memory cells on a bit line, which makes the bit line capacitance increase continuously and greatly increases the delay of full swing discharge of the bit line and its dynamic power consumption.

[0003] In order to avoid the problem of excessive delay in reading stored information due to slow discharge of the bit line, a sense amplifier is usually used in static random access memory (SRAM) to sense the voltage difference between the two ends of the bit line and quickly amplify and read the stored data. At the same time, the design of read-write separation and independent read bit line is becoming more and more common because it can avoid the data flip risk caused by the half-select problem in the storage array. Therefore, the sense amplifier that can identify the change of the single-ended read bit line voltage information is becoming more and more popular.

[0004] At present, latch-type sensitive amplifiers are widely used in SRAM circuits due to their simple structure and the ability to quickly amplify the bit line voltage difference information through internal cross-coupled positive feedback. The latch-type sensitive amplifier consists of two pairs of cross-coupled inverters to form the core structure of data amplification: a pair of voltage-controlled transmission tubes are used to control the input of the bit line information, and an NMOS transistor is used as the enable control terminal and power supply current source of the circuit. However, due to the threshold voltage problem of the input tube, the working range of the traditional latch-type sensitive amplifier can only perform sensitive amplification function at medium and high voltages. If the input is all low voltage, sensitive amplification cannot be performed. At the same time, since the latch-type sensitive amplifier has a differential structure inside, it will introduce an offset voltage - that is, when the bit line voltage difference signal is less than a certain voltage, the latch-type sensitive amplifier will not be able to identify or identify errors. Summary of the invention

[0005] In order to overcome the problems of limited comparison range and insufficient stability caused by offset voltage of latch-type sense amplifiers, the present invention provides a full-swing input sense amplifier, module and chip.

[0006] The technical solution provided by the present invention is:

[0007] A full swing input type sensitive amplifier includes an output circuit and a precharge circuit. The output circuit uses a latch circuit composed of two PMOS tubes and two NMOS tubes inversely coupled; the latch nodes Q and QB of the latch circuit are used as output nodes of the quantization result. The precharge routing enable signal SAEN controls the start-up and is used to pull the output nodes Q and QB to the same potential before comparison.

[0008] The full-swing input type sense amplifier also includes an adaptive gating circuit; the adaptive gating circuit provides two discharge paths for the output nodes Q and QB respectively, and responds to input signals V with different swings. IN and V IP The corresponding discharge path is adaptively selected, thereby realizing the comparison of two full-swing input signals. Among them, the adaptive selection circuit is composed of 4 PMOS tubes P5~P8 and 7 NMOS tubes N3~N9, and the circuit connection relationship is as follows:

[0009] The sources of P5 and P6 are connected to the power supply VDD; the drain of P5 is connected to the source of P7, and the drain of P6 is connected to the source of P8; the drains of N8 and P7 are connected to the gate of N3; the drains of N9 and P8 are connected to the gate of N6; the drains of N3 and N4 are connected to the source of one of the NMOS tubes in the output circuit; the drains of N5 and N6 are connected to the source of another NMOS tube in the output circuit; the sources of N3 to N6 are connected to the drain of N7, and the sources of N7, N8 and N9 are connected to VSS; the gate of N7 is connected to the enable signal SAEN; the gates of N8, N9, P5 and P6 are connected to the inverted enable signal NSAEN; the gates of P7 and N5 are connected to the input signal V IP ; The gate of P8 and N4 is connected to the input signal V IN .

[0010] In the sensitive amplifier of the present invention, the output circuit is composed of two PMOS tubes P2 and P3 and two NMOS tubes N1 and N2. The circuit connection relationship is: the source of P2 and P3 is connected to the power supply VDD; the drain of P2 and N1 is connected to the gate of P3 and N2 and serves as one of the latch nodes Q; the drain of P3 and N2 is connected to the gate of P2 and N1 and serves as another latch node QB.

[0011] As a further improvement of the present invention, the pre-charging circuit is composed of two PMOS tubes P1 and P4. The sources of P1 and P4 are connected to the power supply VDD; the drains of P1 and P4 are connected to the latch nodes Q and QB respectively; and the gates of P1 and P4 are connected to the enable signal SAEN.

[0012] As a further improvement of the present invention, the full-swing input type sensitive amplifier also includes an offset suppression circuit for reducing the offset voltage occurring during the circuit quantization process. The offset suppression circuit includes a PMOS tube P9; P9 is connected between the sources of N1 and N2; and the gate of P9 is connected to the enable signal SAEN.

[0013] As a further improvement of the present invention, the offset suppression circuit further includes a buffer Buffer1 connected between the output node Q and the external circuit, and a buffer Buffer2 connected between the output node QB and the external circuit.

[0014] When the full-swing input type sensitive amplifier provided by the present invention is used to read data from an SRAM circuit or to quantize the result of a logic operation on a CIM circuit based on an SRAM, the input signal V IN and V IP The ports are respectively connected to the bit lines on both sides of each SRAM unit or CIM unit.

[0015] As a further improvement of the present invention, the operation logic of the full-swing input type sense amplifier is as follows:

[0016] (1) When the enable signal SAEN is at a high level and the inverting enable signal NSAEN is at a low level, the full-swing input type sense amplifier is in the working mode and is used to detect the input signal V IN and V IP Compare the size relationship.

[0017] (2) When the enable signal SAEN is at a low level and the inverted enable signal NSAEN is at a high level, the full-swing input type sense amplifier is in a reset mode, which is used to pull the two output nodes to the same potential and wait for the next comparison.

[0018] As a further improvement of the present invention, the input signal V supported by the full-swing input type sense amplifier is IN and V IP The swing range is divided into high amplitude region, medium amplitude region and low amplitude region. When the two input signals are in the high amplitude region, N4 and N5 are turned on to form a discharge path; when the two input signals are in the low amplitude region, N3 and N6 are turned on to form a discharge path; when the two input signals are in the medium amplitude region, N3, N4, N5 and N6 are all turned on to form a discharge path.

[0019] During each comparison, the discharge rate of each discharge path formed depends on the input signal V connected to each gate terminal. IN and V IP size.

[0020] The present invention also includes a comparison module, which is packaged by the full-swing input type sensitive amplifier as mentioned above; the comparator module includes a power port VDD, a ground terminal VSS, an enable terminal SAEN, an inverting enable terminal NSAEN, two input terminals VIN and VIP, and two output terminals DOUT and DOUT_BAR.

[0021] The input terminals VIN and VIP are respectively used to input two input signals to be compared; the output terminals DOUT and DOUT_BAR are respectively used to output the comparison result and its inverted value.

[0022] The present invention also includes a chip, which includes an SRAM array or a CIM array based on SRAM. In the SRAM array or CIM array, a comparator module as described above is connected to the bit lines on both sides of each column of circuit units. The comparator module is used to read the data stored in the circuit unit of the SRAM array or quantify the result of the logic operation in the circuit unit of the CIM array.

[0023] The technical solution provided by the present invention has the following beneficial effects:

[0024] The present invention improves the input circuit of the existing voltage-controlled current-type sense amplifier and designs a new adaptive gating circuit. The adaptive gating circuit designs two discharge paths for each output node of the sense amplifier, one controlled by an NMOS tube and the other controlled by a PMOS tube, and provides different path selections for input signals in different swing ranges. The advantage of the PMOS tube being able to be precisely regulated under low voltage input conditions is then utilized to overcome the problem that the existing sense amplifier cannot be compared under low amplitude input signal conditions, so that the sense amplifier supports "full swing" input.

[0025] The present invention also designs an offset suppression circuit to solve the problem of mismatch in the discharge path state of the sensitive amplifier under different operating states. The offset suppression circuit can share charges between corresponding nodes according to the enable signal in different modes, thereby reducing the offset voltage. In addition, the present invention also uses two buffers to isolate the output node from the outside, further reducing the offset voltage of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 This is the circuit diagram of a traditional voltage-controlled current-type sense amplifier.

[0027] Figure 2 4 is a circuit diagram of a full-swing input type sense amplifier provided in Example 1 of the present invention.

[0028] Figure 3 This is a circuit state diagram of the full-swing input type sense amplifier provided in Example 1 of the present invention in the working mode.

[0029] Figure 4 This is a circuit state diagram of the full-swing input type sense amplifier provided in Example 1 of the present invention in reset mode.

[0030] Figure 5 This is a circuit diagram of a full-swing input type sense amplifier with offset voltage suppression performance provided in Example 1 of the present invention.

[0031] Figure 6 This is a signal flow chart of the operation process of the comparison module in Example 2 of the present invention.

[0032] Figure 7 The figure is a comparison chart of the differential amplification performance of the traditional scheme and the scheme of the present invention under input voltages of different amplitudes in the test experiment.

[0033] Figure 8 It is a comparison diagram of the offset voltages of the traditional solution and the solution of the present invention at different process angles in the test experiment. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0035] Example 1

[0036] The circuit design of the classic sense amplifier (SA) used in the traditional SRAM circuit is as follows Figure 1 As shown, it includes an input circuit, an output circuit and a pre-charging circuit. Among them, the output circuit is composed of 2 PMOS tubes and 2 NMOS tubes, and the four MOS tubes are inversely cross-coupled to form a latch circuit; the latch nodes Q and QB of the latch circuit serve as the output nodes of the quantization result. The pre-charging circuit includes two PMOS tubes P1 and P4 respectively connected between the power supply VDD and the output nodes Q and QB. P1 and P4 are started by the enable signal SAEN and are used to pull the output nodes Q and QB to the same potential before comparison. The input circuit includes 3 NMOS tubes N3~N5; among them, N3 and N4 are respectively connected between the source and the low end of the two NMOS of the latch circuit, and use the input signal V IP and V IN As their respective gate control signals, N3 and N4 are grounded through N5, and the gate of N5 is connected to the enable signal SAEN to control the working mode of the circuit.

[0037] exist Figure 1In the classic circuit design, when SAEN is high, the circuit is in reset mode. At this time, the output nodes Q and QB are pulled high by P1 and P4 respectively. When SAEN is low, the circuit starts to work. At this time, the input signal V IP and V IN They are used to control the on and off of N3 and N4 respectively. When one of them is at a high level and the other is at a low level, the NMOS tube on the low level side will be turned on, thereby pulling the output node on the corresponding side down to a low level. On the other side, since the corresponding NMOS is turned off, a discharge path cannot be formed, so that the output node on the corresponding side remains at a high level. Finally, V is output through the output node. IP and V IN The size relationship between them.

[0038] However, in this circuit, the formation of the discharge path is controlled by only two NMOS tubes N3 and N4. Since the NMOS tube is in the cut-off state at low voltage, when the two input signals V IP and V IN When both are lower than the threshold voltage Vth of the NMOS tube, no matter how much the voltage difference of the input signals on both sides is, the NMOS tube on the corresponding side will not be turned on. This causes the discharge paths to the ground of the two output nodes to be always turned off, and the coupled latch structure cannot be formed in the output circuit. That is: Figure 1 The sensitive amplifier cannot compare the input signal in the low amplitude region.

[0039] In order to solve the Figure 1 The sensitive amplifier shown in the figure cannot compare the input signals in the low amplitude region. This embodiment provides a full swing input type sensitive amplifier, which can not only compare the input signals in the medium amplitude region and the high amplitude region, but also compare the two input signals V in the two low amplitude regions below the threshold voltage of the NMOS tube. IP and V IN Make a comparison.

[0040] like Figure 2 As shown, the full swing input type sense amplifier and Figure 1Compared with the classic circuit, the main improvement is reflected in the input circuit part. Specifically, the full-swing input type sense amplifier also includes an output circuit and a precharge circuit. The output circuit adopts a latch circuit composed of two PMOS tubes and two NMOS tubes inversely coupled; the latch nodes Q and QB of the latch circuit are used as the output nodes of the quantization result. The precharge routing enable signal SAEN controls the start. The precharge circuit is used to pull the output nodes Q and QB to the same potential before comparison. In detail, the output circuit is composed of PMOS tubes P2, P3 and NMOS tubes N1, N2. The circuit connection relationship is: the source of P2 and P3 is connected to the power supply VDD; the drain of P2 and N1 is connected to the gate of P3 and N2 and serves as one of the latch nodes Q; the drain of P3 and N2 is connected to the gate of P2 and N1 and serves as another latch node QB. The pre-charging circuit is composed of two PMOS tubes P1 and P4, and the circuit connection relationship is: the source of P1 and P4 is connected to the power supply VDD; the drain of P1 and P4 is connected to the latch node Q and QB respectively; the gate of P1 and P4 is connected to the enable signal SAEN.

[0041] The sensitive amplifier provided in this embodiment belongs to a charge latch type sensitive amplifier, and the sensitive amplifier precharges the output nodes on both sides to a high level before comparison. Then, during operation, the output node is disconnected from the power supply VDD, and according to different input signals, one side of the output node is selected to be grounded and discharged. During the discharge process, the output circuit quickly amplifies the voltage difference between the output nodes Q and QB through the positive feedback coupling of the latch structure to obtain the required comparison result.

[0042] The existing sensitive amplifier cannot detect the input signal V in the low amplitude region. IP and V IN In order to solve the problem of generating the required discharge path, thereby causing functional failure, the full-swing input type sense amplifier provided in this embodiment also includes an adaptive gating circuit; the adaptive gating circuit provides two discharge paths for the output nodes Q and QB respectively, and IN and V IP The corresponding discharge path is adaptively selected, thereby realizing the comparison of two full-swing input signals. The adaptive selection circuit is composed of 4 PMOS tubes P5-P8 and 7 NMOS tubes N3-N9, and the circuit connection relationship is as follows:

[0043] The sources of P5 and P6 are connected to the power supply VDD; the drain of P5 is connected to the source of P7, and the drain of P6 is connected to the source of P8; the drains of N8 and P7 are connected to the gate of N3; the drains of N9 and P8 are connected to the gate of N6; the drains of N3 and N4 are connected to the source of one of the NMOS tubes in the output circuit; the drains of N5 and N6 are connected to the source of another NMOS tube in the output circuit; the sources of N3 to N6 are connected to the drain of N7, and the sources of N7, N8 and N9 are connected to VSS; the gate of N7 is connected to the enable signal SAEN; the gates of N8, N9, P5 and P6 are connected to the inverted enable signal NSAEN; the gates of P7 and N5 are connected to the input signal V IP ; The gate of P8 and N4 is connected to the input signal V IN .

[0044] Combination Figure 2 It can be found that the mechanism of the full-swing input type sense amplifier designed in this embodiment is: two pairs of NMOS transistors N3 to N6 for forming a discharge path are respectively arranged between the two output nodes of the output circuit corresponding to the NMOS transistors and the ground terminal, and the gates of one pair of NMOS transistors (N4 and N5) are respectively connected to the input signal V IN and V IP ; These two MOS tubes can be Figure 1 Like the classic solution, it works when the input signal is in the medium amplitude area and the low amplitude area to compare the magnitude relationship of the two input signals. The gates of the other two NMOS tubes (N3 and N6) are connected to the power supply VDD through the addition of two PMOS tubes (P7 and P8). IP and V IN Connected to the gate terminals of P7 and P8 respectively. In this state, when the two input signals V IP and V IN When in the low amplitude region, although it is impossible to regulate the NMOS tubes N4 and N5, it can regulate the on and off of the PMOS tubes P7 and P8. Then the power supply voltage VDD is introduced to the gate of N3 or N6 to indirectly regulate the on and off state of N3 and N6. Finally, N3 and N6 are controlled by the input signal V IP and V IN When the input signal V is in the low amplitude region, a discharge path is formed to complete the comparison task between the two. In particular, in the solution of this embodiment, when the input signal V IP and V IN When in the middle amplitude range, N3, N4, N5, and N6 will form a discharge path. In order to make the discharge rate of each discharge path consistent with the input signal V IP and V IN The magnitude relationship is linearly related, and this embodiment will especially be used with V INThe gate of the PMOS on the same side of the NMOS tube as the NMOS gate input is connected to V IP ; accordingly, will be with the use of V IP The gate of the PMOS on the same side of the NMOS tube as the NMOS gate input is connected to V IN .

[0045] In summary, the full-swing input type sense amplifier provided in this embodiment supports an input signal V IN and V IP The swing range is divided into high amplitude region, medium amplitude region and low amplitude region. When the two input signals are in the high amplitude region, N4 and N5 are turned on to form a discharge path; when the two input signals are in the low amplitude region, N3 and N6 are turned on to form a discharge path; when the two input signals are in the medium amplitude region, N3, N4, N5 and N6 are all turned on to form a discharge path.

[0046] During each comparison, the discharge rate of each discharge path formed depends on the input signal V connected to each gate terminal. IN and V IP size.

[0047] The operation logic of the full-swing input type sense amplifier provided in this embodiment is as follows:

[0048] (1) When the enable signal SAEN is at a high level and the inverted enable signal NSAEN is at a low level, that is, SAEN=1, NSAEN=0.

[0049] The full-swing input type sense amplifier is in working mode. At this time, the output nodes Q and QB are in a high-level equipotential state, and Figure 3 As shown, P1, P4, N8, and N9 are turned off, and P5, P6, and N7 are turned on. Therefore, the circuit can be used according to the input signal V IP and V IN , controls the conduction state of N3, N4, N5, and N6, forms a discharge path, changes the level state of the output nodes Q and QB, and then realizes the comparison of the input signal.

[0050] (2) When the enable signal SAEN is at a low level and the inverted enable signal NSAEN is at a high level, that is, SAEN=0, NSAEN=1.

[0051] The full-swing input sense amplifier is in reset mode. Figure 4As shown, P1, P4, N8, and N9 are turned on, and P5, P6, and N7 are turned off. In this state, N3, N4, N5, and N6 cannot be grounded through N7; N8 and N9 ground the gates of N3 and N6 to release the charge accumulated in the previous comparison; at the same time, the output nodes Q and QB are directly connected to the power supply VDD, and VDD pulls the two output nodes to the same potential, waiting for the next comparison.

[0052] exist Figure 2 Based on the provided solution capable of realizing a full-swing input type sensitive amplifier, this implementation further provides a circuit solution with better performance. This circuit solution not only has a full-swing input function, but also can solve the circuit's offset voltage problem, further improving the circuit's output accuracy and stability.

[0053] Specifically, Figure 5 As shown, the full swing input type sense amplifier provided in this embodiment also includes an offset suppression circuit for reducing the offset voltage occurring during the circuit quantization process. The offset suppression circuit includes a PMOS tube P9; P9 is connected between the sources of N1 and N2; and the gate of P9 is connected to the enable signal SAEN.

[0054] contrast Figure 2 and Figure 5 It can be found that: the potential state corresponding to the source of N1 is recorded as D, the potential state corresponding to the source of N2 is recorded as F, the potential corresponding to the drain of P7 is recorded as G, and the potential corresponding to the drain of P8 is recorded as H. Then Figure 2 One of the main sources of the offset voltage of the sense amplifier is the mismatch of the two discharge paths of the sense amplifier in the non-enabled state, that is, the voltage mismatch between points D and F and the voltage mismatch between points G and H. Figure 5 In the provided circuit, the newly added PMOS tube P9 in the offset suppression circuit can perform charge sharing between the sources of N1 and N2, thereby effectively alleviating the problem of the mismatch of the discharge path state.

[0055] further, Figure 5 The offset suppression circuit used in the improved sense amplifier shown in the figure also includes a buffer Buffer1 connected between the output node Q and the external circuit, and a buffer Buffer2 connected between the output node QB and the external circuit. Buffer1 and buffer2 isolate the stored nodes from the outside and can also effectively reduce the offset voltage.

[0056] The full-swing input type sense amplifier provided in this embodiment has two typical application scenarios, one is to read data from an SRAM circuit, and the other is to quantize and output the logic operation results in a CIM circuit based on an SRAM. In the above two application scenarios, the input signal V IN and VIP The ports are respectively connected to the bit lines on both sides of each SRAM unit or CIM unit.

[0057] Example 2

[0058] Based on the solution of Example 1, this embodiment further provides a comparison module, which is composed of the Figure 2 or Figure 5 The comparator module includes a power supply port VDD, a ground terminal VSS, an enable terminal SAEN, an inverting enable terminal NSAEN, two input terminals VIN and VIP, and two output terminals DOUT and DOUT_BAR.

[0059] The input terminals VIN and VIP are used to input two input signals to be compared respectively; the output terminals DOUT and DOUT_BAR are used to output the comparison result and its inverted value respectively. The enable terminal SAEN and the inverted enable terminal NSAEN are used as combination signals to switch the operation mode of the comparison module.

[0060] The signal flow diagram of the circuit operation process of the comparison module is as follows Figure 6 As shown in the figure, when SAEN is low and NSAEN is high, the comparison module is in reset mode. At this time, P1, P4, and P6 are turned on, and Q is precharged to a high level (i.e., Q is charged to a high level by VDD through P1), QB is precharged to a high level (i.e., QB is charged to a high level by VDD through P4), D is precharged to a high level (i.e., D is charged to a high level by VDD through N1 and P1), and F is precharged to a high level (i.e., F is charged to a high level by VDD through N2 and P4); N8 and N9 are turned on, and G is discharged to a low level (i.e., G is discharged to a low level by VSS through N8), and H is discharged to a low level (i.e., G is discharged to a low level by VSS through N9); P5, P7, and N7 are turned off.

[0061] When SAEN is high and NSAEN is low, the comparison module circuit is in working mode. At this time, P1, P4, P6, N8, and N9 are turned off, and P5, P7, and N7 are turned on. IN The voltage is less than VIP , the on-current of P8 is less than the on-current of P9, so the voltage at point H is greater than the voltage at point G, making the on-current of N3 less than the on-current of N6, and the on-current of N4 less than the on-current of N5. Q discharges to VSS through N3 and N4, and QB discharges to VSS through N5 and N6, and the discharge speed of QB is greater than the discharge speed of Q, making the voltage of Q greater than the voltage of QB. In addition, because the latch circuit forms a positive feedback coupling, it promotes Q to charge to a high level and QB to discharge to a low level, and quickly amplifies the voltage difference between QB and Q. On the contrary, if V IN The voltage is greater thanVIP The voltage will promote Q to discharge to a low level and QB to charge to a high level.

[0062] The last two buffers isolate Q and QB from the subsequent circuits and output the comparison results to the outside through the output terminals DOUT and DOUT_BAR.

[0063] Example 3

[0064] Based on Embodiments 1 and 2, this embodiment further provides a chip, which includes an SRAM storage chip and a CIM chip based on SRAM. The chip includes an SRAM array or a CIM array based on SRAM formed by a plurality of basic circuit units arranged in an array.

[0065] In particular, in the SRAM array or CIM array, the bit lines on both sides of each column of circuit units are connected with a comparator module as in Embodiment 2. The comparator module is used to read the data stored in the circuit units of the SRAM array or quantify the results of the logic operation in the circuit units of the CIM array.

[0066] Test experiment

[0067] In order to verify the performance of the technical solution provided by the present invention, the technicians conducted a test on the Figure 1 A conventional voltage-controlled current-mode SRAM sense amplifier circuit (abbreviated as CLSA) and a full-swing input sense amplifier provided by the present invention (abbreviated as The proposed SA) are simulated, and the circuit performances of the two are tested and compared.

[0068] 1. Differential amplification performance

[0069] The technicians first tested the performance difference of the two circuits in differential amplification, and the experimental data obtained are as follows: Figure 7 shown.

[0070] analyze Figure 7 From the data:

[0071] Since the CLSA solution only uses NMOS tubes to control the conduction state of the discharge path, and the NMOS tube is in the cut-off state at low voltage, it will not conduct regardless of the difference in input voltage, and the discharge path to ground is always off, and a coupling structure cannot be formed; therefore, when the CLSA voltage is low, DOUT and DOUT_BAR are both high levels, and no comparison result is output. Only when the voltage is high, DOUT is quickly discharged to a low level and DOUT_BAR is quickly charged to a high level.

[0072] For the proposed SA scheme of the present invention, when SAEN is 1, DOUT is quickly discharged to a low level, and DOUT_BAR is pulled to a high level after a short discharge to achieve the output of the comparison result. In the proposed SA scheme, when a single PMOS tube implements a coupled latch structure, VD≈VS=0 is required. Therefore, the PMOS tube Vgs=0 cannot be turned on. Therefore, the input voltage range in which the CLSA scheme can work normally is limited (500mV-900mV), while the proposed SA has a significant input voltage range advantage in comparison and can work within the full swing range (0-900mV).

[0073] 2. Offset voltage performance

[0074] This experiment further analyzes the offset voltage of the two circuits under five process corners: TT, FF, SS, SF, and FS. The experimental data obtained are as follows: Figure 8 shown.

[0075] analyze Figure 8 The data show that the offset voltage of the solution of the present invention is lower than that of the traditional CLSA solution at all process angles, and the reduction of the offset voltage exceeds 45%, and the performance is very outstanding.

[0076] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A full-swing input type sense amplifier, comprising an output circuit and a pre-charge circuit; the output circuit adopts a latch circuit composed of two PMOS tubes and two NMOS tubes inversely coupled; the latch nodes Q and QB of the latch circuit are used as output nodes of quantization results; the pre-charge routing enable signal SAEN controls the start-up and is used to pull the output nodes Q and QB to the same potential before comparison; the characteristics are: The full swing input type sensitive amplifier also includes an adaptive gating circuit; the adaptive gating circuit provides two discharge paths for the output nodes Q and QB respectively, and IN and V IP Adaptively select the corresponding discharge path to compare two full-swing input signals; The adaptive gating circuit is composed of 4 PMOS tubes P5-P8 and 7 NMOS tubes N3-N9, and the circuit connection relationship is as follows: the source of P5 and P6 is connected to the power supply VDD; the drain of P5 is connected to the source of P7, and the drain of P6 is connected to the source of P8; the drain of N8 and P7 is connected to the gate of N3; the drain of N9 and P8 is connected to the gate of N6; the drain of N3 and N4 is connected to the source of one of the NMOS tubes in the output circuit; the drain of N5 and N6 is connected to the source of another NMOS tube in the output circuit; the source of N3-N6 is connected to the drain of N7, and the source of N7, N8 and N9 is connected to VSS; the gate of N7 is connected to the enable signal SAEN; the gates of N8, N9, P5 and P6 are connected to the inverted enable signal NSAEN; the gates of P7 and N5 are connected to the input signal V IP ; The gate of P8 and N4 is connected to the input signal V IN .

2. The full-swing input type sense amplifier according to claim 1, characterized in that: The output circuit is composed of two PMOS tubes P2 and P3 and two NMOS tubes N1 and N2; the circuit connection relationship is: the source of P2 and P3 is connected to the power supply VDD; the drain of P2 and N1 is connected to the gate of P3 and N2 and serves as one of the latch nodes Q; the drain of P3 and N2 is connected to the gate of P2 and N1 and serves as another latch node QB.

3. The full-swing input type sense amplifier according to claim 2, characterized in that: The pre-charging circuit is composed of two PMOS tubes P1 and P4; the sources of P1 and P4 are connected to the power supply VDD; the drains of P1 and P4 are connected to the latch nodes Q and QB respectively; the gates of P1 and P4 are connected to the enable signal SAEN.

4. The full-swing input type sense amplifier according to claim 3, characterized in that: It also includes an offset suppression circuit for reducing the offset voltage occurring during the circuit quantization process; the offset suppression circuit includes a PMOS tube P9; P9 is connected between the sources of N1 and N2; and the gate of P9 is connected to an enable signal SAEN.

5. The full-swing input type sense amplifier according to claim 4, characterized in that: The offset suppression circuit further includes a buffer Buffer1 connected between the output node Q and the external circuit, and a buffer Buffer2 connected between the output node QB and the external circuit.

6. The full-swing input type sense amplifier according to any one of claims 3 to 5, characterized in that: When it is used to read data from an SRAM circuit or to quantify the results of logic operations on a CIM circuit based on SRAM, the input signal V IN and V IP The ports are respectively connected to the bit lines on both sides of each SRAM unit or CIM unit.

7. The full-swing input type sense amplifier according to any one of claims 3 to 5, characterized in that: Its operation logic is as follows: (1) When the enable signal SAEN is at a high level and the inverting enable signal NSAEN is at a low level, the full-swing input type sense amplifier is in the working mode, and is used to IN and V IP Compare the size relationship of (2) When the enable signal SAEN is at a low level and the inverted enable signal NSAEN is at a high level, the full-swing input type sense amplifier is in a reset mode, which is used to pull the two output nodes to the same potential and wait for the next comparison.

8. The full-swing input type sense amplifier according to any one of claims 3 to 5, characterized in that: Input signal V IN and V IP The swing range is divided into high amplitude area, medium amplitude area and low amplitude area; when the input signal is in the high amplitude area, N4 and N5 are turned on to form a discharge path; When the input signal is in the low amplitude region, N3 and N6 are turned on and form a discharge path; when the input signal is in the medium amplitude region, N3, N4, N5, and N6 are all turned on and form a discharge path; During each comparison, the discharge rate of each discharge path formed depends on the input signal V connected to each gate terminal. IN and V IP size.

9. A comparison module, characterized in that: It is packaged by the full-swing input type sense amplifier as described in any one of claims 1 to 4; the comparator module includes a power port VDD, a ground terminal VSS, an enable terminal SAEN, an inverting enable terminal NSAEN, two input terminals VIN and VIP, and two output terminals DOUT and DOUT_BAR; The input terminals VIN and VIP are respectively used to input two input signals to be compared; the output terminals DOUT and DOUT_BAR are respectively used to output the comparison result and its inverted value.

10. A chip comprising an SRAM array or a CIM array based on SRAM, characterized in that: In the SRAM array or CIM array, a comparator module as described in claim 9 is connected to the bit lines on both sides of each column of circuit units, and the comparator module is used to read the data stored in the circuit units of the SRAM array, or quantify the results of logical operations in the circuit units of the CIM array.

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