Structure and method for preparing wafer-level system packaging chip by utilizing Hybrid Bonding and FOWLP technologies

Abstract

The invention relates to a structure and a method for preparing a wafer-level system packaging chip by utilizing Hybrid Bonding and FOWLP technologies. According to the packaging structure and method, the integration of the CIS chip and other types of chips can be realized, the packaging process is completed through the FOWLP technology, the integration of different types of chips is realized, the packaging efficiency can be greatly improved, and the processing cost is remarkably reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor chip packaging, and in particular to a structure and method for preparing a wafer-level system packaging chip by using Hybrid Bonding and FOWLP technologies. Background Art

[0002] Hybrid bonding technology refers to the bonding of the two wafers (or chips) to be bonded. In addition to the copper bump that is sunken at room temperature, the other non-conductive parts of the two wafers (or chips) facing each other must also be bonded. After the Hybrid Bonding process is completed, there is no gap between the wafers (or chips), and no epoxy resin is needed to fill it. The Hybrid Bonding process flow chart is as follows: Figure 1 shown.

[0003] At present, advanced packaging technology mainly refers to flip chip (FC), wafer level package (WLP), 2.5D package (Interposer), 3D package through silicon via (TSV) technology, etc. From the perspective of advanced packaging technology platform segmentation, FC technology is the most widely used, accounting for about 75% of the market share, followed by fan-in wafer level package (FIWLP) and fan-out wafer level package (FOWLP). From the perspective of future development speed, consulting firm Yole Intelligence predicts that from 2018 to 2024, FOWLP will grow rapidly due to the vast market space in the future and will maintain a compound growth rate of 26%. This technology will be mainly used in the fields of mobile Internet, network, and automobile.

[0004] FOWLP is a new packaging technology that can package multiple chips on a wafer to achieve high integration. At the same time, the I / O contacts are designed in the area outside the chip size to increase the number of I / O contacts. At the same time, the metal rewiring layer process is used to increase the wiring area that can be used by the chip, making full use of the effective area of ​​the chip to form a fan-shaped structure. This packaging technology can connect the signal lines and power lines of multiple chips together, thereby reducing the connection lines between chips, reducing power consumption and signal transmission delay. After completing the chip solder ball connection, FOWLP technology can be directly soldered on the printed circuit board without the use of a packaging carrier, which can shorten the signal transmission distance and improve electrical performance. This packaging technology can not only greatly improve the chip integration and performance, reduce cost and power consumption, but also reduce the volume and weight of the package, thereby reducing the difficulty of manufacturing. The application range of FOWLP technology is very wide. It can be applied to various types of chips, including processors, memory, sensors, etc. In addition, fan-out wafer-level packaging can also be applied to various fields, including communications, computers, medical, automobiles, etc. Compared with other advanced packaging technologies, the advantage of FOWLP technology is that it can use high-density wiring manufacturing processes to form a chip packaging structure with lower power loss and stronger functionality, which has more obvious advantages for system packaging technology. The first generation of FOWLP technology is the embedded wafer level ball grid array (Embedded Wafer Level Ball Grid Array, eWLB) technology developed by Infineon of Germany, followed by TSMC's integrated fan-out wafer level packaging (InFO) technology and Freescale's redistributed chip package (RCP) technology. Due to its relatively low cost and powerful functionality, it has gradually been accepted by the market. For example, Apple has adopted fan-out packaging for mass production of A12 processors. At the same time, it has not only developed rapidly in the wireless field, but is now also penetrating into automotive and medical applications. It is believed that most of the devices in our lives in the future will adopt fan-out wafer level packaging technology. As one of the next-generation packaging technologies, FOWLP has developed well in recent years, mainly driven by TSMC providing InFO to the Apple ecosystem. Today's fan-out wafer-level packaging is in a period of rapid growth. According to the latest report from Yole Intelligence, the FOWLP market is experiencing strong growth, with an overall CAGR of 15.1% between 2020 and 2026, and the market size will increase to US$3.425 billion by the end of 2026.Among them, the mobile and consumer sector was US$1.613 billion, the telecommunications and infrastructure sector was US$1.597 billion, and the automotive and travel sector was US$216 million.

[0005] Image sensor chip (CMOS Inage Sensor, CIS) is an image sensor based on semiconductor CMOS technology, which began to be widely used in the late 1990s. Currently, CIS chips have been widely used in mobile phones, cameras, automotive electronics, security and other fields.

[0006] As mobile consumer electronic products such as mobile phones, computers, and digital cameras have higher and higher requirements for the packaging of high-performance, low-power, miniaturized, heterogeneous process integration, and low-cost system-integrated electronic products, high-density, multi-type chip system-level packaging products have gradually become the mainstream in the new generation of electronic products. Therefore, how to combine CIS chips with FOWLP technology to form system-integrated electronic products has always been a hot technology in the field of chip packaging research. Summary of the invention

[0007] In order to solve the above technical problems, the purpose of the present invention is to provide a structure and method for preparing a wafer-level system packaging chip using Hybrid Bonding and FOWLP technology. The packaging structure and method can realize the integration of CIS chips with other types of chips and complete the packaging process through FOWLP technology. While realizing the integration of different types of chips, it can greatly improve the packaging efficiency and significantly reduce the processing cost.

[0008] According to one aspect of the present invention, there is provided a method for preparing a wafer-level system-in-package chip using Hybrid Bonding and FOWLP technology, comprising the following steps:

[0009] S1, cleaning the surface of the wafer-level CIS chip;

[0010] S2, forming an adhesive film layer and a glass layer on the front side of the wafer-level CIS chip;

[0011] S3, thinning the back side of the wafer-level CIS chip and forming a non-bonding layer;

[0012] S4, forming a conductive through-hole structure on the back side of the wafer-level CIS chip;

[0013] S5, forming a conductive structure on the back side of the wafer-level CIS chip;

[0014] S6, forming a non-bonding layer on the silicon-based carrier wafer;

[0015] S7, forming a conductive through-hole structure on the silicon-based carrier;

[0016] S8, forming a conductive structure on the silicon-based carrier wafer;

[0017] S9, bonding the wafer-level CID chip and the silicon-based carrier together;

[0018] S10, thinning the back side of the bonded silicon-based carrier sheet and forming a groove structure;

[0019] S11, pasting the second type chip in the bonding sheet groove structure;

[0020] S12, forming a first insulating layer on the bonded wafer;

[0021] S13, forming a first metal redistribution layer on the bonded wafer;

[0022] S14, forming a second insulating layer on the bonded wafer;

[0023] S15, forming a second metal redistribution layer (i.e., pad) on the bonded wafer;

[0024] S16, planting balls on the second metal redistribution layer of the wafer after bonding;

[0025] S17, cutting to obtain a single Die.

[0026] The material of the insulating layer in steps S12 and S14 is epoxy resin, silicon oxide insulating material or other insulating material; in this embodiment, the insulating layer material is photosensitive epoxy resin. The material of the metal redistribution layer in steps S13 and S15 is one or a combination of two or more of aluminum, copper, gold, platinum, nickel, and tin; in this embodiment, the insulating layer metal redistribution layer material is copper.

[0027] The present invention provides a structure and method for preparing a wafer-level system-on-chip package using Hybrid Bonding and FOWLP technologies, which uses the Hybrid Bonding technology to integrate a CIS chip with other types of chips and completes the entire packaging process through the FOWLP technology.

[0028] According to another aspect of the present invention, a wafer-level system-in-package chip structure prepared by the above method using Hybrid Bonding and FOWLP technology includes a wafer-level CIS chip, a silicon-based carrier, and a wafer-level CID chip; the front side of the wafer-level CIS chip is provided with an adhesive film layer and a glass layer;

[0029] The back of the wafer-level CIS chip is thinned and a non-bonding layer is formed; a conductive through-hole structure is set on the back of the wafer-level CIS chip; a conductive structure is set on the back of the wafer-level CIS chip; a non-bonding layer is set on the silicon-based carrier; a conductive through-hole structure is set on the silicon-based carrier; a conductive structure is set on the silicon-based carrier; the wafer-level CID chip and the silicon-based carrier are bonded together; after bonding, the back of the silicon-based carrier is thinned and a groove structure is formed; a second type of chip is pasted in the groove structure of the bonding sheet; a first insulating layer is set on the bonded wafer; a first metal redistribution layer is set on the bonded wafer; a second insulating layer is set on the bonded wafer; a second metal redistribution layer is set on the bonded wafer; a ball is planted on the second metal redistribution layer of the bonded wafer; and a single Die is obtained by cutting.

[0030] Furthermore, the wafer-level chip comprises a CIS chip (10), a photosensitive area arranged on the upper surface of the CIS chip (10), and a CIS chip conductive structure (12); an adhesive film layer (13) with high light transmittance and a glass layer (14) with high light transmittance are sequentially arranged on the upper surface of the wafer-level CIS chip.

[0031] The back side of a wafer-level CIS chip is thinned and a non-conductive layer (15) is provided; a conductive structure through hole (205) is provided on the structure at a position corresponding to the conductive structure of the wafer-level CIS chip, the conductive structure through hole (205) passes through the non-conductive layer (15) and the CIS chip (10); and a conductive structure (16) is provided at the conductive through hole structure (205).

[0032] Furthermore, a non-conductive layer (102) is provided on the silicon-based carrier (101), a through-hole structure (303) is formed on the silicon-based carrier (101) with the non-conductive layer (102), and a conductive structure (103) is formed on the through-hole structure (303).

[0033] Furthermore, the wafer-level CIS chip formed by the conductive structure (16) and the silicon-based carrier (101) formed by the conductive structure (103) are bonded by hybrid bonding technology, and the two wafers are bonded to form a non-conductive layer (104) and a conductive structure (105); a groove structure (303) is provided on the wafer-level structure after the bonding.

[0034] The groove structure is provided with a second type chip (107) which is thinned and cut by an adhesive film (106), a conductive structure (108) is provided on the second type chip (107), and a gap structure (304) is formed between the second type chip (107) and the groove structure 303; a first insulating layer (109) is provided on the wafer-level structure of the conductive structure (108) to form a conductive through-hole structure (306); and a first metal redistribution layer (110) is formed on the wafer-level structure of the conductive through-hole structure (306).

[0035] A second insulating layer (111) and a conductive through-hole structure (308) are arranged on the wafer-level structure of the first metal redistribution layer (110).

[0036] A second metal redistribution layer (112) is formed on the wafer-level structure of the conductive through-hole structure (308); solder balls (113) are implanted on the wafer-level structure of the second metal redistribution layer (112); and a single die is obtained by cutting the wafer implanted with the solder balls (113).

[0037] The beneficial effects of the present invention are mainly the following three points: (1) Hybrid Bonding technology is used for bonding, which can achieve higher density contact connection (more than one million contacts can be made in a 1×1 cm chip) and smaller contact spacing connection (the spacing can be miniaturized to less than 1 micron). (2) The CIS chip is integrated with other types of chips to achieve high-performance, low-power, miniaturized, heterogeneous process integration, and low-cost system integrated electronic products. (3) The integrated combined chip is completed through the entire packaging process through FOWLP technology, thereby improving packaging efficiency and reducing packaging costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 Figure 1 is a flow chart of hybrid bonding: (a) the appearance of the unbonded specimen, (b) the dielectric material bonding step, (c) the copper contact bonding process with increased temperature, and (d) the stress distribution state inside the contact at high temperature.

[0039] Figure 2 Schematic diagram of the structure of a wafer-level image sensor (CIS) chip.

[0040] Figure 3 for Figure 2 The schematic diagram of the structure is that an adhesive film layer and a glass layer with high light transmittance are sequentially formed on the upper surface of a wafer-level CIS chip.

[0041] Figure 4 For Figure 3 Schematic diagram of the structure in which the back side of a wafer-level CIS chip is thinned and a non-conductive layer is formed in the Hybrid Bonding technology.

[0042] Figure 5 For Figure 4 A schematic diagram of a structure in which a conductive structure through hole is formed at a position corresponding to the conductive structure of a wafer-level CIS chip.

[0043] Figure 6 For Figure 5 A conductive structure is formed at the conductive through-hole structure of the structure shown.

[0044] Figure 7 It is used to form a non-conductive layer in the Hybrid Bonding technology on a silicon-based carrier.

[0045] Figure 8 For Figure 7 A through-hole structure is formed on the silicon-based carrier wafer with a non-conductive layer.

[0046] Fig. 9 For Figure 8 A conductive structure is formed on the structure shown.

[0047] Fig.10 The figure is a schematic diagram of bonding the wafer-level CIS chip obtained in step (5) to the silicon-based carrier obtained in step (8) through the Hybrid Bonding technology.

[0048] Fig.11 For Fig.10 A groove structure is formed on the wafer-level structure.

[0049] Fig.12 To place the thinned and cut second type chips on the Fig.11 Schematic diagram of the groove structure shown.

[0050] Fig.13 For Fig.12 A first insulating layer and a conductive through-hole structure are formed on the wafer-level structure.

[0051] Fig.14 For Fig.13 A first metal redistribution layer is formed on the wafer-level structure shown.

[0052] Fig.15 For Fig.14 A second insulating layer and a conductive via structure are formed on the wafer-level structure.

[0053] Fig.16 For Fig.15 The second metal redistribution layer on the wafer-level structure is shown.

[0054] Fig.17 For Fig.16 Schematic diagram of completing ball implantation on the wafer level structure shown.

[0055] Fig.18 This is a schematic diagram of combining CIS chips with other types of chips through Hybrid Bonding technology and completing packaging through FOWLP technology. DETAILED DESCRIPTION

[0056] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0057] (1) For Figure 2 The surface of the wafer-level image sensor (CIS) chip shown in the figure is cleaned. 10 is the chip, 11 is the photosensitive area of ​​the CIS chip, 12 is the conductive structure of the CIS chip (ie, Al Pad), 201 is the upper surface of the CIS chip, and 202 is the lower surface of the CIS chip.

[0058] (2) Figure 2 The upper surface of the wafer-level CIS chip shown in FIG. 1 is sequentially formed with an adhesive film layer and a glass layer having high light transmittance characteristics, and the result is as shown in FIG. Figure 3 The structure shown in FIG. 13 is an adhesive film layer with high light transmittance, 14 is a glass layer with high light transmittance, and 203 is the surface of the glass layer.

[0059] (3) Yes Figure 3 The back side of the wafer-level CIS chip is thinned and a non-conductive layer is formed in the Hybrid Bonding technology to obtain the following Figure 4 The structure shown in FIG. 15 is a non-conductive layer, and the material of the layer in this embodiment is SiO2. 204 is the upper surface of the non-conductive layer 15.

[0060] (4) Figure 4 A conductive structure through hole is formed at a position corresponding to the conductive structure of the wafer-level CIS chip on the structure shown in FIG. Figure 5 In the structure shown, the conductive structure through hole penetrates the non-conductive layer 15 and the CIS chip 10. 205 is a conductive structure through hole.

[0061] (5) Figure 5 A conductive structure is formed at the conductive through-hole structure shown in the structure, and a conductive structure is obtained as shown in the figure. Figure 6 The structure shown in FIG. 16 is a conductive structure.

[0062] (6) In Figure 7 A non-conductive layer in the Hybrid Bonding technology is formed on the silicon-based carrier shown in FIG. Figure 7 The structure shown in FIG. 101 is a silicon-based carrier, 102 is a non-conductive layer, and in this embodiment, the material of the layer is SiO2. 301 is the lower surface of the silicon-based carrier, and 302 is the upper surface of the non-conductive layer.

[0063] (7) Figure 7 A through hole structure is formed on the silicon-based carrier with a non-conductive layer as shown in FIG. Figure 8 The structure shown in FIG. 303 is a through hole structure.

[0064] (8) In Figure 8 A conductive structure is formed on the structure shown in FIG. Fig. 9 The structure shown in FIG. 103 is a conductive structure.

[0065] (9) Bonding the wafer-level CIS chip obtained in step (5) to the silicon-based carrier obtained in step (8) by using a Hybrid Bonding technology to obtain Fig.10 The structure shown in FIG. 104 is a non-conductive layer formed after two wafers are bonded together, and 105 is a conductive structure formed after two wafers are bonded together.

[0066] (10) Fig.10 A groove structure is formed on the wafer-level structure as shown, and a Fig.11 The structure shown in FIG. 303 is a groove structure.

[0067] (11) Place the thinned and cut second type chips on the Fig.11 In the groove structure shown in FIG. Fig.12 106 is an adhesive film, 107 is a second type chip, 108 is a second type chip conductive structure (ie, AlPad), and 304 is a gap structure newly formed after the second type chip is placed in the groove structure 303 .

[0068] (12) Fig.12 A first insulating layer is formed on the wafer-level structure shown in FIG. 1 and a conductive through-hole structure is formed to obtain a structure as shown in FIG. Fig.13 The structure shown in FIG. 109 is a first insulating layer, 305 is an upper surface of the first insulating layer, and 306 is a conductive through-hole structure formed on the first insulating layer.

[0069] (13) Fig.13 The first metal redistribution layer is formed on the wafer-level structure shown in FIG. Fig.14 The structure shown in FIG. 110 is the first metal redistribution layer.

[0070] (14) Fig.14 A second insulating layer and a conductive through-hole structure are formed on the wafer-level structure shown in FIG. Fig.15 The structure shown in FIG. 111 is a second insulating layer, 307 is an upper surface of the second insulating layer, and 308 is a conductive through-hole structure formed on the second insulating layer.

[0071] (15) Fig.15 The second metal redistribution layer (i.e., pad) on the wafer-level structure shown in FIG. Fig.16 The structure shown in FIG. 112 is a second metal redistribution layer.

[0072] (16) Fig.16 The ball implantation process is completed on the wafer level structure shown in the figure, and the Fig.17 The structure shown in FIG. 113 is a solder ball structure.

[0073] (17) Fig.17 The wafer is cut into Fig.18 The single chip shown is an integrated chip structure that combines a CIS chip with other types of chips and is packaged using FOWLP technology.

[0074] like Fig.18 As shown in the structure, the present embodiment prepares a system integrated chip structure with high performance, low power consumption, miniaturization, heterogeneous process integration and low cost by combining CIS chips with other types of chips through Hybrid Bonding technology and completing the packaging through FOWLP technology. The specific layers in the structure are as follows: 10-CIS chip, 11-CIS photosensitive area, 12-CIS conductive structure, 13-high-transmittance adhesive film layer, 14-high-transmittance glass layer, 101-silicon-based carrier, 104-non-bonding layer, 105-conductive structure, 106-adhesive film, 107-second type chip, 108-second type chip conductive structure, 109-first insulating layer, 110-first metal redistribution layer, 111-second insulating layer, 112-second metal redistribution layer (pad), 113-conductive structure (solder ball).

[0075] It is worth noting that: in the description of the present invention, the meaning of "multiple" is two or more than two, unless otherwise clearly and specifically defined. In the present invention, unless otherwise clearly stipulated and defined, the terms "install", "connect", "connect", "fix" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection; the circuits described in the present invention are all commonly used circuits in the art, and other related components are all existing commonly used components. For ordinary technicians in the art, the specific meanings of the above terms in the present invention can be understood according to the specific circumstances.

[0076] It is obvious to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential features of the present invention. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-restrictive, and the scope of the present invention is defined by the appended claims rather than the above description, and it is intended that all changes that fall within the meaning and scope of the elements of the claims be included in the present invention. Any reference numeral in a claim should not be regarded as limiting the claim to which it relates.

Claims

1. A method for preparing a wafer-level system-in-package chip using Hybrid Bonding and FOWLP technology, characterized in that: The steps include: S1, cleaning the surface of the wafer-level CIS chip; S2, forming an adhesive film layer and a glass layer on the front side of the wafer-level CIS chip; S3, thinning the back side of the wafer-level CIS chip and forming a non-bonding layer; S4, forming a conductive through-hole structure on the back side of the wafer-level CIS chip; S5, forming a conductive structure on the back side of the wafer-level CIS chip; S6, forming a non-bonding layer on the silicon-based carrier wafer; S7, forming a conductive through-hole structure on the silicon-based carrier; S8, forming a conductive structure on the silicon-based carrier; S9, bonding the wafer-level CID chip and the silicon-based carrier together; S10, thinning the back side of the bonded silicon-based carrier sheet and forming a groove structure; S11, pasting the second type chip in the bonding sheet groove structure; S12, forming a first insulating layer on the bonded wafer; S13, forming a first metal redistribution layer on the bonded wafer; S14, forming a second insulating layer on the bonded wafer; S15, forming a second metal redistribution layer on the bonded wafer; S16, planting balls on the second metal redistribution layer of the wafer after bonding; S17, cutting to obtain a single Die.

2. The method according to claim 1, characterized in that: The material of the insulating layer in steps S12 and S14 is epoxy resin or silicon oxide insulating material.

3. The method according to claim 1, characterized in that: The insulating layer material in steps S12 and S14 is photosensitive epoxy resin.

4. The method according to claim 1, characterized in that: The material of the metal redistribution layer in steps S13 and S15 is one or a combination of two or more of aluminum, copper, gold, platinum, nickel, and tin.

5. The method according to claim 1, characterized in that: The insulating layer metal redistribution layer material in steps S13 and S15 is copper.

6. The method according to claim 1, characterized in that: The CIS chip is integrated with other types of chips using Hybrid Bonding technology and the entire packaging process is completed using FOWLP technology.

7. A wafer-level system-in-package chip structure prepared by using Hybrid Bonding and FOWLP technology according to the method of any one of claims 1 to 6, characterized in that: It comprises a wafer-level CIS chip, a silicon-based carrier, and a wafer-level CID chip; the front side of the wafer-level CIS chip is provided with an adhesive film layer and a glass layer; Performing a thinning process on the back of a wafer-level CIS chip and forming a non-bonding layer; providing a conductive through-hole structure on the back of the wafer-level CIS chip; and providing a conductive structure on the back of the wafer-level CIS chip; A non-bonding layer is provided on a silicon-based carrier; a conductive through-hole structure is provided on the silicon-based carrier; a conductive structure is provided on the silicon-based carrier; a wafer-level CID chip and a silicon-based carrier are bonded together; the back side of the silicon-based carrier is thinned after bonding and a groove structure is formed; a second type of chip is pasted in the groove structure of the bonding sheet; a first insulating layer is provided on the bonded wafer; a first metal redistribution layer is provided on the bonded wafer; a second insulating layer is provided on the bonded wafer; a second metal redistribution layer is provided on the bonded wafer; a ball is planted on the second metal redistribution layer of the bonded wafer; and a single die is obtained by cutting.

8. The wafer-level system-in-package chip structure according to claim 7, characterized in that: A wafer-level chip comprises a CIS chip (10), a photosensitive area arranged on the upper surface of the CIS chip (10), and a CIS chip conductive structure (12); an adhesive film layer (13) with high light transmittance and a glass layer (14) with high light transmittance are sequentially arranged on the upper surface of the wafer-level CIS chip; The back side of a wafer-level CIS chip is thinned and a non-conductive layer (15) is provided; a conductive structure through hole (205) is provided on the structure at a position corresponding to the conductive structure of the wafer-level CIS chip, the conductive structure through hole (205) passes through the non-conductive layer (15) and the CIS chip (10); and a conductive structure (16) is provided at the conductive through hole structure (205).

9. The wafer-level system-in-package chip structure according to claim 7, characterized in that: A non-conductive layer (102) is provided on the silicon-based carrier (101), a through-hole structure (303) is formed on the silicon-based carrier (101) with the non-conductive layer (102), and a conductive structure (103) is formed on the through-hole structure (303).

10. The wafer-level system-in-package chip structure according to claim 8 or 9, characterized in that: Bonding a wafer-level CIS chip formed by a conductive structure (16) and a silicon-based carrier (101) formed by a conductive structure (103) by using a hybrid bonding technology, wherein the two wafers are bonded to form a non-conductive layer (104) and a conductive structure (105); and providing a groove structure (303) on the wafer-level structure after bonding; The groove structure is provided with a second type chip (107) that has been thinned and cut using an adhesive film (106); a conductive structure (108) is provided on the second type chip (107); a gap structure (304) is formed between the second type chip (107) and the groove structure 303; a first insulating layer (109) is provided on the wafer-level structure of the conductive structure (108) to form a conductive through-hole structure (306); and a first metal redistribution layer (110) is formed on the wafer-level structure of the conductive through-hole structure (306); Disposing a second insulating layer (111) and a conductive via structure (308) on the wafer-level structure of the first metal redistribution layer (110); A second metal redistribution layer (112) is formed on the wafer-level structure of the conductive through-hole structure (308); solder balls (113) are implanted on the wafer-level structure of the second metal redistribution layer (112); and a single die is obtained by cutting the wafer implanted with the solder balls (113).

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