Reinforcing ring, semiconductor packaging structure and forming method thereof

Abstract

The invention provides a reinforcing ring, a semiconductor packaging structure and a forming method thereof, and the semiconductor packaging structure comprises a substrate which comprises a chip region used for packaging a chip; the reinforcing ring is positioned on the substrate around the corner of the chip area and surrounds the corner of the chip area; and the chip is packaged on the substrate in the chip area. According to the reinforcing ring, the semiconductor packaging structure and the forming method thereof provided by the invention, the warping degree of the substrate is reduced by using the reinforcing ring, so that the chip is protected from stress generated by warping of the substrate, a low-dielectric-constant material in the chip can be prevented from being broken in the chip packaging process, and the performance and the reliability of a chip device are improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a reinforcement ring, a semiconductor packaging structure and a method for forming the same. Background Art

[0002] The semiconductor packaging process includes the step of packaging the cut chip on the substrate. However, in the flip chip packaging process (FCA), the chip needs to go through a reflow process when it is packaged on the substrate. During reflow, the substrate will warp due to thermal expansion. The warped substrate will generate stress on the chip, causing the low dielectric constant material in the chip to crack, seriously affecting the performance and reliability of the chip device.

[0003] Therefore, it is necessary to provide a more effective and reliable technical solution to avoid the cracking of low dielectric constant materials in the chip during the chip packaging process and improve the performance and reliability of chip devices. Summary of the invention

[0004] The present application provides a reinforcement ring, a semiconductor packaging structure and a method for forming the same, which can prevent the low dielectric constant material in the chip from cracking during the chip packaging process and improve the performance and reliability of the chip device.

[0005] One aspect of the present application provides a reinforcement ring for reducing the warpage of a substrate in a semiconductor packaging structure. The reinforcement ring is quasi-L-shaped and is disposed around the corners of a chip area of ​​the substrate and surrounds the corners of the chip area.

[0006] In some embodiments of the present application, the thermal expansion coefficient of the reinforcement ring is smaller than the thermal expansion coefficient of the substrate and larger than the thermal expansion coefficient of the chip.

[0007] In some embodiments of the present application, the thermal expansion coefficient of the reinforcement ring is 13×10 -6 Up to 14×10 -6 / degrees Celsius.

[0008] In some embodiments of the present application, the material of the reinforcement ring includes copper-nickel alloy.

[0009] In some embodiments of the present application, the reinforcement ring has a handle structure.

[0010] Another aspect of the present application provides a method for forming a semiconductor packaging structure, comprising: providing a substrate, the substrate comprising a chip area for packaging a chip; forming a reinforcement ring as described above on the substrate around the corner of the chip area to surround the corner of the chip area; and packaging the chip on the substrate in the chip area.

[0011] In some embodiments of the present application, a method for forming a reinforcement ring surrounding the corners of the chip area on a substrate around the corners of the chip area includes: applying glue around the corners of the chip area; and adhering the reinforcement ring to the substrate around the corners of the chip area by the glue.

[0012] In some embodiments of the present application, the method for forming the semiconductor package structure further includes: removing the reinforcement ring through the handle structure.

[0013] In some embodiments of the present application, the method for forming the semiconductor packaging structure further includes: forming a heat dissipation cover covering the chip area and the reinforcement ring on the substrate around the reinforcement ring.

[0014] Another aspect of the present application provides a semiconductor packaging structure, comprising: a substrate, the substrate comprising a chip area for packaging a chip; a reinforcement ring as described above, located on the substrate around the corner of the chip area and surrounding the corner of the chip area; and a chip, packaged on the substrate of the chip area.

[0015] In some embodiments of the present application, in the method for forming the semiconductor packaging structure, the reinforcement ring is adhered to the substrate around the corner of the chip area by glue.

[0016] In some embodiments of the present application, the semiconductor packaging structure further includes: a heat dissipation cover located on the substrate around the reinforcement ring and covering the chip area and the reinforcement ring.

[0017] The present application provides a reinforcement ring, a semiconductor packaging structure and a method for forming the same. The reinforcement ring is used to reduce the warping of a substrate, thereby protecting the chip from the stress caused by the warping of the substrate. The low dielectric constant material in the chip can be prevented from cracking during the chip packaging process, thereby improving the performance and reliability of the chip device. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The following figures describe in detail the exemplary embodiments disclosed in this application. The same reference numerals represent similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting, exemplary embodiments, and the drawings are only for the purpose of illustration and description, and are not intended to limit the scope of this application. Other embodiments may also accomplish the inventive intent in this application. It should be understood that the drawings are not drawn to scale.

[0019] in:

[0020] Figure 1 and Figure 2 This is a schematic diagram of the structure of the reinforcement ring described in the embodiment of the present application;

[0021] Figures 3 to 8 It is a structural schematic diagram of each step in the method for forming a semiconductor packaging structure described in an embodiment of the present application. DETAILED DESCRIPTION

[0022] The following description provides specific application scenarios and requirements of the present application, with the purpose of enabling those skilled in the art to make and use the content in the present application. It will be apparent to those skilled in the art that various local modifications to the disclosed embodiments are apparent, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present application. Therefore, the present application is not limited to the embodiments shown, but to the widest scope consistent with the claims.

[0023] The technical solution of the present invention is described in detail below in conjunction with the embodiments and drawings.

[0024] Figure 1 and Figure 2 This is a schematic diagram of the structure of the reinforcement ring described in the embodiment of the present application. Figure 1 is a top view, Figure 2 For along Figure 1 Longitudinal section along the dotted line XX.

[0025] The present application provides a reinforcement ring 100 for reducing the warpage of a substrate in a semiconductor packaging structure. Figure 1 As shown, the reinforcement ring 100 is in an “L” shape and is disposed around the corner of the chip area of ​​the substrate and surrounds the corner of the chip area.

[0026] Since the reinforcement ring 100 is to be disposed around the corners of the chip region of the substrate and surround the corners of the chip region, the shape and size of the reinforcement ring 100 need to match the shape and size of the corners of the chip region.

[0027] refer to Figure 1 As shown, in some embodiments of the present application, the side length d1 of the reinforcement ring 100 is 6 mm to 12 mm, for example, 7 mm, 8 mm, 9 mm, 10 mm or 11 mm, etc. In some embodiments of the present application, the width d2 of the reinforcement ring 100 is 1 mm to 2 mm, for example, 1.5 mm. The two sides of the reinforcement ring 100 may be equal in length.

[0028] refer to Figure 2 As shown, in some embodiments of the present application, the height H1 of the reinforcement ring 100 is 600 micrometers to 1000 micrometers, for example, 700 micrometers, 800 micrometers, or 900 micrometers, etc. The height of the reinforcement ring 100 is lower than the height of the chip.

[0029] In some embodiments of the present application, the material of the reinforcement ring 100 includes a copper-nickel alloy, such as copper-plated nickel, wherein the mass proportion of nickel is 5% to 20%, such as 7.5%, 10%, 12.5%, 15%, etc., and the mass proportion of copper is 80% to 95%. The thermal expansion coefficient of the material of the reinforcement ring 100 is 13×10 -6 Up to 14×10 -6 / degrees Celsius. The thermal expansion coefficient of the material of the reinforcement ring 100 is smaller than the thermal expansion coefficient of the substrate 100 (17×10 -6 -18×10 -6 / degrees Celsius), which is larger than the thermal expansion coefficient of the chip (9×10 -6 -10×10 -6 / degrees Celsius).

[0030] In the semiconductor packaging process, the substrate needs to be processed at a temperature of about 260 degrees Celsius, so the material of the reinforcing ring 100 needs to ensure that the substrate warps less than 15 microns at this temperature to avoid damage to the chip. The warpage refers to the height of the curved depression or bulge on the substrate surface.

[0031] Continue to refer Figure 1 and Figure 2 As shown, in some embodiments of the present application, the reinforcement ring 100 has a handle structure 110. Further, the handle structure 110 has a horizontal hollow layer 120 that penetrates the handle structure 110. The handle structure 110 facilitates the extraction of the reinforcement ring 100. For example, the reinforcement ring 100 can be easily extracted by using a clamping device to penetrate the hollow layer 120 of the handle structure 110. In order to ensure uniform force when extracting the reinforcement ring 100, the handle structure 110 is evenly distributed on the four sides of the upper surface of the reinforcement ring 100.

[0032] In some embodiments of the present application, the shape of the handle structure 110 is the same as that of the reinforcement ring 100, and the side length of the handle structure 110 may be equal to the side length of the reinforcement ring 100. The width of the handle structure 110 is 1 mm to 2 mm, for example, 1.5 mm. Figure 2 As shown, the height H2 of the handle structure 110 is 400 micrometers to 600 micrometers, for example, 500 micrometers.

[0033] In some embodiments of the present application, the material of the handle structure 110 is the same as that of the reinforcement ring 100 , such as copper-nickel alloy.

[0034] In the technical solution of the present application, after the reinforcement ring 100 is arranged around the corners of the chip area of ​​the substrate and surrounds the corners of the chip area, in the FCA step and other steps that require heating, the reinforcement ring 100 can reduce the warping of the substrate caused by thermal expansion, thereby reducing or avoiding the stress on the chip caused by the warping of the substrate, avoiding the rupture of the film layer in the chip, especially the low dielectric constant material layer, thereby improving the performance and reliability of the chip device.

[0035] The present application provides a reinforcement ring, which is used to reduce the warping of the substrate, thereby protecting the chip from the stress caused by the warping of the substrate. The low dielectric constant material in the chip can be prevented from cracking during the chip packaging process, thereby improving the performance and reliability of the chip device.

[0036] Figures 3 to 8 The following is a structural schematic diagram of each step in the method for forming a semiconductor package structure according to an embodiment of the present application. The method for forming a semiconductor package structure according to an embodiment of the present application is described in detail below in conjunction with the accompanying drawings.

[0037] refer to Figure 3 and Figure 4 As shown, Figure 3 is a top view, Figure 4 For along Figure 3 A longitudinal cross-sectional view at the dashed line XX. A substrate 200 is provided, wherein the substrate 200 comprises a chip region 210 for packaging a chip.

[0038] In some embodiments of the present application, the substrate 200 is an ABF substrate. The material of the substrate 200 includes organic composite materials, circuit copper, green paint, etc. The thermal expansion coefficient of the substrate 200 is about 17×10 -6 -18×10 -6 / degrees Celsius.

[0039] refer to Figures 5 to 7 As shown, the reinforcement ring 100 as described above is formed on the substrate 200 around the corner of the chip area 210 to surround the corner of the chip area 210 .

[0040] refer to Figure 5 As shown, glue 220 is applied around the corners of the chip area 210. The glue 220 is, for example, a silver paste material.

[0041] refer to Figure 6 and Figure 7 As shown, Figure 6 is a top view, Figure 7 For along Figure 6Longitudinal cross-sectional view at the dotted line XX. The reinforcement ring 100 is adhered to the substrate 200 around the corners of the chip area 210 by the glue 220. In the embodiment of the present application, the chip area 210 is square and has four corners, so four reinforcement rings 100 are adhered around the four corners of the chip area 210 respectively. The stress of the substrate is most severe at the chip corners, so the reinforcement ring 100 is arranged at the chip area corners to protect the chip to the greatest extent.

[0042] refer to Figure 6 As shown, in some embodiments of the present application, the distance W1 between the reinforcement ring 100 and the chip area 210 is greater than or equal to 1.5 mm.

[0043] refer to Figure 6 As shown, in some embodiments of the present application, the distance W2 between the reinforcement ring 100 and the edge of the substrate 200 is greater than or equal to 3 mm.

[0044] refer to Figure 8 As shown, a chip 230 is packaged on the substrate 200 in the chip area 210. The chip 230 is packaged by FCA process. The material of the chip 230 mainly includes semiconductor material silicon or low dielectric constant material silicon oxide, etc., and its thermal expansion coefficient is 9×10 -6 -10×10 -6 / degrees Celsius.

[0045] In the technical solution of the present application, due to the presence of the reinforcement ring 100, in the FCA process engineering, the warping of the substrate 200 caused by thermal expansion is reduced, and the chip 230 will not be damaged by the stress of the warping of the substrate 200, which can improve the performance and reliability of the chip 230.

[0046] In some embodiments of the present application, the method for forming the semiconductor packaging structure further includes: removing the reinforcement ring 100 through the handle structure 110. The semiconductor packaging process mainly includes the following steps: substrate preheating (substratebake), chip packaging (FCA), underfill, underfill cure, etc. Since the reinforcement ring 100 is used to reduce the warpage of the substrate 200 caused by thermal expansion, the reinforcement ring 100 needs to be set on the substrate before the substrate preheating (substrate bake) step. After the underfill cure (underfill cure) step, there is no longer a high-temperature heating step, so the reinforcement ring 100 can be removed after the underfill cure (underfill cure) step.

[0047] In some embodiments of the present application, the method for forming the semiconductor package structure further includes: forming a heat dissipation cover (not shown) covering the chip region 210 and the reinforcement ring 100 on the substrate 200 around the reinforcement ring 100. The height of the heat dissipation cover is at least 0.3 mm higher than the height of the reinforcement ring.

[0048] In the technical solution of the present application, the original sequence of steps of the semiconductor packaging process is not changed, and it is compatible with the traditional semiconductor packaging process. The steps of sticking and removing the reinforcement ring are relatively simple, and no new complex equipment and instruments are required, and the process is simple. Since the low dielectric constant material in the chip can be prevented from cracking, the use scenarios of the low dielectric constant material in the chip are increased, and the low dielectric constant material can be used in chips of larger sizes. Since reinforcement rings only need to be set at the corners of the chip area, the reinforcement rings can adapt to chips of various sizes, and chips of different sizes can use the same reinforcement ring.

[0049] The present application provides a method for forming a semiconductor packaging structure, which utilizes a reinforcement ring to reduce the warping of a substrate, thereby protecting the chip from the stress generated by the warping of the substrate. The low dielectric constant material in the chip can be prevented from cracking during the chip packaging process, thereby improving the performance and reliability of the chip device.

[0050] The present application also provides a semiconductor packaging structure, referring to Figure 8 As shown, it includes: a substrate 200, the substrate 200 includes a chip area for packaging a chip 230; the reinforcement ring 100 as described above, located on the substrate 200 around the corner of the chip area and surrounding the corner of the chip area; and a chip 230, packaged on the substrate 200 in the chip area.

[0051] In some embodiments of the present application, the reinforcement ring 100 is adhered to the substrate around the chip area by glue.

[0052] In some embodiments of the present application, the semiconductor packaging structure further includes: a heat dissipation cover (not shown in the figure) located on the substrate 200 around the reinforcement ring 100 and covering the chip area and the reinforcement ring.

[0053] The present application provides a reinforcement ring, a semiconductor packaging structure and a method for forming the same. The reinforcement ring is used to reduce the warping of a substrate, thereby protecting the chip from the stress caused by the warping of the substrate. The low dielectric constant material in the chip can be prevented from cracking during the chip packaging process, thereby improving the performance and reliability of the chip device.

[0054] The present application provides a reinforcement ring, a semiconductor packaging structure and a method for forming the same. The reinforcement ring is used to reduce the warping of a substrate, thereby protecting the chip from the stress caused by the warping of the substrate. The low dielectric constant material in the chip can be prevented from cracking during the chip packaging process, thereby improving the performance and reliability of the chip device.

[0055] In summary, after reading the contents of this application, those skilled in the art will appreciate that the aforementioned application contents may be presented only in an exemplary manner and may not be restrictive. Although not explicitly stated herein, those skilled in the art will appreciate that this application is intended to encompass various reasonable changes, improvements and modifications to the embodiments. These changes, improvements and modifications are within the spirit and scope of the exemplary embodiments of this application.

[0056] It should be understood that the term "and / or" used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to another element, or there can also be intermediate elements.

[0057] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it can be directly on the other element or there can be intervening elements. In contrast, the term "directly" means that there are no intervening elements. It should also be understood that the terms "comprising," "containing," "including," or "comprising," when used in this application document, indicate the presence of the recited features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof.

[0058] It should also be understood that although the terms first, second, third, etc. can be used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the teachings of the present application, the first element in some embodiments can be referred to as the second element in other embodiments. The same reference numerals or the same reference signs represent the same elements throughout the specification.

[0059] In addition, the present specification describes exemplary embodiments by reference to idealized exemplary cross-sectional views and / or plan views and / or stereograms. Therefore, differences from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are foreseeable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but should include deviations in shapes caused by, for example, manufacturing. For example, an etched region shown as a rectangle will typically have circular or curved features. Therefore, the region shown in the figure is schematic in nature, and its shape is not intended to illustrate the actual shape of the region of the device nor to limit the scope of the exemplary embodiments.

Claims

1. A reinforcement ring for reducing the warpage of a substrate in a semiconductor packaging structure, characterized in that: The reinforcement ring is in an "L" shape, and is disposed around the corners of the chip area of ​​the substrate and surrounds the corners of the chip area.

2. The reinforcement ring according to claim 1, characterized in that: The thermal expansion coefficient of the reinforcement ring is smaller than the thermal expansion coefficient of the substrate and larger than the thermal expansion coefficient of the chip.

3. The reinforcement ring according to claim 2, characterized in that: The thermal expansion coefficient of the reinforcement ring is 13×10 -6 Up to 14×10 -6 / degrees Celsius.

4. The reinforcement ring according to claim 3, characterized in that: The material of the reinforcement ring includes copper-nickel alloy.

5. The reinforcement ring according to claim 1, characterized in that: The reinforcement ring is provided with a handle structure.

6. A method for forming a semiconductor packaging structure, characterized in that: include: Providing a substrate, the substrate comprising a chip area for packaging a chip; forming a reinforcement ring as claimed in any one of claims 1 to 5 surrounding the corner of the chip area on the substrate around the corner of the chip area; The chip is packaged on the substrate in the chip area.

7. The method for forming a semiconductor package structure according to claim 6, wherein: The method of forming a reinforcement ring surrounding the corner of the chip area on the substrate around the corner of the chip area includes: Applying glue around the corners of the chip area; The reinforcement ring is adhered to the substrate around the corners of the chip area by the glue.

8. The method for forming a semiconductor package structure according to claim 6, wherein: Also includes: The reinforcement ring is removed by the handle structure.

9. The method for forming a semiconductor package structure according to claim 6, wherein: Also includes: A heat dissipation cover covering the chip area and the reinforcement ring is formed on the substrate around the reinforcement ring.

10. A semiconductor packaging structure, characterized in that: include: A substrate, the substrate comprising a chip area for packaging a chip; The reinforcement ring according to any one of claims 1 to 5, located on a substrate around the corner of the chip area and surrounding the corner of the chip area; The chip is packaged on the substrate in the chip area.

11. The semiconductor package structure according to claim 10, wherein: The reinforcement ring is adhered to the substrate around the corners of the chip area by glue.

12. The semiconductor package structure according to claim 10, wherein: Also includes: A heat dissipation cover covering the chip area and the reinforcement ring is disposed on the substrate around the reinforcement ring.

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