Semiconductor packaging structure

Abstract

A semiconductor package structure is provided. The semiconductor package structure includes: a substrate; a first semiconductor die on the substrate, having a first active surface and a first passive surface opposite to the first active surface, and electrically connected to the substrate through a first die pad disposed on the first active surface, the first semiconductor die including a first concave-convex structure on the first passive surface; a first adhesive layer between the first semiconductor die and the substrate and bonded to one of the first active surface and the first passive surface of the first semiconductor die; and a molding layer covering the first semiconductor die on the substrate and bonded to the other of the first active surface and the first passive surface of the first semiconductor die, where the first passive surface of the first semiconductor die is provided by the first concave-convex structure.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor packaging structure, and more particularly, to a packaging structure including a bare die having a concave-convex structure. Background Art

[0002] Generally, a bare chip with a predetermined function can be manufactured by performing a semiconductor process on a wafer, but the manufactured bare chip is easily damaged because its functional structure is exposed to the outside. In order to improve the stability and reliability of the bare chip, a semiconductor packaging technology has been proposed. The semiconductor packaging technology can protect the bare chip by placing the bare chip on a packaging substrate and forming a molding layer encapsulating the bare chip on the packaging substrate. In this case, the bare chip can be bonded to the packaging substrate using an adhesive layer, and can be electrically connected to the packaging substrate and electrically connected to the outside through the packaging substrate.

[0003] In the semiconductor packaging structure obtained by the above-mentioned semiconductor packaging technology, there may be a bonding interface between the bare die and other components (e.g., a molding layer and / or an adhesive layer). However, since the bare die may have a relatively smooth surface (e.g., a relatively smooth passive surface) due to some manufacturing processes (e.g., a thinning process), the bare die and other components (e.g., a molding layer and / or an adhesive layer) may have a reduced interface bonding force at the bonding interface therebetween. Such reduced interface bonding force may cause delamination to easily occur between the internal components of the semiconductor packaging structure (e.g., between the bare die and the molding layer, and / or between the bare die and the adhesive layer), so that the reliability of the semiconductor packaging structure may be reduced. Summary of the invention

[0004] The present disclosure provides a semiconductor package structure with improved reliability.

[0005] According to one aspect of the present disclosure, a semiconductor packaging structure includes: a substrate; a first semiconductor die, on the substrate, having a first active surface and a first passive surface opposite to the first active surface, and electrically connected to the substrate through a first die pad arranged on the first active surface, wherein the first semiconductor die includes a first concave-convex structure on the first passive surface; a first adhesive layer, between the first semiconductor die and the substrate, and bonded to one of the first active surface and the first passive surface of the first semiconductor die; and a molding layer, covering the first semiconductor die on the substrate, and bonded to the other of the first active surface and the first passive surface of the first semiconductor die, wherein the first passive surface of the first semiconductor die is provided by the first concave-convex structure.

[0006] In an embodiment, the mold layer may be bonded to the first active surface of the first semiconductor die, and the first adhesive layer may be embedded in the first concave-convex structure; or the first adhesive layer may be bonded to the first active surface of the first semiconductor die, and the mold layer may be embedded in the first concave-convex structure.

[0007] In an embodiment, the first semiconductor die may have a first thickness in a first direction perpendicular to the first active surface of the first semiconductor die, and a maximum thickness of the first concave-convex structure in the first direction may be less than or equal to 20% of the first thickness.

[0008] In an embodiment, the first concavo-convex structure may be composed of continuously distributed concave portions and convex portions, and the first passive surface of the first semiconductor die may have a surface roughness Rz greater than or equal to 500 nm due to the first concavo-convex structure.

[0009] In an embodiment, the first concavo-convex structure may be composed of continuously and alternately distributed concave portions and convex portions, and when viewed in a cross-sectional view, an inner bottom angle of the concave portion at a position where the concave portion meets an adjacent convex portion may be greater than 90°.

[0010] In an embodiment, the recess may have a polygonal, circular, or elliptical outer peripheral contour when viewed in a plan view.

[0011] In an embodiment, the recess may have a depth greater than or equal to 500 nm in a first direction perpendicular to the first active surface of the first semiconductor die when viewed in a cross-sectional view.

[0012] In an embodiment, the semiconductor package structure may further include: a second semiconductor die, disposed between the first semiconductor die and the substrate, having a second active surface and a second passive surface opposite to the second active surface, and electrically connected to at least one of the substrate and the first semiconductor die through a second die pad disposed on the second active surface; a second adhesive layer, between the second semiconductor die and the substrate, and bonded to one of the second active surface and the second passive surface of the second semiconductor die; a third die, disposed side by side with the second semiconductor die between the first semiconductor die and the substrate, and having a first surface and a second surface opposite to the first surface; and a third adhesive layer, between the third die and the substrate, and bonded to the second surface of the third die. The first adhesive layer may also be bonded to the other of the second active surface and the second passive surface of the second semiconductor die and the first surface of the third die. The molding layer may also surround the first semiconductor die, the second semiconductor die, and the third die on the substrate.

[0013] In an embodiment, the second semiconductor die may further include a second concave-convex structure on the second passive surface, and the second passive surface of the second semiconductor die may be provided by the second concave-convex structure. The first adhesive layer may be bonded to the second active surface of the second semiconductor die, and the second adhesive layer may be embedded in the second concave-convex structure.

[0014] In an embodiment, the third die may be a dummy die, and the third die may include a first dummy concave-convex structure arranged on the first surface and a second dummy concave-convex structure arranged on the second surface, the first surface and the second surface of the third die may be provided by the first dummy concave-convex structure and the second dummy concave-convex structure, respectively, and the first adhesive layer and the third adhesive layer may be respectively embedded in the first dummy concave-convex structure and the second dummy concave-convex structure.

[0015] In an embodiment, the third die may be a functional die, the second surface of the third die may be a passive surface of the third die, the third die may include a third concave-convex structure on the second surface, the second surface of the third die may be provided by the third concave-convex structure, and the third adhesive layer may be embedded in the third concave-convex structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above and other aspects and features will become more apparent from the following description of example embodiments with reference to the accompanying drawings.

[0017] Figure 1is a cross-sectional view schematically illustrating a semiconductor package structure according to example embodiments.

[0018] Figure 2 is a partially enlarged view schematically illustrating a semiconductor package structure according to example embodiments.

[0019] Figure 3A and Figure 3B 2 are a partial enlarged view and a partial plan view schematically illustrating a semiconductor package structure according to example embodiments, respectively.

[0020] Figure 4 is a cross-sectional view schematically illustrating a semiconductor package structure according to example embodiments.

[0021] Figure 5 is a cross-sectional view schematically illustrating a semiconductor package structure according to example embodiments.

[0022] Figure 6 is a cross-sectional view schematically illustrating a semiconductor package structure according to example embodiments.

[0023] Figure 7 is a cross-sectional view schematically illustrating a semiconductor package structure according to example embodiments. DETAILED DESCRIPTION

[0024] Example embodiments will be described more fully with reference to the accompanying drawings showing example embodiments. The embodiments described herein are provided as examples, and therefore, the present disclosure is not limited thereto, but may be implemented in various forms. Each embodiment provided in the following description does not exclude association with another example or another embodiment that is also provided herein or not provided herein but is consistent with the present disclosure. In the accompanying drawings, for clarity, various elements, components, layers, regions, etc. may not be drawn to scale. In the accompanying drawings, the same or similar reference numerals represent the same or similar components.

[0025] It will be understood that, although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. For example, a first element, component, region, layer or part described herein may be named as a second element, component, region, layer or part without departing from the scope of the present disclosure.

[0026] In this specification, when the term "about" is used in conjunction with a numerical value, it means that the associated numerical value may include tolerances or errors around the stated numerical value, such as those caused by manufacturing and / or measurement. In addition, when the words "generally" and "substantially" are used in conjunction with configurations and shapes, it means that the accuracy of the geometric shape is not required, but the tolerance of the shape is within the scope of the present disclosure. In addition, regardless of whether a numerical value or shape is modified as "about" or "substantially", it will be understood that these numerical values ​​and shapes should be interpreted as including manufacturing tolerances or measurement errors around the stated numerical values ​​or shapes.

[0027] Hereinafter, a semiconductor package structure and a method of manufacturing the same according to some example embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0028] Figure 1 is a cross-sectional view schematically illustrating a semiconductor package structure according to example embodiments. Figure 2 Schematically shows a partial enlarged view of a semiconductor package structure according to an example embodiment. Specifically, Figure 2 Schematically shows Figure 1 An enlarged view of an example of region R.

[0029] Reference Figure 1 The semiconductor package structure 100 according to example embodiments of the present disclosure may include a substrate 110 , a semiconductor die 120 on the substrate 110 , an adhesive layer 140 between the substrate 110 and the semiconductor die 120 , and a mold layer 160 covering the semiconductor die 120 on the substrate 110 .

[0030] The substrate 110 may be used as a packaging substrate of the semiconductor packaging structure 100, and a conductive path for signal transmission may be formed therein. The substrate 110 may be an inorganic substrate, an organic substrate, or an organic / inorganic composite substrate. The inorganic substrate may be a semiconductor substrate (such as a silicon substrate), a glass substrate, or a ceramic substrate. The organic substrate may be a plastic substrate. For example, the substrate 110 may be a printed circuit board or an interposer substrate. However, examples of the substrate 110 are not limited thereto. In some example embodiments, for example, the substrate 110 may also be a lead frame.

[0031] The substrate 110 may have a first surface 110t (e.g., an upper surface or top surface) and a second surface 110b (e.g., a lower surface or bottom surface) opposite to the first surface 110t. The first surface 110t and the second surface 110b may be opposite to each other in the thickness direction of the substrate 110. As used herein, the thickness direction of the substrate 110 may refer to a direction substantially perpendicular to the first surface 110t (e.g., an upper surface or top surface) and / or the second surface 110b (e.g., a lower surface or bottom surface) of the substrate 110.

[0032] The substrate 110 may include a substrate body 111, a substrate lower pad 112, and a substrate upper pad 113. The substrate lower pad 112 may be disposed on the substrate body 111 at the first surface 110t of the substrate 110. The substrate upper pad 113 may be disposed on the substrate body 111 at the second surface 110b of the substrate 110. For example, Figure 1 As shown in , the substrate lower pad 112 and the substrate upper pad 113 may be respectively disposed in the lower portion and the upper portion of the substrate body 111, and are respectively exposed from the second surface 110b and the first surface 110t of the substrate 110. However, example embodiments are not limited thereto. For example, in some example embodiments, the substrate lower pad 112 may also be partially disposed or not disposed in the substrate body 111, and partially or entirely protrude below the second surface 110b of the substrate 110. For example, in some example embodiments, the substrate upper pad 113 may also be partially disposed or not disposed in the substrate body 111, and partially or entirely protrude above the first surface 110t of the substrate 110.

[0033] The substrate lower pad 112 and the substrate upper pad 113 may be electrically connected to each other through a conductive path (not shown) inside the substrate 110. The substrate lower pad 112 and the substrate upper pad 113 may be formed of a conductive material (such as a metal and / or a conductive metal nitride). The conductive path inside the substrate 110 may be composed of conductive interconnects (such as a conductive line and a conductive via) formed in the substrate body 111, and may be electrically isolated and / or insulated from each other. The conductive interconnects may be formed of a conductive material (such as a metal and / or a conductive metal nitride).

[0034] The semiconductor die 120 may be disposed on the first surface 110t of the substrate 110. The semiconductor die 120 may be an unpackaged die obtained by a wafer-level semiconductor process. The semiconductor die 120 may be configured to implement a predetermined or set function (e.g., logic processing, data storage, etc.). For example, the semiconductor die 120 may be a logic die and / or a memory die. When the semiconductor die 120 is capable of performing a predetermined or set function, the semiconductor die 120 may be referred to as a functional die.

[0035] In addition, if Figure 1 As shown in , the semiconductor die 120 may have a first surface 120t (e.g., an upper surface or a top surface) and a second surface 120b (e.g., a lower surface or a bottom surface). The first surface 120t and the second surface 120b may be opposite to each other in a thickness direction of the semiconductor die 120. As used herein, the thickness direction of the semiconductor die 120 may refer to a direction substantially perpendicular to the first surface 120t (e.g., an upper surface or a top surface) and / or the second surface 120b (e.g., a lower surface or a bottom surface) of the semiconductor die 120.

[0036] Reference Figure 1 , the semiconductor die 120 may include a die body 121 and a die pad 122. The semiconductor die 120 may be electrically connected to the outside through the die pad 122, and therefore, the surface of the semiconductor die 120 provided with the die pad 122 may be referred to as an "active surface". The surface of the semiconductor die 120 opposite to the active surface may be referred to as an "inactive surface". For example, Figure 1 As shown in , the first surface 120t of the semiconductor die 120 can be an active surface, and the second surface 120b of the semiconductor die 120 can be referred to as a passive surface. However, example embodiments are not limited thereto. For example, depending on the manner in which the semiconductor die 120 is mounted to the substrate 110, the first surface 120t of the semiconductor die 120 (e.g., an upper surface or a top surface) can be one of the active surface and the passive surface of the semiconductor die 120, and the second surface 120b of the semiconductor die 120 (e.g., a lower surface or a bottom surface) can be the other of the active surface and the passive surface of the semiconductor die 120.

[0037] The die body 121 may include a semiconductor material (such as silicon, germanium, or silicon germanium). The die body 121 may have a circuit structure (also referred to as a functional circuit layer; not shown) formed therein for realizing a function. In some example embodiments, the circuit structure in the die body 121 may be formed of, for example, a transistor and an interconnection line, but is not limited thereto. In some example embodiments, the circuit structure may be formed in the die body 121 by a semiconductor process such as an implantation process, a deposition process, a mask process, an etching process, a planarization process, etc., but is not limited thereto. The circuit structure in the die body 121 may be connected to the die pad 122, and may be electrically connected to the outside through the die pad 122.

[0038] The die pad 122 may be disposed on an active surface of the semiconductor die 120. The die pad 122 may be formed of a conductive material such as a metal and / or a conductive metal nitride. Figure 1 As shown in , the die pad 122 may be disposed on the first surface 120t of the semiconductor die 120. For example, the die pad 122 may be disposed on the die body 121 at the first surface 120t of the semiconductor die 120. For example, the die pad 122 may be disposed in an upper portion of the die body 121 and exposed from the first surface 120t of the semiconductor die 120. However, example embodiments are not limited thereto. For example, in some example embodiments, the die pad 122 may be a portion of a redistribution layer (RDL) formed on the die body 121 at the first surface 120t of the semiconductor die 120. In this case, Figure 1 Different from what is shown in FIG. 1 , the die pad 122 may be partially or completely located outside the die body 121 .

[0039] Although not shown, in some example embodiments, on the active surface of the semiconductor die 120 (eg, Figure 1 A passivation layer may be further disposed on the first surface 120t in the semiconductor die 120. In this case, for electrical connection of the semiconductor die 120 to the outside, the die pad 122 may be exposed or protruded from the passivation layer. The passivation layer may be formed of an insulating material.

[0040] Reference Figure 1 The semiconductor package structure 100 may further include bonding wires 130 for wire bonding, and the semiconductor die 120 may be electrically connected to the substrate 110 by wire bonding. Figure 1 As shown in , the substrate pad 113 of the substrate 110 may be disposed in a region of the substrate 110 on which the semiconductor die 120 is not disposed, so as to facilitate connection to the bonding wire 130 .

[0041] The bonding wire 130 may be disposed between the die pad 122 and the substrate pad 113 and bonded to the die pad 122 and the substrate pad 113. The bonding wire 130 may be formed of a conductive material such as a metal such as Ag and Al. The semiconductor die 120 and the substrate 110 may be electrically connected to each other via the die pad 122, the bonding wire 130, and the substrate pad 113.

[0042] Reference Figure 1 , the adhesive layer 140 may be disposed between the semiconductor die 120 and the substrate 110 , and fix the semiconductor die 120 to the substrate 110 .

[0043] like Figure 1 As shown in , the adhesive layer 140 can be bonded to the second surface 120b (e.g., the lower surface or the bottom surface) of the semiconductor die 120, and at the same time bonded to the first surface 110t (e.g., the upper surface or the top surface) of the substrate 110 to fix the semiconductor die 120 on the substrate 110. The adhesive layer 140 can be formed of an adhesive material. For example, the adhesive layer 140 can include an epoxy-based material. For example, the adhesive layer 140 can be a die attach film (Die Attach Film, DAF).

[0044] exist Figure 1 In the semiconductor package structure 100 shown in FIG. 1 , the semiconductor die 120 is mounted on the substrate 110 by wire bonding, and therefore, the second surface 120 b (e.g., the inactive surface) of the semiconductor die 120 may face the substrate 110. In this case, the adhesive layer 140 may be bonded to the inactive surface of the semiconductor die 120 by contacting the inactive surface of the semiconductor die 120, thereby fixing the semiconductor die 120.

[0045] However, the passive surface of the semiconductor die 120 may be relatively smooth (for example, due to a thinning process such as chemical mechanical polishing, backside grinding, etc.), which may cause the semiconductor die 120 and the adhesive layer 140 to have a reduced interface bonding force at the bonding interface therebetween (for example, the passive surface of the semiconductor die 120). Such reduced interface bonding force may cause delamination between the adhesive layer 140 and the semiconductor die 120. The delamination between the adhesive layer 140 and the semiconductor die 120 may cause the reliability of the semiconductor package structure 100 to be reduced.

[0046] Refer again Figure 1 In the semiconductor package structure 100 according to the example embodiment of the present disclosure, the semiconductor die 120 may also include a semiconductor die 120 disposed on a passive surface (eg, Figure 1 The semiconductor die 120 may have a concave-convex structure 123 on the second surface 120b in the embodiment. Figure 1 The second surface 120b) in the embodiment is bonded to the adhesive layer 140 through the concavo-convex structure 123. Figure 1 and Figure 2 As shown in FIG. 1 , the second surface 120 b of the semiconductor die 120 may be provided by the concavo-convex structure 123 . For example, the second surface 120 b of the semiconductor die 120 may have a profile provided by the concavo-convex structure 123 .

[0047] Detailed reference Figure 2 The concavo-convex structure 123 may have a rough texture 123R consisting of concave portions and convex portions continuously distributed in a direction substantially parallel to the second surface 120b of the semiconductor die 120 (eg, a direction substantially perpendicular to the thickness direction of the semiconductor die 120). Figure 2 As shown in FIG. 1 , in the concavo-convex structure 123 (e.g., rough texture 123R), the concave portion may be a portion that is recessed toward the first surface 120t of the semiconductor die, and the convex portion may be a portion that protrudes away from the first surface 120t of the semiconductor die 120. When the concavo-convex structure 123 has the rough texture 123R, the second surface 120b of the semiconductor die 120 provided by the concavo-convex structure 123 may have a profile corresponding to the rough texture 123R. Therefore, the second surface 120b of the semiconductor die 120 may be rough or non-smooth. For example, the second surface 120b of the semiconductor die 120 may have a surface roughness Rz greater than or equal to about 500 nanometers (nm) by the concavo-convex structure 123.

[0048] The concavo-convex structure 123 may be formed at the second surface 120b of the semiconductor die 120 by various suitable processes. For example, the concavo-convex structure 123 may be formed by processes such as etching, sawing, plating, sputtering, or plasma treatment, but is not limited thereto. Etching may include dry etching, wet etching, laser etching, and the like. In some embodiments, the concavo-convex structure 123 may be formed after the thinning process of the semiconductor die 120. Therefore, the second surface 120b of the semiconductor die 120, which is originally relatively smooth due to, for example, the thinning process, may become rough due to the formed concavo-convex structure 123. In addition, after the thinning process of the semiconductor die 120, the process of forming the concavo-convex structure 123 may be performed before or after the slicing process of the semiconductor die 120.

[0049] In some example embodiments, the concavo-convex structure 123 may be irregular in shape. For example, the rough texture 123R of the concavo-convex structure 123 may be irregular. Figure 2 As shown in , the concave and convex portions constituting the rough texture 123R may have uneven sizes (e.g., depth / height, and / or width). In addition, although not shown, when viewed in a plan view, the concave and convex portions constituting the rough texture 123R may be randomly distributed in general. For example, when viewed in a plan view, the concave and convex portions constituting the rough texture 123R may be locally or in small amounts orderly distributed, and overall or in large amounts randomly distributed. In some example embodiments, a concave-convex structure 123 having an irregular shape may be formed by selecting a forming process. For example, when the concave-convex structure 123 is formed by performing wet etching (e.g., chemical etching), dry etching, or laser etching under appropriate conditions, the concave-convex structure 123 may be formed to have an irregular shape.

[0050] exist Figure 2 In the example shown in , the concavo-convex structure 123 may be disposed in the die body 121. For example, the concavo-convex structure 123 may be a part of the die body 121. For example, the concavo-convex structure 123 may be a part of the die body 121 adjacent to the second surface 120b. For example, when the concavo-convex structure 123 is formed by performing a process (e.g., etching or plasma treatment) of removing a part of the die body 121 at the second surface 120b of the semiconductor die 120, the concavo-convex structure 123 may be formed as a part of the die body 121. However, example embodiments are not limited thereto. In some example embodiments, the concavo-convex structure 123 may be a separate component bonded to the die body 121. For example, the concavo-convex structure 123 may be formed by plating or sputtering a suitable material (e.g., an inorganic insulating material) on the die body 121.

[0051] like Figure 2As shown in , the concavo-convex structure 123 may have a maximum thickness h in the thickness direction of the semiconductor die 120. The maximum thickness h of the concavo-convex structure 123 may be a height difference between the highest point (e.g., the valley bottom point of the deepest concave portion of the concavo-convex structure 123) and the lowest point (e.g., the peak top surface of the highest convex portion of the concavo-convex structure 123) of the concavo-convex structure 123 in the thickness direction of the semiconductor die 120. In some example embodiments, the maximum thickness h of the concavo-convex structure 123 may be less than or equal to about 20% of the thickness H of the semiconductor die 120.

[0052] In addition, it should be understood that although the concavo-convex structure 123 having the maximum thickness h is Figure 2 The rough texture 123R is shown to include a portion (e.g., another portion of the die body 121 adjacent to the concavo-convex structure 123), but this is only for the convenience of illustration and description. As described above, the concavo-convex structure 123 is formed along the passive surface (e.g., Figure 1 and Figure 2 The second surface 120b) is formed by distributed concave and convex portions.

[0053] Refer again Figure 1 and Figure 2 , the semiconductor die 120 can be bonded to the adhesive layer 140 at the second surface 120b through the concavo-convex structure 123. As described above, the originally relatively smooth second surface 120b of the semiconductor die 120 can be rough or non-smooth due to the concavo-convex structure 123, so that the second surface 120b of the semiconductor die 120 can have an increased surface area. Therefore, the semiconductor die 120 and the adhesive layer 140 can contact each other with an increased area. Therefore, the interfacial bonding force between the semiconductor die 120 and the adhesive layer 140 can be increased, thereby reducing the risk of delamination between the semiconductor die 120 and the adhesive layer 140. Therefore, the reliability of the semiconductor package structure 100 can be improved.

[0054] In addition, when the semiconductor die 120 is bonded to the adhesive layer 140 through the concavo-convex structure 123, the adhesive layer 140 may be embedded in the concavo-convex structure 123. Figure 2As shown in , a portion of the adhesive layer 140 can extend into the concave portion of the rough texture 123R of the concave-convex structure 123, and at the same time, the convex portion of the rough texture 123R of the concave-convex structure 123 can extend into the adhesive layer 140, so that the semiconductor die 120 and the adhesive layer 140 can form a physical fit at their bonding interface (for example, the second surface 120b of the semiconductor die 120) and generate a mechanical bite force. The generated mechanical bite force can further increase the interfacial bonding force between the semiconductor die 120 and the adhesive layer 140, thereby further reducing the risk of delamination between the semiconductor die 120 and the adhesive layer 140. Therefore, the reliability of the semiconductor package structure 100 can be further improved.

[0055] In some example embodiments, as described above, the concavo-convex structure 123 may be in an irregular shape. In this case, the semiconductor die 120 and the adhesive layer 140 may form a more complex physical fit through the concavo-convex structure 123 having an irregular shape, and the semiconductor die 120 and the adhesive layer 140 may generate a more complexly distributed mechanical bite force at the bonding interface through a more complex physical fit. In this way, the bonding interface between the semiconductor die 120 and the adhesive layer 140 may better resist complex forces (e.g., forces such as compressive stress and / or tensile stress due to factors such as external impact, differences in thermal expansion coefficients, etc.). Therefore, the risk of delamination between the semiconductor die 120 and the adhesive layer 140 may be further reduced. Therefore, the reliability of the semiconductor package structure 100 may be further improved.

[0056] Refer again Figure 1 , a molding layer 160 may be disposed on the substrate 110 to encapsulate the semiconductor die 120. The molding layer 160 may be formed of a molding material (eg, epoxy molding compound).

[0057] The mold layer 160 may cover the semiconductor die 120 on the substrate 110. For example, the mold layer 160 may be disposed on the first surface 120t of the semiconductor die 120. For example, the mold layer 160 may contact the first surface 120t of the semiconductor die 120.

[0058] The mold layer 160 may also cover a portion of the substrate 110 where the semiconductor die 120 is not disposed. For example, the mold layer 160 may also be disposed on a portion of the substrate 110 where the semiconductor die 120 is not disposed. For example, the mold layer 160 may also be in contact with a portion of the substrate 110 where the semiconductor die 120 is not disposed.

[0059] The portion of the mold layer 160 in contact with the substrate 110 may also surround the semiconductor die 120. For example, the portion of the mold layer 160 in contact with the substrate 110 may also contact the side surface of the semiconductor die 120. The portion of the mold layer 160 in contact with the substrate 110 may also surround the adhesive layer 140. For example, the portion of the mold layer 160 in contact with the substrate 110 may also contact the side surface of the adhesive layer 140. Therefore, the mold layer 160 may encapsulate both the semiconductor die 120 and the adhesive layer 140.

[0060] When the semiconductor package structure 100 includes the bonding wires 130 , the mold layer 160 may further surround and cover the bonding wires 130 . That is, the mold layer 160 may further encapsulate the bonding wires 130 .

[0061] Refer again Figure 1 , the semiconductor package structure 100 may further include an external connection terminal 150. The external connection terminal 150 may be disposed below the substrate 110 and electrically connected to the substrate 110. For example, the external connection terminal 150 may be respectively bonded to the substrate underpad 112 of the substrate 110. The external connection terminal 150 may be used to electrically connect the semiconductor package structure 100 to the outside. That is, the semiconductor package structure 100 may use the external connection terminal 150 as an interface terminal to electrically connect to the outside. The external connection terminal 150 may be formed of a conductive material such as a metal or an alloy. In some example embodiments, the external connection terminal 150 may be a solder ball or a conductive bump.

[0062] Figure 3A and Figure 3B 1 and 2 are schematic diagrams of a partial enlarged view and a partial plan view of a semiconductor package structure according to an example embodiment. Figure 3A Schematically shows Figure 1 An enlarged view of an example of region R, and Figure 3B It is along Figure 3A Schematic plan view taken along line II'.

[0063] In addition to the concave-convex structure 123' being composed of concave portions 123G and convex portions 123P having specific shapes and / or distributions, Figure 3A and Figure 3B The semiconductor packaging structure can be Figure 1 and Figure 2 Therefore, the description of the same or similar components will be omitted or simplified below, and reference will be made to Figure 1 and Figure 2 Descriptions of the same or similar components may be equally or similarly applied to Figure 3A and Figure 3B Example embodiments of the present invention.

[0064] Reference Figure 3A and Figure 3B The semiconductor package structure according to an example embodiment of the present disclosure may include a semiconductor die 120 having an inactive surface (eg, Figure 3A The concavo-convex structure 123' on the second surface 120b).

[0065] The concave-convex structure 123' may be composed of concave portions 123G and convex portions 123P that are continuously and alternately distributed. For example, the concave-convex structure 123' may be composed of a plurality of concave portions 123G and a plurality of convex portions 123P, and the plurality of concave portions 123G and the plurality of convex portions 123P may be arranged along the passive surface (e.g., Figure 3A In some example embodiments, the concave-convex structure 123' may be a part of the die body 121 of the semiconductor die 120. For example, Figure 3A As shown in FIG. 1 , the concave-convex structure 123 ′ may be a portion of the die body 121 adjacent to the second surface 120 b. In some example embodiments, the concave-convex structure 123 ′ may be a portion of the die body 121 adjacent to the second surface 120 b. Figure 3A An additional structure is formed on the die body 121 at the second surface 120b in FIG.

[0066] like Figure 3A As shown in, in the concave-convex structure 123', the concave portion 123G may be a portion that is recessed toward the first surface 120t of the semiconductor die, and the convex portion 123P may be a portion that protrudes away from the first surface 120t of the semiconductor die 120. The concave portions 123G adjacent to each other may be spaced apart by the convex portion 123P between them, and the convex portions 123P adjacent to each other may be spaced apart by the concave portion 123G between them. In other words, in the concave-convex structure 123', the concave portions 123G and the convex portions 123P adjacent to each other may intersect with each other. As used herein, the term "intersection" may refer to being adjacent to each other at a side surface or side wall, or sharing a side surface or side wall with each other. When the concave portions 123G and the convex portions 123P adjacent to each other are described as intersecting with each other, the inner side surface or inner side wall of the concave portion 123G and the outer side surface or outer side wall of the convex portion 123P may be the same side surface or side wall.

[0067] The concave portion 123G and the convex portion 123P of the concave-convex structure 123' may have a specific regular shape. Figure 3A In the cross-sectional view shown in FIG. 1 , the concave portion 123G may have a shape whose width decreases toward the first surface 120t of the semiconductor die 120, and the convex portion 123P may have a shape whose width increases toward the first surface 120t of the semiconductor die 120. For example, Figure 3AAs shown in , the cross-sectional shape of the concave portion 123G and the convex portion 123P may be a trapezoid. In some example embodiments, according to the process of forming the concave-convex structure 123', the cross-sectional shape of the concave portion 123G and the convex portion 123P may also be a shape approximating a trapezoid. For example, the cross-sectional shape of the concave portion 123G may be bowl-shaped, and the cross-sectional shape of the convex portion 123P may be an inverted hump-shaped. In some example embodiments, the concave portion 123G may have a depth greater than or equal to about 500nm. For example, the depth of the concave portion 123G may be the valley depth of the concave portion 123G in the cross section in the thickness direction of the semiconductor die 120.

[0068] The passive surface of the semiconductor die 120 (eg, Figure 3A The second surface 120b) in the embodiment may be provided by a concave-convex structure 123' including concave portions 123G and convex portions 123P. Figure 3A As shown in , the second surface 120b of the semiconductor die 120 may include an inner portion 120bI provided by the concave portion 123G of the concave-convex structure 123', an outer portion 120bO provided by the convex portion 123P of the concave-convex structure 123', and a side portion 120bS provided by the sidewall of the concave portion 123G or the convex portion 123P, wherein the side portion 120bS may be between the inner portion 120bI and the outer portion 120bO and connect the inner portion 120bI and the outer portion bO. Since the concave portion 123G and the convex portion 123P of the concave-convex structure 123 are continuously and alternately distributed, the outer portion 120bO, the side portion 120bS and the inner portion 120bI of the second surface 120b of the semiconductor die 120 may be continuously and repeatedly distributed, so that the second surface 120b of the semiconductor die 120 may be uneven or non-smooth.

[0069] In some example embodiments, in the concavo-convex structure 123', the inner bottom angle of the concave portion 123G at the position where it meets the adjacent convex portion 123P is α In other words, in the second surface 120b of the semiconductor die 120, the angle formed between the inner portion 120bI and the side portion 120bS of the second surface 120b may be greater than 90°. α When the angle is greater than 90°, the adhesive layer 140 to be bonded to the semiconductor die 120 may be facilitated to fill the recess 123G, thereby maximizing the area of ​​the semiconductor die 120 in contact with the adhesive layer 140 through the concavo-convex structure 123 ′.

[0070] In addition, if Figure 3AAs shown in , the concavo-convex structure 123' may have a maximum thickness h' in the thickness direction of the semiconductor die 120. The maximum thickness h' of the concavo-convex structure 123' may be the height difference between the highest point (e.g., the valley bottom point of the concave portion 123G) and the lowest point (e.g., the peak top surface of the convex portion 123P) of the concavo-convex structure 123 in the thickness direction of the semiconductor die 120. For example, the maximum thickness h' of the concavo-convex structure 123' may correspond to the height difference between the inner portion 120bI and the outer portion 120bO of the second surface 120b of the semiconductor die 120 in the thickness direction of the semiconductor die 120. In some example embodiments, the maximum thickness h' of the concavo-convex structure 123' may also correspond to the maximum depth of the depth of the concave portion 123G in the thickness direction of the semiconductor die 120. In some example embodiments, the maximum thickness h' of the concavo-convex structure 123' may be less than or equal to about 20% of the thickness H' of the semiconductor die 120.

[0071] As described above, the second surface 120b of the semiconductor die 120 provided by the concavo-convex structure 123' may be uneven or non-smooth, and the semiconductor die 120 may be bonded to the adhesive layer 140 at the second surface 120b through the concavo-convex structure 123'. Therefore, the semiconductor die 120 may contact the adhesive layer 140 with an increased area, so that the interface bonding force between the semiconductor die 120 and the adhesive layer 140 may be increased, thereby reducing the risk of delamination between the semiconductor die and the adhesive layer 140. Therefore, the reliability of the semiconductor package structure may be improved.

[0072] In addition, if Figure 3A As shown in FIG. 1 , a portion of the concave-convex structure 123′ of the semiconductor die 120 (e.g., the convex portion 123P) may extend into the adhesive layer 140, and a portion of the adhesive layer 140 may extend into a portion of the concave-convex structure 123′ of the semiconductor die 120 (e.g., the concave portion 123G). Therefore, the semiconductor die 120 and the adhesive layer 140 may be bonded at their bonding interface (e.g., Figure 3A The second surface 120b in the semiconductor die 120 is physically embedded and generates a mechanical bite force, so that the interface bonding force between the semiconductor die 120 and the adhesive layer 140 is further increased, thereby further reducing the risk of delamination between the semiconductor die 120 and the adhesive layer 140. Therefore, the reliability of the semiconductor package structure can be further improved.

[0073] Reference Figure 3B In some example embodiments, the plurality of concave portions 123G may be arranged in a matrix form in a plan view. However, example embodiments are not limited thereto. For example, according to a specific process and process conditions for forming the concave-convex structure 123', the plurality of concave portions 123G may be arranged in any appropriate form in a plan view.

[0074] In addition, in the concavo-convex structure 123', the convex portion 123P may surround the plurality of concave portions 123G in a plan view and extend continuously. Figure 3B As shown in , adjacent concave portions 123G may be spaced apart from each other by convex portions 123P, and each concave portion 123G may be adjacent to the convex portion 123P surrounding it. Figure 3B As shown in , the concave portion 123G and the convex portion 123P of the concave-convex structure 123 ′ may be complementary in shape at the position where they abut or meet.

[0075] The outer periphery of the concave portion 123G of the concave-convex structure 123' may have a specific regular shape. For example, when viewed in a plan view, the concave portion 123G may have a polygonal, circular, or elliptical outer periphery. Figure 3B In the example shown in FIG. 1 , the recess 123G may have a hexagonal (e.g., regular hexagonal) outer peripheral profile. When the recess 123G has a circular or elliptical outer peripheral profile in a plan view, the adhesive layer 140 may be more easily filled into the recess 123G, thereby more effectively ensuring an increased contact area between the adhesive layer 140 and the semiconductor die 120. When the recess 123G has a polygonal outer peripheral profile in a plan view, the adhesive layer 140 may be interlocked with the recess 123G and the convex portion 123P of the concave-convex structure 123' in a more complex form, so that the mechanical bite force generated by the physical interlocking between the adhesive layer 140 and the semiconductor die 120 may be further increased, thereby further increasing the interface bonding force between the adhesive layer 140 and the semiconductor die 120.

[0076] In some example embodiments, the reference may be formed by etching, plating, cutting, etc. Figure 3A and Figure 3B The concavo-convex structure 123' of the semiconductor die 120 described above. For example, the concavo-convex structure 123' can be formed in the portion of the die body 121 of the semiconductor die 120 that is adjacent to the passive surface (e.g., the second surface 120b) by anisotropic etching. According to appropriate selection of process types and process conditions, the concavo-convex structure 123' and its concave portion 123G and convex portion 123P can be formed to have the configuration and / or arrangement as described above.

[0077] Figure 4 is a cross-sectional view schematically illustrating a semiconductor package structure according to example embodiments.

[0078] In addition to the semiconductor die 120' being mounted to the substrate 110 by a flip chip method through the connection member 130', and the first surface 120t' of the semiconductor die 120' being an inactive surface and bonded to the molding layer 160, Figure 4 The semiconductor package structure 100a can be compared with the reference Figure 1 and Figure 2 The semiconductor package structure 100 described and / or referring to Figure 3A and Figure 3B Therefore, the description of the same or similar components will be omitted or simplified below, and reference will be made to Figures 1 to 3B Descriptions of the same or similar components may be equally or similarly applied to Figure 4 Example embodiments of the present invention.

[0079] Reference Figure 4 , the semiconductor package structure 100a according to the example embodiment of the present disclosure may include a substrate 110, a semiconductor die 120' on the substrate 110, an adhesive layer 140' between the substrate 110 and the semiconductor die 120', and a mold layer 160 covering the semiconductor die 120' on the substrate 110. In addition, the semiconductor package structure 100a may further include a connection member 130' between the substrate 110 and the semiconductor die 120'. In addition, the semiconductor package structure 100a may further include an external connection terminal 150 for electrically connecting the semiconductor package structure 100a to the outside.

[0080] The semiconductor die 120' may be mounted on the substrate 110 by a flip chip method. Figure 4 As shown in , the second surface 120b' (e.g., the lower surface or bottom surface) of the semiconductor die 120' may be an active surface of the semiconductor die 120' on which a die pad (not shown) is disposed, and the first surface 120t' (e.g., the upper surface or top surface) of the semiconductor die 120' may be an inactive surface of the semiconductor die 120' opposite to the active surface. That is, in Figure 4 In the semiconductor package structure 100 a shown in FIG. 1 , an active surface (eg, second surface 120 b ′) of the semiconductor die 120 ′ may face the substrate 110 , and an inactive surface (eg, first surface 120 t ′) of the semiconductor die 120 ′ may face the molding layer 160 .

[0081] When the semiconductor die 120' is mounted by a flip chip method, Figure 4 As shown in , the substrate pads 113 ′ of the substrate 110 may be disposed in a region of the substrate 110 on which the semiconductor die 120 ′ is disposed to overlap and align with the die pads of the semiconductor die 120 , respectively.

[0082] The connection member 130' may be disposed between the semiconductor die 120' and the substrate 110. The connection member 130' may be connected between a die pad of the semiconductor die 120' and a substrate pad 113' of the substrate 110. The semiconductor die 120' and the substrate 110 may be electrically connected to each other through the connection member 130'. The connection member 130' may be formed of a conductive material such as a metal, an alloy, and a conductive metal nitride. In some example embodiments, the connection member 130' may be a solder ball or a conductive bump.

[0083] The adhesive layer 140' may be disposed between the semiconductor die 120' and the substrate 110. The adhesive layer 140' may surround the connection member 130'. For example, the adhesive layer 140' may fill the remaining space between the semiconductor die 120' and the substrate 110 except for the connection member 130'. In addition, the adhesive layer 140' may be bonded to the second surface 120b' of the semiconductor die 120'. In addition, the adhesive layer 140' may be bonded to the first surface 110t of the substrate 110. In some example embodiments, the adhesive layer 140' may include an under-fill or an epoxy resin.

[0084] The mold layer 160 may cover the first surface 120t' of the semiconductor die 120'. The mold layer 160 may be bonded to the first surface 120t' of the semiconductor die 120'. Figure 4 In the semiconductor package structure 100 a , the mold layer 160 may be bonded to the first surface 120 t ′ of the semiconductor die 120 ′ as an inactive surface.

[0085] However, since the passive surface of the semiconductor die 120' is generally relatively smooth after undergoing a thinning process, for example, the semiconductor die 120' and the mold layer 160 may have reduced interfacial bonding force at the bonding interface therebetween (for example, the first surface 120t' of the semiconductor die 120 as the passive surface). Such reduced interfacial bonding force may cause delamination between the mold layer 160 and the semiconductor die 120'. Delamination between the mold layer 160 and the semiconductor die 120' may cause a reduction in the reliability of the semiconductor package structure 100a.

[0086] In the semiconductor package structure 100a according to the exemplary embodiment of the present disclosure, as shown in FIG. Figure 4 As shown in FIG. , semiconductor die 120 ′ may include a passive surface (eg, Figure 4For example, in some example embodiments, the concavo-convex structure 123" may be a portion of the die body 121' of the semiconductor die 120' that is adjacent to the first surface 120t'. For example, in some example embodiments, the concavo-convex structure 123" may be a separate component disposed on the die body 121' at the first surface 120t' of the semiconductor die 120'. Figure 4 The specific structure and formation method of the concave-convex structure 123'' can be referred to in Figure 1 and Figure 2 The concave-convex structure 123 described and reference Figure 3A and Figure 3B Any of the described concavo-convex structures 123 ′ are substantially the same, and thus, redundant descriptions thereof are omitted herein.

[0087] like Figure 4 As shown in , the first surface 120t' of the semiconductor die 120', which is a passive surface, can be provided by the concavo-convex structure 123". Therefore, the semiconductor die 120' can be bonded to the mold layer 160 at the first surface 120t' through the concavo-convex structure 123", and the mold layer 160 can be embedded in the concavo-convex structure 123" of the semiconductor die 120'. In this way, the interface bonding force between the semiconductor die 120' and the mold layer 160 can be increased, thereby reducing the risk of delamination between the semiconductor die 120' and the mold layer 160. Therefore, the reliability of the semiconductor package structure 100a can be improved.

[0088] Figure 5 is a cross-sectional view schematically illustrating a semiconductor package structure according to example embodiments.

[0089] In addition to the second semiconductor die 270 and the dummy die 280 being disposed between the first semiconductor die 220 and the substrate 210, Figure 5 The semiconductor package structure 200 can be compared with the reference Figures 1 to 3B Therefore, the description of the same or similar components will be omitted or simplified below, and reference will be made to Figures 1 to 3B Descriptions of the same or similar components may be equally or similarly applied to Figure 4 Example embodiments of the present invention.

[0090] Reference Figure 5The semiconductor package structure 200 may include a substrate 210, a first semiconductor die 220 on the substrate 210, a second semiconductor die 270 and a dummy die 280 between the first semiconductor die 220 and the substrate 210, a first adhesive layer 240A between the first semiconductor die 220 and the second semiconductor die 270 and the dummy die 280, a second adhesive layer 240B between the second semiconductor die 270 and the substrate 210, a third adhesive layer 240C between the dummy die 280 and the substrate 210, and a molding layer 260 encapsulating the first semiconductor die 220, the second semiconductor die 270 and the dummy die 280 on the substrate 210. Figure 5 As shown in FIG. 2 , the mold layer 260 may surround the first semiconductor die 220, the second semiconductor die 270, and the dummy die 280 on the substrate 210. In addition, the semiconductor package structure 200 may further include an external connection terminal 250 for electrically connecting the semiconductor package structure 200 to the outside.

[0091] The substrate 210 may have a first surface 210t (e.g., an upper surface and a top surface) and a second surface 210b (e.g., a lower surface and a bottom surface) opposite to the first surface 210t. The substrate 210 may include a substrate body 211, a substrate lower pad 212 disposed on the substrate body 211 at the second surface 210b, and a substrate upper pad 213 disposed on the substrate body 211 at the first surface 210t. The substrate lower pad 212 and the substrate upper pad 213 may be electrically connected through a conductive path (not shown) inside the substrate body 211. The substrate 210 may be connected to a reference Figure 1 The substrate 110 described above is substantially the same or similar in shape. The external connection terminal 250 may be below the substrate 210 and electrically connected to the substrate underpad 212. The external connection terminal 250 may be similar to the substrate 110 described above. Figure 1 The described external connection terminals 150 are substantially the same or similar.

[0092] The first semiconductor die 220 may be disposed on the substrate 210. The first semiconductor die 220 may have a first surface 220t and a second surface 220b opposite to the first surface 220t. The first semiconductor die 220 may include a first die body 221, a first die pad 222 on an active surface (i.e., first active surface) of the first semiconductor die 220, and a first concavo-convex structure 223 on an inactive surface (i.e., first inactive surface) of the first semiconductor die 220. The first inactive surface of the first semiconductor die 220 may be provided by the first concavo-convex structure 223. In some example embodiments, the first semiconductor die 220 may be a memory die.

[0093] The second semiconductor die 270 may be disposed on the substrate 210 (e.g., on the first surface 210t of the substrate 210). The second semiconductor die 270 may be disposed in the space between the first semiconductor die 220 and the substrate 210. The second semiconductor die 270 may have a first surface 270t and a second surface 270b opposite to the first surface 270t. The second semiconductor die 270 may include a second die body 271, a second die pad 272 on the active surface (i.e., the second active surface) of the second semiconductor die 270, and a second concave-convex structure 273 on the passive surface (i.e., the second passive surface) of the second semiconductor die 270. The second passive surface of the second semiconductor die 270 may be provided by the second concave-convex structure 273. In example embodiments, the second semiconductor die 270 may be a logic die.

[0094] The first semiconductor die 220 may be fixed on the second semiconductor die 270 by a first adhesive layer 240A between the first semiconductor die 220 and the second semiconductor die 270. The first adhesive layer 240A may be bonded to the second surface 220b of the first semiconductor die 220 and simultaneously bonded to the first surface 270t of the second semiconductor die 270 to fix the first semiconductor die 220 on the second semiconductor die 270.

[0095] The second semiconductor die 270 may be fixed on the substrate 210 by a second adhesive layer 240B between the second semiconductor die 270 and the substrate 210. The second adhesive layer 240B may be bonded to the second surface 270b of the second semiconductor die 270 and simultaneously bonded to the first surface 210t of the substrate 210 to fix the second semiconductor die 270 on the substrate 210.

[0096] Figure 5 The specific configuration and formation method of the first concavo-convex structure 223 and the second concavo-convex structure 273 shown in FIG. Figure 1 and Figure 2 The concave-convex structure 123 described or reference Figure 3A and Figure 3B Any of the described concavo-convex structures 123 ′ are substantially the same or similar, and therefore, redundant descriptions thereof are omitted herein.

[0097] Figure 5An example is shown in which both the first semiconductor die 220 and the second semiconductor die 270 are mounted to the substrate 210 by wire bonding. In such an example, the first semiconductor die 220 may be electrically connected to the substrate 210 by a first bonding wire 230A disposed between the first die pad 222 and the substrate upper pad 213, and the second semiconductor die 270 may be electrically connected to the substrate 210 by a second bonding wire 230B disposed between the second die pad 272 and the substrate upper pad 213. Furthermore, in some example embodiments, the second semiconductor die 270 may also be electrically connected to the first semiconductor die 220 via the substrate 210. Furthermore, although Figure 5 An example is shown in which the first semiconductor die 220 is electrically connected to the substrate 210 through the first bonding wire 230A and is electrically connected to the second semiconductor die 270 via the substrate 210, but example embodiments are not limited thereto. For example, in some example embodiments, the first semiconductor die 220 may be electrically connected to the substrate 210 and the second semiconductor die 270 through separate bonding wires, respectively, or the first semiconductor die 220 may be connected to the second semiconductor die 270 only through the bonding wires without being connected to the substrate 210.

[0098] In the case where the first semiconductor die 220 and the second semiconductor die 270 are provided by wire bonding, Figure 5 As shown in , the first surface 220t and the second surface 220b of the first semiconductor die 220 may be the first active surface and the first passive surface of the first semiconductor die 220, respectively, and the first surface 270t and the second surface 270b of the second semiconductor die 270 may be the second active surface and the second passive surface of the second semiconductor die 270, respectively. In this way, the first semiconductor die 220 may contact the first adhesive layer 240A through the first concavo-convex structure 223 at the second surface 220b as the passive surface, and the first adhesive layer 240A may be embedded in the first concavo-convex structure 223 of the first semiconductor die 220, so that the first semiconductor die 220 and the first adhesive layer 240A may be bonded to each other with an increased interface bonding force. In addition, the second semiconductor die 270 can contact the second adhesive layer 240B through the second concave-convex structure 273 at the second surface 270b as the passive surface, and the second adhesive layer 240B can be embedded in the second concave-convex structure 273 of the second semiconductor die 270, so that the second semiconductor die 270 and the second adhesive layer 240B can be combined with each other with an increased interface bonding force. Therefore, the risk of delamination between the first semiconductor die 220 and the first adhesive layer 240A and / or between the second semiconductor die 270 and the second adhesive layer 240B can be reduced. Therefore, the reliability of the semiconductor package structure 200 can be improved.

[0099] The dummy die 280 may be disposed on the substrate 210 (e.g., on the first surface 210t of the substrate 210). The dummy die 280 may be disposed in the space between the first semiconductor die 220 and the substrate 210. The dummy die 280 and the second semiconductor die 270 may be disposed side by side in the space between the first semiconductor die 220 and the substrate 210. The dummy die 280 may be used as a support to improve the structural stability of the semiconductor package structure 200 (including the second semiconductor die 270 and the first semiconductor die 220 stacked on the second semiconductor die 270). For example, Figure 5 As shown in FIG. 2 , the dummy die 280 may support the first semiconductor die 220 on the substrate 210 to prevent the first semiconductor die 220 disposed on the second semiconductor die 270 from partially overhanging.

[0100] The dummy die 280 may have a first surface 280 t (e.g., an upper surface or top surface) and a second surface 280 b (e.g., a lower surface or bottom surface) opposite to the first surface 280 t. The dummy die 280 may be opposite to each other in a thickness direction of the dummy die 280. As used herein, the thickness direction of the dummy die 280 may be substantially perpendicular to the first surface 280 t (e.g., an upper surface or top surface) and / or the second surface 280 b (e.g., a lower surface or bottom surface) of the dummy die 280.

[0101] like Figure 5 As shown in FIG. 2 , the first adhesive layer 240A may also be disposed between the first semiconductor die 220 and the dummy die 280 on the second surface 220b of the first semiconductor die 220. The first adhesive layer 280A between the first semiconductor die 220 and the dummy die 280 may contact and bond to the second surface 220b of the first semiconductor die 220, and simultaneously contact and bond to the first surface 280t of the dummy die 280. The first semiconductor die 220 may be fixed on the dummy die 280 by the first adhesive layer 240A, thereby obtaining support from the dummy die 280.

[0102] like Figure 5 As shown in FIG. 2 , the dummy die 280 may be fixed on the substrate 210 by a third adhesive layer 240C disposed between the dummy die 280 and the substrate 210. The third adhesive layer 240C may contact and bond to the second surface 280b of the dummy die 280 and simultaneously contact and bond to the first surface 210t of the substrate 210, thereby fixing the dummy die 280 to the substrate 210.

[0103] In some example embodiments, in order to reduce the difference in thermal expansion coefficients between internal components of the semiconductor package structure 200, the dummy die 280 may generally be formed of a material substantially the same as that of the first semiconductor die 220 and / or the second semiconductor die 270. For example, the dummy die 280 may be a die that is similar in structure and / or material to the first semiconductor die 220 and the second semiconductor die 270 but does not perform a function. For example, the dummy die 280 may be a silicon die or a silicon plate in which no functional circuit layer is formed.

[0104] Similar to the passive surface of the semiconductor die manufactured by the wafer-level semiconductor process, the first surface 280t and / or the second surface 280b of the dummy die 280 can be generally manufactured to be relatively smooth. In this case, the interface bonding force between the dummy die 280 and the first adhesive layer 240A and / or the third adhesive layer 240C may be reduced. Such reduced interface bonding force may cause delamination between the dummy die 280 and the first adhesive layer 240A and / or the third adhesive layer 240C. The delamination between the dummy die 280 and the first adhesive layer 240A and / or the third adhesive layer 240C may cause the reliability of the semiconductor package structure 200 to be reduced.

[0105] In the semiconductor package structure 200 according to the exemplary embodiment of the inventive concept, the dummy die 280 may further include a first dummy concave-convex structure 283A on the first surface 280t. The specific configuration and formation method of the first dummy concave-convex structure 283A may be similar to those described in reference to Figures 1 to 3B The concavo-convex structure 123 and the concavo-convex structure 123' described in reference Figure 4 The described concavo-convex structure 123 ″ is similar to any one of the first concavo-convex structure 223 and the second concavo-convex structure 273 , and therefore, redundant descriptions thereof are omitted herein.

[0106] The first surface 280t of the dummy die 280 may be provided by the first dummy concavo-convex structure 283A. In this way, the dummy die 280 may contact the first adhesive layer 240A at the first surface 280t through the first dummy concavo-convex structure 283A, and the first adhesive layer 240A may be embedded in the first dummy concavo-convex structure 283A of the dummy die 280, so that the dummy die 280 and the first adhesive layer 240A may be combined with each other with an increased interface bonding force. Therefore, the risk of delamination between the dummy die 280 and the first adhesive layer 240A may be reduced. Therefore, the reliability of the semiconductor package structure 200 may be improved.

[0107] In addition, in the semiconductor package structure 200 according to the exemplary embodiment of the present inventive concept, the dummy die 280 may further include a second dummy concave-convex structure 283B on the second surface 280b. The specific configuration and formation method of the second dummy concave-convex structure 283B may be the same as that of the reference numeral 280. Figures 1 to 3B The concavo-convex structure 123 and the concavo-convex structure 123 ′ described in reference Figure 4 The described concavo-convex structure 123 ″ is similar to any one of the first concavo-convex structure 223 and the second concavo-convex structure 273 , and therefore, redundant descriptions thereof are omitted herein.

[0108] The second surface 280b of the dummy die 280 can be provided by the second dummy concavo-convex structure 283B. In this way, the dummy die 280 can contact the third adhesive layer 240C at the second surface 280b through the second dummy concavo-convex structure 283B, and the third adhesive layer 240C can be embedded in the second dummy concavo-convex structure 283B of the dummy die 280, so that the dummy die 280 and the third adhesive layer 240C can be combined with each other with an increased interface bonding force. Therefore, the risk of delamination between the dummy die 280 and the third adhesive layer 240C can be reduced. Therefore, the reliability of the semiconductor package structure 200 can be improved.

[0109] Figure 6 is a cross-sectional view schematically illustrating a semiconductor package structure according to example embodiments.

[0110] and Figure 5 Compared with the semiconductor package structure 200, in addition to replacing the dummy die 280 with the third semiconductor die 290, Figure 6 The semiconductor package structure 200' can be Figure 5 Therefore, the description of the same or similar components will be omitted or simplified below, and reference will be made to Figure 5 Descriptions of the same or similar components may be equally or similarly applied to Figure 6 Example embodiments of the present invention.

[0111] Reference Figure 6 The semiconductor package structure 200′ according to the example embodiment of the present disclosure may include a substrate 210, a first semiconductor die 220 on the substrate 210, a second semiconductor die 270 and a third semiconductor die 290 between the first semiconductor die 220 and the substrate 210, and a molding layer 260 covering the first semiconductor die 220, the second semiconductor die 270 and the third semiconductor die 290 on the substrate 210. Figure 6As shown in , the mold layer 260 may surround the first semiconductor die 220, the second semiconductor die 270, and the third semiconductor die 290 on the substrate 210. In addition, the semiconductor package structure 200' may further include a first bonding wire 230A electrically connecting the first semiconductor die to the substrate 210, a second bonding wire 230B electrically connecting the second semiconductor die 270 to the substrate 210, and a third bonding wire 230C electrically connecting the third semiconductor die 290 to the substrate 210. In addition, the semiconductor package structure 200' may further include an external connection terminal 250 for electrically connecting the semiconductor package structure 200' to the outside.

[0112] like Figure 6 As shown in , the third semiconductor die 290 may be disposed between the first semiconductor die 220 and the substrate 210. The third semiconductor die 290 may be a functional die in which a functional circuit layer is formed to perform a predetermined or set function. In some example embodiments, the third semiconductor die 290 may be a logic die or a memory die. When the third semiconductor die 290 is a memory die, the third semiconductor die 290 may be a memory die that is the same as or different from the first semiconductor die 220. When the third semiconductor die 290 is a logic die, the third semiconductor die 290 may perform a logic function different from that of the second semiconductor die 270. For example, in some example embodiments, the second semiconductor die 270 may perform the function of a central processing unit (CPU), and the third semiconductor die 290 may perform the function of a graphics processing unit (GPU). However, example embodiments are not limited thereto, and the second semiconductor die 270 and the third semiconductor die 290 may be designed or manufactured to achieve various desired functional combinations. Furthermore, in some example embodiments, the third semiconductor die 290 may be electrically connected to at least one of the first semiconductor die 220 and the second semiconductor die 270 via the substrate 210. Furthermore, the third semiconductor die 290 may be electrically connected to the outside via the substrate 210. Figure 6 An example is shown in which the third semiconductor die 290 is connected to the substrate 210 and electrically connected to at least one of the first semiconductor die 220 and the second semiconductor die 270 via the substrate 210, but in some example embodiments, the third semiconductor die 290 may also be connected only to at least one of the first semiconductor die 220 and the second semiconductor die 270 without being connected to the substrate 210.

[0113] The third semiconductor die 290 may have a first surface 290 t (e.g., an upper surface or a top surface) and a second surface 290 b (e.g., a lower surface or a bottom surface) opposite to the first surface 290 t. The first surface 290 t of the third semiconductor die 290 may contact and bond to the first adhesive layer 240A, and the second surface 290 b of the third semiconductor die 290 may contact and bond to the third adhesive layer 240C, thereby being fixed between the first semiconductor die 220 and the substrate 210.

[0114] The third semiconductor die 290 may include a die body 291, a third die pad 292 on the active surface of the third semiconductor die 290, and a third concavo-convex structure 293 on the inactive surface of the third semiconductor die 290. The specific configuration and formation method of the third concavo-convex structure 293 may be the same as that of reference 1. Figures 1 to 3B The concavo-convex structure 123 and the concavo-convex structure 123 ′ described in reference Figure 4 The concave-convex structure 123'' described and the reference Figure 5 Any one of the described first concavo-convex structure 223 and the second concavo-convex structure 273 is substantially the same, and thus, redundant descriptions thereof are omitted herein.

[0115] In some example embodiments, Figure 6 As shown in , the third semiconductor die 290 can be mounted on the substrate 210 by wire bonding, in which case the second surface 290b of the third semiconductor die 290 can be a passive surface of the third semiconductor die 290. The second surface 290b of the third semiconductor die 290 can be provided by the third concave-convex structure 293. In this way, the third semiconductor die 290 can contact the third adhesive layer 240C through the third concave-convex structure 293 at the second surface 290b as the passive surface, and the third adhesive layer 240C can be embedded in the third concave-convex structure 293 of the third semiconductor die 290, so that the third semiconductor die 290 and the third adhesive layer 240C can be combined with each other with an increased interface bonding force. Therefore, the risk of delamination between the third semiconductor die 290 and the third adhesive layer 240C can be reduced. Therefore, the reliability on the semiconductor package structure 200' can be improved.

[0116] Figure 7 is a cross-sectional view schematically illustrating a semiconductor package structure according to example embodiments.

[0117] and Figure 5 Compared with the semiconductor package structure 200, except that the second semiconductor die 270' is mounted on the substrate 210 by the flip chip method, and the first semiconductor die 220' is mounted on the second semiconductor die 270' and the dummy die 280 by the flip chip method, Figure 7 The semiconductor package structure 200a can be Figure 5 Therefore, the description of the same or similar components will be omitted or simplified below, and reference will be made to Figure 5 Descriptions of the same or similar components may be equally or similarly applied to Figure 7 Example embodiments of the present invention.

[0118] Reference Figure 7 , a semiconductor package structure 200a according to an example embodiment of the present disclosure may include a substrate 210, a first semiconductor die 220' on the substrate 210, a second semiconductor die 270' and a dummy die 280 between the first semiconductor die 220' and the substrate 210, and a molding layer 260 covering the first semiconductor die 220', the second semiconductor die 270' and the dummy die 280 on the substrate 210. In addition, the semiconductor package structure 200a may further include an external connection terminal 250 for electrically connecting the semiconductor package structure 200a to the outside. In addition, the semiconductor package structure 200a may further include a first connection member 230A' between the first semiconductor die 220' and the second semiconductor die 270' and a second connection member 230B' between the second semiconductor die 270' and the substrate 210.

[0119] The first semiconductor die 220' may be electrically connected to the second semiconductor die 270' through the first connection member 230A'. Although not shown, in some example embodiments, the second semiconductor die 270' may further include vertical connection members such as through silicon vias (TSVs, or "Through Silicon Vias") formed therein. In such example embodiments, the first semiconductor die 220' may also be electrically connected to the substrate 210 via the first connection member 230A', the second connection member 230B', and the vertical connection members in the second semiconductor die 270'.

[0120] The second semiconductor die 270' may be electrically connected to the substrate 210 through the second connection member 230B'. Each of the first connection member 230A' and the second connection member 230B' may be connected to the reference Figure 4 The described connection members 130 ′ are substantially the same or similar, and thus, redundant descriptions thereof are omitted herein.

[0121] The semiconductor package structure 200a may further include a first adhesive layer 240A' surrounding the first connection member 230A' between the first semiconductor die 220' and the second semiconductor die 270', and a second adhesive layer 240B' surrounding the second connection member 230B' between the second semiconductor die 270' and the substrate 210. The first semiconductor die 220' may be fixed to the second semiconductor die 270' by the first adhesive layer 240A'. The second semiconductor die 270' may be fixed to the substrate 210 by the second adhesive layer 240B'. In addition, the first adhesive layer 240A' may also be disposed between the first semiconductor die 220' and the dummy die 280 to fix the first semiconductor die 220' to the dummy die 280. The first adhesive layer 240A' may be connected to the reference die 210. Figure 5 The first adhesive layer 240A described above is substantially the same as or similar to the first adhesive layer 240A, and the second adhesive layer 240B′ may be the same as the first adhesive layer 240A described above. Figure 4 The described adhesive layer 140 ′ is substantially the same or similar, and thus, a redundant description thereof is omitted herein.

[0122] like Figure 7 As shown in , the second surface 220b' (e.g., the lower surface or bottom surface) of the first semiconductor die 220' may be an active surface of the first semiconductor die 220' on which a die pad (not shown) is disposed, and the first surface 220t' (e.g., the upper surface or top surface) of the first semiconductor die 220' may be an inactive surface of the first semiconductor die 220' opposite to the active surface. The active surface of the first semiconductor die 220' (e.g., Figure 7 The second surface 220b' in the first semiconductor die 220 may face the substrate 210, and the inactive surface of the first semiconductor die 220' (eg, Figure 7 The first surface 220 t′ in the mold may face the mold layer 260 .

[0123] In a semiconductor package structure 200a according to an example embodiment of the present disclosure, as shown in FIG. Figure 7 As shown in FIG. , the first semiconductor die 220′ may include a passive surface (eg, Figure 7 For example, in some example embodiments, the first concavo-convex structure 223' may be a portion of the first die body 221' of the first semiconductor die 220' that is adjacent to the first surface 220t'. For example, in some example embodiments, the first concavo-convex structure 223' may be a separate component disposed on the first die body 221' at the first surface 220t' of the first semiconductor die 220'. Figure 7 The specific structure and formation method of the first concavo-convex structure 223' can be referred to in Figures 1 to 3B The concavo-convex structure 123 and the concavo-convex structure 123 ′ described in reference Figure 4 The concave-convex structure 123'' described and the reference Figure 5 Any one of the described first concavo-convex structure 223 and the second concavo-convex structure 273 is substantially the same, and thus, redundant descriptions thereof are omitted herein.

[0124] like Figure 7 As shown in , the first surface 220t' of the first semiconductor die 220' as a passive surface can be provided by the first concavo-convex structure 223'. Therefore, the first semiconductor die 220' can be bonded to the mold layer 260 at the first surface 220t' through the first concavo-convex structure 223', and the mold layer 260 can be embedded in the first concavo-convex structure 223' of the first semiconductor die 220'. In this way, the interface bonding force between the first semiconductor die 220' and the mold layer 260 can be increased, thereby reducing the risk of delamination between the first semiconductor die 220' and the mold layer 260. Therefore, the reliability of the semiconductor package structure 200a can be improved.

[0125] In the semiconductor packaging structure according to the example embodiments of the present disclosure, the bare die may be provided with a concavo-convex structure on its surface which is originally formed to be relatively smooth due to, for example, a thinning process, so that the bare die can be bonded to the adhesive layer and / or the molding layer through the concavo-convex structure instead of the smooth surface. The concavo-convex structure can increase the interface bonding force between the bare die and the adhesive layer and / or the molding layer by increasing the contact area and / or providing a mechanical bite force. Therefore, the risk of delamination between the bare die and the adhesive layer and / or the molding layer can be reduced. Therefore, the reliability of the semiconductor packaging structure can be improved.

[0126] Although specific details of some example embodiments are described in this specification, these specific details should not be interpreted as limitations on the scope of any claimed subject matter, but rather as descriptions of features for specific embodiments. Some features described in this specification in the context of separate embodiments may also be implemented in combination in a single embodiment. On the other hand, different features described in the context of a single embodiment in this specification may also be implemented separately in multiple embodiments or in any suitable subcombination.

[0127] While aspects of the example embodiments have been particularly shown and described above, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor package structure, comprising: substrate; A first semiconductor die, on the substrate, having a first active surface and a first passive surface opposite to the first active surface, and electrically connected to the substrate via a first die pad disposed on the first active surface, wherein the first semiconductor die includes a first concave-convex structure on the first passive surface; a first adhesive layer between the first semiconductor die and the substrate and bonded to one of the first active surface and the first inactive surface of the first semiconductor die; and a molding layer covering the first semiconductor die on the substrate and bonded to the other of the first active surface and the first inactive surface of the first semiconductor die, The first passive surface of the first semiconductor die is provided by the first concave-convex structure.

2. The semiconductor package structure according to claim 1, wherein: The molding layer is bonded to the first active surface of the first semiconductor die, and the first adhesive layer is embedded in the first concave-convex structure; or The first adhesive layer is bonded to the first active surface of the first semiconductor die, and the molding layer is embedded in the first concavo-convex structure.

3. The semiconductor package structure according to claim 1, in, The first semiconductor die has a first thickness in a first direction perpendicular to the first active surface of the first semiconductor die, and Wherein, the maximum thickness of the first concave-convex structure in the first direction is less than or equal to 20% of the first thickness.

4. The semiconductor package structure according to claim 1, in, The first concavo-convex structure is composed of continuously distributed concave parts and convex parts, and The first passive surface of the first semiconductor die has a surface roughness Rz greater than or equal to 500 nm due to the first concave-convex structure.

5. The semiconductor package structure according to claim 1, in, The first concavo-convex structure is composed of concave parts and convex parts that are continuously and alternately distributed, and Wherein, when viewed in a cross-sectional view, an inner bottom angle of the concave portion at a position where the concave portion intersects with an adjacent convex portion is greater than 90°.

6. The semiconductor package structure according to claim 5, wherein: When viewed in a plan view, the recess has a polygonal, circular or elliptical outer peripheral contour.

7. The semiconductor package structure according to claim 1, further comprising: a second semiconductor die disposed between the first semiconductor die and the substrate, having a second active surface and a second passive surface opposite to the second active surface, and electrically connected to at least one of the substrate and the first semiconductor die through a second die pad disposed on the second active surface; a second adhesive layer between the second semiconductor die and the substrate and bonded to one of the second active surface and the second inactive surface of the second semiconductor die; a third die, disposed side by side with the second semiconductor die between the first semiconductor die and the substrate, and having a first surface and a second surface opposite to the first surface; as well as a third adhesive layer between the third die and the substrate and bonded to the second surface of the third die, wherein the first adhesive layer is also bonded to the other of the second active surface and the second passive surface of the second semiconductor die and the first surface of the third die, and The molding layer further surrounds the first semiconductor die, the second semiconductor die and the third die on the substrate.

8. The semiconductor package structure according to claim 7, in, The second semiconductor die further comprises a second concave-convex structure on the second passive surface, the second passive surface of the second semiconductor die is provided by the second concave-convex structure, and The first adhesive layer is bonded to the second active surface of the second semiconductor die, and the second adhesive layer is embedded in the second concave-convex structure.

9. The semiconductor package structure according to claim 7, wherein: The third die is a dummy die, The third die includes a first dummy concave-convex structure disposed on the first surface and a second dummy concave-convex structure disposed on the second surface, The first surface and the second surface of the third die are provided by the first dummy concave-convex structure and the second dummy concave-convex structure, respectively, and The first adhesive layer and the third adhesive layer are respectively embedded in the first dummy concave-convex structure and the second dummy concave-convex structure.

10. The semiconductor package structure according to claim 7, wherein: The third die is a functional die, the second surface of the third die being a passive surface of the third die, The third die includes a third concave-convex structure on the second surface, The second surface of the third die is provided by the third concave-convex structure, and The third adhesive layer is embedded in the third concavo-convex structure.

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