Semiconductor package including plurality of semiconductor chips

Abstract

A semiconductor package includes a first substrate. The first lower semiconductor chip is disposed on the first substrate. A bridge structure is laterally spaced apart from the first lower semiconductor chip on the first substrate. A second substrate is disposed on the first lower semiconductor chip and the bridge structure. The first upper semiconductor chip is disposed on the second substrate. In a plan view, the first upper semiconductor chip is spaced apart from the first lower semiconductor chip. The bridge structure includes a base structure. A conductive via is disposed in the base structure and in contact with the first substrate. The first upper semiconductor chip is electrically connected to the first lower semiconductor chip through a conductive via.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0098358 filed in the Korean Intellectual Property Office on July 27, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The inventive concept relates to a semiconductor package, and more particularly, to a semiconductor package including a plurality of semiconductor chips. Background Art

[0004] A semiconductor package is a structure that houses an integrated circuit (IC) chip, protects the chip from damage, and facilitates connection between the chip incorporated therein and an electronic product. Typically, in a semiconductor package, a semiconductor chip is mounted on a printed circuit board and electrically connected to the printed circuit board by using bonding wiring or bumps. With the development of the electronics industry, various studies are being conducted to increase the reliability, integration, and miniaturization of semiconductor packages. Summary of the invention

[0005] A semiconductor package includes a first substrate. A first lower semiconductor chip is disposed on the first substrate. A bridge structure is laterally spaced apart from the first lower semiconductor chip on the first substrate. A second substrate is disposed on the first lower semiconductor chip and the bridge structure. A first upper semiconductor chip is disposed on the second substrate. In a plan view, the first upper semiconductor chip is spaced apart from the first lower semiconductor chip. The bridge structure includes a base structure, and a conductive via disposed in the base structure and contacting the first substrate. The first upper semiconductor chip is electrically connected to the first lower semiconductor chip through the conductive via.

[0006] A semiconductor package includes a first substrate. A first lower core particle is disposed on the first substrate. A second lower core particle is laterally spaced apart from the first lower core particle on the first substrate. A bridging structure is disposed between the first lower core particle and the second lower core particle on the first substrate. A second substrate is disposed on the second lower core particle and the bridging structure. A first upper core particle is disposed on the second substrate. The first upper core particle is electrically connected to the first lower core particle through the second substrate and the bridging structure.

[0007] The semiconductor package includes a first insulating layer, a first seed pattern and a first redistribution substrate, the first redistribution substrate including a first conductive pattern disposed on the first seed pattern. The first insulating layer includes a photosensitive polymer. The first lower semiconductor chip is disposed on the upper surface of the first redistribution substrate. The second lower semiconductor chip is laterally spaced apart from the first lower semiconductor chip on the upper surface of the first redistribution substrate. The bridge structure is disposed between the first lower semiconductor chip and the second lower semiconductor chip on the upper surface of the first redistribution substrate, respectively. The conductive structure is laterally spaced apart from the second lower semiconductor chip on the upper surface of the first redistribution substrate. The first mold layer covers the first lower semiconductor chip, the second lower semiconductor chip and the bridge structure on the upper surface of the first redistribution substrate. The second redistribution substrate is disposed on the first mold layer and the conductive structure. The first upper semiconductor chip is disposed on the second redistribution substrate. The second mold layer is disposed on the upper surface of the second redistribution substrate and covers the first upper semiconductor chip. The second redistribution substrate includes a second insulating layer, a second seed pattern, and a second conductive pattern disposed on the second seed pattern. The second insulating layer includes a photosensitive polymer. In a plan view, the first upper semiconductor chip is spaced apart from the first lower semiconductor chip. Each bridge structure includes a base structure and a conductive via disposed in the base structure and in contact with the first redistribution substrate. The first upper semiconductor chip is electrically connected to the first lower semiconductor chip through the second redistribution substrate and the conductive via. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1A is a plan view of a semiconductor package according to an embodiment of the present disclosure;

[0010] Figure 1B is along Figure 1A A cross-sectional view of the semiconductor package taken along line I-II;

[0011] Figure 1C is a diagram showing transmission of an electrical signal between a first lower semiconductor chip, a second lower semiconductor chip, and a first upper semiconductor chip according to an embodiment of the present disclosure;

[0012] Figure 2 is a cross-sectional view of a semiconductor package according to an embodiment of the present disclosure;

[0013] Figure 3A is a plan view of a semiconductor package according to an embodiment of the present disclosure;

[0014] Figure 3B is along Figure 3A A cross-sectional view of the semiconductor package taken along line I-II in FIG.

[0015] Figure 4 is a cross-sectional view of a semiconductor package according to an embodiment of the present disclosure; and

[0016] Figure 5 is a cross-sectional view of a semiconductor package according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0017] In the present inventive concept, like reference numerals may refer to like components throughout the specification and drawings. Semiconductor packages according to embodiments of the present inventive concept are described herein.

[0018] Figure 1A is a plan view of a semiconductor package 10 according to an embodiment of the present disclosure. Figure 1B is along Figure 1A 1 is a cross-sectional view of the semiconductor package 10 taken along line I-II in FIG.

[0019] refer to Figure 1A and Figure 1B The semiconductor package 10 may include a first substrate 100 , solder ball terminals 170 , a first lower semiconductor chip 210 , a second lower semiconductor chip 220 , a bridge structure 500 , a conductive pillar 300 , a first mold layer 410 , a second substrate 600 , a second mold layer 420 , and a first upper semiconductor chip 230 .

[0020] The first substrate 100 may include a high-density wiring substrate. For example, the first substrate 100 may include a first wiring, and the first wiring may be arranged in the first substrate 100 at a high density. The first wiring may have a relatively small width and a small spacing. For example, the first substrate 100 may include a redistribution substrate. As an example, the first substrate 100 may include a printed circuit board (e.g., a multi-layer board (MLB) and / or a high-density interconnect (HDI) substrate). Figure 1B , Figure 2 , Figure 3B , Figure 4 and Figure 5 In the embodiment, for convenience, the first substrate 100 is illustrated for the case of a redistribution substrate, but the embodiment is not necessarily limited thereto. Various modifications may be made to the type and components of the first substrate 100.

[0021] For example, when the first substrate 100 includes a redistribution substrate, as Figure 1BAs shown in , the first substrate 100 may include a first insulating layer 101, an under-bump pattern 120, a first redistribution pattern 130, a first seed crystal pattern 135, a first seed crystal pad 155 and a first redistribution pad 150. The first insulating layer 101 may include an organic material (e.g., a photoimageable dielectric (PID) material). The PID material may include a polymer. The PID material may include, for example, a photosensitive polyimide, a polybenzoxazole, a phenolic polymer, and / or a benzocyclobutene polymer. The first insulating layer 101 may be provided in plurality. Various modifications may be made to the number of stacked first insulating layers 101. For example, a plurality of first insulating layers 101 may include the same material. The interface between adjacent first insulating layers 101 may not be observable.

[0022] The first direction D1 may be parallel to the bottom surface of the lowermost first insulation layer 101 among the first insulation layers 101. The second direction D2 may be parallel to the bottom surface of the lowermost first insulation layer 101 and may be substantially perpendicular to the first direction D1. The third direction D3 may be substantially perpendicular to the first direction D1 and the second direction D2.

[0023] The under bump pattern 120 may be disposed in the lowermost first insulating layer 101. The bottom surface of the under bump pattern 120 may not be covered by the lowermost first insulating layer 101. The under bump pattern 120 may be used as a pad for the solder ball terminal 170. The under bump patterns 120 may be spaced laterally from each other and electrically disconnected from each other (e.g., electrically insulated from each other). The fact that two specific components are spaced laterally from each other may mean that the two components are spaced horizontally from each other. "Horizontal" may mean parallel to the bottom surface of the first substrate 100 or the first direction D1. The lower surface of the first substrate 100 may include the bottom surface of the lowermost first insulating layer 101 and the bottom surface of the under bump pattern 120. The under bump pattern 120 may include a metal such as copper.

[0024] The first redistribution pattern 130 may be disposed on the under bump pattern 120 and may be electrically connected to the under bump pattern 120. The first redistribution pattern 130 may include a metal such as copper. Being electrically connected to the first substrate 100 may mean being electrically connected to any one of the first redistribution patterns 130. Electrically connecting two components to each other may include a direct connection between the two components, or an indirect connection with another component disposed therebetween to complete the electrical connection.

[0025] Each first redistribution pattern 130 may include a first via portion and a first wiring portion. The first via portion may be disposed in the corresponding first insulating layer 101. The first wiring portion may be disposed on the first via portion and may be connected to the first via portion without a boundary surface. The width of the first wiring portion may be greater than the width of the first via portion. The first wiring portion may extend to the upper surface of the first insulating layer 101 corresponding thereto. In the present inventive concept, the via may include a component for vertical connection, and the wiring may include a component for horizontal connection. "Vertical" may mean "parallel to the third direction D3".

[0026] The first redistribution pattern 130 may include a first lower redistribution pattern and a first upper redistribution pattern stacked. The first lower redistribution pattern may be disposed on the under bump pattern 120 corresponding thereto. The first upper redistribution pattern may be disposed on the first lower redistribution pattern and contact the first lower redistribution pattern.

[0027] The first seed patterns 135 may be respectively disposed on the lower surfaces of the first redistribution patterns 130. For example, each of the first seed patterns 135 may cover the lower surface and sidewall of the first via portion of the first redistribution pattern 130 corresponding to each of the first seed patterns 135, and the lower surface of the first wiring portion. The first seed pattern 135 may include a material different from that of the under-bump pattern 120 and the first redistribution pattern 130. For example, the first seed pattern 135 may include a conductive seed material. The conductive seed material may include copper, titanium, and / or an alloy thereof. The first seed pattern 135 may be used as a barrier layer to prevent diffusion of the material included in the first redistribution pattern 130.

[0028] The first redistribution pads 150 may be disposed in the uppermost first insulating layer 101 and may extend onto the upper surface of the uppermost first insulating layer 101. The lower portion of each first redistribution pad 150 may be disposed in the uppermost first insulating layer 101. The upper portion of each first redistribution pad 150 may be disposed on the upper surface of the uppermost first insulating layer 101. The upper portion of each first redistribution pad 150 may have a greater width than its lower portion and may be connected to its lower portion. The first redistribution pads 150 may be laterally spaced apart from each other. The first redistribution pads 150 may be disposed on the first redistribution pattern 130 and may be connected to the first redistribution pattern 130. At least one of the first redistribution pads 150 may be connected to the bump under pattern 120 corresponding thereto via the first upper redistribution pattern and the first lower redistribution pattern. Because the first redistribution pattern 130 is provided, any one of the first redistribution pads 150 may not be vertically aligned with the bump under pattern 120 electrically connected to the first redistribution pad 150. Accordingly, the arrangement of the first redistribution pads 150 can be freely designed. The number of the first redistribution patterns 130 stacked between the under bump patterns 120 and the first redistribution pads 150 is not limited to the illustrated arrangement but may be variously modified.

[0029] The first seed pads 155 may be respectively disposed on lower surfaces of the first redistribution pads 150. The first seed pads 155 may be disposed between the first upper redistribution pattern among the first redistribution patterns 130 and the first redistribution pads 150, and may extend between the uppermost first insulating layer 101 and the first redistribution pads 150. The first seed pads 155 may include a material different from that of the first redistribution pads 150. The first seed pads 155 may include, for example, a conductive seed material.

[0030] The solder ball terminals 170 may be disposed below the lower surface of the first substrate 100. For example, the solder ball terminals 170 may be arranged below the lower surface of the under-bump pattern 120, respectively, and may be electrically connected to the under-bump pattern 120. The solder ball terminals 170 may be electrically connected to the first redistribution pattern 130 via the under-bump pattern 120. The solder ball terminals 170 may be electrically separated from each other. The solder ball terminals 170 may include a solder material. The solder material may include, for example, tin, bismuth, lead, silver, or an alloy thereof. The solder material may not include copper, but is not necessarily limited thereto. The solder ball terminals 170 may include a signal solder ball terminal, a ground solder ball terminal, and a power solder ball terminal.

[0031] The first lower semiconductor chip 210 may be mounted on an upper surface of the first substrate 100. For example, the first lower semiconductor chip 210 may be disposed on a central region of the first substrate 100 in a plan view.

[0032] The first lower semiconductor chip 210 may include a first chip pad 215, a first semiconductor die, and a first integrated circuit layer. The lower surface of the first semiconductor die may face the first substrate 100 and may include an active surface. The first integrated circuit layer may include a first insulating layer, a first wire, and a first integrated circuit. The first integrated circuit may include a logic circuit and may be disposed below the lower surface of the first semiconductor die. Alternatively, the first integrated circuit may include a memory circuit. The first insulating layer may be stacked below the lower surface of the first semiconductor die. Any of the first insulating layers may cover the first integrated circuit. The first wire may be disposed between the first insulating layers and may be electrically connected to the first integrated circuit. The first chip pad 215 may be disposed on the lower surface of the first lower semiconductor chip 210. The lower surface of the first lower semiconductor chip 210 may include the lower surface of the first integrated circuit layer. The first chip pad 215 may be electrically connected to the first integrated circuit via a first wire. The first chip pad 215 may include a metal such as aluminum. The component being electrically connected to the semiconductor chip may mean that the component is electrically connected to the integrated circuit via the chip pad of the semiconductor chip.

[0033] The semiconductor package 10 may further include a first lower bump 271. The first lower bump 271 may be disposed between the first substrate 100 and the first lower semiconductor chip 210. For example, the first lower bump 271 may be disposed between the first redistribution pad 150 and the first chip pad 215 corresponding to the first lower bump 271, and may be connected to the first redistribution pad 150 and the first chip pad 215. Accordingly, the first lower semiconductor chip 210 may be electrically connected to the first substrate 100 via the first lower bump 271. The first lower semiconductor chip 210 may be electrically connected to the solder ball terminal 170 via the first substrate 100. The first lower bump 271 may include a solder ball, and the solder ball may include a solder material. The first lower bump 271 may further include a filling pattern. The filling pattern may include a metal different from the solder material. The filling pattern may include, for example, copper.

[0034] The semiconductor package 10 may further include a first underfill layer 431. The first underfill layer 431 may be disposed in a first gap region between the first substrate 100 and the first lower semiconductor chip 210 and may cover sidewalls of the first lower bumps 271. The first underfill layer 431 may include an insulating polymer such as an epoxy polymer.

[0035] The second lower semiconductor chip 220 may be disposed on the upper surface of the first substrate 100. The second lower semiconductor chip 220 may perform a different function from the first lower semiconductor chip 210, but is not necessarily limited thereto. The second lower semiconductor chip 220 may transceive (e.g., send and / or receive) an electrical signal with the first lower semiconductor chip 210 via the first substrate 100.

[0036] The second lower semiconductor chip 220 may include an edge semiconductor chip. For example, in a plan view, the second lower semiconductor chip 220 may be disposed on an edge region of the first substrate 100. In a plan view, the edge region of the first substrate 100 may be disposed between the central region and the sidewall of the first substrate 100. In a plan view, the edge region of the first substrate 100 may surround the central region of the first substrate 100.

[0037] like Figure 1B As shown in , each second lower semiconductor chip 220 may include a second chip pad 225, a second semiconductor die, and a second integrated circuit layer. The lower surface of the second semiconductor die may face the first substrate 100. The second integrated circuit layer may include a second insulating layer, a second wire, and a second integrated circuit. The second integrated circuit may include a logic circuit and may be disposed below the lower surface of the second semiconductor die. Alternatively, the second integrated circuit may include a memory circuit. The second insulating layer may be stacked below the lower surface of the second semiconductor die. Any layer in the second insulating layer may cover the second integrated circuit. The second wire may be disposed between the second insulating layers and may be electrically connected to the second integrated circuit. The second chip pad 225 may be disposed below the lower surface of the second lower semiconductor chip 220 corresponding thereto. The lower surface of the second lower semiconductor chip 220 may include the lower surface of the second integrated circuit layer. The second chip pad 225 may be electrically connected to the second integrated circuit via a second wire. The second chip pad 225 may include a metal such as aluminum.

[0038] Each of the second lower semiconductor chips 220 may be laterally spaced apart from the first lower semiconductor chip 210. In a plan view, the second lower semiconductor chips 220 may be symmetrically disposed with respect to the first lower semiconductor chips 210. For example, the first lower semiconductor chip 210 may be disposed between any two of the second lower semiconductor chips 220.

[0039] For example, Figure 1A As shown in , the second lower semiconductor chip 220 may include a first edge semiconductor chip 221, a second edge semiconductor chip 222, a third edge semiconductor chip 223, and a fourth edge semiconductor chip 224. The first edge semiconductor chip 221 may be laterally spaced apart from the first sidewall 210a of the first lower semiconductor chip 210. For example, one sidewall 221a of the first edge semiconductor chip 221 may face the first sidewall 210a of the first lower semiconductor chip 210 and may be spaced apart from the first sidewall 210a of the first lower semiconductor chip 210. One sidewall 221a of the first edge semiconductor chip 221 may be spaced apart from the first sidewall 210a of the first lower semiconductor chip 210.

[0040] The second edge semiconductor chip 222 may be laterally spaced apart from the second sidewall 210b of the first lower semiconductor chip 210. The second sidewall 210b of the first lower semiconductor chip 210 may face the first sidewall 210a of the first lower semiconductor chip 210. One sidewall 222b of the second edge semiconductor chip 222 may face the second sidewall 210b of the first lower semiconductor chip 210 and may be spaced apart from the second sidewall 210b of the first lower semiconductor chip 210. One sidewall 222b of the second edge semiconductor chip 222 may be parallel to the second sidewall 210b of the first lower semiconductor chip 210.

[0041] The third edge semiconductor chip 223 may be laterally spaced apart from the third sidewall 210c of the first lower semiconductor chip 210. The third sidewall 210c of the first lower semiconductor chip 210 may be adjacent to the first sidewall 210a and the second sidewall 210b. For example, one sidewall 223c of the third edge semiconductor chip 223 may face the third sidewall 210c of the first lower semiconductor chip 210 and may be spaced apart from the third sidewall 210c of the first lower semiconductor chip 210. One sidewall 223c of the third edge semiconductor chip 223 may be parallel to the third sidewall 210c of the first lower semiconductor chip 210.

[0042] The fourth edge semiconductor chip 224 may be laterally spaced apart from the fourth sidewall 210d of the first lower semiconductor chip 210. The fourth sidewall 210d of the first lower semiconductor chip 210 may face the third sidewall 210c. For example, one sidewall 224d of the fourth edge semiconductor chip 224 may face the fourth sidewall 210d of the first lower semiconductor chip 210 and may be spaced apart from the fourth sidewall 210d of the first lower semiconductor chip 210. One sidewall 224d of the fourth edge semiconductor chip 224 may be parallel to the fourth sidewall 210d of the first lower semiconductor chip 210.

[0043] According to some embodiments of the present disclosure, Figure 1AAs shown in , the distance C between the first lower semiconductor chip 210 and the second lower semiconductor chip 220 may be about 50 μm to about 2 mm. For example, the first edge semiconductor chip 221 may be spaced apart from the first sidewall 210 a of the first lower semiconductor chip 210 by a distance C of about 50 μm to about 2 mm. The second edge semiconductor chip 222 may be spaced apart from the second sidewall 210 b of the first lower semiconductor chip 210 by a distance C of about 50 μm to about 2 mm. The third edge semiconductor chip 223 may be spaced apart from the third sidewall 210 c of the first lower semiconductor chip 210 by a distance C of about 50 μm to about 2 mm. The fourth edge semiconductor chip 224 may be spaced apart from the fourth sidewall 210 d of the first lower semiconductor chip 210 by a distance C of about 50 μm to about 2 mm. Since the distance C between the first lower semiconductor chip 210 and the second lower semiconductor chip 220 is about 2 mm or less, the interface between the first lower semiconductor chip 210 and the second lower semiconductor chip 220 may be made more reliable. For example, electrical signal transmission between the first lower semiconductor chip 210 and the second lower semiconductor chip 220 can be performed at high speed. Accordingly, electrical signal transmission between the first lower semiconductor chip 210 and the second lower semiconductor chip 220 can have high bandwidth density, low signal delay characteristics, and increased power efficiency characteristics. Because the distance C between the first lower semiconductor chip 210 and the second lower semiconductor chip 220 is about 5 μm or more, the manufacturing process of the semiconductor package 10 can be performed more easily.

[0044] According to some embodiments of the present disclosure, the length L1 of the first lower semiconductor chip 210 and the length L2 of one sidewall 221a of the first edge semiconductor chip 221 may be the same as each other, or have a difference within about 10 μm. Accordingly, the interface between the first lower semiconductor chip 210 and the first edge semiconductor chip 221 may be made more reliable. The length L1 of the first lower semiconductor chip 210 and the length L3 of one sidewall 222b of the second edge semiconductor chip 222 may be the same as each other, or have a difference within about 10 μm. The interface between the first lower semiconductor chip 210 and the first edge semiconductor chip 221 may be more reliable. In this case, the length L1 of the first lower semiconductor chip 210 may be the same as the length of the first sidewall 210a of the first lower semiconductor chip 210 and the length of the second sidewall 210b of the first lower semiconductor chip 210. The length of a specific component may be measured in a direction parallel to the second direction D2. The width W1 of the first lower semiconductor chip 210 and the width W2 of one sidewall 223c of the third edge semiconductor chip 223 may be the same as each other, or have a difference within about 10 μm. The width W1 of the first lower semiconductor chip 210 and the width W3 of one sidewall 224d of the fourth edge semiconductor chip 224 may be the same as each other, or have a difference within about 10 μm. The width W1 of the first lower semiconductor chip 210 may be the same as the width of the third sidewall 210c and the width of the fourth sidewall 210d of the first lower semiconductor chip 210. Accordingly, the interface between the first lower semiconductor chip 210 and the third edge semiconductor chip 223, and between the first lower semiconductor chip 210 and the fourth edge semiconductor chip 224 may be made more reliable. The same width, length, and level of a particular component may indicate the same error range that may occur in the process.

[0045] For example, the first lower semiconductor chip 210 may have a square shape in a plan view, and the length L1 of the first lower semiconductor chip 210 may be substantially the same as the width W1 of the first lower semiconductor chip 210. However, the inventive concept is not necessarily limited thereto. The second lower semiconductor chip 220 may have a square or rectangular planar shape.

[0046] The semiconductor package 10 may further include a second lower bump 272, such as Figure 1BAs shown in . The second lower bump 272 may be disposed between the first substrate 100 and the second lower semiconductor chip 220. For example, the second lower bump 272 may be disposed between the first redistribution pad 150 and the second chip pad 225 corresponding to the second lower bump 272, and may be connected to the first redistribution pad 150 and the second chip pad 225. Accordingly, the second lower semiconductor chip 220 may be electrically connected to the first substrate 100 via the second lower bump 272. The second lower semiconductor chip 220 may be electrically connected to the first lower semiconductor chip 210 and the solder ball terminal 170 via the first substrate 100. The second lower bump 272 may include a solder ball. The second lower bump 272 may also include a filling pattern.

[0047] The semiconductor package 10 may further include a second underfill layer 432. The second underfill layer 432 may be disposed in the second gap region between the first substrate 100 and the second lower semiconductor chip 220 and may cover sidewalls of the second lower bumps 272. The second underfill layer 432 may include an insulating polymer such as an epoxy polymer.

[0048] The bridge structure 500 may be disposed on the first substrate 100. The bridge structure 500 may be laterally spaced apart from the first lower semiconductor chip 210 and the second lower semiconductor chip 220. The bridge structure 500 may be provided in plurality. A plurality of bridge structures 500 may be respectively disposed between the first lower semiconductor chip 210 and the second lower semiconductor chip 220. For example, Figure 1A As shown in , each of the plurality of bridge structures 500 may be disposed between the first lower semiconductor chip 210 and the first edge semiconductor chip 221, between the first lower semiconductor chip 210 and the second edge semiconductor chip 222, between the first lower semiconductor chip 210 and the third edge semiconductor chip 223, and between the first lower semiconductor chip 210 and the fourth edge semiconductor chip 224. As an example, the number of bridge structures 500 may be the same as the number of second lower semiconductor chips 220. Various modifications may be made to the planar shape, size, and planar area of ​​each of the plurality of bridge structures 500 without being limited to Figure 1A The number of bridge structures 500 may be modified in various ways and need not be limited to Figure 1A as shown in the diagram.

[0049] Each of the plurality of bridge structures 500 may include a base structure 510 and a conductive via 550, such as Figure 1BAs shown in . The base structure 510 may include a semiconductor substrate. The semiconductor substrate may include silicon, germanium, or a combination thereof. As an example, the base structure 510 may include an insulating material. The conductive via 550 may be disposed in the base structure 510. The conductive via 550 may penetrate the base structure 510. The conductive via 550 may be electrically connected to the first lower semiconductor chip 210 via the first substrate 100. Being electrically connected to a plurality of bridging structures 500 may mean being electrically connected to at least one of the conductive vias 550 included in the corresponding bridging structure 500. The conductive via 550 may include a metal (e.g., copper, tungsten, titanium, and alloys thereof). The conductive via 550 may have a first pitch P1. The first pitch P1 may be about 0.4 μm to about 5 μm. Because the first pitch P1 is about 0.4 μm or greater, the manufacturing process of the conductive via 550 may be relatively simple.

[0050] The plurality of bridging structures 500 may further include a first conductive pad 551 and / or a second conductive pad 552. The first conductive pad 551 may be disposed below the lower surface of the substrate structure 510 and may contact the conductive via 550. The second conductive pad 552 may be disposed on the upper surface of the substrate structure 510 and may contact the conductive via 550. The second conductive pad 552 may be electrically connected to the first conductive pad 551 via the conductive via 550. The first conductive pad 551 and the second conductive pad 552 may include a metal (e.g., copper, titanium, and alloys thereof). The plurality of bridging structures 500 may not include an integrated circuit, but are not necessarily limited thereto. As an example, the plurality of bridging structures 500 may further include a passive device or a switching device.

[0051] The semiconductor package 10 may further include a third lower bump 273. The third lower bump 273 may be disposed between the first substrate 100 and the plurality of bridge structures 500. For example, the third lower bump 273 may be disposed between the first redistribution pad 150 and the first conductive pad 551 corresponding to the third lower bump 273, and may contact the first redistribution pad 150 and the first conductive pad 551. Accordingly, the plurality of bridge structures 500 may be electrically connected to the first substrate 100 via the third lower bump 273. The first conductive pad 551 may be omitted, and the third lower bump 273 may be directly connected to the lower surface of the conductive via 550. Each third lower bump 273 may include silver and / or a fill pattern.

[0052] The semiconductor package 10 may further include a third underfill layer 433. The third underfill layer 433 may be disposed in a third gap region between the first substrate 100 and the plurality of bridge structures 500 and may cover sidewalls of the third lower bumps 273. The third underfill layer 433 may include an insulating polymer such as an epoxy polymer.

[0053] The conductive pillar 300 may be disposed on an upper surface of an edge region of the first substrate 100. In a plan view, the conductive pillar 300 may be disposed between the second lower semiconductor chip 220 and the sidewall of the first substrate 100. The conductive pillar 300 may be laterally spaced apart from the second lower semiconductor chip 220 and the first lower semiconductor chip 210. For example, the conductive pillar 300 may have a cylindrical shape. The conductive pillar 300 may have a second pitch ( Figure 1A . The second pitch P2 may be greater than the first pitch P1. The second pitch P2 may be about 40 μm or greater. For example, the second pitch P2 may be about 40 μm to about 1 m. Because the second pitch P2 is about 40 μm or greater, the aspect ratio of the conductive pillar 300 may not be too large. Accordingly, the conductive pillar 300 may have structural stability, and the manufacturing process of the conductive pillar 300 may be more easily performed. The conductive pillars 300 may be respectively disposed on the corresponding first redistribution pads 150, and may be connected to the first redistribution pads 150. Accordingly, the conductive pillars 300 may be electrically connected to the solder ball terminals 170 via the first substrate 100. For example, the conductive pillars 300 may be electrically connected to the power solder ball terminals or the ground solder ball terminals among the solder ball terminals 170. The conductive pillars 300 may include, for example, metal (e.g., copper and / or tungsten). The conductive pillars 300 may include a conductive structure.

[0054] The first mold layer 410 may be disposed on the upper surface of the first substrate 100 and may cover the first lower semiconductor chip 210, the second lower semiconductor chip 220 and the plurality of bridge structures 500. For example, the first mold layer 410 may cover the base structure 510 and may be spaced apart from the conductive via 550. The first mold layer 410 may cover the sidewalls of the conductive pillars 300 and may not extend onto the upper surface of the conductive pillars 300. For example, the upper surface of the first mold layer 410 may be coplanar with the upper surface of the conductive pillars 300. The first mold layer 410 may include an insulating polymer (e.g., an epoxy-based mold compound). The first mold layer 410 may include a material different from the first bottom fill layer 431 to the third bottom fill layer 433. At least one of the first bottom fill layer 431 to the third bottom fill layer 433 may be omitted, and the first mold layer 410 may also extend into the corresponding region among the first gap region, the second gap region, and the third gap region.

[0055] The second substrate 600 may be disposed on the second mold layer 420 and the conductive pillars 300. The second substrate 600 may be disposed on the first lower semiconductor chip 210, the second lower semiconductor chip 220, and the bridge structure 500. The second substrate 600 may be electrically connected to the conductive pillars 300.

[0056] The second substrate 600 may include a high-density wiring substrate. For example, the second substrate 600 may include second wirings, and the second wirings may be arranged in the second substrate 600 at a high density. The second wirings may have a relatively small width and a small spacing. For example, the second substrate 600 may include a redistribution substrate. As an example, the second substrate 600 may include a printed circuit board (e.g., an MLB and / or HDI substrate). Figure 1B , Figure 2 , Figure 3B , Figure 4 and Figure 5 In the embodiment, for convenience, the second substrate 600 is illustrated for the case of a redistribution substrate, but the embodiment is not necessarily limited thereto. Various modifications may be made to the type and components of the second substrate 600.

[0057] According to some embodiments of the present disclosure, when the second substrate 600 includes a redistribution substrate, the second substrate 600 may include a second insulating layer 601, a second redistribution pattern 630, a second seed pattern 635, a second seed pad 655, and a second redistribution pad 650. The second insulating layer 601 may include a plurality of second insulating layers 601. The plurality of second insulating layers 601 may be stacked on the first mold layer 410. The plurality of second insulating layers 601 may include PID material. For example, the plurality of second insulating layers 601 may include the same material. The interface between the adjacent plurality of second insulating layers 601 may not be observable. Various modifications may be made to the number of the second insulating layers 601.

[0058] The second redistribution pattern 630 may be disposed in and on the plurality of second insulating layers 601. Each second redistribution pattern 630 may include a second via portion and a second wiring portion. The second via portion may be disposed in the corresponding second insulating layer 601. The second wiring portion may be disposed on the second via portion and may be connected to the second via portion without a boundary surface. The width of the second wiring portion of each second redistribution pattern 630 may be greater than the width of the upper surface of the second via portion. The second wiring portion of each second redistribution pattern 630 may extend onto the upper surface of the second insulating layer 601. The second redistribution pattern 630 may include a metal such as copper.

[0059] The second redistribution pattern 630 may include a second lower redistribution pattern and a second upper redistribution pattern stacked. The second lower redistribution pattern may be disposed on the corresponding conductive pillar 300 and may contact the corresponding conductive pillar 300. The second upper redistribution pattern may be disposed on the second lower redistribution pattern and may contact the second lower redistribution pattern.

[0060] The second seed patterns 635 may be respectively disposed on the lower surfaces of the second redistribution patterns 630. For example, each second seed pattern 635 may be disposed on the lower surface and sidewall of the second via portion of the second redistribution pattern 630 corresponding to each second seed pattern 635, and may extend to the line of the second wiring portion. The second seed pattern 635 may include a material different from the conductive pillar 300 and the second redistribution pattern 630. For example, the second seed pattern 635 may include a conductive seed material. The second seed pattern 635 may serve as a barrier layer to prevent diffusion of the material included in the second redistribution pattern 630.

[0061] Each second redistribution pad 650 may be disposed on a corresponding second redistribution pattern 630 and may contact the corresponding second redistribution pattern 630. For example, each second redistribution pad 650 may be disposed on a second lower redistribution pattern. The second redistribution pads 650 may be laterally spaced apart from each other. The lower portion of the second redistribution pad 650 may be disposed in the uppermost second insulating layer 601. The upper portion of the second redistribution pad 650 may extend onto the upper surface of the uppermost second insulating layer 601. The second redistribution pad 650 may include a metal such as copper.

[0062] The second redistribution pads 650 may contact the conductive pillars 300 via the second redistribution patterns 630. Because the second redistribution patterns 630 are provided, at least one second redistribution pad 650 may not be vertically aligned with the conductive pillar 300 electrically connected to the at least one second redistribution pad 650. Accordingly, the arrangement of the second redistribution pads 650 may be freely designed. The number of second redistribution patterns 630 stacked between the conductive pillars 300 and the second redistribution pads is not necessarily limited to the arrangement shown, but may be variously modified. For example, one second redistribution pattern 630, or three or more second redistribution patterns 630 may be stacked.

[0063] The second seed pad 655 may be disposed between the uppermost second redistribution pattern 630 and the second redistribution pad 650. The second seed pad 655 may include a conductive seed material.

[0064] The semiconductor package 10 may further include a bridging connection portion 570. The bridging connection portion 570 may be disposed between the bridging structures 500 and may be electrically connected to the bridging structure 500 and the second substrate 600. The bridging connection portion 570 may be disposed on the second conductive pad 552. The corresponding second redistribution pattern 630 among the second redistribution patterns 630 may be connected to the bridging connection portion 570 on the bridging connection portion 570. Accordingly, the second substrate 600 may be electrically connected to the first substrate 100 via the bridging structure 500. For example, the bridging structure 500 may provide a vertical electrical path between the first substrate 100 and the second substrate 600. The vertical electrical path may include a signal path. The bridging connection portion 570 may include a metal via or a metal stud. The bridging connection portion 570 may include, for example, copper, titanium, tungsten, silver (Ag), gold (Au), nickel and / or a combination thereof.

[0065] The first upper semiconductor chip 230 may be disposed on the upper surface of the second substrate 600. The first upper semiconductor chip 230 may be spaced apart from the first lower semiconductor chip 210 in a plan view, and may not overlap with the first lower semiconductor chip 210 in a plan view. The first upper semiconductor chip 230 may be spaced apart from the first lower semiconductor chip 210 in a diagonal direction, such as Figure 1B . The diagonal direction may intersect the first direction, the second direction, and the third direction. The first upper semiconductor chip 230 may perform a different function from the first lower semiconductor chip 210, but is not necessarily limited thereto. The first upper semiconductor chip 230 may transceive (e.g., send and / or receive) an electrical signal with the first lower semiconductor chip 210 via the bridge structure 500. The electrical signal may include a data signal or a processing signal.

[0066] According to some embodiments of the present disclosure, in a plan view, the bridge structure 500 may be disposed between the first lower semiconductor chip 210 and the first upper semiconductor chip 230, respectively. Figure 1A As shown in . Accordingly, the length of the electrical signal path between the first lower semiconductor chip 210 and the first upper semiconductor chip 230 can be shortened. High-speed signal transmission between the first lower semiconductor chip 210 and the first upper semiconductor chip 230 can be facilitated. The total number of the bridge structures 500 can be the same as the total number of the first upper semiconductor chips 230.

[0067] The first upper semiconductor chip 230 may be vertically spaced apart from the upper surface of the second lower semiconductor chip 220. In a plan view, the first upper semiconductor chip 230 may overlap the second lower semiconductor chip 220. The total number of the first upper semiconductor chips 230 may be the same as the total number of the second lower semiconductor chips 220, but is not necessarily limited thereto.

[0068] like Figure 1BAs shown in , each first upper semiconductor chip 230 may include a third chip pad 235, a third semiconductor die, and a third integrated circuit layer. The lower surface of the third semiconductor die may face the second substrate 600. The third integrated circuit layer may include a third insulating layer, a third wire, and a third integrated circuit. The third integrated circuit may include a logic circuit and may be disposed below the lower surface of the third semiconductor die. Alternatively, the third integrated circuit may include a memory circuit. The third insulating layer may be stacked below the lower surface of the third semiconductor die. Any one of the third insulating layers may cover the third integrated circuit. The third wire may be disposed between the third insulating layers and may be electrically connected to the third integrated circuit. The third chip pad 235 may be disposed on the lower surface of the third lower semiconductor chip. The third chip pad 235 may be electrically connected to the third integrated circuit via a third wire. The third chip pad 235 may include a metal such as aluminum.

[0069] The semiconductor package 10 may further include a first conductive bump 274. The first conductive bump 274 may be disposed between the second substrate 600 and the first upper semiconductor chip 230. For example, the first conductive bump 274 may be disposed between the corresponding second redistribution pad 650 and the third chip pad 235, and may be connected to the second redistribution pad 650 and the third chip pad 235. The first conductive bump 274 may include a solder ball. The first conductive bump 274 may also include a filling pattern. The first upper semiconductor chip 230 may be electrically connected to the second substrate 600 via the first conductive bump 274. Accordingly, the first upper semiconductor chip 230 may be electrically connected to the first lower semiconductor chip 210 via the second substrate 600, the bridge structure 500, and the first substrate 100. The conductive via 550 of the bridge structure 500 may include a signal via. For example, the conductive via 550 may transmit an electrical signal between the first lower semiconductor chip 210 and the first upper semiconductor chip 230.

[0070] According to some embodiments of the present disclosure, since the semiconductor package 10 includes the first upper semiconductor chip 230, the sum of the planar areas of the semiconductor chips included in the semiconductor package 10 may be increased. The sum of the planar areas of the semiconductor chips may include the sum of the planar areas of the first lower semiconductor chip 210, the planar areas of the second lower semiconductor chip 220, and the planar areas of the first upper semiconductor chip 230. As the sum of the planar areas of the semiconductor chips increases, the performance of the semiconductor package 10 may be improved.

[0071] According to some embodiments of the present disclosure, since the first upper semiconductor chip 230 overlaps the second lower semiconductor chip 220 in a plan view, the planar area of ​​the semiconductor package 10 can be reduced. According to some embodiments of the present disclosure, although the sum of the planar areas of the semiconductor chips included in the semiconductor package 10 increases, the semiconductor package 10 can be miniaturized.

[0072] The first upper semiconductor chip 230 may be electrically connected to the conductive pillar 300 via the second substrate 600. The second pitch P2 of the conductive pillar 300 may be relatively large. The first upper semiconductor chip 230 may receive a voltage via the conductive pillar 300. The voltage may be a power supply voltage or a ground voltage. According to some embodiments of the present disclosure, since the conductive pillar 300 is used as a voltage supply path having the second pitch P2, the voltage may be stably supplied to the first upper semiconductor chip 230. When the conductive pillar 300 is used as a signal transmission path between the first lower semiconductor chip 210 and the first upper semiconductor chip 230, the length of the signal transmission path between the first lower semiconductor chip 210 and the first upper semiconductor chip 230 may be increased. According to some embodiments of the present disclosure, since the conductive via 550 of the bridge structure 500 is used as a signal transmission path between the first lower semiconductor chip 210 and the first upper semiconductor chip 230, high-speed signal transmission between the first lower semiconductor chip 210 and the first upper semiconductor chip 230 is also possible. According to some embodiments of the present disclosure, the first pitch P1 of the conductive via 550 may be relatively small. For example, because the first pitch P1 of the conductive vias 550 is about 5 μm or less, signal transmission between the first lower semiconductor chip 210 and the first upper semiconductor chip 230 may be suitable for high-performance processing (eg, artificial intelligence (AI)).

[0073] The semiconductor package 10 may further include a first underfill pattern 434. The first underfill pattern 434 may be disposed on the fourth gap region between the second substrate 600 and the first upper semiconductor chip 230 and cover the sidewalls of the first conductive bump 274. The first underfill pattern 434 may include an insulating polymer such as an epoxy polymer.

[0074] The second mold layer 420 may be disposed on the second substrate 600 and cover the first upper semiconductor chip 230. The second mold layer 420 may include an insulating polymer such as an epoxy-based mold compound. The second mold layer 420 may include a material different from the first bottom fill pattern 434. The first bottom fill pattern 434 may be omitted, and the second mold layer 420 may also extend to the lower surface of the first upper semiconductor chip 230 to cover the sidewalls of the first conductive bumps 274.

[0075] In the following, the transmission of electrical signals of the first lower semiconductor chip, the second lower semiconductor chip and the first upper semiconductor chip is described. Where an element is not described in detail with respect to this figure, it is understood that the element is at least similar to a corresponding element already described elsewhere within the present disclosure.

[0076] Figure 1Cis a diagram illustrating transmission of electrical signals among a first lower semiconductor chip, a second lower semiconductor chip, and a first upper semiconductor chip according to an embodiment of the present disclosure.

[0077] As used herein, the term "chiplet" may refer to a smaller integrated circuit (IC) containing a well-defined subset of functionality that can be combined with other chiplets on an interposer in a single package. Figure 1A and Figure 1B refer to Figure 1C , the first lower semiconductor chip 210 may include a first lower core particle. For example, the first lower semiconductor chip 210 may include a core core particle or a hub core particle. The core particle may include an intellectual property (IP) block unit formed by dividing the logic semiconductor chip according to the function. The logic semiconductor chip may constitute a processor and may be used as a processor. Unlike this case, each core particle may not operate as an independent processor, but the core particles may be connected to each other to operate as at least one processor. The processor may include core particles connected to each other.

[0078] According to some embodiments of the present disclosure, the first integrated circuit of the first lower semiconductor chip 210 may form at least one IP block unit. When the first lower semiconductor chip 210 includes a core particle, the IP block unit of the first lower semiconductor chip 210 may include a first communication IP unit. The first lower semiconductor chip 210 may transmit and receive (e.g., send and / or receive) signals to and from another semiconductor chip or another core particle via the first communication IP unit. The first communication IP unit may include a die-to-die (D2D) IP. The first communication IP unit may not include an accelerator cache coherent interconnect (CCIX), but is not necessarily limited thereto.

[0079] The second lower semiconductor chip 220 may include a second lower core particle. The second integrated circuit of each second lower semiconductor chip 220 may form at least one IP block unit. As an example, the IP block unit of the second lower semiconductor chip 220 may perform a function different from the IP block unit of the first lower core particle, or may have a design different from the IP block unit. Any IP block unit in the second lower semiconductor chip 220 may perform the same or different function as any other IP block unit in the second lower semiconductor chip 220, or may have a design the same or different from any other IP block unit in the second lower semiconductor chip 220. When the second lower semiconductor chip 220 includes a core particle, the IP block unit of each second lower semiconductor chip 220 may include a second communication IP unit. The second communication IP unit may include a D2D IP. Each second lower semiconductor chip 220 may receive and transmit (e.g., send and / or receive) signals to and from other semiconductor chips or other core particles via the second communication IP unit.

[0080] The first upper semiconductor chip 230 may include a first upper core particle. The third integrated circuit of each first upper semiconductor chip 230 may form at least one IP block unit. For example, the IP block unit of the first upper semiconductor chip 230 may perform a different function from the IP block unit of the first lower semiconductor chip 210 and have a different design. The IP block unit of the first upper semiconductor chip 230 may perform the same or different function as the IP block unit of the second lower semiconductor chip 220, or may have the same or different design as the IP block unit of the second lower semiconductor chip 220. Any one IP block unit in the first upper semiconductor chip 230 may perform the same or different function as any other IP block unit in the first upper semiconductor chip 230, or may have the same or different design as any other IP block unit in the first upper semiconductor chip 230. When the first upper semiconductor chip 230 includes a core particle, the IP block unit of each first upper semiconductor chip 230 may include a third communication IP unit. Each first upper semiconductor chip 230 may receive and transmit (e.g., send and / or receive) signals to and from other semiconductor chips or other core particles via the third communication IP unit. The third communication IP unit may include a D2D IP.

[0081] The first upper semiconductor chip 230 and the second lower semiconductor chip 220 may be electrically connected to the first lower semiconductor chip 210. When each of the first lower semiconductor chip 210, the second lower semiconductor chip 220 and the first upper semiconductor chip 230 is a core particle, the first lower semiconductor chip 210, the second lower semiconductor chip 220 and the first upper semiconductor chip 230 may constitute a processor. The processor may include, for example, a central processing unit (CPU), a graphics processing unit (GPU), a data processing unit (DPU), and / or a neural processing unit (NPU). In this case, the first communication IP unit may contact the second communication IP unit, respectively, and the first lower semiconductor chip 210 may be respectively and electrically connected to the second lower semiconductor chip 220. The first communication IP unit may contact the third communication IP unit, respectively, and the first lower semiconductor chip 210 may be respectively and electrically connected to the first upper semiconductor chip 230. Figure 1C The arrows in illustrative examples may schematically indicate electrical connections between the first lower semiconductor chip 210 and the second lower semiconductor chip 220 , and electrical connections between the first lower semiconductor chip 210 and the first upper semiconductor chip 230 . Figure 1CThe arrows may correspond to the cardinality of the first lower semiconductor chip 210. The cardinality of the first lower semiconductor chip 210 may be the same as the number of semiconductor chips / chips electrically connected to the first lower semiconductor chip 210 without passing through other semiconductor chips or other cores. For example, when a specific core / semiconductor chip is electrically connected to the first lower semiconductor chip 210 without passing through other cores / semiconductor chips and passing through the first substrate 100, and Figure 1B When the second substrate 600 or at least one bridge structure 500 is formed in the lower semiconductor chip 210, the electrical connection between the chip / semiconductor chip and the first lower semiconductor chip 210 may correspond to the cardinality. When a specific chip / semiconductor chip is electrically connected to the first lower semiconductor chip 210 via other chip / semiconductor chips, a bottleneck phenomenon may occur in the process of electrically connecting the specific chip / semiconductor chip to the first lower semiconductor chip 210.

[0082] According to some embodiments of the present disclosure, not only the second lower semiconductor chip 220 but also the first upper semiconductor chip 230 may be electrically connected to the first lower semiconductor chip 210. Figure 1B As shown in , the first upper semiconductor chip 230 can be electrically connected to the first lower semiconductor chip 210 via the bridge structure 500. Because the first upper semiconductor chip 230 is connected to the first lower semiconductor chip 210 without passing through other core particles / semiconductor chips, the cardinality of the first lower semiconductor chip 210 can be increased. The bottleneck phenomenon in the electrical connection between the first upper semiconductor chip 230 and the first lower semiconductor chip 210 can be reduced or avoided. According to some embodiments of the present disclosure, because the cardinality of the first lower semiconductor chip 210 is increased, the semiconductor package 10 can have reduced signal delay, low power consumption, and increased bandwidth. As an example, although Figure 1C It is shown that the first lower semiconductor chip 210 is electrically connected to four second lower semiconductor chips 220 and four first upper semiconductor chips 230, and accordingly, the cardinality of the first lower semiconductor chips 210 is eight, but the number of core particles / semiconductor chips electrically connected to the first lower semiconductor chip 210 and the cardinality of the first lower semiconductor chip 210 are not necessarily limited thereto, and various modifications may be made.

[0083] Figure 2 is a diagram of a semiconductor package 10A according to an embodiment, and may correspond to Figure 1A In the case where an element is not described in detail with respect to this figure, it is understood that the element is at least similar to a corresponding element that has been described elsewhere within the present disclosure.

[0084] Together with Figure 1A refer to Figure 2The semiconductor package 10A may include a first substrate 100, solder ball terminals 170, a first lower semiconductor chip 210, a second lower semiconductor chip 220, a bridge structure 500, a conductive pillar 300, a first mold layer 410, a second substrate 600, a second mold layer 420, a first upper semiconductor chip 230, and an additional heat dissipation structure 700. The second mold layer 420 and the first upper semiconductor chip 230 may be connected to the reference Figures 1A to 1C However, the upper surface of the second mold layer 420 may be disposed at substantially the same level as the upper surface of the first upper semiconductor chip 230. The level of the component may mean a vertical level.

[0085] The heat dissipation structure 700 may be disposed above the upper surface of the first upper semiconductor chip 230. The heat dissipation structure 700 may also extend to the upper surface of the second molding layer 420. The heat dissipation structure 700 may include a heat sink, a heat block, or a thermal interface material (TIM) layer. The heat dissipation structure 700 may include, for example, metal. During operation of the semiconductor package 10A, the heat generated by the first upper semiconductor chip 230 may be quickly dissipated to the outside via the heat dissipation structure 700.

[0086] Figure 3A is a plan view of a semiconductor package 10B according to an embodiment of the present disclosure. Figure 3B is along Figure 3A 1 is a cross-sectional view of the semiconductor package 10B taken along line I-II in FIG.

[0087] refer to Figure 3A and Figure 3B The semiconductor package 10B may include a first substrate 100, solder ball terminals 170, a first lower semiconductor chip 210, a second lower semiconductor chip 220, a bridge structure 500, a conductive pillar 300, a first mold layer 410, a second substrate 600, a second mold layer 420, a first upper semiconductor chip 230, and an additional second upper semiconductor chip 240.

[0088] The first lower semiconductor chip 210 may be connected to the reference Figures 1A to 1C The first lower semiconductor chip 210 may include a first chip pad 215, a first semiconductor die, a first integrated circuit layer, and an additional first through hole 216 and an upper pad 217. The first through hole 216 may penetrate the first semiconductor die of the first lower semiconductor chip 210. The first through hole 216 may be electrically connected to the first chip pad 215 or the first integrated circuit. The upper pad 217 may be exposed on the upper surface of the first lower semiconductor chip 210 and may be in contact with the first through hole 216.

[0089] The semiconductor package 10B may further include a chip connection portion 575. The chip connection portion 575 may be disposed between the first lower semiconductor chip 210 and the second substrate 600, and may be electrically connected to the first lower semiconductor chip 210 and the second substrate 600. For example, the chip connection portion 575 may be disposed on the upper pads 217, respectively. The corresponding second redistribution pattern 630 may contact the chip connection portion 575. Accordingly, the second substrate 600 may be electrically connected to the first lower semiconductor chip 210 via the chip connection portion 575. The chip connection portion 575 may include a metal via or a metal stud. The chip connection portion 575 may include, for example, copper, titanium, tungsten, Ag, Au, nickel, and / or a combination thereof.

[0090] The second upper semiconductor chip 240 may be disposed on the second substrate 600 and may be laterally spaced apart from the first upper semiconductor chip 230. The second upper semiconductor chip 240 may be disposed between the first upper semiconductor chips 230. Figure 3A As shown in , the second upper semiconductor chip 240 may overlap with the first lower semiconductor chip 210. Accordingly, although the semiconductor package 10B includes the second upper semiconductor chip 240, the semiconductor package 10B may be miniaturized. According to some embodiments of the present disclosure, since the semiconductor package 10B includes the second upper semiconductor chip 240, the sum of the planar areas of the semiconductor chips included in the semiconductor package 10B may be increased. The sum of the planar areas of the semiconductor chips may include the planar area of ​​the first lower semiconductor chip 210, the planar area of ​​the second lower semiconductor chip 220, the planar area of ​​the first upper semiconductor chip 230, and the sum of the planar areas of the second upper semiconductor chip 240. Accordingly, the performance of the semiconductor package 10B may be increased.

[0091] like Figure 3B As shown in , each second upper semiconductor chip 240 may include a fourth chip pad 245, a fourth semiconductor die and a fourth integrated circuit layer. The lower surface of the fourth semiconductor die may face the second substrate 600. The fourth integrated circuit layer may include a fourth insulating layer, a fourth wire and a fourth integrated circuit. The fourth integrated circuit may include a logic circuit and may be disposed below the lower surface of the fourth semiconductor die. Alternatively, the fourth integrated circuit may include a memory circuit. The fourth insulating layer may be stacked below the lower surface of the fourth semiconductor die. Any one of the fourth insulating layers may cover the fourth integrated circuit. The fourth wire may be disposed between the fourth insulating layers and may be connected to the fourth integrated circuit. The fourth chip pad 245 may be disposed on the lower surface of the second upper semiconductor chip 240. The lower surface of the second upper semiconductor chip 240 may include the lower surface of the second integrated circuit layer. The fourth chip pad 245 may be electrically connected to the fourth integrated circuit via a fourth wire. The fourth chip pad 245 may include a metal such as aluminum.

[0092] The semiconductor package 10B may further include a second conductive bump 275. The second conductive bump 275 may be disposed between the second substrate 600 and the second upper semiconductor chip 240. For example, the second conductive bump 275 may be disposed between the second redistribution pad 650 and the fourth chip pad 245 corresponding to the second conductive bump 275, and may be connected to the second redistribution pad 650 and the fourth chip pad 245. The second conductive bump 275 may include a solder ball. The second conductive bump 275 may also include a filling pattern. The second upper semiconductor chip 240 may be electrically connected to the second substrate 600 via the second conductive bump 275. Accordingly, the second upper semiconductor chip 240 may be electrically connected to the first integrated circuit of the first lower semiconductor chip 210 via the second substrate 600, the chip connection portion 575, and the first through hole 216. The second upper semiconductor chip 240 may transceive (e.g., send and / or receive) a data signal or an electrical signal (e.g., a processing signal) to and from the first lower semiconductor chip 210. As an example, the second upper semiconductor chip 240 may perform a different function from that of the first lower semiconductor chip 210 .

[0093] According to an embodiment of the present disclosure, the second upper semiconductor chip 240 may include a second upper core particle. The fourth integrated circuit of the second upper semiconductor chip 240 may form at least one IP block unit. For example, the IP block unit of the second upper semiconductor chip 240 may perform a different function from the IP block unit of the first lower semiconductor chip 210 and have a different design. The IP block unit of the second upper semiconductor chip 240 may perform the same or different function as the IP block unit of the first upper semiconductor chip 230, or may have the same or different design as the IP block unit of the first upper semiconductor chip 230. The IP block unit of the second upper semiconductor chip 240 may perform the same or different function as the IP block unit of the second lower semiconductor chip 220, or may have the same or different design as the IP block unit of the second lower semiconductor chip 220. When the second upper semiconductor chip 240 includes a core particle, the IP block unit of the second upper semiconductor chip 240 may include a fourth communication IP unit. The fourth communication IP unit may include a D2D IP. The first through-via 216 may be used as a signal transmission path between the first communication IP unit of the first lower semiconductor chip 210 and the fourth communication IP unit of the second upper semiconductor chip 240 .

[0094] According to some embodiments of the present disclosure, the first lower semiconductor chip 210, the second lower semiconductor chip 220, the first upper semiconductor chip 230, and the second upper semiconductor chip 240 may constitute one processor. Since the second upper semiconductor chip 240 is connected to the first lower semiconductor chip 210 without passing through other core particles / semiconductor chips, the cardinality of the first lower semiconductor chip 210 may be increased. The semiconductor package 10B may have reduced signal delay, low power consumption, and increased bandwidth.

[0095] The second upper semiconductor chip 240 may be electrically connected to at least one of the conductive pillars 300 via the second substrate 600. The second upper semiconductor chip 240 may receive a voltage via at least one conductive pillar 300. The voltage may be a power supply voltage or a ground voltage. When the conductive pillar 300 is used as a signal transmission path between the first lower semiconductor chip 210 and the second upper semiconductor chip 240, the length of the signal transmission path between the first lower semiconductor chip 210 and the second upper semiconductor chip 240 may be increased. According to some embodiments of the present disclosure, since the conductive pillar 300 is used as a voltage supply path having the second pitch P2, a voltage may be stably supplied to the second upper semiconductor chip 240.

[0096] According to some embodiments of the present disclosure, since the second upper semiconductor chip 240 overlaps the first lower semiconductor chip 210 in a plan view, and the second upper semiconductor chip 240 is electrically connected to the first integrated circuit of the first lower semiconductor chip 210 via the chip connection portion 575 and the first through-hole 216, the length of the signal transmission path between the first lower semiconductor chip 210 and the second upper semiconductor chip 240 can be reduced. Accordingly, the signal transmission between the first lower semiconductor chip 210 and the second upper semiconductor chip 240 can be performed at high speed. The signal transmission between the first lower semiconductor chip 210 and the second upper semiconductor chip 240 can be suitable for high-performance processing (e.g., AI).

[0097] The semiconductor package 10B may further include a second underfill pattern 435. The second underfill pattern 435 may be disposed in the fifth gap region between the second substrate 600 and the second upper semiconductor chip 240 and may cover the sidewalls of the second conductive bump 275. The second underfill pattern 435 may include an insulating polymer such as an epoxy polymer.

[0098] The second mold layer 420 may cover the sidewalls of the second upper semiconductor chip 240 . The second underfill pattern 435 may be omitted, and the second mold layer 420 may also extend to the lower surface of the second upper semiconductor chip 240 and may cover the sidewalls of the second conductive bumps 275 .

[0099] Figure 4is a diagram of a semiconductor package 10C according to an embodiment of the present disclosure, and may correspond to Figure 3A The cross section is taken along line I-II in FIG.

[0100] Together with Figure 3A refer to Figure 4 , the semiconductor package 10C may include a first substrate 100', solder ball terminals 170, a first lower semiconductor chip 210, a second lower semiconductor chip 220, a bridge structure 500, a conductive pillar 300, a first mold layer 410, a second substrate 600, a second mold layer 420, a first upper semiconductor chip 230, and a second upper semiconductor chip 240. However, the semiconductor package 10C may not include the semiconductor chip 230 and the second upper semiconductor chip 240 that have been referred to. Figure 1B The first lower bump 271 , the second lower bump 272 , the third lower bump 273 , and the first to third underfill layers 431 to 433 are described.

[0101] The first substrate 100' may include a redistribution substrate. The first substrate 100' may include a first insulating layer 101, a first redistribution pattern 130, a first seed pattern 135, a first seed pad 155, and a first redistribution pad 150. However, the first substrate 100' may not include a reference Figure 1B The first substrate 100′ may be in direct contact with the first lower semiconductor chip 210, the second lower semiconductor chip 220, the bridge structure 500, and the first mold layer 410. For example, the uppermost first insulating layer 101 may be in direct contact with the lower surface of the first lower semiconductor chip 210, the lower surface of the second lower semiconductor chip 220, the lower surface of the bridge structure 500, and the lower surface of the first mold layer 410. The first seed crystal patterns 135 may be respectively disposed on the upper surfaces of the first redistribution patterns 130. The first seed crystal patterns 135 in the uppermost first insulating layer 101 may be in contact with the first chip pad 215, the second chip pad 225, the first conductive pad 551, or the conductive pillar 300. The first seed crystal patterns 135 may be respectively disposed on the upper surfaces of the first redistribution patterns 130.

[0102] The semiconductor package 10C may be manufactured using a chip-first process, but is not necessarily limited thereto.

[0103] Figure 5 is a diagram of a semiconductor package 10D according to an embodiment of the present disclosure, and may correspond to Figure 3A In the case where an element is not described in detail with respect to this figure, it is understood that the element is at least similar to a corresponding element that has been described elsewhere within the present disclosure.

[0104] Together with Figure 3A refer to Figure 5, the semiconductor package 10D may include a first substrate 100, solder ball terminals 170, a first lower semiconductor chip 210, a second lower semiconductor chip 220, a connection substrate 350, a bridge structure 500, a first mold layer 410, a second substrate 600, a second mold layer 420, a first upper semiconductor chip 230, and a second upper semiconductor chip 240. The semiconductor package 10D may further include a fourth lower bump 277, a fourth bottom filling layer 437, and a conductive connection portion 577.

[0105] The connection substrate 350 may be disposed on the upper surface of the edge region of the first substrate 100. The connection substrate 350 may include a substrate hole 390 penetrating the inside of the connection substrate 350. As an example, the connection substrate 350 may be manufactured by forming the substrate hole 390 penetrating the upper and lower surfaces of the printed circuit board. The first lower semiconductor chip 210, the second lower semiconductor chip 220, and the bridge structure 500 may be disposed in the substrate hole 390 of the connection substrate 350. The second lower semiconductor chip 220 may be spaced apart from the inner sidewall of the connection substrate 350.

[0106] The connection substrate 350 may include a base layer 353 and a conductive structure 301. The base layer 353 may include an insulating material. The base layer 353 may include, for example, a carbon-based material, a ceramic, or a polymer. The conductive structure 301 may be disposed in the base layer 353. The connection substrate 350 may also include a first pad 351 and a second pad 352. The first pad 351 may be disposed on the lower surface of the conductive structure 301 and may be in contact with the conductive structure 301. The second pad 352 may be disposed on the conductive structure 301 and may be in contact with the conductive structure 301. The second pad 352 may be exposed on the upper surface of the base layer 353. The conductive structure 301, the first pad 351, and the second pad 352 may include a metal. The conductive structure 301 may be provided in plurality, and the plurality of conductive structures 301 may be electrically separated from each other. The conductive structure 301 may include, for example, copper, aluminum, tungsten, titanium, iron, and / or alloys thereof.

[0107] The conductive structure 301 can be connected with the reference Figure 1A and Figure 1B ,or Figure 3A and Figure 3B The conductive pillar 300 is the same or similar to the conductive pillar 300 described in the embodiment of FIG. Figure 1A and Figure 1B ,or Figure 3A and Figure 3BThe conductive pillars 300 described in the embodiments are substantially the same as the electrical connections. For example, the first upper semiconductor chip 230 and the second upper semiconductor chip 240 may be electrically connected to the conductive structure 301 via the second substrate 600. The first upper semiconductor chip 230 and the second upper semiconductor chip 240 may receive a voltage via the conductive pillars 300. Accordingly, the voltage may be stably supplied to the first upper semiconductor chip 230 and the second upper semiconductor chip 240. The conductive structure 301 may not be used as a signal transmission path. Hereinafter, a single conductive structure 301 is described.

[0108] The fourth lower bump 277 may be disposed between the first substrate 100 and the connection substrate 350. The fourth lower bump 277 may be disposed between the first pad 351 and the corresponding first redistribution pad 150, and may contact the first pad 351 and the first redistribution pad 150 corresponding thereto. The conductive structure 301 may be electrically connected to the first substrate 100 via the fourth lower bump 277. The fourth lower bump 277 may include at least one of a solder ball and a filling pattern. The fourth lower bump 277 may include a metal.

[0109] The fourth underfill layer 437 may be disposed in a gap between the first substrate 100 and the connection substrate 350, and may encapsulate the fourth lower bump 277. The fourth underfill layer 437 may include an insulating polymer.

[0110] The conductive connection portion 577 may be disposed between the connection substrate 250 and the second substrate 600, and may be electrically connected to the connection substrate 250 and the second substrate 600. For example, the conductive connection portion 577 may be disposed on the second pad 352. The corresponding second redistribution pattern 630 in the second redistribution pattern 630 may be connected to the conductive connection portion 577. Accordingly, the second substrate 600 may be electrically connected to the conductive structure 301 via the conductive connection portion 577. The conductive connection portion 577 may include, for example, a metal via or a metal stud. The conductive connection portion 577 may include, for example, copper, titanium, tungsten, Ag, Au, nickel, and / or a combination thereof.

[0111] The embodiments of the inventive concept may be combined with each other. Figures 1A to 1C Embodiments of the semiconductor package 10, Figure 2 Embodiments of a semiconductor package 10A Figure 3A and Figure 3B Embodiments of a semiconductor package 10B Figure 4 An embodiment of a semiconductor package 10C, and Figure 5 The embodiments of the semiconductor package 10D may be combined with each other. For example, Figure 3A and Figure 3B Semiconductor package 10B, Figure 4 The semiconductor package 10C and Figure 5The semiconductor package 10D may further include a reference Figure 2 The heat dissipation structure 700 described above. Alternatively, Figures 1A to 1C A semiconductor package 10, or Figure 5 The semiconductor package 10D may include Figure 4 The first substrate 100' described in the embodiments of the present invention can be variously combined.

[0112] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor package, comprising: a first substrate; A first lower semiconductor chip is disposed on the first substrate; a bridging structure disposed on the first substrate and laterally spaced apart from the first lower semiconductor chip; a second substrate, disposed on the first lower semiconductor chip and the bridge structure; as well as A first upper semiconductor chip is disposed on the second substrate, wherein the first upper semiconductor chip is spaced apart from the first lower semiconductor chip, Wherein, the bridging structure comprises: Base structure; and a conductive via disposed in the base structure and contacting the first substrate, and Wherein, the first upper semiconductor chip is electrically connected to the first lower semiconductor chip through the conductive via.

2. The semiconductor package according to claim 1, wherein The bridge structure is disposed between the first lower semiconductor chip and the first upper semiconductor chip.

3. The semiconductor package according to claim 1 , further comprising a second lower semiconductor chip disposed on the first substrate and laterally spaced apart from the first lower semiconductor chip, in, The bridge structure is disposed between the first lower semiconductor chip and the second lower semiconductor chip.

4. The semiconductor package according to claim 3, wherein: A distance between the first lower semiconductor chip and the second lower semiconductor chip is about 50 μm to about 2 mm.

5. The semiconductor package according to claim 3, wherein: One side wall of the second lower semiconductor chip faces the first side wall of the first lower semiconductor chip.

6. The semiconductor package according to claim 5, wherein: A length of the one sidewall of the second lower semiconductor chip and a length of the first sidewall of the first lower semiconductor chip are equal to each other or have a difference of about 10 μm or less.

7. The semiconductor package of claim 1 , further comprising a conductive pillar laterally spaced apart from the first lower semiconductor chip on an upper surface of the first substrate, in, The conductive vias have a first pitch, Wherein, the conductive pillars have a second spacing, and Wherein, the first spacing is smaller than the second spacing.

8. The semiconductor package according to claim 7, in, The conductive vias include signal vias, and Wherein, a voltage is configured to be supplied to the conductive pillar.

9. The semiconductor package according to claim 1, in, The first lower semiconductor chip includes a first die, and The first upper semiconductor chip includes a second core particle.

10. The semiconductor package according to claim 1, further comprising a second upper semiconductor chip disposed on the second substrate and vertically spaced apart from an upper surface of the first lower semiconductor chip, in, The first lower semiconductor chip further includes a through hole penetrating the interior thereof, and Wherein, the second upper semiconductor chip is electrically connected to the through-hole through the second substrate.

11. The semiconductor package according to claim 1, in, The first upper semiconductor chip is provided in plurality, Wherein, the bridging structure is provided in plurality, and The number of the plurality of first upper semiconductor chips is equal to the number of the plurality of bridge structures.

12. The semiconductor package according to claim 1, further comprising a molding layer disposed between the first substrate and the second substrate, in, The molding layer covers the sidewalls of the base structure and is spaced apart from the conductive via.

13. A semiconductor package, comprising: a first substrate; A first lower core particle is disposed on the first substrate; a second lower core particle disposed on the first substrate and laterally spaced apart from the first lower core particle; A bridging structure, between the first lower core particle and the second lower core particle, and disposed on the first substrate; A second substrate, disposed on the second lower core particle and the bridge structure; as well as A first upper core particle is disposed on the second substrate, The first upper core is electrically connected to the first lower core via the second substrate and the bridge structure.

14. The semiconductor package according to claim 13, wherein: The first upper core particle is spaced apart from the first lower core particle.

15. The semiconductor package according to claim 13, in, The second lower core particle includes a first edge core particle, a second edge core particle, a third edge core particle and a fourth edge core particle, and wherein one side wall of the first edge core particle faces the first side wall of the first lower core particle and is spaced apart from the first side wall of the first lower core particle, wherein one side wall of the second edge core particle faces the second side wall of the first lower core particle and is spaced apart from the second side wall of the first lower core particle, wherein one side wall of the third edge core particle faces the third side wall of the first lower core particle and is spaced apart from the third side wall of the first lower core particle, and One side wall of the fourth edge core particle faces the fourth side wall of the first lower core particle and is spaced apart from the fourth side wall of the first lower core particle.

16. The semiconductor package according to claim 15, in, The one side wall of the first edge core particle extends parallel to the first side wall of the first lower core particle, wherein the one side wall of the second edge core particle extends parallel to the second side wall of the first lower core particle, wherein the one side wall of the third edge core particle extends parallel to the third side wall of the first lower core particle, and The one side wall of the fourth edge core particle extends parallel to the fourth side wall of the first lower core particle.

17. A semiconductor package, comprising: A first redistribution substrate comprising a first insulating layer, a first seed crystal pattern, and a first conductive pattern disposed on the first seed crystal pattern, wherein the first insulating layer comprises a photosensitive polymer; a first lower semiconductor chip disposed on an upper surface of the first redistribution substrate; a second lower semiconductor chip disposed on the upper surface of the first redistribution substrate and laterally spaced apart from the first lower semiconductor chip; a bridging structure, between the first lower semiconductor chip and the second lower semiconductor chip, respectively disposed on the upper surface of the first redistribution substrate; a conductive structure disposed on the upper surface of the first redistribution substrate and laterally spaced apart from the second lower semiconductor chip; a first molding layer disposed on the upper surface of the first redistribution substrate and covering the first lower semiconductor chip, the second lower semiconductor chip and the bridge structure; a second redistribution substrate disposed on the first molding layer and the conductive structure; a first upper semiconductor chip disposed on the second redistribution substrate; and a second molding layer disposed on an upper surface of the second redistribution substrate and covering the first upper semiconductor chip, The second redistribution substrate includes a second insulating layer, a second seed crystal pattern, and a second conductive pattern disposed on the second seed crystal pattern, wherein the second insulating layer includes a photosensitive polymer. wherein the first upper semiconductor chip is spaced apart from the first lower semiconductor chip, Wherein, each of the bridging structures comprises: Base structure; and a conductive via disposed in the base structure and in contact with the first redistribution substrate, and The first upper semiconductor chip is electrically connected to the first lower semiconductor chip through the second redistribution substrate and the conductive vias.

18. The semiconductor package according to claim 17, in, The conductive structure includes a conductive column, wherein the first upper semiconductor chip is electrically connected to the conductive pillar through the second redistribution substrate, Wherein, the conductive vias have a first spacing, and The conductive pillars have a second spacing greater than the first spacing.

19. The semiconductor package according to claim 17, in, The second lower semiconductor chip comprises: a first edge semiconductor chip spaced apart from a first sidewall of the first lower semiconductor chip by a distance of about 50 μm to about 2 mm; a second edge semiconductor chip spaced apart from the second sidewall of the first lower semiconductor chip by a distance of about 50 μm to about 2 mm; a third edge semiconductor chip spaced apart from a third sidewall of the first lower semiconductor chip by a distance of about 50 μm to about 2 mm; and The fourth edge semiconductor chip is spaced apart from the fourth sidewall of the first lower semiconductor chip by a distance of about 50 μm to about 2 mm.

20. The semiconductor package according to claim 17, in, The first lower semiconductor chip includes a first communication intellectual property IP unit, Wherein, each second lower semiconductor chip includes a second communication IP unit, and Each of the first upper semiconductor chips includes a third communication IP unit.

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