Power semiconductor packaging structure

Abstract

The power semiconductor packaging structure provided by the embodiment of the invention comprises the components of a substrate which is provided with a first surface and a second surface which are oppositely arranged; the chip is arranged on the first surface of the substrate, a first electrode bonding pad is arranged on the surface, deviating from the substrate, of the chip, and a second electrode bonding pad connected with the first surface of the substrate is arranged on the surface, facing the substrate, of the chip; the packaging body at least packages the first surface of the substrate and the chip, and the second surface of the substrate is at least partially exposed out of the packaging body; a first terminal connected to the first electrode pad; the second terminal comprises a connecting section encapsulated in the packaging body and connected with the substrate and a leading-out section exposed out of the packaging body, the connecting section is provided with a lower surface facing the first surface of the substrate and an upper surface deviating from the first surface of the substrate, and the lower surface of the connecting section is connected with the substrate through a connecting material; and a convex structure is arranged on the lower surface of the connecting section. The projection structure can limit the connecting material, provides a larger contact area, and improves the reliability.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic devices, and in particular to a power semiconductor packaging structure. Background Art

[0002] For power semiconductor packaging structures, the package is usually used to accommodate and protect chips with different functions made of different semiconductor materials such as silicon (Si), silicon carbide (SiC), gallium nitride (GaN), etc. These chips can be configured into various device types, such as microprocessors, discrete devices, amplifiers, controllers, sensors, etc. In the power semiconductor packaging structure, the chip is mounted on a substrate, and the package is typically made of an electrically insulating encapsulating material such as plastic, resin or ceramic to seal and protect the chip from moisture and dust particles, and various conductive terminals are connected to various pads of the chip and partially extend out of the package for external access.

[0003] Currently, the commonly used power semiconductor packaging structures have increasingly higher demands on power density, and the current demand that a single power semiconductor packaging structure can carry is also increasing. Therefore, higher requirements are placed on the electrical reliability, current carrying capacity, insulation performance and safety performance of the power semiconductor packaging structure. Summary of the invention

[0004] In view of this, an embodiment of the present invention provides a power semiconductor packaging structure to improve its electrical reliability.

[0005] Specifically, an embodiment of the present invention provides a power semiconductor packaging structure, for example, including: a substrate, a chip, a package body, a first terminal and a second terminal. The substrate has a first surface and a second surface arranged opposite to each other. The chip is arranged on the first surface of the substrate, the surface of the chip facing away from the substrate is configured with a first electrode pad, and the surface of the chip facing the substrate is configured with a second electrode pad, and the second electrode pad is connected to the first surface of the substrate. The package body at least encapsulates the first surface of the substrate and the chip, and the second surface of the substrate is at least partially exposed outside the package body. The first terminal includes a first connecting section and a first lead-out section, the first connecting section is encapsulated in the package body and connected to the first electrode pad of the chip, and the first lead-out section is exposed outside the package body. The second terminal includes a second connecting section and a second lead-out section, the second connecting section is encapsulated in the package body and connected to the substrate, and the second lead-out section is exposed outside the package body; wherein the second connecting section has a lower surface facing the first surface of the substrate and an upper surface facing away from the first surface of the substrate, the lower surface of the second connecting section is connected to the substrate by welding or sintering through a connecting material located between the lower surface of the second connecting section and the first surface of the substrate, and the lower surface of the second connecting section is configured with a protruding structure.

[0006] The above-mentioned embodiments of the present invention can have the following beneficial effects: in the embodiments of the present invention, a protruding structure is configured on the lower surface of the second connecting section of the second terminal, and the protruding structure can limit the connecting material. At the same time, the surface area of ​​the protruding structure is larger than the surface area of ​​the existing planar structure, that is, a larger connection contact area can be provided, so that a higher connection quality can be obtained between the second connecting section and the first surface of the substrate, which is beneficial to improving the electrical reliability of the entire power semiconductor packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The specific implementation modes of the present invention will be described in detail below with reference to the accompanying drawings.

[0008] Figure 1 A schematic diagram of the three-dimensional structure of a power semiconductor packaging structure provided by an embodiment of the present invention.

[0009] Figure 2 for Figure 1 A schematic three-dimensional structure diagram of a power semiconductor package structure from another perspective.

[0010] Figure 3A for Figure 1 The three-dimensional structural schematic diagram of an embodiment of the power semiconductor package structure after the package body is removed is shown.

[0011] Figure 3Bfor Figure 1 The three-dimensional structural schematic diagram of another embodiment of the power semiconductor package structure after the package body is removed is shown.

[0012] Figure 4 for Figure 3A A schematic partial side view of the structure shown.

[0013] Figure 5 for Figure 4 A partial enlarged schematic diagram of the structure shown.

[0014] Figure 6 for Figure 3A A partial enlarged schematic diagram of the structure shown.

[0015] Figure 7 for Figure 1 A schematic top view of the insulating layer and the current-carrying layer of the substrate in the power semiconductor packaging structure is shown.

[0016] Figure 8 for Figure 3A A schematic top view of a portion of the structure shown.

[0017] Fig. 9 for Figure 1 A left side schematic diagram of a power semiconductor package structure is shown.

[0018] Fig.10 for Figure 1 A rear view schematic diagram of a power semiconductor package structure is shown.

[0019] Fig.11 for Fig.10 A partial enlarged schematic diagram of the structure shown.

[0020] Fig.12 A schematic diagram of the three-dimensional structure of another power semiconductor packaging structure provided by an embodiment of the present invention with the packaging body omitted.

[0021] [Description of Reference Numerals]

[0022] 10-power semiconductor packaging structure, 11-substrate, 110-insulating layer, 112-current passing layer, 1121-power area, 1122-groove, 1123-driving area, 1123a, 1123c-ends, 1123b-middle part, 1123u-concave part, 1125-another driving area, 1125n-convex part, 114-heat dissipation layer, 11T-first surface of substrate, 11B-second surface of substrate, 12-resistance, 13-chip, S-first electrode pad, D-second electrode pad, G-third electrode pad, 141, 142, 143-connecting material, 15-package body, SW1-first side wall, SW2-second side wall, SW21-first Side wall section, SW3-third side wall, SW4-fourth side wall, 15T-top surface, 15B-bottom surface, 151-annular boss, 151S-end surface of annular boss, 16-first terminal, 161-first connecting section, 1611-head end connecting portion, 1612-second inclined connecting portion, 1613-cantilever, 1613a-recessed portion, 1613b-convex portion, 1613g-through groove, 1613U-top surface of cantilever, 1613L-bottom surface of cantilever, 1614-first inclined connecting portion, 1615-end connecting portion, 1616-water vapor blocking groove, 1617-middle connecting portion, 163-first lead-out section, 163B-lower surface of first lead-out section, 16 3S-end surface of the first lead-out section, 17-second terminal, 171-second connecting section, 171T-upper surface of the second connecting section, 171B-lower surface of the second connecting section, 1710-toothed structure, 1710a-convex structure, h1-protruding height, 1710c-recessed structure, h2-recessed depth, 1712-locking hole, 1716-water vapor blocking groove, 173-second lead-out section, 173T-third surface, 173B-fourth surface, 173a-front end transverse portion, 173b-first bending portion, 173c-middle transverse portion, 173d-second bending portion, 173e-rear end transverse portion, 18-third terminal, 183-second longitudinal portion, 183 a-second lower end parallel portion, 183b-second arc-shaped portion, 183c-second upper end parallel portion, R-radius, 19-fourth terminal, 193-first longitudinal portion, 193a-first lower end parallel portion, 193b-first arc-shaped portion, 193c-first upper end parallel portion, A1-first direction, A2-second direction, A3-third direction, BW-metal bonding wire, W0, W1, W2-width, t1, t2-thickness, W4, W5-maximum width, h4-height, h3-distance, K-width, L-width, d1, d2, d3, d4, d5, d6, d7, d8, d10-distance, d9-width, β-angle, θ-angle, α-bending angle. DETAILED DESCRIPTION

[0023] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0024] In order to enable those skilled in the art to better understand the technical solution of the present invention, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work should fall within the scope of protection of the present invention.

[0025] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0026] It should also be noted that the division of multiple embodiments in the present invention is only for the convenience of description and should not constitute a special limitation. The features in various embodiments can be combined and referenced to each other without contradiction.

[0027] See also Figure 1 , Figure 2 and Figure 3A The embodiment of the present invention provides a power semiconductor package structure 10, which includes, for example: a substrate 11, a chip 13, a package body 15, a first terminal 16 and a second terminal 17. The number of the chip 13 can be one or more. Figure 3A The four shown are merely illustrative examples.

[0028] In some embodiments, see Figures 1 to 5, the substrate 11 has a first surface 11T and a second surface 11B which are arranged opposite to each other. The chip 13 is arranged on the first surface 11T of the substrate 11, and the surface of the chip 13 which is away from the substrate 11 is provided with a first electrode pad S, and the surface of the chip 13 which is facing the substrate 11 is provided with a second electrode pad D, and the second electrode pad D is connected to the first surface 11T of the substrate 11. The package 15 at least encapsulates the first surface 11T of the substrate 11 and the chip 13, and the second surface 11B of the substrate 11 is, for example, partially or completely exposed to the outside of the package 15. The first terminal 15 can be used as a current introduction / lead-out terminal, which, for example, includes a first connecting section 161 and a first lead-out section 163 connected to the first connecting section 161, the first connecting section 161 is encapsulated in the package 15 and connected to the first electrode pad S of the chip 13, and the first lead-out section 163 is exposed to the outside of the package 15. The second terminal 17 can be used as a current extraction / introduction terminal, which includes, for example, a second connection section 171 and a second lead section 173 connected to the second connection section 171, wherein the second connection section 171 is enclosed in the package body 15 and, for example, connected to the substrate 11, and the second lead section 173 is exposed outside the package body 15. In addition, it is worth noting that, in other embodiments, each of the chips 13 is not limited to Figure 5 The vertical chip shown in the figure may also be a horizontal chip; specifically, when a horizontal chip is used, the second electrode pad D is arranged on the surface of the chip 13 away from the substrate 11, and the second connection section 171 of the second terminal 17 may be connected to the second pad D through a metal bonding wire; when a horizontal chip is used Figure 5 In the vertical chip shown, since the second electrode pad D is on the surface of the chip 13 facing the substrate 11 , the second connection section 171 of the second terminal 17 can be electrically connected to the chip 13 through the substrate 11 .

[0029] In some embodiments, see Figure 3A , Figure 4 and Figure 5 The second electrode pad D is connected to the first surface 11T of the substrate 11 through a connecting material 142. The connecting material 142 here can be a welding material, such as high-performance welding materials such as SnSb5 and SAC305, which can be welded in the form of welding sheets or solder paste, and the thickness is, for example, 50-200 microns (μm); or, the connecting material 142 is a sintered material, such as Ag, Cu, etc., which forms a high-performance connection layer after sintering, and the thickness is, for example, 20-50μm.

[0030] In some embodiments, see Figure 3A , Figure 4 and Figure 6The second connection section 171 has a lower surface 171B facing the first surface 11T of the substrate 11 and an upper surface 171T away from the first surface 11T of the substrate 11. The lower surface 171B of the second connection section 171 is connected to the substrate 11 by welding or sintering through a connection material 143 located between the lower surface 171B of the second connection section 171 and the first surface 11T of the substrate 11, and a protruding structure 1710a is disposed on the lower surface 171B of the second connection section 171. The connection material 143 here can be a welding material, such as a high-performance welding material such as SnSb5, SAC305, etc., which can be welded in the form of a welding sheet or a solder paste, and the thickness is, for example, 50-200μm; or the connection material 143 is a sintering material, such as Ag, Cu, etc., which forms a high-performance connection layer after sintering, and the thickness is, for example, 20-50μm. In this embodiment, the protruding structure 1710a can provide a certain limiting effect on the connecting material, and the surface area of ​​the protruding structure 1710a is larger than the surface area of ​​the existing planar structure. Therefore, a higher connection quality can be obtained between the second connecting section 173 and the first surface 11T of the substrate 11, which is beneficial to improving the electrical reliability of the entire power semiconductor packaging structure 10.

[0031] In some embodiments, see Figure 3A , Figure 4 and Figure 6 The upper surface 171T of the second connecting section 173 is provided with a recessed structure 1710c at a position corresponding to the protruding structure 1710a. It is worth mentioning that the recessed structure 1710c here can be matched with the package body 15 in a concave-convex manner, thereby further improving the connection firmness between the second terminal 17 and the substrate 11.

[0032] In some embodiments, see Figure 3A , Figure 4 and Figure 6In the first direction A1, the protruding height h1 of the protruding structure 1710a relative to the lower surface 171B of the second connecting segment 171 is equal to the recessed depth h2 of the recessed structure 1710c relative to the upper surface 171T of the second connecting segment 171, so that the entire second terminal 17 can have a substantially uniform thickness; the protruding structure 1710a is formed by extruding from the upper surface 171T of the second connecting segment 171 to the lower surface 171B of the second connecting segment 171. The first direction A1 here is the direction from the upper surface 171T of the second connecting segment 171 to the lower surface 171B of the second connecting segment 171, which is usually also the direction from the first surface 11T of the substrate 11 to the second surface 11B of the substrate 11. In this embodiment, the protruding structure 1710a is formed by extrusion, which can improve the availability of the protruding structure 1710a, thereby simplifying the production of the second terminal 17.

[0033] In some embodiments, see Figure 6 , the protruding structure 1710a contacts the first surface 11T of the substrate 11, and the end of the protruding structure 1710a close to the first surface 11T of the substrate 11 is arc-shaped. In addition, in other embodiments, the protruding structure 1710a may not contact the first surface 11T of the substrate 11. In this case, the gap between the protruding structure 1710a and the first surface 11T of the base 11 is filled with a connecting material 143 (such as a welding material or a sintered material). In addition, in other embodiments, the end of the protruding structure 1710a close to the first surface 11T of the substrate 11 is not limited to an arc shape, and may also be a plane.

[0034] In some embodiments, see Figure 3A , Figure 4 and Figure 6 , in the first direction A1, the protrusion height h1 of the protrusion structure 1710a relative to the lower surface 171B of the second connection section 171 is 0.02 mm-0.1 mm. It is worth mentioning here that if the protrusion height h1 is too large, it is easy to cause unnecessary increase in the overall thickness of the power semiconductor packaging structure 10 in the first direction A1. On the contrary, if the protrusion height h1 is too small, the limiting effect on the connection material 143 is limited.

[0035] In some embodiments, see Figure 1 , Figure 2 , Figure 3A and Figure 6The package body 15 includes a first side wall SW1 and a second side wall SW2 that are opposite and spaced apart, and a third side wall SW3 and a fourth side wall SW4 that are opposite and spaced apart, the third side wall SW3 is located between the first side wall SW1 and the second side wall SW2 and connects the first side wall SW1 and the second side wall SW2, the fourth side wall SW4 is located between the first side wall SW1 and the second side wall SW2 and connects the first side wall SW1 and the second side wall SW2, the second lead-out section 173, for example, extends from the second side wall SW2 and is exposed outside the package body 15; in the third direction A3, the second connecting section 171 includes a plurality of tooth-shaped nodes that are spaced apart from each other. The tooth-like structure 1710 is provided with the protruding structure 1710a on the surface facing the first surface 11T of the substrate 11 (i.e., a part of the lower surface 171B of the second connecting section 171). Each tooth-like structure 1710a is connected to the first surface 11T of the substrate 11 by welding or sintering through the connecting material 143. The end of each tooth-like structure 1710 close to the second lead-out section 173 is provided with a locking hole 1712 penetrating the second terminal 17. The locking hole 1712 can improve the locking ability of the power semiconductor packaging structure 10. The locking hole 1712 here is, for example, a hollow structure, and its shape is not specifically limited. The third direction A3 here is the direction from the third side wall SW3 to the fourth side wall SW4, which is, for example, perpendicular to the first direction A1. In addition, it is worth mentioning that, in some other embodiments, a single tooth-like structure 1710 is not limited to be configured with a single protruding structure 1710 a , and it may also be configured with multiple protruding structures 1710 a .

[0036] In some embodiments, see Figure 1 , Figure 2 , Figure 3A and Fig.10 In the second direction A2, the second lead-out section 173 includes a front transverse portion 173a, a first bending portion 173b, a middle transverse portion 173c, a second bending portion 173d and a rear transverse portion 173e connected in sequence, wherein the first bending portion 173b, the middle transverse portion 173c and the second bending portion 173d together form an arched bending structure; in the second direction A2, a distance d1 from the middle transverse portion 173c to the package body 15 is greater than 2 mm; and an angle β at a connection between the first bending portion 173b and the front transverse portion 173a is 105 degrees to 165 degrees. The second direction A2 here is a direction from the first side wall SW1 to the second side wall SW2, which is, for example, perpendicular to both the first direction A1 and the third direction A3.

[0037] In some embodiments, see Figures 1 to 5, the number of the chips 13 is N, the N chips 13 include a plurality of chip groups arranged at intervals in the third direction A3, and each chip group includes M chips 13, M is an integer greater than 1 and less than N; the first connecting section 161 includes a plurality of cantilevers 1613 spaced apart in the third direction A3, each of the cantilevers 1613 includes M recesses 1613a spaced apart in the second direction A2 and a convex portion 1613b located between each two adjacent recesses 1613a, and each of the convex portions 1613b connects two adjacent recesses 1613a on opposite sides in the second direction A2; the plurality of cantilevers 1613 correspond to the plurality of chip groups one by one, and the M recesses 1613a of each cantilever 1613 are connected to each of the first electrode pads S of the M chips 13 of a corresponding chip group one by one. This multi-chip parallel design can make the power semiconductor packaging structure 10 have a lower thermal resistance. For example, Figure 3A Four (corresponding to N=4) chips 13 are illustrated, which form two chipsets arranged at intervals in the third direction A3, each chipset includes two (corresponding to M=2) chips 13, and two cantilevers 1613 are illustrated. It should be noted that the value of N is not limited to four, it can be more, such as six, etc., and accordingly, the number of chips in a single chipset is not limited to two, it can be more, such as three, etc.; furthermore, the number of chipsets is not limited to two, it can be more, such as three, etc., and accordingly, the number of cantilevers 1613 is not limited to two, it can be more, such as three, etc. It is worth mentioning that in other embodiments, N=1, N=2 or N=3, and the number of cantilevers 1613 can also be one.

[0038] In some embodiments, see Figure 3A , Figure 4 and Figure 5 The recessed portion 1613a of the cantilever 1613 is connected to the first electrode pad S of the corresponding chip 13 through the connecting material 141. The connecting material 141 here can be a welding material, such as high-performance welding materials such as SnSb5 and SAC305, which can be welded in the form of welding sheets or solder paste, and the thickness is, for example, 50-200μm; or, the connecting material 141 is a sintered material, such as Ag, Cu, etc., which forms a high-performance connection layer after sintering, and the thickness is, for example, 20-50μm.

[0039] In some embodiments, see Figure 3A and Figure 4The first connecting section 161 also includes a head end connecting portion 1611 and a terminal connecting portion 1615; the head end connecting portion 1611 is connected to the first lead-out section 163, each of the cantilevers 1613 is located between the head end connecting portion 1611 and the terminal connecting portion 1615 in the first direction A2, and the recessed portion 1613a of each cantilever 1613 closest to the head end connecting portion 1611 is connected to the head end connecting portion 1611, and the recessed portion 1613a of each cantilever 1613 closest to the terminal connecting portion 1615 is connected to the head end connecting portion 1611. The recessed portion 1613a of the connecting portion 1615 is connected to the end connecting portion 1615; and the package body 15 encapsulates at least a portion of the substrate 11, the multiple chip groups, the first connecting segment 161 of the first terminal 16 (for example, the head end connecting portion 1611, the multiple cantilevers 1613 and the end connecting portion 1615) and a portion of the second terminal 17 (for example, the second connecting segment 171), and the first lead-out segment 163 of the first terminal 16 is exposed outside the package body 15. The first connecting section 161 of the first terminal 16 of the present embodiment has a plurality of cantilevers 1613 configured therein, at which a recess 1613a is provided at the connection with each chip 13, and two adjacent recesses 1613a are connected by a protrusion 1613b, that is, a sinking design is adopted, which makes the adjacent chips 13 have an arched connection, and can effectively avoid the short circuit problem caused by the too small distance between the first terminal 16 and the substrate 11 between the chips in the coplanar connection design; combined with the configuration of the head end connection part 1611 and the end connection part 1615, it increases the structural stability of the first terminal 16 and can improve the current sharing effect between multiple chips.

[0040] In some embodiments, see Figure 3A and Figure 4 The terminal connection portion 1615 is spaced apart from the recessed portion 1613a of each cantilever 1613 closest to the terminal connection portion 1615 in the first direction A1 and the second direction A2. The first connection section 161, for example, further includes a plurality of first inclined connection portions 1614, and the plurality of first inclined connection portions 1614 correspond one-to-one to the plurality of cantilevers 1613. One end of each first inclined connection portion 1614 is connected to the recessed portion 1613a of the corresponding cantilever 1613 closest to the terminal connection portion 1615, and the other end of each first inclined connection portion 1614 extends in a direction away from the first surface 11T of the substrate 11 and is connected to the terminal connection portion 1615.

[0041] In some embodiments, see Figure 3A and Figure 4The head end connection portion 1611 is spaced apart from the recessed portion 1613a of each cantilever 1613 closest to the head end connection portion 1611 in the first direction A1 and the second direction A2. The first connection section 161, for example, also includes a plurality of second inclined connection portions 1612, and the plurality of second inclined connection portions 1612 correspond one-to-one to the plurality of cantilevers 1613. One end of each second inclined connection portion 1612 is connected to the recessed portion 1613a of the corresponding cantilever 1613 closest to the head end connection portion 1611, and the other end of each second inclined connection portion 1612 extends in a direction away from the first surface 11T of the substrate 11 and is connected to the head end connection portion 1611.

[0042] In some embodiments, each of the chips 13 can be a chip with different functions made of semiconductor materials such as silicon (Si), silicon carbide (SiC), gallium nitride (GaN), such as a metal oxide semiconductor field effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), a Schottky barrier diode (SBD), a fast recovery diode (FRD), etc.

[0043] In some embodiments, see Figure 1 , Figure 2 and Figure 3A The first lead section 163, for example, extends from the first side wall SW1 and is exposed outside the package body 15. The power semiconductor package structure 10, for example, also includes a third terminal 18. The surface of at least one chip 13 facing away from the substrate 11 is also provided with a third electrode pad G (for example, a gate pad). The third terminal 18 is connected to the third electrode pad G through a metal bonding wire BW. A portion of the third terminal 18 extends from the first side wall SW1 and is exposed outside the package body 15. The power semiconductor package structure 10, for example, also includes a fourth terminal 19. The fourth terminal 19 is located between the first lead section 163 and the third terminal 18 in the third direction A3, and the fourth terminal 19 is spaced apart from the first lead section 163 and the third terminal 18 in the third direction A3.

[0044] In some embodiments, see Figure 3A and Figure 4The substrate 11 includes, for example, an insulating layer 110 and a flow layer 112 and a heat dissipation layer 114 located on opposite sides of the insulating layer 110, the surface of the flow layer 112 away from the insulating layer 110 is, for example, the first surface 11T, the surface of the heat dissipation layer 114 away from the insulating layer 110 is, for example, the second surface 11B, and the second connection section 171 is connected to the flow layer 112 through the connection material 143. For example, the flow layer 112 can be made of metal materials such as Cu and Al, which can be used as a conductive circuit to connect the chip 13, the first terminal 16 and the second terminal 17; the heat dissipation layer 114 can be made of metal materials such as Cu and Al, which can provide large-area heat dissipation conditions. The material of the insulating layer 110 can be various ceramic materials with high insulation, thermal conductivity and mechanical strength, such as Al2O3, Si3N4, AlN, etc.

[0045] In some embodiments, see Figure 1 and Figure 3A , the fourth terminal 19 is formed by extending from one end of the first connecting section 161 close to the first lead-out section 163 toward a direction away from the first connecting section 161, and the fourth terminal 19, the first connecting section 161 and the first lead-out section 163 are an integral structure. The fourth terminal 19, as a branch terminal led out from the first terminal 16, can be used as a separate driving source terminal. This design can reduce the driving voltage fluctuation of the main circuit inductance agent. It is worth mentioning that in some other embodiments, the fourth terminal 19 and the first terminal 16 can also be independent of each other rather than an integral structure.

[0046] In some embodiments, see Figure 3A and Figure 7 The first surface 11T of the substrate 11, for example, the upper surface of the current-carrying layer 112, includes a power area 1121 and a driving area 1123 spaced apart from each other in the second direction A2, the area of ​​the power area 1121 is larger than the area of ​​the driving area 1123, the chip 30 is disposed in the power area 1121, the third terminal 18 is connected to the driving area 1123 via a metal bonding wire BW, and the third electrode pad G is connected to the driving area 1123 via a metal bonding wire BW. Here, the power area 1121 has a larger overall area, which can provide a larger chip placement position for multiple chips 13 to be connected in parallel to conduct current, thereby obtaining a higher current level.

[0047] In some embodiments, see Figure 3B and Figure 7, a single groove 1122 is arranged between the power area 1121 and the driving area 1123. Since the current-carrying layer 112 uses only a single groove 1122 to separate the power area 1121 and the driving area 1123, it reduces the shape / area mismatch of the metal layers (i.e., the current-carrying layer 112 and the heat dissipation layer 114) on the opposite sides of the insulating layer 110, reduces the deformation of the insulating layer 110 under high temperature conditions, and thus improves the reliability of the power semiconductor packaging structure 10. Furthermore, a plurality of chip groups are arranged in the power area 1121, and the driving area 1123 is provided with at least one resistor 12, and the third terminal 18 is connected to the driving area 1123 through a metal bonding wire BW, and the third electrode pad G of at least one of the chips 13 is connected to the surface of the at least one resistor 12 away from the current-carrying layer 112 through the metal bonding wire BW. For example, Figure 3B , four resistors 12 and four chips 13 are shown, the four chips 13 are divided into two chip groups and are arranged in the power area 1121, each chip 13 is configured with a third electrode pad G, and each third electrode pad G is connected to a resistor 12. It is worth mentioning that in other embodiments, only the third electrode pads G of some chips 13 may be connected to the surface of the resistor 12 away from the current-carrying layer 112, while the third electrode pads G of another part of the chips 13 may be connected to the surface of the driving area 1123 of the current-carrying layer 112, or even some chips 13 may not be configured with the third electrode pads G.

[0048] Based on the above, the resistor 12 is, for example, a resistor with two electrodes on the upper and lower surfaces, and a fixed resistance value between the electrodes, and its resistance value is, for example, 1-20 ohms (Ω), and its length and width dimensions are, for example, 0.5*0.5-2*2mm, and its thickness is, for example, 0.1-1mm. It is worth mentioning that, due to the differences in inherent parameters between chips in actual production, there may be differences in gate parameters and chip internal resistance. In actual use, the differences in these parameters will cause large differences in the on / off characteristics of different chips in the same device, resulting in a short board effect in the device. Therefore, by adding resistor 12 to provide a resistance between the outside of a device and chip 13, this difference can be reduced and the current sharing effect between chips can be increased.

[0049] In some embodiments, see Figure 7 , the area ratio of the power area 1121 to the driving area 1123 is greater than 8; this is more conducive to the flow layer 112 providing a large area flow, supporting a larger chip total area, thereby achieving a higher current level and lower resistance, and ensuring that multiple chips have enough placement area in a small size package. Taking the design using four chips 13 as an example, the total chip area is greater than 80mm 2 , effectively improving the current carrying capacity of the power semiconductor packaging structure 10.

[0050] In some embodiments, see Figure 7 In the second direction A2, the width W0 of the groove 1122 is, for example, 0.4-1.6 mm, which can ensure that there is enough placement area for multiple chips in a small-size package. Figure 6 In the first direction A1, the thickness t1 of the current-carrying layer 112 is, for example, 0.5-1 mm, and the thickness t2 of the insulating layer 110 is, for example, 0.25-0.64 mm; the thickness t1 of the current-carrying layer 112 is designed to increase the cross-sectional area of ​​the conductive path and reduce the resistance; the thickness t2 of the insulating layer 110 is designed to ensure sufficient insulation capacity. Furthermore, the thickness of the heat dissipation layer 114 in the first direction A1 is, for example, equal to the thickness t1 of the current-carrying layer 112.

[0051] In some embodiments, see Figure 7 In the third direction A3, the driving area 1123 includes a middle portion 1123b and two end portions 1123a and 1123c extending from the middle portion 1123b to opposite ends in a gradually widening manner, and the side of the power area 1121 close to the driving area 1123 protrudes toward the middle portion 1123b of the driving area 1123. In this embodiment, the two end portions 1123a and 1123c of the driving area 1123 are designed to be thicker and the width of the space portion 1123b is reduced, so that the area of ​​the power area 1121 can be further increased.

[0052] In some embodiments, see Figure 7 , the ratio of the maximum width W4 of each of the end portions 1123a, 1123c to the maximum width W5 of the middle portion 1123b is greater than 1.5.

[0053] In some embodiments, see Figure 3A and Figure 7, the two ends 1123 are respectively used as bonding areas, the multiple chip groups include a first chip group and a second chip group, the surface of each chip 13 in the first chip group facing away from the first surface 11T of the substrate 11 is configured with a third electrode pad G, and the surface of each chip 13 in the second chip group facing away from the first surface 11T of the substrate 11 is configured with the third electrode pad G; in the third direction A3, the third electrode pad G of each chip 13 in the first chip group is located on the side of the first chip group away from the second chip group, and is connected to one of the two ends, such as 1123a, through a metal bonding wire BW, and the third electrode pad G of each chip 13 in the second chip group is located on the side of the second chip group away from the first chip group, and is connected to the other of the two ends, such as 1123c, through a metal bonding wire BW. Figure 3A Taking the four chips 13 shown as an example, the four chips 13 are arranged in a rectangular arrangement and are divided into two chip groups. In the third direction A3, the two chip groups are placed with the third electrode pads G facing outward, which is conducive to the arrangement of metal bonding wires BW connecting each third electrode pad G and the driving area 1123.

[0054] In some embodiments, see Figure 1 , Figure 2 , Fig. 9 and Fig.10 The package body 15, for example, further includes a top surface 15T and a bottom surface 15B that are arranged opposite to each other, the first side wall SW1, the second side wall SW2, the third side wall SW3 and the fourth side wall SW4 respectively connect the top surface 15T and the bottom surface 15B, the second surface 11B of the substrate 11 is partially or completely exposed to the outside of the package body 15 on the side where the bottom surface 15B of the package body 15 is located; the portion of the fourth terminal 19 exposed to the outside of the package body 15 is bent in a direction away from the bottom surface 15B of the package body 15 to form a first longitudinal portion 193, and the portion of the third terminal 18 exposed to the outside of the package body 15 is bent in a direction away from the bottom surface 15B of the package body 15 to form a first longitudinal portion 193. The package body 15 is bent in the direction of the bottom surface 15B to form a second longitudinal portion 183; in the second direction A2, the distance d3 between each of the first longitudinal portion 193 and the second longitudinal portion 183 and the package body 15 is greater than 2.8 mm, and the distance d2 between the end surface 163S of the first lead-out section 163 away from the package body 15 and each of the first longitudinal portion 193 and the second longitudinal portion 183 is greater than 0.3 mm; and in the direction away from the bottom surface 15B of the package body 15, the first longitudinal portion 193 and the second longitudinal portion 183 are first parallel to each other, then away from each other, and then parallel to each other again (such as Fig. 9 shown).

[0055] In some embodiments, see Figure 2 and Fig.11 The bottom surface 15B of the package body 15 is provided with an annular boss 151 protruding from the bottom surface 15B, and the height h4 of the annular boss 151 relative to the bottom surface 15B in the first direction A1 is greater than or equal to 0.2 mm, for example, 0.2 mm, 0.5 mm or 1 mm; the second surface 11B of the substrate 11 is exposed to the outside of the package body 15 through the annular boss 151. In this embodiment, by configuring the annular boss 151 at the bottom of the package body 15, the annular boss 151 provides a connection interface between the heat dissipation surface of the power semiconductor package structure 10 (that is, the portion of the second surface 11B of the substrate 11 exposed to the outside of the package body 15) and the heat sink (not shown in the figure), and the raised distance also provides a larger creepage distance, thereby increasing the insulation capability of the device under high voltage conditions.

[0056] In some embodiments, see Figure 2 and Fig.11 The height h4 of the annular boss 151 relative to the bottom surface 15B of the package body 15 in the first direction A1 is 0.2-0.5 mm; the second surface 11B of the substrate 11 and the end surface 151S of the annular boss 151 away from the bottom surface 15B of the package body 15 are in the same plane.

[0057] In some embodiments, see Fig.11 In the second direction A2, the distance d5 from the outer side surface of the annular boss 151 to the second surface 11B of the substrate 11 is greater than 0.5 mm, so as to increase the creepage distance and electrical clearance from the second lead-out section 173 to the heat dissipation surface (that is, at least a portion of the second surface 11B of the substrate 11).

[0058] In some embodiments, see Fig.11The second lead-out section 173 has a third surface 173T and a fourth surface 173B that are disposed opposite to each other in the first direction A1, and the fourth surface 173B is located between the third surface 173T and the bottom surface 15B of the package body 15 in the first direction A1. In the second direction A2, the distance d4 between the third surface 173T of the second lead-out section 173 and the outer side surface of the annular boss 151 is greater than 3.6 mm, or the distance between the fourth surface 173B of the second lead-out section 173 and the outer side surface of the annular boss 151 is greater than 3.6 mm, so as to increase the creepage distance and electrical clearance from the second lead-out section 173 to the heat dissipation surface (i.e., at least a portion of the second surface 11B of the substrate 11). In the first direction A1, the distance h3 from the fourth surface 173B of the second lead-out section 173 to the bottom surface 15B of the package body 15 is greater than 1.5 mm to increase the creepage distance and electrical clearance from the second lead-out section 173 to the heat dissipation surface (i.e., at least a portion of the second surface 11B of the substrate 11).

[0059] In some embodiments, see Fig.10 In the first direction A1, the distance between the lower surface 163B of the first lead-out section 163 of the first terminal 16 and the fourth surface 173B of the second lead-out section 173 of the second terminal 17 is, for example, 0 mm-0.1 mm.

[0060] In some embodiments, see Fig.11 , in the second direction A2, the second lead section 173 is spaced apart from the bottom surface 15B of the package body 15, and the second side wall SW2 includes a first side wall section SW21 located between the second lead section 173 and the bottom surface 15B of the package body 15 in the first direction A1, and the angle θ between the first side wall section SW21 and the first direction A1 is, for example, 3 degrees to 10 degrees. It is worth mentioning that the package body 15 can be used to protect the internal chip 13 and substrate 11 on the one hand, and can also play a sealing role to prevent external water vapor, dust, corrosive gas, etc. from entering the interior to increase device reliability, and can also play a role in increasing the insulation distance to increase device reliability. In the process of forming the package body 15, through a designed mold, for example, Figure 3A After the structure shown is placed, the encapsulation material, such as the plastic encapsulation material, is melted and injected into the mold by injection molding. The molten plastic encapsulation material will fill the gap between the mold and the structure to be encapsulated. After cooling, the plastic encapsulation material hardens and forms, and finally demolding is performed. In this embodiment, the angle θ is designed to be 3 degrees to 10 degrees, which is conducive to demolding, so the angle θ can also be called the demolding angle.

[0061] In some embodiments, see Figure 3A , Figure 4 and Figure 8 The width of the second terminal 17 in the third direction A3 decreases from the outside of the encapsulation body 15 towards the inside of the encapsulation body 15, for example, W2 < W1. The width W2 of one end of the second connection segment 171 connected to the first surface 11T of the substrate 11 in the third direction A3 is less than the width K of the substrate 11 in the third direction A3, that is, W2 < K. A plurality of dentate structures 1710 spaced from each other in the third direction A3 are provided at one end of the second connection segment 171 connected to the first surface 11T of the substrate 11. Each dentate structure 1710 is connected to the substrate 11 by a connecting material 143 in a welding or sintering manner. A mold clamping hole 1712 penetrating the second terminal 17 is provided at one end of each dentate structure 1710 close to the second lead segment 173.

[0062] In some embodiments, referring to Figure 8 the plurality of dentate structures 1710 provided at one end of the second connection segment 171 connected to the first surface 11T of the substrate 11, for example, have the same width L in the third direction A3. Of course, they may also have different widths. In other embodiments, one end of the second connection segment 171 connected to the first surface 11T of the substrate 11 is a monolithic structure instead of a plurality of dentate structures 1710 spaced from each other.

[0063] In some embodiments, referring to Figure 1 、 Figure 2 and Figure 3A the third terminal 18 includes a first part encapsulated in the encapsulation body 15 and a second part extending from the first side wall SW1 of the encapsulation body 15 and exposed outside the encapsulation body 15; the fourth terminal 19 includes a first part encapsulated in the encapsulation body 15 and a second part extending from the first side wall SW1 of the encapsulation body 15 and exposed outside the encapsulation body 15; in the third direction A3, the second part of the fourth terminal 19 is located between the second part of the third terminal 18 and the first lead segment 163, and any two of the second part of the fourth terminal 19, the second part of the third terminal 18, and the first lead segment 163 are spaced apart. Furthermore, referring to Fig.10The second portion of the third terminal 18 is bent along a direction away from the bottom surface 15B of the package body 15 to form a second longitudinal portion 183, and the bending angle α is, for example, 80 degrees to 100 degrees; the second portion of the fourth terminal 19 is bent along a direction away from the bottom surface 15B of the package body 15 to form a first longitudinal portion 193, and the bending angle α is, for example, 80 degrees to 100 degrees; in the second direction A2, the first longitudinal portion 193 and the second longitudinal portion 183 are both located between the package body 15 and the end surface 163S of the first lead-out section 163 away from the package body 15.

[0064] In some embodiments, see Fig. 9 , a width d9 of the first lead-out section 163 in the third direction A3 is greater than a distance d8 between two opposite side surfaces of the third terminal 18 and the fourth terminal 19 in the third direction A3.

[0065] In some embodiments, see Fig. 9 In the direction away from the bottom surface 15B of the package body 15, the first longitudinal portion 193, for example, includes a first lower end parallel portion 193a, a first arc portion 193b and a first upper end parallel portion 193c arranged in sequence; in the direction away from the bottom surface 15B of the package body 15, the second longitudinal portion 183, for example, includes a second lower end parallel portion 183a, a second arc portion 183b and a second upper end parallel portion 183c arranged in sequence; the distance d6 between the first lower end parallel portion 193a and the second lower end parallel portion 183a is smaller than the distance d7 between the first upper end parallel portion 193c and the second upper end parallel portion 183c, and the radius R of each of the first arc portion 193b and the second arc portion 183b is, for example, 5-8mm.

[0066] In some embodiments, Fig. 9 As shown, the curvature of the first arc-shaped portion 193b is smaller than the curvature of the second arc-shaped portion 183b; and, in the first direction A1, the distance d10 from the interface between the first lower end parallel portion 193a and the first arc-shaped portion 193b to the bending point of the second portion of the fourth terminal 19 (i.e., the portion exposed outside the package body 15) is, for example, 2-4 mm.

[0067] In some embodiments, see Figure 3A, the first connecting section 161 has a water vapor blocking groove 1616, such as a V-shaped groove, at one end close to the first lead-out section 163, which prevents water vapor from entering the package body 15; the second connecting section 171 has a water vapor blocking groove 1716, such as a V-shaped groove, at one end close to the second lead-out section 173, which prevents water vapor from entering the package body 15. It is worth mentioning that the depth and width of the water vapor blocking groove 1616 and the water vapor blocking groove 1716 are not specifically limited.

[0068] In some embodiments, see Fig.12 Each cantilever 1613 is provided with a through slot 1613g penetrating the top surface 1613U and the bottom surface 1613L of the cantilever 1613. The through slot 1613g extends along the second direction A2, from the recessed portion 1613a of the cantilever 1613 closest to the head end connection portion 1611, through each of the protruding portions 1613b of the cantilever 1613, and extends to the recessed portion 1613a of the cantilever 1613 closest to the terminal connection portion 1615. Here, the top surface 1613U of the cantilever 1613 is the surface of the cantilever 1613 facing away from the chip 13, and the bottom surface 1613L of the cantilever 1613 is the surface of the cantilever 1613 facing the chip 13. Since each cantilever 1613 is provided with the through groove 1613g, it helps to prevent the connection material 141 on the surface of the chip 13, such as welding material, from overflowing during welding, and it helps to reduce the stress of the first terminal 16 during the process and use of the product, thereby improving the reliability of the product. Fig.12 The two chip groups shown have a total of four chips 13 as a schematic example. A through groove 1613g is provided on the two cantilevers 1613. The through groove 1613g is a slender strip-shaped through groove, which extends in the second direction A2 from one of the two recessed portions 1613a through the raised portion 1613b between the two recessed portions 1613a and to the other recessed portion 1613a.

[0069] In some embodiments, see Fig.12, the first connection section 161 also includes an intermediate connection portion 1617, the intermediate connection portion 1617 is located between the head end connection portion 1611 and the terminal connection portion 1615 in the second direction A2, the intermediate connection portion 1617 is located between the protrusions 1613b of the two adjacent cantilevers 1613 in the third direction A3, and the intermediate connection portion 1617 connects the protrusions 1613b of the two adjacent cantilevers 1613. By providing the intermediate connection portion 1617 and the terminal connection portion 1615, on the one hand, the stability of the first terminal 16 itself can be improved, so that it is not easy to deform during the product production process, and on the other hand, the imbalance of the current flowing through the first electrode pad S of each chip 13 can be effectively reduced. Still with Fig.12 The two chip groups shown have a total of four chips 13 as a schematic example, and each of the two cantilevers 1613 has two recessed portions 1613a and a raised portion 1613b located between the two recessed portions 1613a, and the intermediate connecting portion 1617 is connected between the two raised portions 1613b of the two cantilevers 1613 in the third direction A3. It is worth mentioning that in other embodiments, the number of the intermediate connecting portions 1617 can be multiple, and in the third direction A3, the raised portions 1613b of each two adjacent cantilevers 1613 are connected by one intermediate connecting portion 1617.

[0070] In some embodiments, see Fig.12The substrate 11 includes an insulating layer 110 and a current-carrying layer 112 disposed on the insulating layer 110, and the multiple chip groups are located on a side of the current-carrying layer 112 away from the insulating layer 110; the surface of each chip 13 in the multiple chip groups away from the substrate 11 is also configured with a third electrode pad G and a fourth electrode pad K; the current-carrying layer 112 includes a power area 1121, a driving area 1123 and another driving area 1125 spaced apart from each other in the second direction A2, and the driving area 1123 is located between the power area 1121 and the another driving area 1125; the multiple chip groups are disposed in the power area 1121, and the driving area 1123 is provided with multiple resistors 12, and the power semiconductor packaging structure also includes a first The third terminal 18 and the fourth terminal 19, the first terminal 16, the third terminal 18 and the fourth terminal 19 are arranged in a spaced relationship in the third direction A3, the third terminal 18 is connected to the driving area 1123 through a metal bonding wire BW, the third electrode pad G of each chip 13 in the plurality of chip groups is connected to the surface of the plurality of resistors 12 away from the current-carrying layer 112 through a metal bonding wire BW, and the fourth terminal 19 is connected to the other driving area 1125 through a metal bonding wire BW to connect to the fourth electrode pad K of each chip 13 in the plurality of chip groups, that is, the fourth electrode pad K of each chip 13 in the plurality of chip groups is connected to the other driving area 1125 through a metal bonding wire BW. Fig.12 The two chip groups shown have a total of four chips 13 as a schematic example, and each chip 13 is connected to a surface of a resistor 12 facing away from the current-carrying layer 112 through a metal bonding wire BW, and different chips 13 are connected to different resistors 12; furthermore, the two chips 13 in each chip group are connected to the other driving area 1125 through the metal bonding wire BW in a cascade manner, for example, a fourth electrode pad K of one of the two chips 13 is connected to a fourth electrode pad K of the other chip 13 through the metal bonding wire BW, and another fourth electrode pad K of the other chip 13 is further connected to the other driving area 1125 through the metal bonding wire BW.

[0071] In some embodiments, see Fig.12 A concave portion 1123u is provided on a side of the driving area 1123 facing the other driving area 1125, and a convex portion 1125n is provided on a side of the other driving area 1125 facing the driving area 1123, and the convex portion 1125n corresponds to the concave portion 1123u in position.

[0072] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1. A power semiconductor packaging structure, characterized in that: include: A substrate having a first surface and a second surface disposed opposite to each other; A chip is arranged on the first surface of the substrate, a surface of the chip facing away from the substrate is provided with a first electrode pad, a surface of the chip facing the substrate is provided with a second electrode pad, and the second electrode pad is connected to the first surface of the substrate; A package body, encapsulating at least the first surface of the substrate and the chip, wherein the second surface of the substrate is at least partially exposed outside the package body; A first terminal, comprising a first connecting section and a first lead-out section, wherein the first connecting section is enclosed in the package body and connected to the first electrode pad of the chip, and the first lead-out section is exposed outside the package body; A second terminal, comprising a second connecting section and a second lead section, wherein the second connecting section is enclosed in the package body and connected to the substrate, and the second lead section is exposed outside the package body; The second connecting section has a lower surface facing the first surface of the substrate and an upper surface facing away from the first surface of the substrate, the lower surface of the second connecting section is connected to the substrate by welding or sintering through a connecting material located between the lower surface of the second connecting section and the first surface of the substrate, and the lower surface of the second connecting section is configured with a protruding structure.

2. The power semiconductor packaging structure according to claim 1, characterized in that: A recessed structure is disposed on the upper surface of the second connecting section at a position corresponding to the raised structure.

3. The power semiconductor packaging structure according to claim 2, characterized in that: In a first direction from the upper surface of the second connecting segment to the lower surface of the second connecting segment, a protruding height of the convex structure relative to the lower surface of the second connecting segment is equal to a concave depth of the concave structure relative to the upper surface of the second connecting segment; The protruding structure is formed by extruding from the upper surface of the second connecting section to the lower surface of the second connecting section.

4. The power semiconductor packaging structure according to claim 1, characterized in that: The protruding structure contacts or does not contact the first surface of the substrate, and an end of the protruding structure close to the first surface of the substrate is arc-shaped.

5. The power semiconductor packaging structure according to claim 1, characterized in that: In a first direction from the upper surface of the second connecting segment to the lower surface of the second connecting segment, a protruding height of the protruding structure relative to the lower surface of the second connecting segment is 0.02 mm-0.1 mm.

6. The power semiconductor packaging structure according to claim 1, characterized in that: The package body comprises a first side wall and a second side wall which are opposite to and spaced apart from each other, and a third side wall and a fourth side wall which are opposite to and spaced apart from each other, the third side wall is located between the first side wall and the second side wall and connects the first side wall and the second side wall, the fourth side wall is located between the first side wall and the second side wall and connects the first side wall and the second side wall, and the second lead section extends from the second side wall and is exposed outside the package body; In the third direction from the third side wall to the fourth side wall, the second connecting section includes a plurality of tooth-like structures spaced apart from each other, the surface of each tooth-like structure facing the first surface of the substrate is provided with the protruding structure, each tooth-like structure is connected to the first surface of the substrate by welding or sintering through the connecting material, and a locking hole penetrating the second terminal is provided at one end of each tooth-like structure close to the second lead-out section.

7. The power semiconductor packaging structure according to claim 6, characterized in that: In a second direction from the first side wall to the second side wall, the second lead-out section includes a front transverse portion, a first bending portion, a middle transverse portion, a second bending portion and a rear transverse portion connected in sequence, and the first bending portion, the middle transverse portion and the second bending portion together form an arched bending structure; In the second direction, the distance from the middle transverse portion to the package body is greater than 2 mm; The angle between the first bending portion and the front end transverse portion is 105 degrees to 165 degrees.

8. The power semiconductor packaging structure according to claim 1, characterized in that: The package body comprises a first side wall and a second side wall which are opposite to and spaced apart from each other, and a third side wall and a fourth side wall which are opposite to and spaced apart from each other, the third side wall is located between the first side wall and the second side wall and connects the first side wall and the second side wall, the fourth side wall is located between the first side wall and the second side wall and connects the first side wall and the second side wall, and the second lead section extends from the second side wall and is exposed outside the package body; The number of the chips is N, the N chips include a plurality of chip groups arranged at intervals in the third direction from the third sidewall to the fourth sidewall, and each of the chip groups includes M chips, where M is an integer greater than 1 and less than N; The first connecting section includes a plurality of cantilevers spaced apart in the third direction, each of the cantilevers includes M recessed portions spaced apart in the second direction from the first side wall to the second side wall and a protruding portion between each adjacent two of the recessed portions, the plurality of cantilevers correspond one-to-one to the plurality of chip groups, and the M recessed portions of each cantilever are connected one-to-one to each of the first electrode pads of the M chips of a corresponding chip group.

9. The power semiconductor packaging structure according to claim 6, characterized in that: The first lead-out section extends from the first side wall and is exposed outside the package body; The power semiconductor package structure further includes a third terminal, a surface of at least one chip facing away from the substrate is further provided with a third electrode pad, the third terminal is connected to the third electrode pad via a metal bonding wire, and a portion of the third terminal extends from the first side wall and is exposed outside the package body; The power semiconductor package structure further includes a fourth terminal, the fourth terminal being located between the first lead section and the third terminal in the third direction, and the fourth terminal being spaced apart from the first lead section and the third terminal in the third direction; The substrate includes an insulating layer and a current-carrying layer and a heat-dissipating layer respectively located on opposite sides of the insulating layer. The surface of the current-carrying layer facing away from the insulating layer is the first surface, the surface of the heat-dissipating layer facing away from the insulating layer is the second surface, and the second connecting section is connected to the current-carrying layer through the connecting material.

10. The power semiconductor packaging structure according to claim 9, characterized in that: The fourth terminal is formed by extending from an end of the first connecting section close to the first lead-out section toward a direction away from the first connecting section, and the fourth terminal, the first connecting section and the first lead-out section are an integral structure; and / or, The first surface of the substrate includes a power area and a driving area spaced apart from each other in the second direction, the area of ​​the power area is larger than the area of ​​the driving area, the chip is arranged in the power area, the third terminal is connected to the driving area through a metal bonding wire, and the third electrode pad is connected to the driving area through a metal bonding wire.

11. The power semiconductor packaging structure according to claim 9, characterized in that: The package body comprises a top surface and a bottom surface which are arranged opposite to each other, the first side wall, the second side wall, the third side wall and the fourth side wall are respectively connected to the top surface and the bottom surface, and the second surface of the substrate is exposed outside the package body at the side where the bottom surface of the package body is located; The portion of the fourth terminal exposed outside the package body is bent along a direction away from the bottom surface of the package body to form a first longitudinal portion, and the portion of the third terminal exposed outside the package body is bent along a direction away from the bottom surface of the package body to form a second longitudinal portion; in the second direction, the distance between each of the first longitudinal portion and the second longitudinal portion to the package body is greater than 2.8 mm, and the distance between the end surface of the first lead-out section away from the package body and each of the first longitudinal portion and the second longitudinal portion is greater than 0.3 mm; and, in the direction away from the bottom surface of the package body, the first longitudinal portion and the second longitudinal portion are first parallel to each other, then away from each other, and then parallel to each other again.

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