A flash chip three-dimensional package structure and a package method

Abstract

A FLASH chip three-dimensional stacked packaging structure and packaging method belong to the technical field of semiconductor chip packaging. Through wafer rewiring containing FLASH chip, multi-layer wiring substrate and wire bonding technology, the wafer rewiring technology is used to lead out the front electrode of the FLASH chip to the front of the chip and the back of the multi-layer substrate according to the setting, the copper column bump is formed for interconnection when stacking, the wire bonding and multi-layer substrate interconnection are used, and the flip chip packaging technology is used to realize the vertical stacking integration of the chip by interconnecting the substrate BGA and the copper column bump. The problems of difficult interconnection welding, limited electrode quantity layout, mismatch of thermal expansion coefficient between materials and high packaging cost in the prior art are solved, and high packaging density FLASH chip stacking packaging is realized. It is widely used in the technical field of high-performance, low-cost microsystem SiP packaging.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor chip packaging technology, and more specifically to the field of three-dimensional semiconductor chip packaging technology. In particular, it relates to a three-dimensional stacked packaging structure and packaging method for FLASH chips. Background Technology

[0002] Embedded FLASH memory simplifies the design and connection process by integrating memory chips, controllers, and interfaces, providing a convenient, compact, and highly integrated storage solution, widely used in embedded systems and mobile devices. To meet the demand for low-cost FLASH chip packaging with high integration and miniaturization, 3D stacking packaging technology is currently one of the most important packaging technologies. Chip stacking through redistribution, bumps, and through-silicon vias (TSVs) is the most widely used 3D stacking packaging technology; however, this type of packaging technology is costly and only suitable for high-integration memory stacking packages like HBM. For memory chips with low to medium package density (such as eMMC chips), stacking through redistribution, bumps, and TSVs is also costly. Therefore, achieving low-to-medium density memory chip stacking packaging based on the low-cost advantages of traditional packaging and the flexibility of redistribution and bumps is a technical challenge that urgently needs to be overcome.

[0003] Existing technical defects:

[0004] Driven by the demands of electronic devices for high-performance, miniaturized, and modular chips, traditional two-dimensional system integration methods using multiple FLASH chips are no longer sufficient to meet these requirements. For example... Figure 1As shown, although current packaging technology designs have achieved multi-layer chip stacking, the number and layout of electrodes on the packaged chips limit the integration of memory chips with higher packaging density. For example, Chinese patent application CN117790483A discloses a computing-memory integrated chip stacking packaging structure, which integrates computing chips and memory chips by stacking chips in a staggered manner on a carrier board (multi-layer substrate), interconnecting the chips and the carrier board through wire bonding, and interconnecting the back of the carrier board through BGA. Chinese patent application CN117612952A discloses an LGA packaging stacking method and structure, which mainly uses soft glue to form a stepped mold, then stacks the chips in a Z-shape on the mold, and interconnects them through wire bonding. Both of these methods achieve memory chip stacking packaging through staggered stacking, and this type of staggered stacking packaging structure has significant limitations and restricted applications. Chinese patent application number CN117878064A discloses a method for vertical stacking. By bonding the memory chip leads to the substrate, and using redistribution technology to distribute the chip electrodes on the back of the substrate, an intermediate stacked chip-substrate structure with vertical interconnect structure is fabricated in the same way. This type of solution has difficulty in interconnect soldering during stacking, and the redistribution and interconnect structure fabrication are carried out after mounting on the substrate. Due to the mismatch of thermal expansion coefficients between different materials, the risk of misalignment of the stacked structure is relatively large.

[0005] In view of this, the present invention is hereby proposed. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to solve the problems of difficult interconnection and welding, limited electrode number layout, mismatch of thermal expansion coefficients between materials, and high packaging cost in the prior art when chips are stacked in a staggered or vertical manner on a carrier board (multilayer substrate).

[0007] The inventive concept of this invention is as follows: by using wafer redistribution, multilayer wiring substrate and wire bonding technology, the front electrode of the FLASH chip is divided into two parts and led out to the front of the chip and the back of the multilayer substrate respectively. The FLASH chip electrode is led out as a dual electrode by using wafer redistribution technology, and copper pillar bumps are formed for interconnection during stacking. The chip is interconnected with the multilayer substrate by wire bonding. The chip is vertically stacked and integrated by using flip-chip packaging technology to interconnect the substrate BGA and copper pillar bumps.

[0008] Therefore, the present invention provides a three-dimensional stacked packaging structure for FLASH chips, such as... Figure 2 As shown. Includes:

[0009] FLASH chip 1, chip top electrode 101, chip surface redistribution layer 2, chip surface redistribution passivation layer 3, chip surface redistribution interconnect copper pillar 4, multilayer substrate 5, substrate wiring circuit 501, chip bonding layer 6, bonding wire 7, molding compound 8, substrate BGA 9, interlayer filler layer 10.

[0010] The back side of the multilayer substrate 5 is substrate BGA9, and the front side is the chip bonding area and the wire bonding area. Substrate BGA9 is connected to the chip bonding area and the wire bonding area through wiring circuit 501 in the substrate.

[0011] The FLASH chip 1 is bonded to the chip bonding area through the chip bonding layer 6.

[0012] The chip surface redistribution passivation layer 3 is located on the surface of the FLASH chip 1.

[0013] The chip surface redistribution layer 2 is located on the surface of the chip surface redistribution passivation layer 3. The lead bonding area and the chip surface redistribution interconnect copper pillar 4 on the surface of the chip surface redistribution layer 2 are connected to the electrodes (on-chip electrodes 101) on the chip surface.

[0014] The lead bonding area on the surface of the redistribution layer 2 of the chip and the lead bonding area on the front side of the multilayer substrate 5 are bonded together by bonding leads 7 according to the circuit connection specifications.

[0015] The substrate and chip are sealed and bonded by the molding layer 8, with the upper surface of the chip surface redistribution interconnect copper pillars 4 exposed and the bottom surface of the substrate BGA9 exposed, forming a FLASH chip packaging unit.

[0016] The FLASH chip packaging unit consists of two or more units, with an interlayer filler layer 10 between adjacent FLASH chip packaging units. The upper substrate BGA9 is soldered to the lower chip surface redistribution interconnect copper pillars 4.

[0017] The packaging method of the three-dimensional stacked packaging structure of the FLASH chip, such as Figure 3-4 As shown. Includes the following steps:

[0018] Step S1: Fabrication of multilayer wiring substrate and preparation of FLASH chip wafer;

[0019] Step S2: Redewire the FLASH wafer surface to bring out the electrodes on the FLASH chip to the designed location.

[0020] Step S3: Fabricate copper pillars on the intermediate layers (excluding the top layer) and the redistribution layers of the bottom layer;

[0021] Step S4: Thin and dic the FLASH wafer that has been rewired and made of copper pillars;

[0022] Step S5: Mount the thinned FLASH chip onto the multilayer substrate;

[0023] Step S6: Interconnect the redistribution leads to the multilayer substrate design electrodes via wire bonding;

[0024] Step S7: Apply a molding compound to protect the wire bonding structure, exposing the top copper pillars and the back of the substrate;

[0025] Step S8: Perform metal BGA balling on the back of the substrate to form a FLASH chip packaging unit;

[0026] Step S9: According to the settings, with the top layer FLASH chip package unit as the base and the BGA side facing up, the top of the set layer FLASH chip package unit is sequentially soldered to the corresponding position of the bottom BGA of the lower layer chip using a flip-chip method.

[0027] Step S10: Fill the gaps between the FLASH chip packaging units with interlayer filler layer 10 and cure it to obtain a FLASH chip with a three-dimensional stacked packaging structure.

[0028] Technical effects of the present invention:

[0029] By re-laying the electrodes of the FLASH chip into a dual-electrode structure using wafer redistribution and bump technology, and using wire bonding technology to achieve bottom interconnection of the chip, and flip-chip packaging technology to achieve top interconnection of the chip, the three-dimensional stacking of FLASH chips is realized.

[0030] It changes the traditional method of misaligned stacking and wire bonding interconnection, and achieves low-cost three-dimensional vertical stacking by using mature and low-cost wafer redistribution technology, flip-chip technology and wire bonding technology, thereby reducing the package area.

[0031] It breaks through the limitations of traditional FLASH chip misaligned stacking packaging structure, and avoids the use of expensive wafer-level 3D packaging technology.

[0032] It achieves high-density packaging while also reducing the package size.

[0033] It achieves high-density, low-cost FLASH chip stacking packaging, with a larger stacking quantity than traditional staggered wire bonding stacking, and a smaller packaged product size. The stacking packaging cost is lower than wafer-level 3D packaging, and the packaging process technology is less difficult.

[0034] It can be widely used in the field of high-performance, low-cost microsystem SiP packaging technology. Attached Figure Description

[0035] Figure 1 This is a schematic diagram of an existing FLASH chip stacking and packaging structure.

[0036] Figure 2 This is a schematic diagram of the three-dimensional stacked packaging structure of the FLASH chip of the present invention.

[0037] Figure 3 This is a schematic flowchart of the FLASH chip three-dimensional stacking packaging process of the present invention.

[0038] Figure 4 This is a schematic diagram of the three-dimensional stacking and packaging process of the FLASH chip of the present invention.

[0039] Figure 5 This is a schematic diagram of the interconnection structure of the intermediate layer of the single FLASH chip stacked package according to the present invention.

[0040] Figure 6 This is a schematic diagram of the interconnection structure of the intermediate layer of the dual FLASH chip stacked package of the present invention.

[0041] Figure 7 This is a schematic diagram of the bump array in the intermediate layer of the single FLASH chip stacked package of the present invention.

[0042] In the diagram: 1 is the FLASH chip (referred to as chip), 101 is the top electrode of the chip, 2 is the redistribution layer on the chip surface (referred to as redistribution layer), 3 is the passivation layer on the chip surface redistribution (referred to as passivation layer), 4 is the copper pillar for redistribution interconnection on the chip surface (referred to as copper pillar bump or copper pillar), 401 is the copper pillar metal barrier layer (referred to as barrier layer), 5 is the multilayer substrate (referred to as substrate), 501 is the wiring circuit in the substrate, 6 is the chip bonding layer, 7 is the bonding wire (referred to as lead or bonding wire), 8 is the molding layer, 9 is the substrate BGA (referred to as BGA), and 10 is the interlayer filler layer (referred to as filler layer). Detailed Implementation

[0043] like Figure 2-7 As shown, the specific implementation of the FLASH chip three-dimensional stacked packaging structure and packaging method is as follows:

[0044] The FLASH chip is square, with dimensions ranging from 3mm*3mm to 15mm*15mm.

[0045] The redistribution layer forms a dual-electrode interconnect when the chip electrodes are led out, namely a first electrode and a second electrode. The first electrode is used for stacking to interconnect corresponding electrodes on the multilayer substrate using wire bonding, while the second electrode is used for stacking to interconnect corresponding electrodes on the multilayer substrate using flip-chip bonding. The electrode density is 10 pins / mm. 2 ~200 pins / mm 2The redistribution wire is made of copper. The electrodes are formed on the surface of the redistribution wire by electrochemical copper plating, chemical nickel-palladium-gold plating, etc. The redistribution wire width is 2μm to 30μm, the redistribution wire spacing is 2μm to 30μm, and the redistribution wire thickness is 1μm to 20μm.

[0046] The copper pillar protrusions are cubic or cylindrical, with a width / diameter of 80μm to 600μm and a height higher than the height of the encapsulation. They are distributed inside the wire bonding electrode and the distribution types include ring distribution, array distribution, etc.

[0047] The metal barrier layer is located on the top surface of the copper pillar protrusion. The barrier layer is a nickel barrier layer with a thickness of 1μm to 5μm.

[0048] The multilayer substrate includes multilayer wiring ceramic substrate (multilayer co-fired ceramic substrate), organic substrate, etc. The multilayer substrate is wired with copper metal inside. The upper electrode is higher than the substrate plane and is distributed in the periphery of the multilayer substrate. The electrode size is 40μm * 40μm to 600μm * 600μm. The electrode material is copper, copper-nickel-gold, etc.

[0049] The lead wire (bonding wire) is made of copper wire, gold wire, etc., with a wire diameter of 10μm to 30μm.

[0050] The number of chips mounted on each multilayer substrate is at least one.

[0051] The diameter of the BGA ball is the same as the width or diameter of the copper pillar bump, and the material of the BGA is tin-lead, tin-silver-copper, etc.

[0052] The following is an example of a single-chip structure per layer:

[0053] The 12-inch wafers that have completed FLASH chip manufacturing are rewired, and the electrodes on the chip are led out to the designed locations through the rewires, presenting a dual-electrode shape (first electrode and second electrode). The rewire layer is made of copper, and a seed layer is deposited by magnetron sputtering, followed by electrochemical deposition. The linewidth / line spacing is 10μm / 10μm, and the thickness is 5μm.

[0054] The first electrode is evenly distributed around the FLASH chip, with a size of 65μm*65μm, made of copper, and the electrode height is 10μm higher than the passivation layer.

[0055] The second electrode is uniformly distributed inside the first electrode of the FLASH chip. A cylindrical copper pillar with a diameter of 90 μm and a height of 100 μm is fabricated on the second electrode, and a 3 μm thick nickel barrier layer is deposited on the copper pillar by electrochemical deposition.

[0056] The FLASH wafers that have been rewired and fabricated with copper pillars are thinned and diced to a thickness of 150μm. After dicing, the chip size is 12mm*4.9mm.

[0057] The substrate is an LTCC multilayer co-fired ceramic substrate. The front electrodes are distributed around the perimeter of the substrate, and the back electrodes are located directly below the second electrode of the mounted FLASH chip. The electrode dimensions are 80μm*80μm*20μm, and the material is copper. The substrate dimensions are 13.5mm*6.5mm*0.2mm.

[0058] The diced chip is then mounted onto an LTCC multilayer co-fired ceramic substrate. The first electrode is then interconnected with the front electrode of the multilayer substrate using copper wires with a diameter of 20 μm, and finally encapsulated with epoxy molding compound (EMC) to protect the wire bonding structure. The copper pillars are higher than the overall encapsulation height.

[0059] BGA balls were implanted on the back electrode of a multilayer substrate. The material was SAC305 and the ball diameter was 120μm to obtain a stacked chip structure layer.

[0060] The stacked chip structure layers are stacked and integrated according to the set structure using flip-chip bonding, and finally interlayer filling is performed to obtain a four-layer single FLASH chip stacked package structure.

[0061] The following is an example of a dual-chip structure per layer:

[0062] The 12-inch wafers that have completed FLASH chip manufacturing are rewired, and the electrodes on the chip are led out to the designed locations through the rewire, presenting a dual-electrode shape (first electrode and second electrode). The rewire layer is made of copper, and is fabricated by depositing a seed layer by magnetron sputtering followed by electrochemical deposition, with a linewidth / line spacing of 10μm / 10μm and a thickness of 5μm.

[0063] The first electrode is evenly distributed around the three sides of the FLASH chip, with a size of 65μm*65μm and made of copper. The electrode height is 10μm higher than the passivation layer.

[0064] The second electrode is uniformly distributed inside the first electrode of the FLASH chip. A cylindrical copper pillar with a diameter of 90 μm and a height of 100 μm is fabricated on the second electrode, and a 3 μm thick nickel barrier layer is deposited on the copper pillar by electrochemical deposition.

[0065] The FLASH wafers that have completed rewiring and copper pillar fabrication are thinned and diced to a thickness of 150μm. After dicing, the chip size is 12mm*4.9mm.

[0066] The substrate is an LTCC multilayer co-fired ceramic substrate. The front electrodes are distributed around the perimeter of the substrate, and the back electrodes are located directly below the second electrode of the mounted FLASH chip. The electrode dimensions are 80μm*80μm*20μm. The front electrode material is copper-nickel-gold, and the back electrode material is copper. The substrate dimensions are 13.5mm*13.5mm*0.2mm, with a chip spacing of 1mm.

[0067] The diced chip is then mounted onto an LTCC ceramic multilayer substrate. The first electrode is then interconnected with the front electrode of the multilayer substrate using 18μm diameter gold wires, and EMC encapsulation is performed to protect the wire bonding structure. The copper pillars are higher than the overall encapsulation height.

[0068] BGA balls were implanted on the back electrode of a multilayer substrate. The material was SAC305 and the ball diameter was 120μm to obtain a stacked chip structure layer.

[0069] The stacked chip structure layers are stacked and integrated according to the set structure using flip-chip bonding, and finally interlayer filling is performed to obtain a four-layer dual FLASH chip stacked package structure.

[0070] This invention can achieve an electrode density of 10 pins / mm 2 ~200pin / mm 2 The stacked packaging of FLASH chips has a larger number of stacks than traditional staggered wire bonding stacking, and the packaged product is smaller in size; the cost of stacked packaging is lower than wafer-level 3D packaging, and the packaging process technology is less difficult.

[0071] Finally, it should be noted that the above embodiments are merely examples for clear illustration. This invention includes, but is not limited to, the above embodiments, and it is neither necessary nor possible to exhaustively describe all possible implementations. Those skilled in the art can make other variations or modifications based on the above description. All implementation schemes that meet the requirements of this invention are within the protection scope of this invention.

Claims

1. A three-dimensional stacked packaging structure for FLASH chips, characterized in that: Includes FLASH chip, chip surface redistribution layer, chip surface redistribution passivation layer, chip surface redistribution interconnect copper pillar, multilayer substrate, chip bonding layer, bonding wire, molding compound layer, substrate BGA, and interlayer filler layer. The back of the multilayer substrate is a substrate BGA, and the front is a chip bonding area and a wire bonding area. The substrate BGA is connected to the chip bonding area and the wire bonding area through wiring circuits in the substrate. The FLASH chip is bonded to the chip bonding area via a chip bonding layer; The chip surface redistribution passivation layer is located on the surface of the FLASH chip; The chip surface redistribution layer is located on the surface of the chip surface redistribution passivation layer, and the lead bonding area and the chip surface redistribution interconnect copper pillars on the surface of the chip surface are connected to the on-chip electrodes on the chip surface. The lead bonding area on the redistribution layer surface of the chip and the lead bonding area on the front side of the multilayer substrate are bonded together by bonding leads according to the circuit connection specifications. After the substrate and chip are sealed and bonded by the molding layer, the upper surface of the chip surface redistribution interconnect copper pillars is exposed, and the bottom surface of the substrate BGA is exposed, forming a FLASH chip packaging unit. The FLASH chip packaging unit consists of two or more units, with an interlayer filler layer between two adjacent FLASH chip packaging units. The upper substrate BGA is soldered to the lower chip surface redistribution interconnect copper pillars.

2. The FLASH chip three-dimensional stacked packaging structure as described in claim 1, characterized in that: The FLASH chip is square, with dimensions ranging from 3mm*3mm to 15mm*15mm.

3. The FLASH chip three-dimensional stacked packaging structure as described in claim 1, characterized in that: The redistribution layer forms the first and second interconnects when the chip electrodes are led out, and the electrode density of the redistribution layer is 10 pins / mm. 2 ~200 pins / mm 2 The rewire width is 2μm to 30μm, the rewire spacing is 2μm to 30μm, and the rewire thickness is 1μm to 20μm.

4. The FLASH chip three-dimensional stacked packaging structure as described in claim 1, characterized in that: The redistribution layer is made of copper, and the electrodes of the redistribution layer are formed on the redistribution surface by electrochemical copper plating or electroless nickel-palladium-gold plating.

5. The FLASH chip three-dimensional stacked packaging structure as described in claim 1, characterized in that: The copper pillars are located inside the wire bonding electrodes and are distributed in a ring or array. The copper pillars are cubic or cylindrical, with a width / diameter of 80μm to 600μm and a height greater than the thickness of the encapsulation.

6. The FLASH chip three-dimensional stacked packaging structure as described in claim 1, characterized in that: The top surface of the copper pillar is a metal barrier layer.

7. The FLASH chip three-dimensional stacked packaging structure as described in claim 6, characterized in that: The barrier layer is a nickel barrier layer with a thickness of 1μm to 5μm.

8. The FLASH chip three-dimensional stacked packaging structure as described in claim 1, characterized in that: The multilayer substrate is a multilayer co-fired ceramic substrate or a multilayer organic substrate. The multilayer substrate is wired with copper metal. The upper electrode is higher than the substrate plane and is distributed in the periphery of the multilayer substrate. The electrode size is 40μm * 40μm to 600μm * 600μm. The electrode material is copper or copper-nickel-gold.

9. The FLASH chip three-dimensional stacked packaging structure as described in claim 1, characterized in that: The lead wire is made of copper or gold wire with a diameter of 10μm to 30μm.

10. The FLASH chip three-dimensional stacked packaging structure as described in claim 1, characterized in that: The number of chips mounted on each multilayer substrate is at least one.

11. The FLASH chip three-dimensional stacked packaging structure as described in claim 1, characterized in that: The ball diameter of the BGA is the same as the width or diameter of the copper pillar, and the material of the BGA is a tin-lead alloy or a tin-silver-copper alloy.

12. The packaging method for a three-dimensional stacked packaging structure of a FLASH chip as described in claim 1, characterized in that, Includes the following steps: Step S1: Fabrication of multilayer wiring substrate and preparation of FLASH chip wafer; Step S2: Redewire the FLASH wafer surface to bring out the electrodes on the FLASH chip to the designed location. Step S3: Fabricate copper pillars on the redistribution layer; Step S4: Thin and dic the FLASH wafer that has been rewired and made of copper pillars; Step S5: Mount the thinned FLASH chip onto the multilayer substrate; Step S6: Interconnect the redistribution leads to the multilayer substrate design electrodes via wire bonding; Step S7: Apply a molding compound to protect the wire bonding structure, exposing the top copper pillars and the back of the substrate; Step S8: Perform metal BGA balling on the back of the substrate to form a FLASH chip packaging unit; Step S9: According to the settings, with the top layer FLASH chip package unit as the base and the BGA side facing up, the top of the set layer FLASH chip package unit is sequentially soldered to the corresponding position of the bottom BGA of the lower layer chip using a flip-chip method. Step S10: Fill the gaps between the FLASH chip packaging units with interlayer filler layers and then cure them to obtain a FLASH chip with a three-dimensional stacked packaging structure.

13. The packaging method for a three-dimensional stacked packaging structure of a FLASH chip as described in claim 1, characterized in that: The redistribution layer is first deposited as a seed layer by magnetron sputtering, and then fabricated by electrochemical deposition. The linewidth / spacing is 10 μm / 10 μm, and the thickness is 5 μm.

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