System and method for duty cycle characterization

Abstract

A method includes: coupling a first signal to an impedance; determining a first average current of the first signal passing through the impedance for a first time, the first average current corresponding to a duty cycle of the first signal; coupling the second signal to the impedance; determining a second average current of the second signal passing through the impedance for a second time, the second average current corresponding to the first duty cycle of the second signal; determining a first work period according to the first average current and the second average current; determining a third average current of the second signal passing through the impedance for a third time, the third average current corresponding to a second duty cycle of the second signal; determining a second work period according to the first average current and the third average current; and averaging the first duty cycle and the second duty cycle.

Description

Technical Field

[0001] The present invention relates to a system and method for duty cycle characterization. Background Art

[0002] Electronic circuits are often used to measure timing quantities between signal timings, such as jitter, duty cycle, pulse width, frequency, and signal delay. These electronic circuits are typically included in at least one integrated circuit (IC) manufactured in a semiconductor process. Typically, one or more timing measurement circuits are included in the electronic circuit to perform the timing measurement. The timing measurement circuits are complex circuits that use a large area of ​​silicon. In addition, calibrating the timing measurement circuits increases the cost of owning and operating the electronic circuit.

[0003] Typically, duty cycle characterization is critical in electronic circuits including built-in self-test (BIST) and / or level shifters. In addition, high-speed duty cycle characterization is required and more challenging than low-speed duty cycle characterization. Summary of the invention

[0004] According to an embodiment of the present invention, a method for duty cycle characterization includes: coupling a first signal to an impedance; determining a first average current of the first signal passing through the impedance within a first time, the first average current corresponding to the duty cycle of the first signal; coupling a second signal to the impedance; determining a second average current of the second signal passing through the impedance within a second time, the second average current corresponding to the first duty cycle of the second signal; determining the first duty cycle based on the first average current and the second average current; determining a third average current of the second signal passing through the impedance within a third time, the third average current corresponding to the second duty cycle of the second signal; determining the second duty cycle based on the first average current and the third average current; and averaging the first duty cycle and the second duty cycle to obtain an average duty cycle of the second signal.

[0005] According to an embodiment of the present invention, a method for duty cycle characterization includes: coupling a DC signal to an impedance; determining a first current of the DC signal passing through the impedance; coupling a periodic signal to the impedance; determining a second current of the periodic signal passing through the impedance to reach a reference voltage VSS within a first number of clock cycles of the periodic signal; determining a first duty cycle based on the first current and the second current; determining a third current of the periodic signal from a power supply VDD through the impedance within a second number of clock cycles of the periodic signal; determining a second duty cycle based on the first current and the third current; and averaging the first duty cycle and the second duty cycle to determine the duty cycle of the periodic signal.

[0006] According to an embodiment of the present invention, a system for duty cycle characterization includes a logic circuit, an impedance, and a measurement circuit. The logic circuit has at least one input and an output, the at least one input is configured to receive a first signal and a second signal, and the output is configured to provide a first output signal corresponding to the first signal and a second output signal corresponding to the second signal. The impedance is connected to the output and configured to receive the first output signal and the second output signal. The measurement circuit is connected to the impedance and configured to determine a first average current passing through the impedance based on the first output signal, determine a second average current passing through the impedance to a reference voltage based on the second signal, and determine a third average current from a power source through the impedance based on the second signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a diagram schematically illustrating a resistor configured to receive an input signal IN and an ammeter configured to measure an output current Iout flowing through the resistor according to some embodiments.

[0008] Figure 2 is a diagram schematically illustrating a DC input signal and a DC output current Idc according to some embodiments.

[0009] Figure 3 is a diagram schematically illustrating an average output current Ix through a resistor due to a periodic signal according to some embodiments.

[0010] Figure 4 is a diagram schematically illustrating a periodic signal with a non-linear fall time that may cause errors in duty cycle characterization, according to some embodiments.

[0011] Figure 5 is a diagram schematically illustrating that as the frequency of a periodic signal increases, nonlinear rise and fall times become a larger portion of the periodic signal, according to some embodiments.

[0012] Figure 6 is a diagram schematically illustrating a first circuit for determining a first duty cycle based on a time interval during which a periodic signal is at a high voltage, according to some embodiments.

[0013] Figure 7 is a diagram schematically illustrating a periodic signal having nonlinear rise and fall times biased toward the “1” region and an average output current Ia according to some embodiments.

[0014] Figure 8 is a diagram schematically illustrating a second circuit for determining a second duty cycle of a periodic signal based on a time interval during which the periodic signal is at a low voltage, according to some embodiments.

[0015] Fig. 9 is a diagram schematically illustrating a periodic signal having nonlinear rise and fall times unfavorable to the “0” region and an average output current Ib according to some embodiments.

[0016] Fig.10 is a diagram schematically illustrating a system for duty cycle characterization according to some embodiments.

[0017] Fig.11 is a diagram schematically illustrating a logic circuit according to some embodiments.

[0018] Fig.12 is a diagram schematically illustrating a measurement circuit according to some embodiments.

[0019] Fig.13 is a graph schematically illustrating a percentage of error in a TCC duty cycle measurement for a first duty cycle of a periodic signal, according to some embodiments.

[0020] Fig.14 is a graph schematically illustrating the error percentage of Error_TCC vs Out with respect to the frequency of the periodic input signal IN according to some embodiments.

[0021] Fig.15 is a diagram schematically illustrating a percentage error in a TCC duty cycle measurement of a first duty cycle of a periodic signal and a percentage error in a TCC duty cycle measurement of a second duty cycle of the periodic signal, according to some embodiments.

[0022] Fig.16 is a diagram schematically illustrating averaging a first duty cycle measurement value and a second duty cycle measurement value to obtain an average duty cycle with an error percentage closer to 0% according to some embodiments.

[0023] Fig.17 is a graph schematically illustrating the percentage of error in TCC duty cycle measurements for a periodic signal having a 40% duty cycle, according to some embodiments.

[0024] Fig.18 is a diagram schematically illustrating averaging a first duty cycle measurement value and a second duty cycle measurement value to obtain an average duty cycle with an error percentage closer to 0% according to some embodiments.

[0025] Fig.19 is a diagram schematically illustrating a method of obtaining an average duty cycle measurement value according to some embodiments.

[0026] Fig. 20 is a diagram schematically illustrating another method of obtaining an average duty cycle measurement value according to some embodiments.

[0027] Fig.21 is a block diagram schematically illustrating an example of a computer system configured to provide the presently disclosed semiconductor device according to some embodiments.

[0028] Fig. 22 is a block diagram of a semiconductor device manufacturing system and a semiconductor device manufacturing process associated therewith according to some embodiments. DETAILED DESCRIPTION

[0029] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0030] The following disclosure provides many different embodiments or examples for implementing the different features of the provided target. Specific examples of components and arrangements are described below to simplify the disclosure. Of course, these are only examples and are not intended to be limiting. For example, the following description of forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, rather than representing the relationship between the various embodiments and / or configurations discussed.

[0031] Additionally, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," and the like may be used herein to describe the relationship of one component or feature to another (other) component or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0032] Duty cycle characterization is a key specification in some electronic circuits, such as transmit / receive (TX / RX) post-driver circuits and high-speed ring oscillators (RO). As described herein, based on the concept of energy conservation, a time to current conversion (TCC) circuit can be used to convert time intervals (e.g., time intervals during which a periodic signal is high) into current. The duty cycle of a periodic signal (i.e., the percentage of time that the periodic signal is high) can be determined based on this current measurement and the current measurement of another signal with a known duty cycle. For example, the duty cycle of a periodic signal such as a clock signal can be determined based on the ratio of the average current of the periodic signal through an impedance divided by the average current of a direct current (DC) current through the impedance. Each of the signals passes through an impedance such as a resistor, and the ratio of the average current due to the periodic signal divided by the DC current is the duty cycle, which can be divided by the frequency (i.e., multiplied by the period of the periodic signal) to provide the time that the periodic signal is high. This duty cycle characterization for low speed clock signals provides low errors, such as 0.02% error at 100 mega-Hertz (MHz). However, this type of duty cycle characterization for high speed clock signals provides higher errors, such as 2% error at 10 giga-Hertz (GHz). The TCC method is described in U.S. Patent 8,664,978, entitled "Methods and Apparatus for Time to Current Conversion," issued on March 4, 2014, which is incorporated by reference in its entirety.

[0033] The error in the duty cycle measurement is at least partially due to nonlinear rise and fall times, which can cause errors in the TCC. In addition, as the frequency increases, the weight of the nonlinear rise and fall times increases. To improve the accuracy of the duty cycle measurement, a first duty cycle is determined based on the time interval when the periodic signal is high and a second duty cycle is determined based on the time interval when the periodic signal is low. The first duty cycle and the second duty cycle are averaged to provide a more accurate duty cycle measurement value of the periodic signal.

[0034] For example, if the nonlinear portion of the periodic signal is more favorable in the high voltage or "1" region and less favorable in the low voltage or "0" region, averaging the duty cycle from the two regions provides a more accurate representation of the duty cycle, such as closer to 0%.

[0035] The disclosed embodiment provides a method, which includes: coupling a first signal to an impedance; determining a first average current of the first signal passing through the impedance within a first time, the first average current corresponding to the duty cycle of the first signal; coupling a second signal to the impedance; determining a second average current of the second signal passing through the impedance within a second time, the second average current corresponding to the first duty cycle of the second signal; determining the first duty cycle based on the first average current and the second average current; determining a third average current of the second signal passing through the impedance within a third time, the third average current corresponding to the second duty cycle of the second signal; determining the second duty cycle based on the first average current and the third average current; and averaging the first duty cycle and the second duty cycle to obtain the average duty cycle of the second signal.

[0036] Some other disclosed embodiments provide a system, the system comprising a logic circuit, an impedance, and a measurement circuit. The logic circuit has at least one input and has an output, the at least one input is configured to receive a first signal and a second signal, and the output is configured to provide a first output signal corresponding to the first signal and a second output signal corresponding to the second signal. The impedance is connected to the output and configured to receive the first output signal and the second output signal. The measurement circuit is connected to the impedance and configured to determine a first average current through the impedance based on the first output signal, determine a second average current through the impedance to a reference voltage based on the second signal, and determine a third average current from a power source through the impedance based on the second signal.

[0037] Some further disclosed embodiments include a measurement circuit configured to determine a first duty cycle of a second signal based on a first average current and a second average current, to determine a second duty cycle of the second signal based on the first average current and a third average current, and to determine a duty cycle of the second signal based on an average of the first duty cycle and the second duty cycle.

[0038] Advantages of the methods and systems disclosed herein include improved accuracy of duty cycle measurements and increased speed of determining duty cycle.

[0039] Figures 1 to 3 is a diagram schematically illustrating a TCC technique for duty cycle characterization of a periodic signal 20 according to some embodiments. The periodic signal 20 is converted into a current during the time Tx when the periodic signal 20 is a high voltage to provide an average output current Ix within a frequency period Tck of the periodic signal 20. The duty cycle of the periodic signal 20 (i.e., the percentage of time when the periodic signal 20 is a high voltage) is determined based on the average output current Ix divided by the DC output current Idc of the DC input signal 22 within the frequency period Tck.

[0040] Figure 1 is a diagram schematically illustrating a resistor 24 configured to receive an input signal IN and an ammeter 26 configured to measure an output current Iout flowing through the resistor 24 according to some embodiments. The resistor 24 is connected to the ammeter 26. The resistor 24 receives the input signal IN and provides the output current Iout to the ammeter 26. The resistor 24 can be any suitable resistance value.

[0041] Figure 2 is a diagram schematically illustrating a DC input signal 22 and a DC output current Idc according to some embodiments. The DC input signal 22 is provided to a resistor 24, wherein the DC input signal 22 has a voltage of Vdc. A current passes through the resistor 24 to provide a DC output current Idc, which in some embodiments is an average DC current passing through the resistor 24 within a frequency period Tck of the periodic signal 20.

[0042] Figure 3 is a diagram schematically illustrating an average output current Ix through a resistor 24 due to a periodic signal 20 according to some embodiments. A periodic signal 20 is provided as an input signal IN, wherein the periodic signal 20 has a high voltage portion 28 at a voltage Vdc and a low voltage portion 30 at 0 volts. Current passes through the resistor 24 during the high voltage portion 28, but does not pass through the resistor 24 during the low voltage portion 30. The current passing through the resistor 24 during the high voltage portion 28 is averaged within a frequency period Tck of the periodic signal 20 to provide an average output current Ix.

[0043] The duty cycle of the periodic signal 20 is determined by dividing the average output current Ix by the DC output current Idc, so that the ratio of the average output current Ix to the DC output current Idc is the duty cycle. In some embodiments, this ratio is divided by the frequency of the periodic signal 20 (i.e., multiplied by the frequency cycle Tck of the periodic signal 20) to provide the time Tx that the periodic signal 20 is high.

[0044] This duty cycle characterization for low speed clock signals provides a low error, such as 0.02% error at 100 MHz, while this duty cycle characterization for high speed clock signals provides a higher error, such as 2% error at 10 GHz.

[0045] Figure 4 is a diagram schematically illustrating a periodic signal 20 having a nonlinear fall time that can cause errors in duty cycle characterization according to some embodiments. The nonlinear rise and fall times can produce larger than expected currents or smaller than expected currents during high voltage portions 28 and low voltage portions 30 of the periodic signal 20. In addition, it is difficult to predict whether the nonlinearity favors larger or smaller currents.

[0046] like Figure 4 As shown in FIG. 1 , the periodic signal 20 includes a first portion 32 that provides a larger than expected current during the high voltage portion 28 and a second portion 34 that provides a smaller than expected current during the low voltage portion 30. This introduces errors into the duty cycle characterization described above.

[0047] Figure 5 is a diagram schematically illustrating that as the frequency of the periodic signal increases, the nonlinear rise and fall times 36 become a larger portion of the periodic signal according to some embodiments. In the periodic signal 38, the nonlinear rise and fall times 36 are a smaller portion of the periodic signal 38 than in the periodic signal 40. Additionally, in the periodic signal 40, the nonlinear rise and fall times 36 are a smaller portion of the periodic signal 40 than in the periodic signal 42.

[0048] Thus, as the frequency of the periodic signal increases, the weight of the nonlinear rise and fall times 36 increases, which increases the error introduced into the duty cycle characterization.

[0049] Figures 6 to 9The present invention is a diagram schematically illustrating a method and system for duty cycle characterization according to some embodiments, wherein the method and system improve the accuracy of duty cycle measurement. To improve the accuracy of duty cycle measurement, a first duty cycle is determined based on a time interval when a periodic signal is at a high voltage and a second duty cycle is determined based on a time interval when the periodic signal is at a low voltage. The first duty cycle measurement value and the second duty cycle measurement value are averaged to provide a more accurate duty cycle measurement value of the periodic signal.

[0050] For example, if the nonlinear rise and fall times of the periodic signal are more biased toward the high voltage or "1" region and less biased toward the low voltage or "0" region, the first duty cycle measurement is skewed in one direction and the second duty cycle measurement is skewed in another direction, so that averaging the first duty cycle measurement and the second duty cycle measurement provides a duty cycle measurement with an error closer to 0% than either the first duty cycle measurement or the second duty cycle measurement.

[0051] Figure 6 is a diagram schematically illustrating a first circuit 50 for determining a first duty cycle based on a time interval during which a periodic signal is at a high voltage, according to some embodiments. The first circuit 50 includes a resistor 52 connected to an ammeter 54. One end of the resistor 52 receives an input signal IN and the other end of the resistor 52 receives a reference voltage VSS. An output current Iout flows from the input signal IN through the resistor 52 to the reference voltage VSS, and the ammeter 54 measures the output current Iout, wherein the absolute value of the output current Iout is used to determine the first duty cycle. The resistor 52 can be any suitable resistance value.

[0052] Figure 7 is a diagram schematically illustrating a periodic signal 56 having nonlinear rise and fall times 58 biased toward the "1" region and an average output current Ia according to some embodiments. A periodic signal 56 is provided as an input signal IN, wherein the periodic signal 56 has a high voltage portion 60 at a voltage Vdc and a low voltage portion 62 at 0 volts. The output current Iout passes from the periodic signal 56 through the resistor 52 to the reference voltage VSS during the high voltage portion 60, but does not pass through the resistor 52 during the low voltage portion 62. The current passing through the resistor 52 during the high voltage portion 60 is averaged within the frequency period Tck of the periodic signal 56 to provide the average output current Ia within the frequency period Tck.

[0053] The first duty cycle of the periodic signal 56 based on the high voltage or "1" region is determined by dividing the average output current Ia by the DC output current Idc through the resistor 52. The ratio of the average output current Ia to the DC output current Idc is the duty cycle. In some embodiments, this ratio is divided by the frequency of the periodic signal 56 (i.e., multiplied by the frequency period Tck of the periodic signal 56) to provide the time Tx that the periodic signal 56 is high. Figure 7 As shown in , the nonlinear rise and fall times 58 are biased toward the "1" region, which introduces errors into the first duty cycle measurement based on the "1" region.

[0054] In other examples, the nonlinear rise and fall times 58 may be biased toward the "1" region or may not be biased toward the "1" region. If the nonlinear rise and fall times 58 are biased toward the "1" region, then the nonlinear rise and fall times 58 are not biased toward the "0" region. Likewise, if the nonlinear rise and fall times 58 are not biased toward the "1" region, then the nonlinear rise and fall times 58 are biased toward the "0" region.

[0055] Figure 8 is a diagram schematically illustrating a second circuit 70 for determining a second duty cycle of a periodic signal 56 based on a time interval at which the periodic signal 56 is at a low voltage according to some embodiments. The second circuit 70 includes a resistor 72 connected to an ammeter 74. One end of the resistor 72 receives an input signal IN and the other end of the resistor 72 receives a power supply voltage VDD. The output current Iout flows from the power supply voltage VDD through the resistor 72 to the input signal IN. The ammeter 74 measures the output current Iout, wherein the absolute value of the output current Iout is used to determine the second duty cycle. The resistor 72 can be any suitable resistance value. In some embodiments, the resistor 72 is the same as the resistor 52.

[0056] Fig. 9 is a diagram schematically illustrating a periodic signal 56 having non-linear rise and fall times 58 that are not biased toward the "0" region and an average output current Ib according to some embodiments. A periodic signal 56 is provided as an input signal IN, wherein the periodic signal 56 has a high voltage portion 60 at a voltage Vdc and a low voltage portion 62 at 0 volts. The output current Iout reaches the periodic signal 56 from the power supply voltage VDD through a resistor 72 during the low voltage portion 62, but does not pass through the resistor 72 during the high voltage portion 60. The current passing through the resistor 72 during the low voltage portion 62 is averaged within the frequency period Tck of the periodic signal 56 to provide the average output current Ib.

[0057] The second duty cycle of the periodic signal 56 based on the low voltage or "0" region is determined by dividing the average output current Ib by the DC output current Idc through the resistor 72. This provides a ratio of the average output current Ib to the DC output current Idc. This ratio is subtracted from 1 to obtain the second duty cycle, which is the percentage of time that the periodic signal 56 is at a high voltage. In some embodiments, this ratio is divided by the frequency of the periodic signal 56 (i.e., multiplied by the frequency cycle Tck of the periodic signal 56) to provide the time Tb that the periodic signal 56 is at a low voltage. In some embodiments, the duty cycle percentage is divided by the frequency of the periodic signal 56 (i.e., multiplied by the frequency cycle Tck of the periodic signal 56) to provide the second time Ta that the periodic signal 56 is at a high voltage. As Fig. 9 As shown in , the nonlinear rise and fall times 58 are not biased towards the "0" region, which will introduce errors into the second duty cycle measurement based on the "0" region.

[0058] The first duty cycle measurement and the second duty cycle measurement are averaged to provide a more accurate duty cycle measurement of the periodic signal 56 .

[0059] Fig.10 1 is a diagram schematically illustrating a system 100 for duty cycle characterization according to some embodiments. The system 100 includes a logic circuit 102, an impedance 104, and a measurement circuit 106. The logic circuit 102 is electrically connected to the impedance 104, and the impedance 104 is electrically connected to the measurement circuit 106.

[0060] The logic circuit 102 has a first input 108, a second input 110, and an output 112. The first input 108 receives the TestDC signal, the second input 110 receives the input signal IN, and the output 112 provides an output signal Out to the impedance 104.

[0061] If the Test DC signal is at a low voltage, the logic circuit 102 provides a high voltage, such as the power supply voltage VDD, at the output 112. When the output 112 is at the power supply voltage VDD, the current through the impedance 104 is the output current Idc.

[0062] If the Test DC signal is at a high voltage, the output 112 follows the input signal IN, such as a periodic signal, provided at the second input 110. The output signal Out is provided to the impedance 104 for duty cycle characterization, including determining a first duty cycle of the periodic signal and a second duty cycle of the periodic signal, as described above.

[0063] Impedance 104 is connected to output 112 of logic circuit 102 and is configured to receive power supply voltage VDD and a periodic signal in output signal Out. In some embodiments, impedance 104 is a resistor R.

[0064] The measuring circuit 106 is connected to the impedance 104 and is configured to determine the output current Idc flowing through the impedance 104 in response to the Test DC signal being at a low voltage and the output 112 being at the DC power supply voltage VDD. In addition, the measuring circuit 106 is configured to determine a first average output current Iout1 within a frequency period Tck of the periodic signal, the first average output current Iout1 being based on a current flowing through the impedance 104 from a high voltage portion of the periodic signal to reach a reference voltage VSS. In addition, the measuring circuit 106 is configured to determine a second average output current Iout2 within a frequency period Tck of the periodic signal, the second average output current Iout2 being based on a current flowing through the impedance 104 from the power supply voltage VDD to reach a low voltage portion of the periodic signal.

[0065] In addition, the measurement circuit 106 is configured to determine a first duty cycle of the periodic signal according to the first average output current Iout1 and the DC output current Idc, determine a second duty cycle of the periodic signal according to the second average output current Iout2 and the DC output current Idc, and determine an average duty cycle of the periodic signal based on an average value of the first duty cycle and the second duty cycle.

[0066] In some embodiments, the measurement circuit 106 is configured to determine a first duty cycle according to the first average output current Iout1 and the DC output current Idc by dividing the first average output current Iout1 by the DC output current Idc. In some embodiments, the measurement circuit 106 is configured to determine a second duty cycle according to the second average output current Iout2 and the DC output current Idc by dividing the second average output current Iout2 by the DC output current Idc to obtain a first result and subtracting the first result from one (1) to obtain a second duty cycle.

[0067] Fig.11 1 is a diagram schematically illustrating a logic circuit 102 according to some embodiments. The logic circuit 102 includes a NAND gate 120 and an inverter 122. The first input 108 is connected to one input of the NAND gate 120 and the second input 110 is connected to the input of the inverter 122. The output of the inverter 122 is connected to the other input of the NAND gate 120, and the output of the NAND gate 120 provides an output signal Out at an output 112.

[0068] In operation, if the Test DC signal is a low voltage, the NAND gate 120 provides a high voltage, such as the power supply voltage VDD, at the output 112. Additionally, if the Test DC signal is a high voltage, the output 112 follows the input signal IN, wherein the inverter 122 inverts the input signal IN and the NAND gate 120 inverts the output of the inverter 122 to follow the input signal IN at the output 112.

[0069] Fig.12 1 is a diagram schematically illustrating a measurement circuit 106 according to some embodiments. The measurement circuit 106 includes a switch 124 and a current measurement and duty cycle determination circuit 126. The switch 124 is connected to the impedance 104 and is configured to switch between a reference voltage VSS and a power supply voltage VDD to measure the current through the impedance during the high voltage portion and the low voltage portion of the periodic signal, respectively. The current measurement and duty cycle determination circuit 126 is configured to implement the duty cycle characterization functions described herein.

[0070] Fig.13 is a graph schematically illustrating a percentage of error in a TCC duty cycle measurement for a first duty cycle of a periodic signal according to some embodiments. The first duty cycle measurement is based only on a high voltage portion of the periodic signal.

[0071] In this example, use Fig.10 The system 100 shown performs duty cycle measurement. The logic circuit 102 receives a high voltage in the input signal Test DC at a first input 108 and receives a periodic input signal IN at a second input 110. The logic circuit 102 provides a periodic output signal Out at an output 112 that follows the periodic input signal IN. The output signal Out passes through the impedance 104 to the reference signal VSS and the measurement circuit 106 to obtain a first duty cycle measurement value.

[0072] The duty cycle measurement of the periodic signal is performed at different frequencies Freq 130 of the periodic signal. The frequencies Freq 130 are in the range from 0.1 GHz to 10.1 GHz and the duty cycle Duty_IN 132 of each of the periodic input signals IN is 50%.

[0073] Duty_OUT 134 is the duty cycle of the periodic output signal OUT at the output 112. Duty_OUT 134 increases from 50% at 0.1 GHz to 50.27% at 10.1 GHz. In addition, Duty_TCC 136 is the duty cycle of the periodic signal measured at the measurement circuit 106 and the reference voltage VSS. Duty_TCC 136 decreases from 49.98% at 0.1 GHz to 48.39% at 10.1 GHz. This causes the error percentage in the TCC duty cycle measurements from Duty_OUT 134 to Duty_TCC 136 of Error_TCC vs Out 138 to be in the range of -0.02% at 0.1 GHz to -1.88% at 10.1 GHz, thereby increasing negatively with the increase of the frequency Freq 130 of the periodic input signal IN.

[0074] Fig.14 1 is a graph schematically illustrating the error percentage of Error_TCC vs Out 138 relative to the frequency of the periodic input signal IN according to some embodiments. The frequency is plotted along the x-axis 140 and the Error_TCC vs Out 138 is plotted along the y-axis 142. The error percentage of Error_TCC vs Out 138 ranges from -0.02% at 0.1 GHz to -1.88% at 10.1 GHz, and increases negatively as the frequency Freq 130 increases.

[0075] Fig.15 1 is a diagram schematically illustrating the error percentage in TCC duty cycle measurements for a first duty cycle 150 of a periodic signal and the error percentage in TCC duty cycle measurements for a second duty cycle 152 of the periodic signal according to some embodiments. The first duty cycle measurements are based only on the high voltage portion of the periodic signal and the second duty cycle measurements are based only on the low voltage portion of the periodic signal. The frequency of the periodic signal is plotted along the x-axis 154 and Error_TCC vs Out is plotted along the y-axis 156.

[0076] In this example, use Fig.10The system 100 shown performs duty cycle measurement. The logic circuit 102 receives a high voltage in the input signal Test DC at a first input 108 and receives a periodic input signal IN at a second input 110. The logic circuit 102 provides a periodic output signal Out at an output 112 that follows the periodic input signal IN. In the first duty cycle measurement, current flows from the output 112 through the impedance 104 to the reference signal VSS and the measurement circuit 106 during the high voltage portion of the periodic output signal Out to obtain a first duty cycle measurement value. In the second duty cycle measurement, current flows from the power supply voltage VDD and the measurement circuit 106 through the impedance 104 to the output 112 during the low voltage portion of the periodic output signal Out to obtain a second duty cycle measurement value.

[0077] The error percentage Error_TCC vs Out in the duty cycle measurement value of the first duty cycle increases negatively as the frequency 154 increases, and the error percentage Error_TCC vs Out in the duty cycle measurement value of the second duty cycle increases positively as the frequency 154 increases.

[0078] Fig.16 is a diagram schematically illustrating averaging a first duty cycle measurement with a second duty cycle measurement to obtain an average duty cycle with an error percentage closer to 0% according to some embodiments. The frequency of the periodic signal is plotted along the x-axis 158 and the average duty cycle error is plotted along the y-axis 160.

[0079] The measurement circuit 106 determines a first duty cycle of the periodic signal and a second duty cycle of the periodic signal. The measurement circuit then determines an average duty cycle of the periodic signal, which reduces the error percentage of the duty cycle measurements at each of the different frequencies 158.

[0080] Averaging the first duty cycle measurement value and the second duty cycle measurement value will produce an average duty cycle measurement value, where the negative error percentage of the first duty cycle measurement value is offset by the positive error percentage of the second duty cycle measurement value. This will make the duty cycle measurement value have an error percentage closer to 0%.

[0081] Fig.171 is a diagram schematically illustrating the error percentage in the TCC duty cycle measurement of a periodic signal having a 40% duty cycle according to some embodiments. The error percentage in the TCC duty cycle measurement includes a first duty cycle 170 of the periodic signal and a second duty cycle 172 of the periodic signal. The first duty cycle measurement is based on a high voltage portion of the periodic signal and the second duty cycle measurement is based on a low voltage portion of the periodic signal. The frequency of the periodic signal is plotted along the x-axis 174 and Error_TCC vs Out is plotted along the y-axis 176.

[0082] In this example, use Fig.10 The system 100 shown performs duty cycle measurement. The logic circuit 102 receives a high voltage in the input signal Test DC at a first input 108 and receives a periodic input signal IN at a second input 110. The logic circuit 102 provides a periodic output signal Out at an output 112 that follows the periodic input signal IN. In the first duty cycle measurement, current flows from the output 112 through the impedance 104 to the reference signal VSS and the measurement circuit 106 during the high voltage portion of the periodic output signal Out to obtain a first duty cycle measurement value. In the second duty cycle measurement, current flows from the power supply voltage VDD and the measurement circuit 106 through the impedance 104 to the output 112 during the low voltage portion of the periodic output signal Out to obtain a second duty cycle measurement value.

[0083] The error percentage Error_TCC vs Out in the duty cycle measurement value of the first duty cycle increases negatively as the frequency 174 increases, and the error percentage Error_TCC vs Out in the duty cycle measurement value of the second duty cycle increases positively as the frequency 174 increases.

[0084] Fig.18 is a diagram schematically illustrating averaging a first duty cycle measurement with a second duty cycle measurement to obtain an average duty cycle with an error percentage closer to 0% according to some embodiments. The frequency of the periodic signal is plotted along the x-axis 178 and the average duty cycle error is plotted along the y-axis 180.

[0085] The measurement circuit 106 determines a first duty cycle of the periodic signal and a second duty cycle of the periodic signal. The measurement circuit then determines an average duty cycle of the periodic signal, which reduces the error percentage of the duty cycle measurements at each of the different frequencies 178.

[0086] Averaging the first duty cycle measurement value and the second duty cycle measurement value will produce an average duty cycle measurement value, where the negative error percentage of the first duty cycle measurement value is offset by the positive error percentage of the second duty cycle measurement value. This will make the duty cycle measurement value have an error percentage closer to 0%.

[0087] Fig.19 is a diagram schematically illustrating a method of obtaining an average duty cycle measurement value according to some embodiments. At 200, the method includes coupling a first signal to an impedance, and at 202, the method includes determining a first average current of the first signal through the impedance over a first time. The first average current corresponds to a duty cycle of the first signal. In some embodiments, coupling the first signal to the impedance includes coupling a DC signal to the impedance.

[0088] At 204, the method includes coupling the second signal to the impedance. In some embodiments, coupling the second signal to the impedance includes coupling a periodic signal to the impedance.

[0089] At 206, the method includes determining a second average current of the second signal through the impedance during the second time. The second average current corresponds to a first duty cycle of the second signal. In some embodiments, determining the second average current of the second signal through the impedance includes determining a second average current of the second signal through the impedance to reach a reference voltage VSS during the second time.

[0090] At 208, the method includes determining a first duty cycle based on the first average current and the second average current. In some embodiments, determining the first duty cycle based on the first average current and the second average current includes dividing the second average current by the first average current. In some embodiments, determining the first duty cycle based on the first average current and the second average current includes dividing the second average current by the first average current to obtain a current ratio, and multiplying the current ratio by a cycle period of the periodic signal.

[0091] At 210, the method includes determining a third average current of the second signal through the impedance during a third time. The third average current corresponds to a second duty cycle of the second signal. In some embodiments, determining the third average current of the second signal through the impedance includes determining a third average current of the second signal from a power supply VDD through the impedance during the third time. In some embodiments, the first time is equal to each of the second time and the third time. In some embodiments, the second time is equal to the third time.

[0092] At 212, the method includes determining a second duty cycle based on the first average current and the third average current. In some embodiments, determining the second duty cycle based on the first average current and the third average current includes dividing the third average current by the first average current to obtain a first result, and subtracting the first result from one to obtain a second result. In some embodiments, determining the second duty cycle based on the first average current and the third average current includes dividing the third average current by the first average current to obtain a first result, subtracting the first result from one to obtain a second result, and multiplying the second result by a cycle period of the periodic signal.

[0093] At 214 , the method includes averaging the first duty cycle and the second duty cycle to obtain an average duty cycle of the second signal.

[0094] Fig. 20 is a diagram schematically illustrating another method of obtaining an average duty cycle measurement value according to some embodiments. At 220, the method includes coupling a DC signal to an impedance, and at 222, the method includes determining a first current of the DC signal through the impedance.

[0095] At 224, the method includes coupling the periodic signal to the impedance, and at 226, the method includes determining a second current that flows from the periodic signal through the impedance to a reference voltage VSS within a first number of clock cycles of the periodic signal. At 228, the method includes determining a first duty cycle based on the first current and the second current. In some embodiments, determining the first duty cycle based on the first current and the second current includes dividing the second current by the first current. In some embodiments, determining the first duty cycle based on the first current and the second current includes dividing the second current by the first current to obtain a current ratio, and multiplying the current ratio by a period of the periodic signal.

[0096] At 230, the method includes determining a third current of the periodic signal from the power supply VDD through the impedance within a second number of clock cycles. At 232, the method includes determining a second duty cycle based on the first current and the third current. In some embodiments, determining the second duty cycle based on the first current and the third current includes dividing the third current by the first current to obtain a first result, and subtracting the first result from one to obtain a second result. In some embodiments, determining the second duty cycle based on the first current and the third current includes dividing the third current by the first current to obtain a first result, subtracting the first result from one to obtain a second result, and multiplying the second result by the period of the periodic signal.

[0097] At 234 , the method includes averaging the first duty cycle and the second duty cycle to determine a duty cycle of the periodic signal.

[0098] Fig.21is a block diagram schematically illustrating an example of a computer system 300 configured to provide a semiconductor device of the present disclosure, according to some embodiments. Some or all of the design, layout, manufacturing, testing, and operation of a semiconductor device (also referred to as a semiconductor circuit) may be performed by or using the computer system 300. In some embodiments, the computer system 300 includes an electronic design automation (EDA) system. In some embodiments, the semiconductor device is an IC.

[0099] In some embodiments, system 300 is a general purpose computing device including processor 302 and non-transitory computer readable storage medium 304. Computer readable storage medium 304 may be encoded with (e.g., store) computer program code such as executable instructions 306. Execution of instructions 306 by processor 302 (at least in part) provides tools for implementing some or all of the functions of system 300 (e.g., pre-layout simulation, post-layout simulation, routing, re-routing, final layout, testing, and operation of semiconductor devices). In addition, fabrication tools 308 are included to further layout and physically implement the design and manufacture of semiconductor devices. In some embodiments, execution of instructions 306 by processor 302 (at least in part) provides tools for implementing some or all of the functions of system 300. In some embodiments, system 300 includes a commercial router. In some embodiments, system 300 includes an automatic place and route (APR) system.

[0100] The processor 302 is electrically coupled to the computer readable storage medium 304 via the bus 310 and is electrically coupled to the I / O interface 312 via the bus 310. The network interface 314 is also electrically coupled to the processor 302 via the bus 310. The network interface 314 is connected to a network 316 so that the processor 302 and the computer readable storage medium 304 can be connected to external components using the network 316. The processor 302 is configured to execute computer program code or instructions 306 encoded in the computer readable storage medium 304 to cause the system 300 to perform some or all of the functions of the system 300, such as providing the semiconductor devices and methods disclosed herein and other functions of the system 300. In some embodiments, the processor 302 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application specific integrated circuit (ASIC), and / or a suitable processing unit.

[0101] In some embodiments, the computer-readable storage medium 304 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, the computer-readable storage medium 304 may include semiconductor or solid-state memory, magnetic tape, a removable computer disk, random access memory (RAM), read-only memory (ROM), a hard disk, and / or an optical disk. In some embodiments using optical disks, the computer-readable storage medium 304 may include a compact disk-read only memory (CD-ROM), a compact disk-read / write memory (CD-R / W), and / or a digital video disc (DVD).

[0102] In some embodiments, computer readable storage medium 304 stores computer program code or instructions 306 configured to cause system 300 to perform some or all of the functions of system 300. In some embodiments, computer readable storage medium 304 also stores information that facilitates performing some or all of the functions of system 300. In some embodiments, computer readable storage medium 304 stores database 318, which includes one or more of a component library, a digital circuit cell library, and a database.

[0103] System 300 includes an I / O interface 312 that is coupled to external circuitry. In some embodiments, I / O interface 312 includes a keyboard, keypad, mouse, trackball, trackpad, touch screen, and / or cursor arrow keys for transmitting information and commands to processor 302.

[0104] The network interface 314 is coupled to the processor 302 and enables the system 300 to communicate with a network 316 connected to one or more other computer systems. The network interface 314 may include a wireless network interface such as Bluetooth, wireless fidelity (WIFI), Worldwide Interoperability for Microwave Access (WIMAX), General Packet Radio Service (GPRS), or wideband code division multiple access (WCDMA); or a wired network interface such as Ethernet (ETHERNET), universal serial bus (USB), or Institute of Electrical and Electronic Engineers-1364 (IEEE-1364). In some embodiments, some or all of the functions of the system 300 may be implemented in two or more systems similar to the system 300.

[0105] The system 300 is configured to receive information via the I / O interface 312. The information received via the I / O interface 312 includes one or more of instructions, data, design rules, component and cell libraries, and / or other parameters processed by the processor 302. The information is passed to the processor 302 via the bus 308. In addition, the system 300 is configured to receive information related to a user interface (UI) via the I / O interface 312. This UI information can be stored as UI 320 in the computer readable storage medium 304.

[0106] In some embodiments, some or all of the functions of system 300 are implemented via an independent software application executed by a processor. In some embodiments, some or all of the functions of system 300 are implemented in a software application as a part of an additional software application. In some embodiments, some or all of the functions of system 300 are implemented as a plug-in (plug-in) of a software application. In some embodiments, at least one of the functions of system 300 is implemented as a software application as a part of an EDA tool. In some embodiments, some or all of the functions of system 300 are implemented as a software application used by system 300. In some embodiments, a layout diagram is generated using a tool (e.g., VIRTUOSO or another suitable layout generation tool available from Cadence Design Systems).

[0107] In some embodiments, wiring, layout and other processes are achieved as a function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage units or memory units, such as one or more optical disks (e.g., digital video disks or digital versatile disks (DVDs)), magnetic disks (e.g., hard disks), semiconductor memories (e.g., ROM and RAM), and memory cards, and the like.

[0108] As described above, embodiments of the system 300 include a fabrication tool 308 for implementing the manufacturing process of the system 300. For example, based on the final layout, a photolithography mask may be generated, which is used to fabricate a semiconductor device via the fabrication tool 308.

[0109] Combination Fig. 22 Other aspects of the disclosed device are disclosed, Fig. 22 is a block diagram of a semiconductor device manufacturing system 322 and a semiconductor device manufacturing process associated therewith according to some embodiments. In some embodiments, the manufacturing system 322 is used to fabricate one or more semiconductor masks and / or at least one component in a layer of a semiconductor device based on the layout diagram.

[0110] exist Fig. 22 , semiconductor device manufacturing system 322 includes entities that interact with each other in the design, development, and manufacturing cycles and / or services associated with manufacturing semiconductor devices (such as the semiconductor devices described herein), such as design division 324, mask division 326, and semiconductor device manufacturing plant / fab ("fab") 328. The entities in system 322 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more of the other entities and provides services to one or more of the other entities and / or receives services from one or more of the other entities. In some embodiments, a single larger company owns two or more of design division 324, mask division 326, and semiconductor device fabrication plant 328. In some embodiments, two or more of design division 324, mask division 326, and semiconductor device fabrication plant 328 coexist in a common facility and use common resources.

[0111] The design division (or design team) 324 generates a semiconductor device design layout 330. The semiconductor device design layout 330 includes various geometric patterns or semiconductor device layouts designed for semiconductor devices. The geometric patterns correspond to patterns of metal layers, oxide layers, or semiconductor layers that constitute various components of the semiconductor structure to be manufactured. The various layers are combined to form various semiconductor device features. For example, a portion of the semiconductor device design layout 330 includes various semiconductor device features to be formed in a semiconductor substrate (e.g., a silicon wafer) and in various material layers disposed on the semiconductor substrate, such as diagonal vias, active regions or active areas, gate electrodes, sources, drains, metal lines, local vias, and openings for bonding pads. The design division 324 implements a design program to form the semiconductor device design layout 330. The semiconductor device design layout 330 exists in one or more data files having information of the geometric patterns. For example, the semiconductor device design layout 330 can be expressed in a GDSII file format or a DFII file format. In some embodiments, the design process includes one or more of analog circuit design, digital circuit design, logic circuit design, standard cell circuit design, power distribution network (PDN) design, PDN design including power via design, power voltage rail design, reference voltage rail design, placement and routing routines, and physical layout design.

[0112] The mask division 326 includes mask data preparation 332 and mask fabrication 334. The mask division 326 uses the semiconductor device design layout 330 to produce one or more masks 336 to be used to fabricate various layers of a semiconductor device or semiconductor structure. The mask division 326 performs mask data preparation 332, wherein the semiconductor device design layout 330 is converted into a representative data file (RDF). The mask data preparation 332 provides the RDF to the mask fabrication 334. The mask fabrication 334 includes a mask writer that converts the RDF into an image on a substrate, such as a mask (reticle 336) or a semiconductor wafer 338. The mask data preparation 332 manipulates the design layout 330 to comply with the characteristics of the mask writer and / or the guidelines of the semiconductor device fabrication plant 328. In Fig. 22 In FIG. 3 , mask data preparation 332 and mask production 334 are shown as separate components. In some embodiments, mask data preparation 332 and mask production 334 may be collectively referred to as mask data preparation.

[0113] In some embodiments, mask data preparation 332 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those caused by diffraction, interference, other process effects, and the like. OPC adjusts semiconductor device design layout 330. In some embodiments, mask data preparation 332 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shifting masks, other suitable techniques, and the like, or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

[0114] In some embodiments, mask data preparation 332 includes a mask rule checker (MRC) that uses a set of mask creation rules containing certain geometric and / or connectivity constraints to check the semiconductor device design layout 330 that has been subjected to the process in OPC to ensure sufficient margins to take into account the variability of the semiconductor manufacturing process, etc. In some embodiments, the MRC modifies the semiconductor device design layout 330 to compensate for the limitations during mask production 334, which may cancel a portion of the modifications implemented by OPC to meet the mask creation rules.

[0115] In some embodiments, mask data preparation 332 includes lithography process checking (LPC), which simulates the process to be performed by semiconductor device fabrication plant 328. LPC simulates this process based on semiconductor device design layout 330 to create a simulated finished device. Process parameters in LPC simulation may include parameters associated with various processes of a semiconductor device manufacturing cycle, parameters associated with tools used to manufacture semiconductor devices, and / or other aspects of the manufacturing process. LPC considers various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, and the like, or combinations thereof. In some embodiments, after a simulated finished device has been created by LPC, if the simulated device does not sufficiently meet the design rules in terms of shape, OPC and / or MRC are repeated to further refine the semiconductor device design layout 330.

[0116] For the sake of clarity, the above description of mask data preparation 332 has been simplified. In some embodiments, mask data preparation 332 includes additional features, such as modifying logic operations (LOPs) of semiconductor device design layout 330 according to manufacturing rules. In addition, the processes applied to semiconductor device design layout 330 during mask data preparation 332 may be performed in a variety of different orders.

[0117] After the mask data preparation 332 and during the mask fabrication 334, a mask 336 or a set of masks 336 are fabricated based on the modified semiconductor device design layout 330. In some embodiments, the mask fabrication 334 includes performing one or more lithography exposures based on the semiconductor device design layout 330. In some embodiments, an electron-beam (e-beam) or a mechanism consisting of multiple electron beams is used to form a pattern on the mask (photomask or stencil) 336 based on the modified semiconductor device design layout 330. The mask 336 can be formed by various techniques. In some embodiments, the mask 336 is formed using a binary technique. In some embodiments, the mask pattern includes opaque areas and transparent areas. A radiation beam (e.g., an ultraviolet (UV) beam) used to expose an image-sensitive material layer (e.g., a photoresist) coated on a wafer is blocked by the opaque area and transmitted through the transparent area. In one example, a binary mask version of mask 336 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque areas of the binary mask. In another example, mask 336 is formed using a phase shift technique. In a phase shift mask (PSM) version of mask 336, various features in a pattern formed on the phase shift mask are configured to have an appropriate phase difference to enhance resolution and imaging quality. In various examples, the phase shift mask can be an attenuated PSM or an alternating PSM. The mask produced by mask fabrication 334 is used in various processes. For example, such a mask is used in an ion implantation process to form various doped regions in semiconductor wafer 338, in an etching process to form various etched regions in semiconductor wafer 338, and / or in other suitable processes.

[0118] Semiconductor device fabrication plant 328 includes wafer fabrication 340. Semiconductor device fabrication plant 328 is a semiconductor device fabrication enterprise that includes one or more fabrication facilities for fabricating a variety of different semiconductor device products. In some embodiments, semiconductor device fabrication plant 328 is a semiconductor foundry. For example, there may be a fabrication facility for front end of line (FEOL) fabrication of multiple semiconductor device products, while a second fabrication facility may provide back end of line (BEOL) fabrication for interconnect and packaging of semiconductor device products, and a third fabrication facility may provide other services for the foundry enterprise.

[0119] The semiconductor device fabrication factory 328 uses the mask 336 fabricated by the mask division 326 to fabricate the semiconductor structure or semiconductor device 342 disclosed herein. Therefore, the semiconductor device fabrication factory 328 at least indirectly uses the semiconductor device design layout 330 to fabricate the semiconductor structure or semiconductor device 342 disclosed herein. In addition, the semiconductor wafer 338 includes a silicon substrate or other appropriate substrate on which a material layer is formed, and the semiconductor wafer 338 further includes one or more of various doped regions, dielectric features, multilevel interconnects, and the like (formed at subsequent manufacturing steps). In some embodiments, the semiconductor wafer 338 is fabricated by the semiconductor device fabrication factory 328 using the mask 336 to form the semiconductor structure or semiconductor device 342 disclosed herein. In some embodiments, the semiconductor device fabrication includes performing one or more lithography exposures based at least indirectly on the semiconductor device design layout 330.

[0120] Embodiments of the present disclosure include systems and methods for duty cycle characterization using TCC. To reduce errors in duty cycle measurements, a first duty cycle is determined based on time intervals when a periodic signal is at a high voltage and a second duty cycle is determined based on time intervals when the periodic signal is at a low voltage. The first duty cycle and the second duty cycle are averaged to provide a duty cycle measurement with less error. For example, if the nonlinear portion of the periodic signal is more biased toward a high voltage or "1" region and less biased toward a low voltage or "0" region, averaging the first duty cycle and the second duty cycle provides a duty cycle measurement with a smaller error percentage (e.g., closer to 0%).

[0121] The disclosed embodiments provide a method, the method comprising: coupling a first signal to an impedance; and determining a first average current of the first signal passing through the impedance in a first time, wherein the first average current corresponds to a duty cycle of the first signal. The method further comprises: coupling a second signal to the impedance; determining a second average current of the second signal passing through the impedance in a second time, wherein the second average current corresponds to a first duty cycle of the second signal; and determining the first duty cycle based on the first average current and the second average current. The method further comprises: determining a third average current of the second signal passing through the impedance in a third time, wherein the third average current corresponds to a second duty cycle of the second signal; and determining the second duty cycle based on the first average current and the third average current. Then, the method comprises averaging the first duty cycle and the second duty cycle to obtain an average duty cycle of the second signal.

[0122] In a related embodiment, coupling the first signal to the impedance includes coupling a direct current signal to the impedance. In a related embodiment, coupling the second signal to the impedance includes coupling a periodic signal to the impedance. In a related embodiment, determining the second average current of the second signal passing through the impedance includes determining the second average current of the second signal passing through the impedance to reach a reference voltage VSS in the second time. In a related embodiment, determining the first duty cycle based on the first average current and the second average current includes dividing the second average current by the first average current. In a related embodiment, determining the first duty cycle based on the first average current and the second average current includes dividing the second average current by the first average current to obtain a current ratio, and multiplying the current ratio by a cycle period of the periodic signal. In a related embodiment, determining the third average current of the second signal passing through the impedance includes determining the third average current of the second signal passing through the impedance from a power supply VDD in the third time. In a related embodiment, determining the second duty cycle based on the first average current and the third average current includes dividing the third average current by the first average current to obtain a first result, and subtracting the first result from one to obtain a second result. In a related embodiment, determining the second duty cycle based on the first average current and the third average current includes dividing the third average current by the first average current to obtain a first result, subtracting the first result from one to obtain a second result, and multiplying the second result by a cycle period of the periodic signal. In a related embodiment, the first time is equal to each of the second time and the third time. In a related embodiment, the second time is equal to the third time.

[0123] Advantages of the methods and systems disclosed herein include increased accuracy of duty cycle measurements and increased speed in determining duty cycle measurements.

[0124] According to some embodiments, a method includes: coupling a first signal to an impedance; determining a first average current of the first signal passing through the impedance within a first time, the first average current corresponding to a duty cycle of the first signal; coupling a second signal to the impedance; determining a second average current of the second signal passing through the impedance within a second time, the second average current corresponding to a first duty cycle of the second signal; determining a first duty cycle based on the first average current and the second average current; determining a third average current of the second signal passing through the impedance within a third time, the third average current corresponding to a second duty cycle of the second signal; determining a second duty cycle based on the first average current and the third average current; and averaging the first duty cycle and the second duty cycle to obtain an average duty cycle of the second signal.

[0125] According to some other embodiments, a method includes: coupling a DC signal to an impedance; determining a first current of the DC signal passing through the impedance; coupling a periodic signal to the impedance; determining a second current of the periodic signal passing through the impedance to reach a reference voltage VSS within a first number of clock cycles of the periodic signal; determining a first duty cycle based on the first current and the second current; determining a third current of the periodic signal from a power supply VDD through the impedance within a second number of clock cycles of the periodic signal; determining a second duty cycle based on the first current and the third current; and averaging the first duty cycle and the second duty cycle to determine the duty cycle of the periodic signal.

[0126] In a related embodiment, determining the first duty cycle based on the first current and the second current includes dividing the second current by the first current. In a related embodiment, determining the first duty cycle based on the first current and the second current includes dividing the second current by the first current to obtain a current ratio, and multiplying the current ratio by the period of the periodic signal. In a related embodiment, determining the second duty cycle based on the first current and the third current includes dividing the third current by the first current to obtain a first result, and subtracting the first result from one to obtain a second result. In a related embodiment, determining the second duty cycle based on the first current and the third current includes dividing the third current by the first current to obtain a first result, subtracting the first result from one to obtain a second result, and multiplying the second result by the period of the periodic signal.

[0127] According to some further disclosed aspects, a system includes a logic circuit, an impedance, and a measurement circuit. The logic circuit has at least one input and has an output, the at least one input being configured to receive a first signal and a second signal, and the output being configured to provide a first output signal corresponding to the first signal and a second output signal corresponding to the second signal. The impedance is connected to the output and configured to receive the first output signal and the second output signal. The measurement circuit is connected to the impedance and configured to determine a first average current through the impedance based on the first output signal, a second average current through the impedance to a reference voltage based on the second signal, and a third average current from a power source through the impedance based on the second signal.

[0128] In a related embodiment, the measurement circuit is configured to determine a first duty cycle of the second signal based on the first average current and the second average current, determine a second duty cycle of the second signal based on the first average current and the third average current, and determine the duty cycle of the second signal based on an average of the first duty cycle and the second duty cycle. In a related embodiment, the measurement circuit is configured to determine the first duty cycle based on the first average current and the second average current by dividing the second average current by the first average current. In a related embodiment, the measurement circuit is configured to determine the second duty cycle based on the first average current and the third average current by dividing the third average current by the first average current to obtain a first result and subtracting the first result from one to obtain a second result.

[0129] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for duty cycle characterization, characterized in that include: coupling a first signal to an impedance; determining a first average current of the first signal passing through the impedance within a first time, the first average current corresponding to a duty cycle of the first signal; coupling a second signal to the impedance; determining a second average current of the second signal passing through the impedance within a second time, the second average current corresponding to a first working period of the second signal; determining the first working period according to the first average current and the second average current; determining a third average current of the second signal passing through the impedance within a third time, the third average current corresponding to a second working cycle of the second signal; determining the second working period according to the first average current and the third average current; as well as The first duty cycle and the second duty cycle are averaged to obtain an average duty cycle of the second signal.

2. The method according to claim 1, characterized in that Coupling the second signal to the impedance includes coupling a periodic signal to the impedance.

3. The method according to claim 2, characterized in that Determining the second average current of the second signal passing through the impedance includes determining the second average current of the second signal passing through the impedance to reach a reference voltage VSS within the second time.

4. The method according to claim 3, characterized in that Determining the first duty cycle based on the first average current and the second average current includes dividing the second average current by the first average current.

5. The method according to claim 3, characterized in that: Determining the first duty cycle based on the first average current and the second average current includes dividing the second average current by the first average current to obtain a current ratio, and multiplying the current ratio by a cycle period of the periodic signal.

6. The method according to claim 2, characterized in that Determining the third average current of the second signal passing through the impedance includes determining the third average current of the second signal passing through the impedance from a power source VDD within the third time.

7. The method according to claim 6, characterized in that Determining the second duty cycle based on the first average current and the third average current includes dividing the third average current by the first average current to obtain a first result, and subtracting the first result from one to obtain a second result.

8. The method according to claim 6, characterized in that Determining the second duty cycle based on the first average current and the third average current includes dividing the third average current by the first average current to obtain a first result, subtracting the first result from one to obtain a second result, and multiplying the second result by a cycle period of the periodic signal.

9. A method for duty cycle characterization, characterized in that include: Couples a DC signal into an impedance; determining a first current of the DC signal passing through the impedance; coupling a periodic signal into the impedance; determining a second current of the periodic signal passing through the impedance to reach a reference voltage VSS within a first number of clock cycles of the periodic signal; determining a first working cycle according to the first current and the second current; determining a third current of the periodic signal from a power source VDD through the impedance within a second number of clock cycles of the periodic signal; determining a second working cycle according to the first current and the third current; as well as The first duty cycle and the second duty cycle are averaged to determine a duty cycle of the periodic signal.

10. A system for duty cycle characterization, characterized in that: include: a logic circuit having at least one input configured to receive a first signal and a second signal and having an output configured to provide a first output signal corresponding to the first signal and a second output signal corresponding to the second signal; an impedance connected to the output and configured to receive the first output signal and the second output signal; as well as A measurement circuit is connected to the impedance and is configured to determine a first average current passing through the impedance based on the first output signal, a second average current passing through the impedance to reach a reference voltage based on the second signal, and a third average current from a power source through the impedance based on the second signal.

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