OSC circuit, integrated OSC circuit and integrated circuit chip

Abstract

The invention provides an OSC circuit, an integrated OSC circuit and an integrated circuit chip, and the OSC circuit comprises an annular oscillation circuit which comprises an NAND gate, a frequency control module and a phase inverter module, the first input end of the NAND gate is a control signal input end, the second input end of the NAND gate is electrically connected with the output end of the phase inverter module, and the frequency control module is electrically connected with the output end of the phase inverter module; the output end of the NAND gate is electrically connected with the input end of the frequency control module; wherein when the control signal input end receives a first control signal, the annular oscillation circuit is used for outputting a first clock signal, when the control signal input end receives a second control signal, the annular oscillation circuit is used for stopping outputting the first clock signal, and the frequency control module is used for controlling the frequency of the first clock signal. It can be understood that if necessary, the power supply circuit can keep the power-on state and continuously output the power supply, and a user can input different control signals to the control signal input end to quickly control the ring oscillation circuit to be switched on or switched off.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit design, and in particular to an OSC circuit, an integrated OSC circuit and an integrated circuit chip. Background Art

[0002] Many electronic circuits require clock signals to ensure normal operation. Usually, the clock signal is output by an integrated oscillator (OSC) circuit to ensure the normal operation of other electronic circuits. In order to ensure the normal operation of the integrated OSC circuit, in addition to the OSC circuit, an OSC power supply circuit is also required to power the OSC circuit.

[0003] In the related art, a control signal is set for the OSC power supply circuit, and the user can control the on or off of the OSC power supply circuit by controlling the control signal of the OSC power supply circuit. When the OSC power supply circuit outputs power stably, the OSC circuit starts to work.

[0004] However, since the OSC circuit needs to wait until the OSC power supply circuit is stable before it can start working, when the subsequent electronic circuit needs a clock signal and the situation is urgent, the OSC circuit cannot generate a clock signal in time; and if the OSC power supply circuit and the OSC circuit are always turned on, it will affect the life of each device in the OSC circuit and consume more energy.

[0005] It should be pointed out that the information disclosed in the background technology section of this application is only intended to deepen the understanding of the general background technology of this application, and should not be regarded as an admission or suggestion in any form that the information constitutes prior art already known to those skilled in the art. Summary of the invention

[0006] In view of this, the present application provides an OSC circuit, an integrated OSC circuit and an integrated circuit chip, so as to solve the problem in the prior art that when the subsequent electronic circuit needs a clock signal and the situation is urgent, the OSC circuit cannot generate a clock signal in time; and if the power supply circuit and the OSC circuit are always turned on, it will affect the life of each device and consume more energy.

[0007] In a first aspect, an embodiment of the present application provides an OSC circuit, including:

[0008] A ring oscillation circuit comprises a NAND gate, a frequency control module and an inverter module, wherein the first input end of the NAND gate is a control signal input end, the second input end of the NAND gate is electrically connected to the output end of the inverter module, and the output end of the NAND gate is electrically connected to the input end of the frequency control module;

[0009] When the control signal input end receives a first control signal, the ring oscillation circuit is used to output a first clock signal; when the control signal input end receives a second control signal, the ring oscillation circuit is used to stop outputting the first clock signal; and the frequency control module is used to control the frequency of the first clock signal.

[0010] In the embodiment of the present application, the OSC circuit includes a ring oscillation circuit, which includes a NAND gate, and the input end of the NAND gate is a control signal input end. When the control signal input end receives a first control signal, the ring oscillation circuit is used to output a first clock signal; when the control signal input end receives a second control signal, the ring oscillation circuit stops outputting the first clock signal, that is, the user can control the conduction or disconnection of the ring oscillation circuit by inputting different control signals to the control signal input end. In some possible implementations, the power supply circuit can remain in a powered-on state and continuously output power supply. When the OSC circuit needs to work, the first control signal is input to the control signal input end to turn on the OSC circuit; when the OSC circuit is finished working, the second control signal is input to the control signal input end to turn off the OSC circuit, thereby protecting the service life of each device in the OSC circuit and saving energy.

[0011] In a possible implementation, the inverter module includes:

[0012] N inverters are connected in series in sequence, the input end of the first inverter is electrically connected to the output end of the NAND gate, the output end of the last inverter is electrically connected to the second input end of the NAND gate, and N is an even number greater than or equal to 2.

[0013] In the embodiment of the present application, the first input terminal of the NAND gate is used as the control signal input terminal. It can be understood that when the control signal input terminal receives the first control signal (high level), the output signal of the NAND gate is logically opposite to the signal received by the second input terminal of the NAND gate. At this time, the role of the NAND gate is equivalent to that of an inverter; when the control signal input terminal receives the second control signal (low level), the NAND gate continues to output a high level. Since the output terminal of the NAND gate is electrically connected to the input terminal of the inverter, the inverter cannot work normally when it receives a high level. Therefore, when the control input terminal receives the second control signal, the ring oscillation circuit is in a disconnected state.

[0014] In a possible implementation, the frequency control module includes:

[0015] M inverters, the M inverters are sequentially connected in series, the input end of the first inverter is electrically connected to the output end of the NAND gate, the output end of the last inverter is electrically connected to the input end of the first inverter among the N inverters, and M is an odd number;

[0016] a third resistor, a first end of the third resistor being electrically connected to an input end of a first inverter among the M inverters;

[0017] A fourth capacitor, wherein a first end of the fourth capacitor is electrically connected to the output end of the last inverter among the M inverters, and a second end of the fourth capacitor is electrically connected to the second end of the third resistor and the input end of the first direction device in the inverter module.

[0018] In an embodiment of the present application, a frequency control module is added between the output end of the NAND gate and the input end of the first inverter among the N inverters to control the oscillation frequency of the ring oscillation circuit. Specifically, the frequency control module includes M inverters, a third resistor and a fourth capacitor.

[0019] In a possible implementation manner, the third resistor is an adjustable resistor.

[0020] It can be understood that the frequency of the ring oscillation circuit can be adjusted by adjusting the resistance value of the third resistor.

[0021] In a second aspect, an embodiment of the present application provides an integrated OSC circuit, including:

[0022] A power supply circuit, used for outputting power supply;

[0023] The OSC circuit according to any one of the first aspects, wherein the OSC circuit is used to receive the power supply.

[0024] In a possible implementation, the power supply circuit includes:

[0025] A current source module, used for outputting a constant current;

[0026] A first PMOS tube, wherein a source of the first PMOS tube is used to connect to a high level, and a gate of the first PMOS tube is electrically connected to a first output end of the current source module;

[0027] a first resistor, wherein a first end of the first resistor is electrically connected to a drain of the first PMOS tube;

[0028] a second PMOS tube, wherein a source of the second PMOS tube is electrically connected to the second end of the first resistor, and a gate of the second PMOS tube is electrically connected to a drain of the second PMOS tube;

[0029] a first NMOS transistor, wherein a gate of the first NMOS transistor is electrically connected to a drain of the first NMOS transistor, a gate of the second PMOS transistor, and a drain of the second PMOS transistor, respectively, and a source of the first NMOS transistor is grounded;

[0030] a second NMOS tube, wherein the drain of the second NMOS tube is electrically connected to the second output end of the current source module, the gate of the second NMOS tube is electrically connected to the gate of the first NMOS tube, and the source of the second NMOS tube is grounded;

[0031] a third NMOS tube, wherein the gate of the third NMOS tube is electrically connected to the drain of the second NMOS tube, the drain of the third NMOS tube is electrically connected to the gate of the first PMOS tube, and the source of the third NMOS tube is grounded;

[0032] Wherein, the drain of the first PMOS tube is used to output power supply.

[0033] In the embodiment of the present application, a voltage divider module is formed by the first PMOS tube, the first resistor, the second PMOS tube and the first NMOS tube to provide power supply for the OSC circuit. The voltage of the power supply is equal to the sum of the voltage drops on the first resistor, the second PMOS tube and the first NMOS tube, and is not affected by the high-level voltage. Moreover, the voltage required for the first PMOS tube, the second PMOS tube and the first NMOS tube to work in the saturation region at the same time is relatively small. Even if the OSC power supply circuit works at a low voltage, it can still ensure that the first PMOS tube, the second PMOS tube and the first NMOS tube work in the saturation region at the same time, thereby ensuring the stability of the power supply.

[0034] In a possible implementation manner, the first resistor is an adjustable resistor.

[0035] It can be understood that the voltage drop on the first resistor can be adjusted by adjusting the resistance value of the first resistor, thereby adjusting the voltage of the power supply.

[0036] In a possible implementation, the OSC power supply circuit further includes:

[0037] A third PMOS tube, wherein the gate of the third PMOS tube is electrically connected to the drain of the first PMOS tube, the source of the third PMOS tube is electrically connected to the gate of the first PMOS tube, and the drain of the third PMOS tube is grounded.

[0038] In an embodiment of the present application, when the current in the OSC circuit suddenly increases, the voltage of the power supply will suddenly decrease. When the voltage of the power supply decreases to the voltage threshold, the third PMOS tube is turned on, quickly pulling down the gate voltage of the first PMOS tube, so that the first PMOS tube responds quickly and outputs a higher voltage, thereby raising the voltage of the power supply.

[0039] In a possible implementation, the current source module includes:

[0040] a fourth PMOS tube, wherein the source of the fourth PMOS tube is used to connect to a high level, the gate of the fourth PMOS tube is electrically connected to the drain of the fourth PMOS tube, the drain of the fourth PMOS tube is electrically connected to a current source unit, and the current source unit is used to output a constant current;

[0041] a fifth PMOS tube, wherein the source of the fifth PMOS tube is used to connect to a high level, and the gate of the fifth PMOS tube is electrically connected to the gate of the fourth PMOS tube;

[0042] a sixth PMOS tube, wherein the source of the sixth PMOS tube is used to connect to a high level, and the gate of the sixth PMOS tube is electrically connected to the gate of the fifth PMOS tube;

[0043] Among them, the node between the gate of the fourth PMOS tube, the gate of the fifth PMOS tube and the gate of the sixth PMOS tube is used to connect a high level, the drain of the fifth PMOS tube is the first output end of the current source module, and the drain of the sixth PMOS tube is the second output end of the current source module.

[0044] In a possible implementation, the OSC power supply circuit further includes:

[0045] a seventh PMOS tube, wherein the source of the seventh PMOS tube is used to connect to a high level, the gate of the seventh PMOS tube is used to receive a third control signal, and the drain of the seventh PMOS tube is electrically connected to the gate of the fourth PMOS tube;

[0046] an eighth PMOS tube, wherein the source of the eighth PMOS tube is used to connect to a high level, the gate of the eighth PMOS tube is used to receive the third control signal, and the drain of the eighth PMOS tube is electrically connected to the gate of the first PMOS tube;

[0047] a ninth PMOS tube, wherein a source of the ninth PMOS tube is electrically connected to a drain of the fourth PMOS tube, a gate of the ninth PMOS tube is used to receive a fourth control signal, and a drain of the ninth PMOS tube is electrically connected to the current source unit;

[0048] a fourth NMOS tube, wherein the source of the fourth NMOS tube is grounded, the gate of the fourth NMOS tube is used to receive the fourth control signal, and the gate of the fourth NMOS tube is electrically connected to the drain of the second NMOS tube;

[0049] a fifth NMOS tube, wherein the source of the fifth NMOS tube is grounded, the gate of the fifth NMOS tube is used to receive the fourth control signal, and the gate of the fifth NMOS tube is electrically connected to the gate of the second NMOS tube;

[0050] a sixth NMOS tube, wherein a drain of the sixth NMOS tube is electrically connected to a drain of the third PMOS tube, a gate of the sixth NMOS tube is used to receive the third control signal, and a source of the sixth NMOS tube is grounded;

[0051] The third control signal and the fourth control signal are different.

[0052] In the embodiment of the present application, multiple MOS tubes are used to control the conduction or disconnection of each branch in the OSC power supply circuit, thereby realizing rapid shutdown of the OSC power supply circuit.

[0053] In a possible implementation, the OSC power supply circuit further includes:

[0054] A first capacitor, wherein a first end of the first capacitor is electrically connected to a gate of the third NMOS transistor;

[0055] a second resistor, wherein a first end of the second resistor is electrically connected to a second end of the first capacitor, and a second end of the second resistor is electrically connected to a drain of the second NMOS transistor;

[0056] a second capacitor, wherein a first end of the second capacitor is electrically connected to the gate of the first PMOS transistor, and a second end of the second capacitor is electrically connected to the drain of the first PMOS transistor;

[0057] A third capacitor, wherein a first end of the third capacitor is electrically connected to the drain of the first PMOS tube, and a second end of the third capacitor is electrically connected to the drain of the second PMOS tube.

[0058] In the embodiment of the present application, the stability of the OSC power supply circuit is ensured by setting a resistor and a plurality of capacitors, thereby ensuring that the OSC power supply circuit outputs a stable power supply.

[0059] In a possible implementation, the integrated OSC circuit further includes:

[0060] A level conversion module, wherein a first input end of the level conversion module is electrically connected to an output end of any one of the inverters in the ring oscillation circuit, and a second input end of the level conversion module is electrically connected to an input end of any one of the inverters;

[0061] A D flip-flop, the input end of the D flip-flop is electrically connected to the output end of the level conversion module, and the D flip-flop is used to output a third clock signal, and the frequency of the third clock signal is 50% of the frequency of the first clock signal.

[0062] In an embodiment of the present application, the level of the first clock signal is converted from the level of the power supply to a high level through a level conversion module, and the clock signal after the level conversion is input into a D flip-flop, thereby outputting a third clock signal, and the frequency of the third clock signal is 50% of the frequency of the first clock signal.

[0063] In a possible implementation, the level conversion module includes:

[0064] a seventh NMOS tube, wherein a gate of the seventh NMOS tube is electrically connected to an output end of any one of the inverters in the ring oscillation circuit, and a source of the seventh NMOS tube is grounded;

[0065] an eighth NMOS tube, wherein a gate of the eighth NMOS tube is electrically connected to an input terminal of any one of the inverters, and a source of the eighth NMOS tube is grounded;

[0066] a tenth PMOS tube, wherein the gate of the tenth PMOS tube is electrically connected to the drain of the eighth NMOS tube, the drain of the tenth PMOS tube is electrically connected to the drain of the seventh NMOS tube, and the source of the tenth PMOS tube is used to connect to a high level;

[0067] an eleventh PMOS tube, wherein the gate of the eleventh PMOS tube is electrically connected to the drain of the seventh NMOS tube, the drain of the eleventh PMOS tube is electrically connected to the drain of the eighth NMOS tube, and the source of the eleventh PMOS tube is used to connect to a high level;

[0068] Among them, the gate of the seventh NMOS tube is the first input end of the level conversion module, the gate of the eighth NMOS tube is the second input end of the level conversion module, and the node between the drain of the eighth NMOS tube, the gate of the tenth PMOS tube and the drain of the eleventh PMOS tube is the output end of the level conversion module.

[0069] In a third aspect, an embodiment of the present application provides an integrated circuit chip, including:

[0070] The integrated OSC circuit of any one of the second aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0071] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0072] Figure 1 A schematic diagram of the structure of an OSC circuit provided in an embodiment of the present application;

[0073] Figure 2 A schematic diagram of the structure of a ring oscillator circuit provided in an embodiment of the present application;

[0074] Figure 3 A schematic diagram of the structure of an inverter provided in an embodiment of the present application;

[0075] Figure 4 A schematic diagram of the structure of another ring oscillator circuit provided in an embodiment of the present application;

[0076] Figure 5 A schematic diagram of the structure of another integrated OSC circuit provided in an embodiment of the present application;

[0077] Figure 6 A schematic diagram of the structure of another ring oscillator circuit provided in an embodiment of the present application;

[0078] Figure 7 A schematic diagram of the structure of an inverter module provided in an embodiment of the present application;

[0079] Figure 8 A schematic diagram of the structure of another ring oscillator circuit provided in an embodiment of the present application;

[0080] Fig. 9 A schematic diagram of the structure of an output circuit provided in an embodiment of the present application;

[0081] Fig.10 A schematic diagram of the structure of a level conversion module provided in an embodiment of the present application;

[0082] Fig.11 A schematic diagram of the structure of an integrated OSC circuit provided in an embodiment of the present application;

[0083] Fig.12 A schematic diagram of the structure of an OSC power supply circuit provided in an embodiment of the present application;

[0084] Fig.13 A schematic diagram of the structure of another OSC power supply circuit provided in an embodiment of the present application;

[0085] Fig.14 A voltage fluctuation comparison diagram of a power supply provided in an embodiment of the present application;

[0086] Fig.15 A schematic diagram of the structure of another OSC power supply circuit provided in an embodiment of the present application;

[0087] Fig.16 A schematic diagram of the structure of another OSC power supply circuit provided in an embodiment of the present application;

[0088] Fig.17 A schematic diagram of the structure of another integrated OSC circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0089] In order to better understand the technical solution of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0090] It should be clear that the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0091] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms "a", "said" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0092] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0093] Many electronic circuits require clock signals to ensure normal operation. Usually, the clock signal is output by an integrated oscillator (OSC) circuit to ensure the normal operation of other electronic circuits. In order to ensure the normal operation of the integrated OSC circuit, in addition to the main OSC circuit, a power supply circuit is also required to supply power to the OSC circuit.

[0094] In the related art, a control signal is set for the OSC power supply circuit, and the user can control the on or off of the OSC power supply circuit by controlling the control signal of the OSC power supply circuit. When the OSC power supply circuit outputs power stably, the OSC circuit starts to work.

[0095] For ease of understanding, an embodiment of the present application provides a schematic diagram of the structure of an OSC circuit in the related art.

[0096] See also Figure 1 , is a schematic diagram of the structure of an OSC circuit provided in an embodiment of the present application. Figure 1 As shown, the OSC circuit 100 includes a ring oscillation circuit 1001, and the ring oscillation circuit 1001 is used to receive a power supply and output a first clock signal.

[0097] In the related art, a ring oscillator circuit includes X inverters, which are connected in series in sequence, and the input end of the first inverter is electrically connected to the output end of the last inverter, where X is an odd number greater than or equal to 3. For ease of understanding, a detailed description is given below taking X=3 as an example.

[0098] See also Figure 2 , is a schematic diagram of the structure of a ring oscillator circuit provided in an embodiment of the present application. Figure 2 As shown, the ring oscillator circuit 1001 includes: a first inverter MC1, a second inverter MC2 and a third inverter MC3. The first inverter, the second inverter and the third inverter are connected in series, and the input end of the first inverter (the first inverter) is electrically connected to the output end of the last inverter (the third inverter). It can be understood that the three inverters form a closed loop to achieve an alternating oscillation output of a fixed frequency. The input end of the ring oscillator circuit is electrically connected to the output end of the OSC power supply circuit, and the power supply VDD_OSC output by the OSC power supply circuit provides power for the three inverters. In the embodiment of the present application, the output end of the third inverter is the output of the ring oscillator circuit, and the node between any two of the three inverters can be used as the output end of the ring oscillator circuit.

[0099] For ease of understanding, an embodiment of the present application also provides a structural schematic diagram of an inverter.

[0100] See also Figure 3 , is a schematic diagram of the structure of an inverter provided in an embodiment of the present application. Figure 3 As shown, the inverter MC is composed of a PMOS tube and an NMOS tube, and the source of the PMOS tube is used to connect a high level, which can be a power supply voltage or a power supply voltage, the gate of the NMOS tube is electrically connected to the gate of the PMOS tube, the drain of the NMOS tube is electrically connected to the drain of the PMOS tube, and the source of the NMOS tube is grounded, wherein the node between the gate of the PMOS tube and the gate of the NMOS tube is the input end of the inverter, and the node between the drain of the PMOS tube and the drain of the NMOS tube is the output end of the inverter.

[0101] In a possible implementation, the ring oscillation circuit also includes a frequency adjustment module, which includes: M inverters (M is an odd number), a resistor and a capacitor. Among them, the M inverters are connected in series in sequence, the input end of the first inverter is electrically connected to the output end of the first inverter among the X inverters, and the output end of the last inverter is electrically connected to the input end of the first inverter among the X inverters, and M is an odd number; the first end of the resistor is electrically connected to the input end of the first inverter among the M inverters; the first end of the capacitor is electrically connected to the output end of the last inverter among the M inverters, and the second end of the capacitor is electrically connected to the second end of the capacitor. Taking one inverter as an example, the ring oscillation circuit with a frequency adjustment module is described in detail below.

[0102] Specifically, see Figure 4 , is a schematic diagram of the structure of another ring oscillator circuit provided in an embodiment of the present application. Figure 4 As shown, in Figure 2 Based on the ring oscillator circuit shown, Figure 4 The ring oscillator circuit shown also includes: a fourth inverter MC4, a third resistor R3 and a fourth capacitor C4. The input end of the fourth inverter is electrically connected to the output end of the first inverter, the first end of the third resistor is electrically connected to the input end of the fourth inverter, the first end of the fourth capacitor is electrically connected to the output end of the fourth inverter, and the second end of the fourth capacitor is electrically connected to the second end of the third resistor.

[0103] In a possible implementation, the third resistor is an adjustable resistor. It is understandable that the oscillation frequency of the ring oscillation circuit can be adjusted by adjusting the resistance value of the third resistor.

[0104] In the above embodiment, a control signal is set for the OSC power supply circuit, and the user can control the on or off of the OSC power supply circuit by controlling the control signal of the OSC power supply circuit. When the OSC power supply circuit outputs power stably, the OSC circuit starts to work. However, since the OSC circuit needs to wait until the OSC power supply circuit is stable before starting to work, when the subsequent electronic circuit needs a clock signal and the situation is urgent, the OSC circuit cannot generate a clock signal in time; and if the power supply circuit and the OSC circuit are always turned on, the life of each component in the OSC circuit will be affected, and more energy will be consumed.

[0105] In view of the above problems, an embodiment of the present application provides an OSC circuit, wherein the OSC circuit includes a ring oscillator circuit, wherein the ring oscillator circuit includes a control signal input terminal, and when the control signal input terminal receives a first control signal, the ring oscillator circuit is used to output a first clock signal; when the control signal input terminal receives a second control signal, the ring oscillator circuit stops outputting the first clock signal, that is, the user can control the on or off of the ring oscillator circuit by inputting different control signals to the control signal input terminal. In some possible implementations, the power supply circuit can remain in a powered-on state and continuously output power supply. When the OSC circuit needs to work, a first control signal is input to the control signal input terminal to turn on the OSC circuit; when the OSC circuit is finished working, a second control signal is input to the control signal input terminal to turn off the OSC circuit, thereby protecting the service life of each device in the OSC circuit and saving energy.

[0106] In an embodiment of the present application, the ring oscillation circuit includes a control signal input terminal. When the control signal input terminal receives a first control signal, the ring oscillation circuit is used to output a first clock signal. When the control signal input terminal receives a second control signal, the ring oscillation circuit is used to stop outputting the first clock signal.

[0107] Specifically, see Figure 5 , is a schematic diagram of the structure of another integrated OSC circuit provided in an embodiment of the present application. Figure 5 As shown, the ring oscillator circuit in this figure is Figure 1 The OSC circuit shown in the figure also includes a control signal input terminal (OSC_ENP). It can be understood that when the user needs the OSC circuit to oscillate and generate the first clock signal, the first control signal can be input to the OSC_ENP port, and when the user does not need the OSC circuit to oscillate and generate the first clock signal, the second control signal can be input to the OSC_ENP port.

[0108] In a possible implementation, the ring oscillation circuit includes: a NAND gate, a frequency control module and an inverter module, wherein the first input end of the NAND gate is a control signal input end, when the control signal input end receives a first control signal, the ring oscillation circuit is used to output a first clock signal, when the control signal input end receives a second control signal, the ring oscillation circuit is used to stop outputting the first clock signal, and the frequency control module is used to control the frequency of the first clock signal. The ring oscillation circuit is described in detail below.

[0109] See also Figure 6 , is a schematic diagram of the structure of another ring oscillator circuit provided in an embodiment of the present application. Figure 6As shown, the ring oscillator circuit 1001 includes: a NAND gate, a frequency control module 601 and an inverter module 602. Among them, the first input end (OSC_ENP) of the NAND gate is a control signal input end, the second input end of the NAND gate is electrically connected to the output end of the inverter module 602, and the output end of the NAND gate is electrically connected to the input end of the frequency control module 601.

[0110] The inverter module 602 includes N inverters, which are sequentially connected in series, the input end of the first inverter is electrically connected to the output end of the NAND gate, and the output end of the last inverter is electrically connected to the second input end of the NAND gate, and N is an even number greater than or equal to 2. The following takes N as 2 as an example for detailed description.

[0111] See also Figure 7 , is a schematic diagram of the structure of an inverter module provided in an embodiment of the present application. Figure 7 As shown, the inverter module 602 includes a fifth inverter MC5 and a sixth inverter MC6. The input end of the fifth inverter is electrically connected to the output end of the NAND gate; the input end of the sixth inverter is electrically connected to the output end of the fifth inverter, and the output end of the sixth inverter is electrically connected to the second input end of the NAND gate, wherein the output end of the sixth inverter is the output end of the inverter module 602. It should be noted that the node between any two inverters can be used as the output end of the ring oscillation circuit, and the embodiment of the present application does not impose specific restrictions on this.

[0112] like Figure 4 As described in the embodiment, the ring oscillation circuit also includes a frequency adjustment module, which includes: M inverters, the M inverters are connected in series in sequence, the input end of the first inverter is electrically connected to the output end of the NAND gate, the output end of the last inverter is electrically connected to the input end of the first inverter among the N inverters, and M is an odd number; a resistor, the first end of the resistor is electrically connected to the input end of the first inverter among the M inverters; a capacitor, the first end of the capacitor is electrically connected to the output end of the last inverter among the M inverters, and the second end of the capacitor is electrically connected to the second end of the resistor. For ease of understanding, the embodiment of the present application also provides a structural schematic diagram of another ring oscillation circuit.

[0113] See also Figure 8 , is a schematic diagram of the structure of another ring oscillator circuit provided in an embodiment of the present application. Figure 8 As shown, in Figure 7On the basis of the ring oscillation circuit shown in FIG. 1 , the ring oscillation circuit further includes: a seventh inverter MC7, a fourth resistor R4 and a fifth capacitor C5. The input end of the seventh inverter is electrically connected to the output end of the NAND gate, the first end of the fourth resistor is electrically connected to the input end of the seventh inverter, the first end of the fifth capacitor is electrically connected to the output end of the seventh inverter, and the second end of the fifth capacitor is electrically connected to the second end of the fourth resistor.

[0114] It should be noted that the OSC circuit cannot directly output the first clock signal, so the integrated OSC circuit in the embodiment of the present application also includes an output circuit, which is used to receive the first clock signal output by the OSC circuit and output the second clock signal or the third clock signal. The following is a detailed description in conjunction with the accompanying drawings and specific embodiments.

[0115] In a possible implementation, the integrated OSC circuit includes a level conversion module and Y inverters, the first input end of the level conversion module is electrically connected to the output end of any inverter in the ring oscillation circuit, the second input end of the level conversion module is electrically connected to the input end of the inverter, the Y inverters are connected in series in sequence, the input end of the first inverter is electrically connected to the output end of the level conversion module, the output end of the last inverter is used to output the second clock signal, and Y is greater than or equal to 1. The following takes Y as 1 as an example for detailed description.

[0116] In a possible implementation, some electronic circuits require a clock signal of a specific frequency, so the Y inverters in the output module can be replaced with D flip-flops.

[0117] See also Fig. 9 , is a schematic diagram of the structure of an output circuit provided in an embodiment of the present application. Fig. 9 As shown, the output circuit includes a level conversion module 900 and a D flip-flop, and the input end of the D flip-flop is electrically connected to the output end of the level conversion module. The D flip-flop is used to output a third clock signal, and the frequency of the third clock signal is 50% of the frequency of the first clock signal.

[0118] In a possible implementation, the level conversion module includes two NMOS transistors and two PMOS transistors.

[0119] Specifically, see Fig.10 , is a schematic diagram of the structure of a level conversion module provided in an embodiment of the present application. Fig.10As shown, the level conversion module 900 includes a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, a tenth PMOS transistor MP10 and an eleventh PMOS transistor MP11. The gate of the seventh NMOS tube is electrically connected to the output end of any inverter in the ring oscillation circuit, and the source of the seventh NMOS tube is grounded; the gate of the eighth NMOS tube is electrically connected to the input end of any inverter, and the source of the eighth NMOS tube is grounded; the gate of the tenth PMOS tube is electrically connected to the drain of the eighth NMOS tube, the drain of the tenth PMOS tube is electrically connected to the drain of the seventh NMOS tube, and the source of the tenth PMOS tube is used to connect to a high level; the gate of the eleventh PMOS tube is electrically connected to the drain of the seventh NMOS tube, the drain of the eleventh PMOS tube is electrically connected to the drain of the eighth NMOS tube, and the source of the eleventh PMOS tube is used to connect to a high level; the gate of the seventh NMOS tube is the first input end of the level conversion module, the gate of the eighth NMOS tube is the second input end of the level conversion module, and the node between the drain of the eighth NMOS tube, the gate of the tenth PMOS tube and the drain of the eleventh PMOS tube is the output end of the level conversion module.

[0120] It can be understood that, through the level conversion module, the amplitude of the first clock signal can be adjusted to the power supply voltage VDD or any other voltage.

[0121] The above embodiment is an OSC circuit part in an integrated OSC circuit. In the above embodiment, the user can control the on or off of the ring oscillation circuit by inputting different control signals to the control signal input terminal. In some possible implementations, the power supply circuit can remain in a powered-on state and continuously output the power supply. When the OSC circuit needs to work, a first control signal is input to the control signal input terminal to turn on the OSC circuit; when the OSC circuit is finished working, a second control signal is input to the control signal input terminal to turn off the OSC circuit, thereby protecting the service life of each device in the OSC circuit and saving energy.

[0122] In addition to the OSC circuit, the integrated OSC circuit also includes an OSC power supply circuit to supply power to the OSC circuit. Specifically, a detailed description will be given below in conjunction with the accompanying drawings.

[0123] See also Fig.11 , is a schematic diagram of the structure of an integrated OSC circuit provided in an embodiment of the present application. Fig.11 As shown, the integrated OSC circuit includes an OSC power supply circuit 1100 and an OSC circuit 100. The input end of the OSC circuit 100 is electrically connected to the output end of the OSC power supply circuit 1100, the OSC power supply circuit 1200 is used to output power supply, and the OSC circuit 100 is used to receive power supply.

[0124] The embodiment of the present application also provides a structural schematic diagram of an OSC power supply circuit, which is described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0125] See also Fig.12 , is a schematic diagram of the structure of an OSC power supply circuit provided in an embodiment of the present application. Fig.12 As shown, the OSC power supply circuit 1100 includes a current source module IDC, a first PMOS transistor MP1, a first resistor R1, a second PMOS transistor MO2, a first NMOS transistor MN1, a second NMOS transistor MN2 and a third NMOS transistor MN3. Fig.12 As shown, a current source module is used to output a constant current, and the current source module includes: a fourth PMOS tube MP4, a fifth PMOS tube MP5, a sixth PMOS tube MP6 and a current source unit IDC'. The source of the fourth PMOS tube is used to connect to a high level, the gate of the fourth PMOS tube is electrically connected to the drain of the fourth PMOS tube, the drain of the fourth PMOS tube is electrically connected to the current source unit, and the current source unit is used to output a constant current; the source of the fifth PMOS tube is used to connect to a high level, the gate of the fifth PMOS tube is electrically connected to the gate of the fourth PMOS tube; the source of the sixth PMOS tube is used to connect to a high level, and the gate of the sixth PMOS tube is electrically connected to the gate of the fifth PMOS tube; wherein the node between the gate of the fourth PMOS tube, the gate of the fifth PMOS tube and the gate of the sixth PMOS tube is used to connect to a high level, the drain of the fifth PMOS tube is the first output end of the current source module, the drain of the sixth PMOS tube is the second output end of the current source module, the first output end of the current source module is used to output a first current I1, and the second output end of the current source module is used to output a second current I2. In practical applications, I1 and I2 can be provided respectively by a current source module, or I1 can be provided by a first current source module and I2 can be provided by a second current source module. In the embodiment of the present application, I1 and I2 are provided respectively by a current source module. In the present embodiment, the first current I1 is equal to the second current I2, but this should not be used as a limitation on the protection scope of the present application. Those skilled in the art can set the first current I1 and the second current I2 to any value according to actual needs.

[0126] The source of the first PMOS tube is used to connect to a high level, and the gate of the first PMOS tube is electrically connected to the first output end of the current source module; the first end of the first resistor is electrically connected to the drain of the first PMOS tube; the source of the second PMOS tube is electrically connected to the second end of the first resistor, and the gate of the second PMOS tube is electrically connected to the drain of the second PMOS tube; the gate of the first NMOS tube is electrically connected to the drain of the first NMOS tube, the gate of the second PMOS tube, and the drain of the second PMOS tube, respectively, and the source of the first NMOS tube is grounded; the drain of the second NMOS tube is electrically connected to the second output end of the current source module, the gate of the second NMOS tube is electrically connected to the gate of the first NMOS tube, and the source of the second NMOS tube is grounded; the gate of the third NMOS tube is electrically connected to the drain of the second NMOS tube, the drain of the third NMOS tube is electrically connected to the gate of the first PMOS tube, and the source of the third NMOS tube is grounded; wherein, the drain of the first PMOS tube is used to output the power supply. It should be pointed out that in order to more clearly show the circuit structure of the OSC power supply circuit, some related circuits are not shown in the figure.

[0127] Specifically, in the embodiment of the present application, if the OSC power supply circuit is to work normally, that is, the MOS tube in the circuit works in the saturation region, VDD≥Vdsat(MP1)+Vgs(MP2)+Vgs(MN1)+Vdsat(IDC) is required. It can be understood that Vdsat(MP1) is much smaller than Vgs(MP1), and in the embodiment of the present application, the width-to-length ratio of the first PMOS tube is relatively large, and Vdsat is very small (only tens of millivolts), so even if the power supply voltage VDD is low (for example, 1.5V), the OSC power supply circuit can work normally, thereby outputting a stable power supply.

[0128] When the OSC power supply circuit works normally, the first PMOS tube is turned on, the current source module provides a constant current I1 for the third NMOS tube, and provides a constant current I2 for the second NMOS tube. Since the second NMOS tube and the first NMOS tube form a current mirror, the current of the branch where the first NMOS tube is located is I2. Among them, the currents I1 and I2 can be the same or different, that is, I1 and I2 can be provided respectively by a current source module, or I1 can be provided by the first current source module and I2 can be provided by the second current source module. Those skilled in the art can set the number of current source modules and the magnitude of the currents I1 and I2 according to actual needs.

[0129] When the OSC power supply circuit works normally, the current provided by the first PMOS tube is divided into two parts: the power supply part and the first resistor, the second PMOS tube and the first NMOS tube part, and the voltage of these two parts is the same, so the power supply voltage VDD_OSC is actually: VDD_OSC = I2 × R1 + Vgs (MP2) + Vgs (MN1). When R1 is 0, the power supply voltage VDD_OSC is the minimum, that is, VDD_OSC = Vgs (MP2) + Vgs (MN1). Since the power supply is output by the first PMOS tube, the upper limit of the power supply voltage is VDD_OSC = VDD-Vdsat (MP1), where Vdsat (MP1) is very small, only about tens of millivolts. That is to say, in the embodiment of the present application, Vgs(MP2)+Vgs(MN1)≤VDD_OSC<VDD-Vdsat(MP1), wherein Vgs(MP2)+Vgs(MN1) is relatively small, approximately 1.2V, and VDD-Vdsat(MP1) is approximately equal to VDD, so the voltage range of VDD_OSC is relatively wide. Because when the OSC circuit oscillates, it will draw current, thereby affecting the voltage of the OSC circuit, and the VDD_OSC with a wider voltage range can suppress the influence of the OSC circuit drawing current on the OSC circuit voltage, thereby making the OSC power supply circuit output a relatively stable power supply.

[0130] In a possible implementation, the first resistor is an adjustable resistor. As described above, the voltage VDD_OSC of the power supply is actually: VDD_OSC=I2×R1+Vgs(MP2)+Vgs(MN1). The user can control the voltage VDD_OSC of the power supply by adjusting the resistance value of the first resistor R1.

[0131] When the OSC power supply circuit outputs a relatively stable power supply, in some cases, the voltage of the power supply will change significantly. For example, when the OSC circuit is just started, a large current is drawn instantly, and the voltage of the power supply will drop significantly. In the embodiment of the present application, by adding a third NMOS tube, the OSC power supply circuit forms a negative feedback loop.

[0132] Specifically, when the voltage of the power supply is greatly reduced, since the voltage of the power supply is the same as the voltage of the branch where the first resistor, the second PMOS tube and the first NMOS tube are located, the voltage of the branch is reduced. In other words, the gate voltage of the second NMOS tube is reduced, because the gate and drain voltages of the MOS tube change in opposite directions, so the drain voltage of the second NMOS tube (that is, the gate of the third NMOS tube) increases, so the drain voltage of the third NMOS tube (that is, the gate of the first PMOS tube) decreases. Since the conduction degree between the drain and the source increases when the gate voltage of the PMOS tube is reduced, a higher power supply can be provided, thereby ensuring the stability of the power supply.

[0133] In a possible implementation, the OSC circuit is composed of a plurality of inverters of the same specifications, and the inverter is composed of a PMOS tube and an NMOS tube. In the embodiment of the present application, the second PMOS tube in the OSC power supply circuit has the same specifications as the PMOS tube in the inverter, and the first NMOS tube has the same specifications as the NMOS tube in the inverter. It can be understood that when any MOS tube in the inverter of the OSC circuit is affected by temperature or process and causes Vth to change, VDD_OSC may change. However, since the second PMOS tube and the first NMOS tube in the OSC power supply circuit have the same specifications as the MOS tube in the inverter, the Vth change of the second PMOS tube and the first NMOS tube is the same as the Vth change of the MOS tube in the inverter, thereby offsetting the influence of temperature and process on VDD_OSC. For example, when the internal resistance of the inverter in the OSC circuit becomes smaller due to the process angle, the oscillation frequency of the OSC circuit will be accelerated. Since the second PMOS tube and the first NMOS tube have the same process as the MOS tube in the inverter, the resistance of the second PMOS tube and the first NMOS tube also becomes smaller, thereby reducing the voltage VDD_OSC of the power supply, thereby reducing the oscillation frequency of the OSC circuit. Therefore, the OSC power supply circuit can ensure a stable output power supply under all processes, voltages and temperatures (PVT).

[0134] In a possible implementation, in order to enable the OSC power supply circuit to respond faster when the power supply voltage drops significantly, a PMOS tube is added to the OSC power supply circuit.

[0135] See also Fig.13 , is a schematic diagram of the structure of another OSC power supply circuit provided in an embodiment of the present application. Fig.12 The OSC power supply circuit shown, Fig.13A third PMOS tube is added to the OSC power supply circuit shown, the gate of the third PMOS tube is electrically connected to the drain of the first PMOS tube, the source of the third PMOS tube is electrically connected to the gate of the first PMOS tube, and the drain of the third PMOS tube is grounded.

[0136] When the voltage of the power supply drops significantly, the gate voltage of the third PMOS tube also drops significantly. When the difference between the gate voltage of the third PMOS tube and the source voltage of the third PMOS tube is greater than or equal to the turn-on voltage of the third PMOS tube, the third PMOS tube is turned on. At this time, the gate of the first PMOS tube is directly grounded, and the first PMOS tube is turned on instantly, instantly raising the voltage of the power supply. It can be understood that Figure 3 The OSC power supply circuit shown responds faster to a significant decrease in the power supply voltage, and the power supply voltage can be stabilized near a desired voltage more quickly.

[0137] To facilitate understanding, an embodiment of the present application also provides a voltage fluctuation comparison diagram of a power supply.

[0138] See also Fig.14 , is a voltage fluctuation comparison diagram of a power supply provided in an embodiment of the present application. Fig.14 As shown in Figure 2, both curves are voltage variation curves of the power supply. The OSC power supply circuit corresponding to the dotted line is Fig.13 The OSC power supply circuit shown in FIG. 1 is a solid line corresponding to the OSC power supply circuit. Fig.12 The OSC power supply circuit shown. Obviously, when the voltage of the power supply is greatly reduced, the voltage of the power supply corresponding to the dotted line increases faster, that is, Fig.13 The OSC supply circuit shown has a faster response speed. Fig.14 The horizontal line in the middle is the expected voltage V0. When the voltage of the power supply drops significantly, the power supply voltage shown by the dotted line only needs t1-t0 to recover to the expected voltage V0. The power supply voltage shown needs t2-t0 to recover to the expected voltage V0. Obviously, t1-t0 is much longer than t2-t0. So compared to Fig.12 The OSC power supply circuit shown, Fig.13 The OSC power supply circuit shown can make the voltage of the power supply reach the desired voltage V0 faster. Therefore, Fig.13 The OSC power supply circuit shown responds faster to a significant decrease in the power supply voltage, and the power supply voltage can be stabilized near a desired voltage more quickly.

[0139] In the above embodiment, the first PMOS tube, the first NMOS tube, the second NMOS tube, the fourth PMOS tube, the fifth PMOS tube and the sixth PMOS tube are always kept in the on state, that is, the OSC power supply circuit is always kept in the powered-on state and continuously outputs the power supply. However, this will have a certain impact on the life of the OSC power supply circuit. Therefore, in a possible implementation, some MOS tubes are added to the OSC power supply circuit to receive the control signal input by the user, so as to control the on and off of the OSC power supply circuit. In view of this, the embodiment of the present application provides another OSC power supply circuit.

[0140] See also Fig.15 , is a schematic diagram of the structure of another OSC power supply circuit provided in an embodiment of the present application. Fig.15 As shown, the OSC power supply circuit, based on the OSC power supply circuit of the above embodiment, further includes: a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a fourth NMOS tube, a fifth NMOS tube and a sixth NMOS tube. Among them, the source of the seventh PMOS tube is used to connect to a high level, the gate of the seventh PMOS tube is used to receive a third control signal, and the drain of the seventh PMOS tube is electrically connected to the gate of the fourth PMOS tube; the source of the eighth PMOS tube is used to connect to a high level, the gate of the eighth PMOS tube is used to receive a third control signal, and the drain of the eighth PMOS tube is electrically connected to the gate of the first PMOS tube; the source of the ninth PMOS tube is electrically connected to the drain of the fourth PMOS tube, the gate of the ninth PMOS tube is used to receive a fourth control signal, and the drain of the ninth PMOS tube is electrically connected to the current source unit. ; The source of the fourth NMOS tube is grounded, the gate of the fourth NMOS tube is used to receive the fourth control signal, and the gate of the fourth NMOS tube is electrically connected to the drain of the second NMOS tube; the source of the fifth NMOS tube is grounded, the gate of the fifth NMOS tube is used to receive the fourth control signal, and the gate of the fifth NMOS tube is electrically connected to the gate of the second NMOS tube; the drain of the sixth NMOS tube is electrically connected to the drain of the third PMOS tube, the gate of the sixth NMOS tube is used to receive the third control signal, and the source of the sixth NMOS tube is grounded; wherein the third control signal and the fourth control signal are different. In the embodiment of the present application, the third control signal interface is Fig.15 The fourth control signal interface is POWER_ENP shown in Fig.15 POWER_ENN shown.

[0141] It can be understood that the seventh PMOS tube can control the conduction and disconnection of the fourth PMOS tube, the fifth PMOS tube and the sixth PMOS tube, the eighth PMOS tube can control the conduction and disconnection of the first PMOS tube, the fifth NMOS tube can control the conduction and disconnection of the third NMOS tube, the fifth NMOS tube can control the conduction and disconnection of the first NMOS tube and the second NMOS tube, and the sixth NMOS tube can realize the control of the third PMOS tube. When the sixth NMOS tube is turned on, if the gate voltage of the third PMOS tube is greatly reduced to cause the third PMOS tube to be turned on, the gate voltage of the first PMOS tube will be approximately 0, and a rapid response to the change of the power supply can be realized at this time. However, when the sixth NMOS tube is disconnected, even if the gate voltage of the third PMOS tube is greatly reduced to cause the third PMOS tube to be turned on, the gate voltage of the first PMOS tube will not be reduced to 0, and the third PMOS tube cannot be used to realize a rapid response to the change of the power supply. The ninth PMOS tube can prevent the current of the current source unit from backflowing into the OSC power supply circuit when the OSC power supply circuit stops working, thereby protecting the components in the OSC power supply circuit.

[0142] It can be understood that when POWER_ENP=VDD and POWER_ENN=0, the seventh PMOS tube, the eighth PMOS tube, the fifth NMOS tube and the fourth NMOS tube are all disconnected, the ninth PMOS tube and the sixth NMOS tube are all turned on, and the OSC power supply circuit works normally; when POWER_ENP=0 and POWER_ENN=VDD, the seventh PMOS tube, the eighth PMOS tube, the fifth NMOS tube and the fourth NMOS tube are all turned on, the ninth PMOS tube and the sixth NMOS tube are all disconnected, and the OSC power supply circuit stops working.

[0143] In a possible implementation, in order to make the OSC power supply circuit more stable, multiple capacitors and resistors are added to the OSC power supply circuit. For ease of understanding, the present application embodiment also provides a schematic diagram of the structure of another OSC power supply circuit.

[0144] See also Fig.16 , is a schematic diagram of the structure of another OSC power supply circuit provided in an embodiment of the present application. Fig.16 As shown, the OSC power supply circuit is Fig.15On the basis of the OSC power supply circuit shown, it also includes: a first capacitor C1, a second resistor R2, a second capacitor C2 and a third capacitor C3. The first end of the first capacitor is electrically connected to the gate of the third NMOS tube; the first end of the second resistor is electrically connected to the second end of the first capacitor, and the second end of the second resistor is electrically connected to the drain of the second NMOS tube; the first end of the second capacitor is electrically connected to the gate of the first PMOS tube, and the second end of the second capacitor is electrically connected to the drain of the first PMOS tube; the first end of the third capacitor is electrically connected to the drain of the first PMOS tube, and the second end of the third capacitor is electrically connected to the drain of the second PMOS tube.

[0145] It can be understood that the first capacitor and the second resistor are connected in series to separate the poles of the second NMOS tube and the third NMOS tube, and can prevent voltage mutations and absorb overvoltages in the peak state. The second capacitor is a feedforward path for the power supply VDD_OSC. In the time domain, the drain voltage and the gate voltage of the first PMOS tube change in the same direction through the charge pump effect. For example, when the OSC circuit causes VDD_OSC to drop due to oscillation, the voltage of the second capacitor drops synchronously due to the charge pump effect, thereby causing the gate voltage of the first PMOS tube to decrease, and the first PMOS tube is quickly turned on to quickly pull up VDD_OSC, and vice versa. The third capacitor is a zero-point capacitor, which is used to compensate for the phase shift introduced by the feedback circuit.

[0146] The above embodiments are all OSC power supply circuit parts in the integrated OSC circuit. In the above embodiments, the power supply is provided for the OSC circuit through voltage division by the first PMOS tube, the first resistor, the second PMOS tube and the first NMOS tube. The voltage of the power supply is equal to the sum of the voltage drops on the first resistor, the second PMOS tube and the first NMOS tube, and is not affected by the high-level voltage. Moreover, the voltage required for the MOS tubes in the circuit to work in the saturation region at the same time is relatively small. Even if the OSC power supply circuit works at a low voltage, the MOS tubes in the circuit can still be ensured to work in the saturation region at the same time, thereby ensuring the stability of the power supply.

[0147] See also Fig.17, is a structural diagram of another integrated OSC circuit provided in an embodiment of the present application. Through the integrated OSC circuit provided in an embodiment of the present application, on the one hand, the OSC circuit includes a ring oscillation circuit, and the ring oscillation circuit includes a control signal input terminal. When the control signal input terminal receives a first control signal, the ring oscillation circuit is used to output a first clock signal; when the control signal input terminal receives a second control signal, the ring oscillation circuit stops outputting the first clock signal, that is, the user can control the conduction or disconnection of the ring oscillation circuit by inputting different control signals to the control signal input terminal. In some possible implementations, the power supply circuit can remain in a powered-on state and continuously output power supply. When the OSC circuit is required to work, a first control signal is input to the control signal input terminal to turn on the OSC circuit; when the OSC circuit is finished working, a second control signal is input to the control signal input terminal to turn off the OSC circuit, thereby protecting the service life of each device in the OSC circuit and saving energy. On the other hand, the power supply is provided for the OSC circuit through voltage division by the first PMOS tube, the first resistor, the second PMOS tube and the first NMOS tube. The voltage of the power supply is equal to the sum of the voltage drops on the first resistor, the second PMOS tube and the first NMOS tube, and is not affected by the high-level voltage. Moreover, the voltage required for the MOS tubes in the circuit to work in the saturation region at the same time is relatively small. Even if the OSC power supply circuit works at a low voltage, the MOS tubes in the circuit can still be ensured to work in the saturation region at the same time, thereby ensuring the stability of the power supply.

[0148] In the embodiments of the present application, "at least one" refers to one or more, and "plurality" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent the existence of A alone, the existence of A and B at the same time, and the existence of B alone. Among them, A and B can be singular or plural. The character " / " generally indicates that the previous and subsequent associated objects are in an "or" relationship. "At least one of the following" and similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b and c can be represented by: a, b, c, ab, ac, bc, or abc, where a, b, c can be single or multiple.

[0149] Those of ordinary skill in the art will appreciate that the various units and algorithm steps described in the embodiments disclosed herein can be implemented in a combination of electronic hardware, computer software, and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0150] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0151] In several embodiments provided in the present application, any function can be stored in a computer-readable storage medium if it is implemented in the form of a software functional unit and sold or used as an independent product. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, etc., and other media that can store program codes.

[0152] In this specification, the same or similar parts between the various embodiments can be referred to each other. In particular, for the device embodiment and the terminal embodiment, since they are basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the description in the method embodiment.

Claims

1. An OSC circuit, characterized in that: include: A ring oscillation circuit comprises a NAND gate, a frequency control module and an inverter module, wherein the first input end of the NAND gate is a control signal input end, the second input end of the NAND gate is electrically connected to the output end of the inverter module, and the output end of the NAND gate is electrically connected to the input end of the frequency control module; When the control signal input end receives a first control signal, the ring oscillation circuit is used to output a first clock signal; when the control signal input end receives a second control signal, the ring oscillation circuit is used to stop outputting the first clock signal; and the frequency control module is used to control the frequency of the first clock signal.

2. The circuit according to claim 1, characterized in that The inverter module comprises: N inverters are connected in series in sequence, the input end of the first inverter is electrically connected to the output end of the NAND gate, the output end of the last inverter is electrically connected to the second input end of the NAND gate, and N is an even number greater than or equal to 2.

3. The circuit according to claim 2, characterized in that The frequency control module comprises: M inverters, the M inverters are sequentially connected in series, the input end of the first inverter is electrically connected to the output end of the NAND gate, the output end of the last inverter is electrically connected to the input end of the first inverter among the N inverters, and M is an odd number; a third resistor, a first end of the third resistor being electrically connected to an input end of a first inverter among the M inverters; A fourth capacitor, wherein a first end of the fourth capacitor is electrically connected to an output end of the last inverter among the M inverters, and a second end of the fourth capacitor is electrically connected to a second end of the third resistor and an input end of the first inverter in the inverter module, respectively.

4. The circuit according to claim 3, characterized in that The third resistor is an adjustable resistor.

5. An integrated OSC circuit, characterized in that: include: A power supply circuit, used for outputting power supply; The OSC circuit according to any one of claims 1 to 4, wherein the OSC circuit is used to receive the power supply.

6. The circuit according to claim 5, characterized in that The power supply circuit comprises: A current source module, used for outputting a constant current; A first PMOS tube, wherein a source of the first PMOS tube is used to connect to a high level, and a gate of the first PMOS tube is electrically connected to a first output end of the current source module; a first resistor, wherein a first end of the first resistor is electrically connected to a drain of the first PMOS tube; a second PMOS tube, wherein a source of the second PMOS tube is electrically connected to the second end of the first resistor, and a gate of the second PMOS tube is electrically connected to a drain of the second PMOS tube; a first NMOS transistor, wherein a gate of the first NMOS transistor is electrically connected to a drain of the first NMOS transistor, a gate of the second PMOS transistor, and a drain of the second PMOS transistor, respectively, and a source of the first NMOS transistor is grounded; a second NMOS tube, wherein the drain of the second NMOS tube is electrically connected to the second output end of the current source module, the gate of the second NMOS tube is electrically connected to the gate of the first NMOS tube, and the source of the second NMOS tube is grounded; a third NMOS tube, wherein the gate of the third NMOS tube is electrically connected to the drain of the second NMOS tube, the drain of the third NMOS tube is electrically connected to the gate of the first PMOS tube, and the source of the third NMOS tube is grounded; Wherein, the drain of the first PMOS tube is used to output power supply.

7. The circuit according to claim 6, characterized in that The first resistor is an adjustable resistor.

8. The circuit according to claim 6, characterized in that The OSC power supply circuit further includes: A third PMOS tube, wherein the gate of the third PMOS tube is electrically connected to the drain of the first PMOS tube, the source of the third PMOS tube is electrically connected to the gate of the first PMOS tube, and the drain of the third PMOS tube is grounded.

9. The circuit according to claim 8, characterized in that The current source module comprises: a fourth PMOS tube, wherein the source of the fourth PMOS tube is used to connect to a high level, the gate of the fourth PMOS tube is electrically connected to the drain of the fourth PMOS tube, the drain of the fourth PMOS tube is electrically connected to a current source unit, and the current source unit is used to output a constant current; a fifth PMOS tube, wherein the source of the fifth PMOS tube is used to connect to a high level, and the gate of the fifth PMOS tube is electrically connected to the gate of the fourth PMOS tube; a sixth PMOS tube, wherein the source of the sixth PMOS tube is used to connect to a high level, and the gate of the sixth PMOS tube is electrically connected to the gate of the fifth PMOS tube; Among them, the node between the gate of the fourth PMOS tube, the gate of the fifth PMOS tube and the gate of the sixth PMOS tube is used to connect a high level, the drain of the fifth PMOS tube is the first output end of the current source module, and the drain of the sixth PMOS tube is the second output end of the current source module.

10. The circuit according to claim 9, characterized in that The OSC power supply circuit further includes: a seventh PMOS tube, wherein the source of the seventh PMOS tube is used to connect to a high level, the gate of the seventh PMOS tube is used to receive a third control signal, and the drain of the seventh PMOS tube is electrically connected to the gate of the fourth PMOS tube; an eighth PMOS tube, wherein the source of the eighth PMOS tube is used to connect to a high level, the gate of the eighth PMOS tube is used to receive the third control signal, and the drain of the eighth PMOS tube is electrically connected to the gate of the first PMOS tube; a ninth PMOS tube, wherein a source of the ninth PMOS tube is electrically connected to a drain of the fourth PMOS tube, a gate of the ninth PMOS tube is used to receive a fourth control signal, and a drain of the ninth PMOS tube is electrically connected to the current source unit; a fourth NMOS tube, wherein the source of the fourth NMOS tube is grounded, the gate of the fourth NMOS tube is used to receive the fourth control signal, and the gate of the fourth NMOS tube is electrically connected to the drain of the second NMOS tube; a fifth NMOS tube, wherein the source of the fifth NMOS tube is grounded, the gate of the fifth NMOS tube is used to receive the fourth control signal, and the gate of the fifth NMOS tube is electrically connected to the gate of the second NMOS tube; a sixth NMOS tube, wherein a drain of the sixth NMOS tube is electrically connected to a drain of the third PMOS tube, a gate of the sixth NMOS tube is used to receive the third control signal, and a source of the sixth NMOS tube is grounded; The third control signal and the fourth control signal are different.

11. The circuit according to claim 10, characterized in that The OSC power supply circuit further includes: A first capacitor, wherein a first end of the first capacitor is electrically connected to a gate of the third NMOS transistor; a second resistor, wherein a first end of the second resistor is electrically connected to a second end of the first capacitor, and a second end of the second resistor is electrically connected to a drain of the second NMOS transistor; a second capacitor, wherein a first end of the second capacitor is electrically connected to the gate of the first PMOS transistor, and a second end of the second capacitor is electrically connected to the drain of the first PMOS transistor; A third capacitor, wherein a first end of the third capacitor is electrically connected to the drain of the first PMOS tube, and a second end of the third capacitor is electrically connected to the drain of the second PMOS tube.

12. The circuit according to claim 5, characterized in that The integrated OSC circuit further comprises: A level conversion module, wherein a first input end of the level conversion module is electrically connected to an output end of any one of the inverters in the ring oscillation circuit, and a second input end of the level conversion module is electrically connected to an input end of any one of the inverters; A D flip-flop, the input end of the D flip-flop is electrically connected to the output end of the level conversion module, and the D flip-flop is used to output a third clock signal, and the frequency of the third clock signal is 50% of the frequency of the first clock signal.

13. The circuit according to claim 12, characterized in that The level conversion module comprises: a seventh NMOS tube, wherein a gate of the seventh NMOS tube is electrically connected to an output end of any one of the inverters in the ring oscillation circuit, and a source of the seventh NMOS tube is grounded; an eighth NMOS tube, wherein a gate of the eighth NMOS tube is electrically connected to an input terminal of any one of the inverters, and a source of the eighth NMOS tube is grounded; a tenth PMOS tube, wherein the gate of the tenth PMOS tube is electrically connected to the drain of the eighth NMOS tube, the drain of the tenth PMOS tube is electrically connected to the drain of the seventh NMOS tube, and the source of the tenth PMOS tube is used to connect to a high level; an eleventh PMOS tube, wherein the gate of the eleventh PMOS tube is electrically connected to the drain of the seventh NMOS tube, the drain of the eleventh PMOS tube is electrically connected to the drain of the eighth NMOS tube, and the source of the eleventh PMOS tube is used to connect to a high level; Among them, the gate of the seventh NMOS tube is the first input end of the level conversion module, the gate of the eighth NMOS tube is the second input end of the level conversion module, and the node between the drain of the eighth NMOS tube, the gate of the tenth PMOS tube and the drain of the eleventh PMOS tube is the output end of the level conversion module.

14. An integrated circuit chip, characterized in that: include: The integrated OSC circuit according to any one of claims 5 to 13.

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