Device and method for improving precision of PTP (Precision Time Protocol) timestamp based on phase-shift coding

Abstract

The invention discloses a device for improving the precision of a PTP timestamp based on phase shift coding, and the device comprises a first FPGA PLL module, a reference clock generated by the first FPGA PLL module is inputted into a second FPGA PLL module to generate N phase clocks in a split-phase manner, a coding module extracts a hardware timestamp from an RTC timing module when a physical layer PHY chip sends and receives a data effective signal, and the coding module carries out the phase shift coding on the hardware timestamp. And encoding the hardware timestamp by using the reference clock and the phase clock, thereby generating a corrected timestamp. The invention further discloses a method for improving the precision of the PTP timestamp based on phase-shift coding, clock phase splitting and coding are realized through the FPGA, so that the precision of the timestamp of the time synchronization message received by the receiving end is improved, the precision of the timestamp of the receiving end is greatly improved under the conditions that the clock frequency is not improved and FPGA logic resources are saved, and the precision of the time synchronization message is improved. And thus, the PTP time synchronization precision is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of time synchronization, and in particular to a device for improving the precision of a PTP timestamp based on phase-shift coding, and also to a method for improving the precision of a PTP timestamp based on phase-shift coding. Background Art

[0002] As a network time synchronization technology based on Ethernet, PTP can achieve sub-microsecond accurate time synchronization and has been widely used in navigation, positioning, communication, rail transportation, smart grid and other fields. PTP records timestamps at the network physical layer and exchanges message data through the master-slave link. The slave node receives and sends the timestamps based on the received t 1 ,t 2 ,t 3 ,t 4 The four timestamps calculate the average delay of the master-slave link and the master-slave node clock offset Offset, and perform time correction to achieve time synchronization between the master and slave nodes. Figure 1 As shown, when the default round-trip path is symmetrical, the formula is satisfied:

[0003]

[0004] Where Offset is the clock deviation between the master and slave nodes; t 1 The timestamp of the time when the PTP master node sends the Sync message; t 2 The timestamp of the moment when the PTP slave node receives the Sync message; t 3 The timestamp of the moment when the PTP slave node sends the Delay_Req message in the PTP message period; t 4 The timestamp of the time when the PTP master node receives the Delay_Req message.

[0005] For the transmitter, the timestamp is recorded at the rising edge of the clock, so t 1 and t 3 The timestamp is accurate; for the receiving end, local clock sampling is required when receiving data. When the valid signal RX_DV of the received data output by the physical layer PHY chip arrives, the hardware timestamp is recorded when the rising edge of the local clock arrives. Due to the delay in the transmission process, the time when the data arrives at the receiving end is not consistent with the time when the rising edge of the local clock of the receiving end arrives. Therefore, the local clock frequency of the receiving end limits the time synchronization accuracy of PTP.

[0006] The traditional method can improve the resolution of the timestamp by increasing the clock frequency. However, since the highest frequency that the FPGA digital phase-locked loop can reach is related to its process and rate level, when the reference clock is too high, a series of metastable problems will occur. Therefore, the traditional method has very limited improvement in timestamp accuracy. Clock phase splitting technology can generate multiple phase clocks through a digital phase-locked loop, and then multiple phase split phase clocks sample the signal, thereby improving timestamp accuracy. However, this consumes a lot of digital logic resources and has high requirements for FPGA timing. Summary of the invention

[0007] The purpose of the present invention is to provide a device for improving the accuracy of PTP timestamp based on phase shift coding in view of the above problems existing in the prior art, and also to provide a method for improving the accuracy of PTP timestamp based on phase shift coding.

[0008] In order to achieve the above-mentioned purpose, the present invention adopts the following technical measures:

[0009] A device for improving the accuracy of PTP timestamp based on phase shift coding comprises a clock module, the clock module outputs a system input clock CLK to a first FPGA PLL module, the first FPGA PLL module divides the input system input clock CLK to generate a physical layer PHY chip working clock CLK_PHY and a reference clock, the reference clock is recorded as clock CLK_0; the physical layer PHY chip working clock CLK_PHY provides a working clock for the physical layer PHY chip, the clock CLK_0 is respectively input to a second FPGA PLL module, an encoding module and an RTC timing module; the second FPGA PLL module generates N phase clocks by phase separation, which are recorded as clocks CLK_i, i∈{1, 2, ...N}, i represents the sequence number of the phase clock; the clock CLK_i is also input to the encoding module; the physical layer PHY chip generates a valid received data signal RX_DV to the encoding module after receiving a data message, and at the same time, the encoding module extracts the hardware timestamp at this time from the RTC timing module, and the hardware timestamp is encoded by the encoding module to generate a corrected timestamp.

[0010] As mentioned above, the total number and phase interval of the phase clocks satisfy the following formula:

[0011]

[0012] Where N is the total number of phase clocks, and N is a positive odd number. is the phase interval.

[0013] In the encoding module as described above, the clocks CLK_i, i∈{1, 2, ...N} are respectively input into the corresponding D flip-flops in the encoding module. When each D flip-flop receives the rising edge of the valid signal RX_DV for receiving data, each D flip-flop latches the level value of the corresponding clock and temporarily stores it in the register array A of the array register of the encoding module. The array register of the encoding module is also provided with a binary reference array M. The reference array M is input into the shift register of the encoding module for N shift cycles, and each shift obtains the corresponding comparison array M. b ; After the clock level value is temporarily stored in register array A, register array A is compared with array M b The data is input to the FPGA logic operation module of the encoding module and matched, and the FPGA logic operation module calculates the corrected timestamp.

[0014] The device for improving the accuracy of PTP timestamp based on phase shift coding as described above is built on both the PTP master node and the PTP slave node.

[0015] As mentioned above, the PTP slave node also builds a slave node CPU processing unit, which receives the data message forwarded by the physical layer PHY chip of the PTP slave node and parses the corresponding timestamp. The slave node CPU processing unit also receives the corrected timestamp output by the encoding module, and outputs the master-slave node clock deviation from the slave node CPU processing unit.

[0016] A method for improving the accuracy of PTP timestamp based on phase shift coding, using the device for improving the accuracy of PTP timestamp based on phase shift coding as described above, comprises the following steps:

[0017] Step 1: A device for improving the accuracy of PTP timestamp based on phase shift coding is built on both the PTP master node and the PTP slave node, and after a stable Ethernet link is established between the physical layer PHY chip of the PTP master node and the physical layer PHY chip of the PTP slave node, the PTP time synchronization of the PTP master node and the PTP slave node is calibrated;

[0018] Step 2: In each PTP message cycle, when the encoding module at the receiving end receives the rising edge of the receive data valid signal RX_DV from the physical layer PHY chip at the receiving end, the encoding module obtains the hardware timestamp from the RTC timing module, calculates and outputs the corrected timestamp.

[0019] A method for improving the accuracy of PTP timestamp based on phase shift coding, using the device for improving the accuracy of PTP timestamp based on phase shift coding as described above, comprises the following steps:

[0020] Step 1: A device for improving the accuracy of PTP timestamp based on phase shift coding is built on both the PTP master node and the PTP slave node, and after a stable Ethernet link is established between the physical layer PHY chip of the PTP master node and the physical layer PHY chip of the PTP slave node, the PTP time synchronization of the PTP master node and the PTP slave node is calibrated;

[0021] Step 2: In each PTP message cycle,

[0022] The physical layer PHY chip of the PTP master node sends a Sync message to the physical layer PHY chip of the PTP slave node. The physical layer PHY chip of the PTP master node records the time when the Sync message is sent, which is recorded as the timestamp t 1 , and the timestamp is t 1 Encapsulate into Sync message;

[0023] After the physical layer PHY chip of the PTP slave node receives the Sync message, the physical layer PHY chip of the PTP slave node sends the Sync message to the slave node CPU processing unit to parse out the timestamp t 1 At the same time, the encoding module of the PTP slave node calculates the corrected timestamp of the moment when the PTP slave node receives the Sync message, which is recorded as timestamp t 2p ; Then the encoding module will timestamp t 2p Sent to the slave node CPU processing unit;

[0024] The physical layer PHY chip of the PTP slave node sends a Delay_Req message to the physical layer PHY chip of the PTP master node. The physical layer PHY chip of the PTP slave node records the time when the Delay_Req message is sent, which is recorded as the timestamp t 3 , the physical layer PHY chip of the PTP slave node will timestamp t 3 Send to the slave node CPU processing unit;

[0025] After the physical layer PHY chip of the PTP master node receives the Delay_Req message, the encoding module of the PTP master node calculates the corrected timestamp of the moment when the PTP master node receives the Delay_Req message, which is recorded as timestamp t 4p ;

[0026] The physical layer PHY chip of the PTP master node sends a Delay_Resp message to the physical layer PHY chip of the PTP slave node, and the timestamp is t 4p Encapsulate into Delay_Resp message;

[0027] The physical layer PHY chip of the PTP slave node receives the Delay_Resp message and sends the Delay_Resp message to the slave node CPU processing unit, which parses the timestamp t 4p Combined with the timestamp t 1 , timestamp t 2p and timestamp t 3 Calculate the master-slave node clock offset Offset:

[0028]

[0029] Where Offset is the clock deviation between the master and slave nodes; t 1 The timestamp of the time when the PTP master node sends the Sync message; t 2p The corrected timestamp of the moment when the PTP slave node receives the Sync message; t 3 The timestamp of the moment when the PTP slave node sends the Delay_Req message in the PTP message period; t 4p It is the corrected timestamp of the time when the PTP master node receives the Delay_Req message.

[0030] Obtaining the corrected timestamp as described above specifically includes the following steps:

[0031] Step 2.1, when the encoding module at the receiving end receives the rising edge of the valid signal RX_DV of the received data from the physical layer PHY chip, the encoding module obtains the hardware timestamp timestamp from the RTC timing module, and the (N+1) D flip-flops in the encoding module at the receiving end latch the corresponding clock level value at the rising edge of the valid signal RX_DV of the received data, and store it in the register array A, A=[x 0 ,x 1 ,x 2 ,...,x i ,...,x N ], x i is the level value corresponding to the clock CLK_i latched by the D flip-flop, i∈{0,1,…N}, N is the total number of phase clocks;

[0032] For Sync messages, the receiving end is the PTP slave node; for Delay_Req messages, the receiving end is the PTP master node;

[0033] Step 2.2: In the array register of the encoding module, the value of the binary reference array M is cyclically shifted left bit by bit, and each left shift obtains the corresponding comparison array M b , the comparison array M obtained by left shifting in the bth cycle b The number of shifts relative to the reference array M is denoted as the number of shifts m b, compare array number b∈{0,1,…N}, where the comparison array M 0 Equal to the reference array M, each loop starting from the first loop, shifts left by 1 bit based on the previous loop;

[0034] Step 2.3: In the encoding module, the FPGA logic operation module converts the register array A and the comparison array M after circular left shift b ,b∈{0,1,…N} to match, and determine whether there is an integer b∈[0,N] that makes the register array A and the comparison array M b The same, then calculate the corrected timestamp timestamp_precise of the data message received by the receiving end;

[0035]

[0036] Where timestamp is the hardware timestamp; b represents the comparison array number, b is an integer, b∈{0, 1, ...N}; T represents the period of the reference clock and the phase clock, and the periods of the reference clock and the phase clock are equal; m b Indicates the number of shifts, m 0 =0;M b Represents the comparison array, M 0 =M; A is the register array; reference array Indicates any Indicates existence;

[0037] For the PTP slave node, the hardware timestamp timestamp is the hardware timestamp extracted by the encoding module of the PTP slave node after the physical layer PHY chip of the PTP slave node receives the Sync message and sends the valid signal RX_DV to the encoding module of the PTP slave node. The corresponding calculated corrected timestamp timestamp_precise is the timestamp t 2p ;

[0038] For the PTP master node, the hardware timestamp timestamp is the hardware timestamp extracted by the encoding module of the PTP master node after the physical layer PHY chip of the PTP master node receives the Delay_Req message and sends the receive data valid signal RX_DV to the encoding module of the PTP master node. The corresponding calculated corrected timestamp timestamp_precise is the timestamp t 4p .

[0039] Compared with the prior art, the present invention has the following beneficial effects:

[0040] The present invention processes a factor that affects the PTP time synchronization accuracy, namely, the timestamp accuracy of the data received by the receiving end. By using a clock phase division technology based on shift coding, the timestamp accuracy of the data received by the receiving end is increased by (N+1) times while reducing the consumption of logic resources, thereby improving the PTP time synchronization accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 The figure is a schematic diagram of the PTP message end-to-end single-step mode delay request-response mechanism.

[0042] Figure 2 A module diagram of a device for improving PTP timestamp accuracy based on phase-shift coding;

[0043] Among them, 1—clock module; 2—first FPGA PLL module; 3—physical layer PHY chip; 4—second FPGA PLL module; 5—encoding module; 6—RTC timing module;

[0044] CLK—is the system input clock, provided by the clock module;

[0045] CLK_PHY—is the working clock of the physical layer PHY chip, generated by the first FPGA PLL module;

[0046] CLK_0—is the reference clock, generated by the first FPGA PLL module, and is recorded as clock CLK_0;

[0047] CLK_1, CLK_2, CLK_3, CLK_4, CLK_5, CLK_6, ..., CLK_N—phase clocks, generated by the second FPGA PLL module, recorded as clocks CLK_1, CLK_2, CLK_3, CLK_4, CLK_5, CLK_6, ..., CLK_N;

[0048] RX_DV—is the valid signal for receiving data, output by the physical layer PHY chip;

[0049] timestamp—is the hardware timestamp, output by the RTC timing module;

[0050] timestamp_precise—is the corrected timestamp, output by the encoding module.

[0051] Figure 3 The present invention is a schematic diagram of a specific implementation method of a method for improving the PTP timestamp accuracy based on phase shift coding. DETAILED DESCRIPTION

[0052] In order to facilitate those skilled in the art to understand and apply the present invention, the present invention is further described in detail below in conjunction with implementation examples. It should be understood that the implementation examples described herein are only used to illustrate and explain the present invention and are not used to limit the present invention.

[0053] Example 1

[0054] This embodiment provides a device for improving the accuracy of PTP timestamp based on phase shift coding, which is respectively built on the PTP master node and the PTP slave node. Figure 2 As shown, it includes a clock module 1, a first FPGA PLL module 2, a physical layer PHY chip 3, a second FPGA PLL module 4, an encoding module 5 and an RTC timing module 6.

[0055] The connection relationship of the above components is as follows:

[0056] The clock module 1 provides a system input clock CLK and inputs it to the first FPGA PLL module 2. The first FPGA PLL module 2 divides the input system input clock CLK to generate a physical layer PHY chip working clock CLK_PHY and a reference clock. The reference clock is recorded as clock CLK_0, wherein the physical layer PHY chip working clock CLK_PHY provides a working clock for the physical layer PHY chip 3; the clock CLK_0 is respectively input to the second FPGA PLL module 4, the encoding module 5 and the RTC timing module 6, and provides a working clock for the second FPGA PLL module 4, the encoding module 5 and the RTC timing module 6; the second FPGA PLL module 4 generates N phase clocks in phase division, and each phase clock is recorded as: clock CLK_1, clock CLK_2...clock CLK_i...clock CLK_N, i is the sequence number of the phase clock, i∈{1,2,...N}, N is the total number of phase clocks, and each phase clock is also input to the encoding module 5. After receiving the data message, the physical layer PHY chip 3 generates a valid signal RX_DV to the encoding module 5. At the same time, the encoding module 5 extracts the hardware timestamp at this time from the RTC timing module 6. The hardware timestamp is encoded by the encoding module 5 to generate a corrected timestamp. For the PTP slave node, the received data message is a Sync message, and the corrected timestamp corresponding to the moment when the PTP slave node receives the Sync message is recorded as timestamp t 2p For the PTP master node, the received data message is the Delay_Req message, and the corrected timestamp corresponding to the moment when the PTP master node receives the Delay_Req message is the timestamp t 4p .

[0057] In this embodiment, the frequency of the system input clock CLK output by the clock module 1 is 10 MHz; the clock frequency of the physical layer PHY chip working clock CLK_PHY generated by the first FPGA PLL module 2 is 125 MHz; the clock frequency of the clock CLK_0 generated by the first FPGA PLL module 2 (that is, the clock CLK_0 input by the second FPGA PLL module 4) is 125 MHz; the total number N of phase clocks output by the second FPGA PLL module 4 is equal to 7 and the clock frequencies of the 7 phase clocks are all 125 MHz.

[0058] The first FPGA PLL module 2, the second FPGA PLL module 4, the encoding module 5 and the RTC timing module 6 are all implemented based on FPGA.

[0059] The total number N of phase clocks and the phase interval Satisfy the formula: N is a positive odd number. In this embodiment, the second FPGA PLL module 4 performs clock phase shifting according to the clock CLK_0 with an input frequency of 125 MHz to generate 7 phase intervals The phase angles of the clocks CLK_1, CLK_2, ..., and CLK_7 are 45°, wherein the phase of the clock CLK_0 is 0, and the clocks CLK_0, CLK_1, CLK_2, ..., and CLK_7 are all provided to the encoding module 5. After receiving the data message, the physical layer PHY chip 3 generates a valid received data signal RX_DV to the encoding module 5. At the same time, the encoding module 5 extracts the hardware timestamp at this time from the RTC timing module 6, and generates a corrected timestamp after encoding:

[0060] In the encoding module 5, the clocks CLK_0, CLK_1, CLK_i, ..., CLK_N are respectively input into the corresponding D flip-flops in the encoding module 5. When each D flip-flop receives the rising edge of the receive data valid signal RX_DV outputted from the physical layer PHY chip 3, each D flip-flop respectively latches the level value of the corresponding clock (including the reference clock and the phase clock) and temporarily stores it in the register array A of the array register of the encoding module 5, A=[x 0 ,x 1 ,x i ,…,x N ]; The array register of the encoding module 5 is also provided with a binary reference array M, The reference array M is input into the shift register of the encoding module 5 and shifted N times. Each shift obtains the corresponding comparison array M. b ; After the clock level value is temporarily stored in register array A, register array A is compared with array M bThe data is input to the FPGA logic operation module of the encoding module 5 and matched. The FPGA logic operation module obtains the corrected timestamp according to the following formula:

[0061]

[0062] Wherein, timestamp is the hardware timestamp, timestamp_precise is the corrected timestamp. In this embodiment, both the hardware timestamp timestamp and the corrected timestamp timestamp_precise are 64 bits; b represents the comparison array number, b is an integer, b∈{0, 1, ...N}; N is the total number of phase clocks; T represents the period of the reference clock and the phase clock, and the period of the reference clock and the phase clock are equal; m b Indicates the number of shifts, m 0 =0;M b Represents the comparison array, M 0 =M; A is the register array; reference array The reference array M value is fixed. Indicates any Indicates existence.

[0063] For the PTP slave node, the hardware timestamp timestamp is the hardware timestamp extracted by the encoding module 5 of the PTP slave node after the physical layer PHY chip 3 of the PTP slave node receives the Sync message and sends the receive data valid signal RX_DV to the encoding module 5 of the PTP slave node. The corresponding calculated corrected timestamp timestamp_precise is the timestamp t 2p ;

[0064] For the PTP master node, the hardware timestamp timestamp is the hardware timestamp extracted by the encoding module 5 of the PTP master node after the physical layer PHY chip 3 of the PTP master node receives the Delay_Req message and sends the received data valid signal RX_DV to the encoding module 5 of the PTP master node. The corresponding calculated corrected timestamp timestamp_precise is the timestamp t 4p .

[0065] Furthermore, in order to use the corrected timestamp (i.e., timestamp t 2p and timestamp t 4p ) to obtain a more accurate master-slave node clock deviation, the PTP slave node also builds a slave node CPU processing unit, the slave node CPU processing unit receives the data message (including Sync message and Delay_Req message) forwarded by the physical layer PHY chip 3 of the PTP slave node and parses out the corresponding timestamp (parse out the timestamp t from the Sync message) 1, parse the timestamp t from the Delay_Resp message 4p ), the slave node CPU processing unit also receives the corrected timestamp output by the encoding module 5, and then outputs the master-slave node clock deviation:

[0066]

[0067] Where Offset is the clock deviation between the master and slave nodes; t 1 The timestamp of the time when the PTP master node sends the Sync message; t 2p The corrected timestamp of the moment when the PTP slave node receives the Sync message; t 3 The timestamp of the moment when the PTP slave node sends the Delay_Req message in the PTP message period; t 4p It is the corrected timestamp of the time when the PTP master node receives the Delay_Req message.

[0068] Example 2

[0069] A method for improving the accuracy of PTP timestamps based on phase shift coding, using the device for improving the accuracy of PTP timestamps based on phase shift coding described in Example 1, such as Figure 3 As shown, the specific steps include:

[0070] Step 1, a device for improving the accuracy of PTP timestamp based on phase shift coding as described in Example 1 is built on both the PTP master node and the PTP slave node, and after a stable Ethernet link is established between the physical layer PHY chip 3 of the PTP master node and the physical layer PHY chip 3 of the PTP slave node, the PTP time synchronization of the PTP master node and the PTP slave node is calibrated;

[0071] At this time, the second FPGA PLL module 4 phase-splits the input clock CLK_0 to generate N phase clocks. The total number N of the phase clocks and the phase interval of the phase clocks satisfy the following formula:

[0072]

[0073] Wherein, N is the total number of phase clocks and is a positive odd number; is the phase interval.

[0074] Step 2: In each PTP message cycle, when the encoding module 5 at the receiving end receives the rising edge of the receive data valid signal RX_DV from the physical layer PHY chip 3, the encoding module 5 obtains the hardware timestamp from the RTC timing module 6, calculates and outputs the corrected timestamp.

[0075] Specifically: the physical layer PHY chip 3 of the PTP master node sends a Sync message to the physical layer PHY chip 3 of the PTP slave node. The physical layer PHY chip 3 of the PTP master node records the time of sending the Sync message, which is recorded as the timestamp t 1 , and the timestamp is t 1 Encapsulate into Sync message;

[0076] After the physical layer PHY chip 3 of the PTP slave node receives the Sync message, the physical layer PHY chip 3 of the PTP slave node sends the Sync message to the slave node CPU processing unit to parse out the timestamp t 1 At the same time, the encoding module 5 of the PTP slave node calculates the corrected timestamp of the moment when the PTP slave node receives the Sync message, which is recorded as timestamp t 2p ; Then the encoding module 5 will timestamp t 2p Sent to the slave node CPU processing unit;

[0077] The physical layer PHY chip 3 of the PTP slave node sends a Delay_Req message to the physical layer PHY chip 3 of the PTP master node. The physical layer PHY chip 3 of the PTP slave node records the time when the Delay_Req message is sent, which is recorded as the timestamp t 3 At the same time, the PTP slave node's physical layer PHY chip 3 sends the timestamp t 3 Send to the slave node CPU processing unit;

[0078] After the physical layer PHY chip 3 of the PTP master node receives the Delay_Req message, the encoding module 5 of the PTP master node calculates the corrected timestamp of the moment when the PTP master node receives the Delay_Req message, which is recorded as timestamp t 4p ;

[0079] The physical layer PHY chip 3 of the PTP master node sends a Delay_Resp message to the physical layer PHY chip 3 of the PTP slave node, and the timestamp is t 4p Encapsulate into Delay_Resp message;

[0080] The physical layer PHY chip 3 of the PTP slave node receives the Delay_Resp message and sends the Delay_Resp message to the slave node CPU processing unit, which parses the timestamp t 4p Combined with the timestamp t 1 , timestamp t 2p and timestamp t 3 The clock deviation Offset between the master and slave nodes is calculated.

[0081] The coding module 5 of the PTP slave node calculates the corrected timestamp of the moment when the PTP slave node receives the Sync message, and the coding module 5 of the PTP master node calculates the corrected timestamp of the moment when the PTP master node receives the Delay_Req message, both of which include the following steps:

[0082] Step 2.1, when the encoding module 5 of the receiving end (for the Sync message, the receiving end is the PTP slave node; for the Delay_Req message, the receiving end is the PTP master node) receives the rising edge of the received data valid signal RX_DV from the physical layer PHY chip 3, the encoding module 5 obtains the hardware timestamp timestamp from the RTC timing module 6, and the (N+1) D flip-flops in the encoding module 5 of the receiving end respectively latch the level value of the corresponding clock (the clock includes the reference clock and the phase clock, and one D flip-flop corresponds to one clock) at the rising edge of the received data valid signal RX_DV, and store it in the register array A, A=[x 0 ,x 1 ,x 2 ,...,x i ,...,x N ], x i is the level value corresponding to the clock CLK_i latched by the D flip-flop, i∈{0,1,…N}, and N is the total number of phase clocks.

[0083] In this embodiment, the number of D flip-flops is 8. The order in which the corresponding register array A latches the level values ​​of each clock is: A = [x 0 ,x 1 ,x 2 ,.x 3 ,x 4 ,x 5 ,x 6 ,x 7 ], where x 0 ,x 1 ,x 2 ,.x 3 ,x 4 ,x 5 ,x 6 ,x 7 , CLK_7 latched by the eight D flip-flops at the arrival time of the received data valid signal RX_DV.

[0084] Step 2.2: A binary reference array M is set in the array register of the encoding module 5. The value of the reference array M is cyclically shifted left bit by bit. Each left shift obtains a corresponding comparison array, which is recorded as comparison array M. b , the comparison array M obtained by left shifting in the bth cycleb The number of shifts relative to the reference array M is denoted as the number of shifts m b , b∈{0,1,…N}. Among them, the comparison array M 0 =Equal to the reference array M. In each cycle starting from the first cycle, the left shift is performed with a step of 1 bit based on the previous cycle. In this embodiment, after 8 left shift cycles, the array M is compared. b is equal to the reference array M, as shown in Figure 1.

[0085] Table 1 Coding table of a specific implementation method for improving PTP timestamp accuracy based on phase shift coding

[0086]

[0087] Among them, A is the register array, m b is the number of shift bits, M b is the comparison array, b is the number of cycles, timestamp is the hardware timestamp, and timestamp_precise is the corrected timestamp.

[0088] Step 2.3: In the encoding module 5, the FPGA logic operation module converts the register array A and the comparison array M after circular left shift b ,b∈{0,1,…N} to match, and determine whether there is an integer b∈[0,N] that makes the register array A and the comparison array M b The same, then calculate the corrected timestamp timestamp_precise of the data message received by the receiving end according to the following formula:

[0089]

[0090] Wherein, timestamp is the hardware timestamp, timestamp_precise is the corrected timestamp. In this embodiment, both the hardware timestamp timestamp and the corrected timestamp timestamp_precise are 64 bits; b represents the comparison array number, b is an integer, b∈{0, 1, ...N}; N is the total number of phase clocks; T represents the period of the reference clock and the phase clock, and the period of the reference clock and the phase clock are equal; m b Indicates the number of shifts, m 0 =0;M b Represents the comparison array, M 0 =M; A is the register array; reference array The reference array M value is fixed. Indicates any Indicates existence.

[0091] For the PTP slave node, the hardware timestamp timestamp is the hardware timestamp extracted by the encoding module 5 of the PTP slave node after the physical layer PHY chip 3 of the PTP slave node receives the Sync message and sends the receive data valid signal RX_DV to the encoding module 5 of the PTP slave node. The corresponding calculated corrected timestamp timestamp_precise is the timestamp t 2p ;

[0092] For the PTP master node, the hardware timestamp timestamp is the hardware timestamp extracted by the encoding module 5 of the PTP master node after the physical layer PHY chip 3 of the PTP master node receives the Delay_Req message and sends the received data valid signal RX_DV to the encoding module 5 of the PTP master node. The corresponding calculated corrected timestamp timestamp_precise is the timestamp t 4p .

[0093] Using clock CLK_0, clock CLK_1, ..., clock CLK_7 to collect the valid data reception signal RX_DV will generate 8 times of resource consumption, and the higher the clock frequency, the more difficult it is to distinguish which clock first collects the arrival time of the RX_DV signal. Therefore, this solution uses the rising edge of the valid data reception signal RX_DV to cooperate with the D flip-flop to collect the level values ​​of clock CLK_0, clock CLK_1, ..., clock CLK_7 corresponding to the rising edge of the valid data reception signal RX_DV, and then according to the data code of the collected level value, that is, the register array A, it is determined between which two clocks the rising edge of the valid data reception signal RX_DV is. The judgment method is: cyclically shift the reference array M left by m b Bit, determine which register array A and which comparison array M b Equal, then use the hardware timestamp timestamp to subtract the corresponding correction time △t, △t = m b *T / (N+1), get a more accurate corrected timestamp timestamp_precise, the corrected time △t represents the time difference between the rising edge of the valid signal RX_DV and the rising edge of the first clock CLK_0 after the valid signal RX_DV (the hardware timestamp timestamp is based on the clock CLK_0). If no comparison array M with the same size as the register array A is found b , it means that the rising edge of the received data valid signal RX_DV coincides with a rising edge of the clock CLK_0, clock CLK_1, ..., clock CLK_7, or there is a counting error. At this time, the hardware timestamp timestamp is used as the corrected timestamp of the data message received by the receiving end.

[0094] In this embodiment, a total of 8 clocks are set, and correspondingly, the accuracy of the corrected timestamp timestamp_precise is improved by 8 times relative to the hardware timestamp timestamp.

[0095] Through the above steps 2.1-2.3, the timestamp of the arrival time of the data message can be corrected at the receiving end, thereby increasing the accuracy of the hardware timestamp by (N+1) times. The corrected timestamp can be used when PTP calculates the round-trip path delay, making the calculation more accurate, thereby improving the accuracy of PTP time synchronization. In each PTP message cycle, when the PTP slave node receives the Delay_Resp message, the slave node CPU processing unit uses the corrected timestamp to calculate the master-slave node clock deviation Offset to satisfy the formula:

[0096]

[0097] Where Offset is the clock deviation between the master and slave nodes; t 1 The timestamp of the time when the PTP master node sends the Sync message; t 2p The corrected timestamp of the moment when the PTP slave node receives the Sync message; t 3 The timestamp of the moment when the PTP slave node sends the Delay_Req message in the PTP message period; t 4p It is the corrected timestamp of the time when the PTP master node receives the Delay_Req message.

[0098] It should be noted that the specific embodiments described in the present invention are merely examples of the spirit of the present invention. Those skilled in the art may make various modifications or additions to the specific embodiments described or replace them in similar ways, but they will not deviate from the spirit of the present invention or exceed the scope defined by the attached claims.

Claims

1. A device for improving PTP timestamp accuracy based on phase shift coding, characterized in that: The invention comprises a clock module (1), wherein the clock module (1) outputs a system input clock CLK to a first FPGA PLL module (2), wherein the first FPGA PLL module (2) divides the input system input clock CLK to generate a physical layer PHY chip working clock CLK_PHY and a reference clock, wherein the reference clock is recorded as clock CLK_0; the physical layer PHY chip working clock CLK_PHY provides a working clock for the physical layer PHY chip (3), and the clock CLK_0 is respectively input to a second FPGA PLL module (4), an encoding module (5) and an RTC timing module (6); the second FPGA The PLL module (4) generates N phase clocks in phase, which are recorded as clocks CLK_i, i∈{1, 2, ...N}, and i represents the sequence number of the phase clock; the clock CLK_i is also input into the encoding module (5); after receiving the data message, the physical layer PHY chip (3) generates a received data valid signal RX_DV to the encoding module (5), and at the same time, the encoding module (5) extracts the hardware timestamp at this time from the RTC timing module (6), and the hardware timestamp is encoded by the encoding module (5) to generate a corrected timestamp.

2. According to claim 1, a device for improving PTP timestamp accuracy based on phase shift coding, characterized in that: The total number and phase interval of the phase clocks satisfy the following formula: Where N is the total number of phase clocks, and N is a positive odd number. is the phase interval.

3. According to claim 2, a device for improving PTP timestamp accuracy based on phase shift coding, characterized in that: In the encoding module (5), clocks CLK_i, i∈{1, 2, ... N} are respectively input into corresponding D flip-flops in the encoding module (5); when each D flip-flop receives a rising edge of a valid received data signal RX_DV, each D flip-flop respectively latches a level value of the corresponding clock and temporarily stores it in a register array A of an array register of the encoding module (5); a binary reference array M is also provided in the array register of the encoding module (5); the reference array M is input into a shift register of the encoding module (5) and shifted N times, and each shift obtains a corresponding comparison array M b ; After the clock level value is temporarily stored in register array A, register array A is compared with array M b The data is input to the FPGA logic operation module of the encoding module (5) and matched, and the FPGA logic operation module calculates the corrected timestamp.

4. According to claim 3, a device for improving PTP timestamp accuracy based on phase shift coding, characterized in that: The device for improving the PTP timestamp accuracy based on phase shift coding is built on both the PTP master node and the PTP slave node.

5. The device for improving PTP timestamp accuracy based on phase shift coding according to claim 4, characterized in that: The PTP slave node also has a slave node CPU processing unit, which receives data messages forwarded by the physical layer PHY chip (3) of the PTP slave node and parses out corresponding timestamps. The slave node CPU processing unit also receives the corrected timestamp output by the encoding module (5), and outputs the master-slave node clock deviation.

6. A method for improving the accuracy of PTP timestamp based on phase shift coding, using the device for improving the accuracy of PTP timestamp based on phase shift coding as described in claim 4, characterized in that: The following steps are involved: Step 1: constructing the device for improving the accuracy of PTP timestamp based on phase shift coding on both the PTP master node and the PTP slave node, and establishing a stable Ethernet link between the physical layer PHY chip (3) of the PTP master node and the physical layer PHY chip (3) of the PTP slave node, and then calibrating the PTP time synchronization of the PTP master node and the PTP slave node; Step 2: In each PTP message cycle, when the encoding module (5) at the receiving end receives the rising edge of the receive data valid signal RX_DV from the physical layer PHY chip (3) at the receiving end, the encoding module (5) obtains the hardware timestamp from the RTC timing module (6), calculates and outputs the corrected timestamp.

7. A method for improving the accuracy of PTP timestamp based on phase shift coding, using the device for improving the accuracy of PTP timestamp based on phase shift coding as described in claim 5, characterized in that: The following steps are involved: Step 1: constructing the device for improving the accuracy of PTP timestamp based on phase shift coding on both the PTP master node and the PTP slave node, and establishing a stable Ethernet link between the physical layer PHY chip (3) of the PTP master node and the physical layer PHY chip (3) of the PTP slave node, and then calibrating the PTP time synchronization of the PTP master node and the PTP slave node; Step 2: In each PTP message cycle, The physical layer PHY chip (3) of the PTP master node sends a Sync message to the physical layer PHY chip (3) of the PTP slave node, and the physical layer PHY chip (3) of the PTP master node records the time of sending the Sync message as a timestamp t1, and the timestamp t1 is encapsulated in the Sync message; After the physical layer PHY chip (3) of the PTP slave node receives the Sync message, the physical layer PHY chip (3) of the PTP slave node sends the Sync message to the CPU processing unit of the slave node to parse out the timestamp t1. At the same time, the encoding module (5) of the PTP slave node calculates the corrected timestamp of the moment when the PTP slave node receives the Sync message, which is recorded as timestamp t 2p ; Then the encoding module (5) converts the timestamp t 2p Sent to the slave node CPU processing unit; The physical layer PHY chip (3) of the PTP slave node sends a Delay_Req message to the physical layer PHY chip (3) of the PTP master node, the physical layer PHY chip (3) of the PTP slave node records the time of sending the Delay_Req message, which is recorded as a timestamp t3, and the physical layer PHY chip (3) of the PTP slave node sends the timestamp t3 to the CPU processing unit of the slave node; After the physical layer PHY chip (3) of the PTP master node receives the Delay_Req message, the encoding module (5) of the PTP master node calculates the corrected timestamp of the moment when the PTP master node receives the Delay_Req message, which is recorded as timestamp t 4p ; The physical layer PHY chip (3) of the PTP master node sends a Delay_Resp message to the physical layer PHY chip (3) of the PTP slave node, and the timestamp is t 4p Encapsulate into Delay_Resp message; The physical layer PHY chip (3) of the PTP slave node receives the Delay_Resp message and sends the Delay_Resp message to the slave node CPU processing unit, which parses the timestamp t 4p Combined with timestamp t1 and timestamp t 2p The clock offset Offset of the master and slave nodes is calculated by using the timestamp t3: Where Offset is the clock deviation between the master and slave nodes; t1 is the timestamp of the time when the PTP master node sends the Sync message; t 2p The corrected timestamp of the moment when the PTP slave node receives the Sync message; t3 is the timestamp of the moment when the PTP slave node sends the Delay_Req message in the PTP message cycle; t 4p It is the corrected timestamp of the time when the PTP master node receives the Delay_Req message.

8. The method for improving PTP timestamp accuracy based on phase shift coding according to any one of claims 6 or 7, characterized in that: Obtaining the corrected timestamp specifically includes the following steps: Step 2.1, when the encoding module (5) at the receiving end receives the rising edge of the valid received data signal RX_DV from the physical layer PHY chip (3), the encoding module (5) obtains the hardware timestamp timestamp from the RTC timing module (6), and the (N+1) D flip-flops in the encoding module (5) at the receiving end latch the level value of the corresponding clock at the rising edge of the valid received data signal RX_DV, and store it in the register array A, A = [x0, x1, x2, ..., x i , ..., x N ], x i is the level value corresponding to the clock CLK_i latched by the D flip-flop, i∈{0, 1, ...N}, N is the total number of phase clocks; For Sync messages, the receiving end is the PTP slave node; for Delay_Req messages, the receiving end is the PTP master node; Step 2.2: In the array register of the encoding module (5), the value of the binary reference array M is cyclically shifted left bit by bit, and each left shift obtains the corresponding comparison array M b , the comparison array M obtained by left shifting after the bth cycle b The number of shifts relative to the reference array M is denoted as the number of shifts m b , compare array serial number b∈{0,1,…N}, where the comparison array M0 is equal to the reference array M. Starting from the first loop, each loop is left-shifted by 1 bit based on the previous loop; Step 2.3: In the encoding module (5), the FPGA logic operation module converts the register array A and the comparison array M after circular left shift into b ,b∈{0,1,…N} to match, and determine whether there is an integer b∈[0,N] that makes the register array A and the comparison array M b The same, then calculate the corrected timestamp timestamp_precise of the data message received by the receiving end; Where timestamp is the hardware timestamp; b represents the comparison array number, b is an integer, b∈{0, 1, ...N}; T represents the period of the reference clock and the phase clock, and the periods of the reference clock and the phase clock are equal; m b Indicates the number of shifts; M b Represents the comparison array, M0=M; A is the register array; reference array Indicates any Indicates existence; For the PTP slave node, the hardware timestamp timestamp is the hardware timestamp extracted by the encoding module (5) of the PTP slave node after the physical layer PHY chip (3) of the PTP slave node receives the Sync message and sends the receive data valid signal RX_DV to the encoding module (5) of the PTP slave node. The corresponding calculated corrected timestamp timestamp_precise is the timestamp t 2p ; For the PTP master node, the hardware timestamp timestamp is the hardware timestamp extracted by the encoding module (5) of the PTP master node after the physical layer PHY chip (3) of the PTP master node receives the Delay_Req message and sends the receive data valid signal RX_DV to the encoding module (5) of the PTP master node. The corresponding calculated corrected timestamp timestamp_precise is the timestamp t 4p .

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