Chip scanning test encryption circuit based on Rossler chaotic system and test method
By adopting a flow password encryption solution based on the Rossler chaos system in the chip scan test, the problem of limited security intensity and testing time in existing technologies, and achieve higher scanning test safety and easier test processes.
Patent Information
- Application Number
- CN202411449184.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-17
- Publication Date
- 2025-01-28
AI Technical Summary
The existing chip scanning and testing security measures have problems such as limited security strength, increased testing time, unstable PUF output and traditional stream encryption solutions facing attacks, making it difficult to effectively resist bypass attacks and information leakage of the scanning chain.
Using a flow password encryption solution based on the Rossler chaos system, the high initial value and non -linear characteristics of the chaos system use the chaos system to generate pseudo -random sequences for encryption to enhance the safety of scanning testing.
Effectively resist the attack on classic flow passwords, improve the security of chip testing, reduce the difficulty of cracking, compatible the standard JTAG interface, simplify test timing, and save test time.
Smart Images
Figure CN119382858A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to integrated circuit testing technology, in particular to the field of integrated circuit testability design security. Background Art
[0002] The JTAG-DfT test solution based on the scan chain improves the controllability and observability of the integrated circuit and facilitates the testing and maintenance of the chip, but it also becomes a backdoor for stealing important information stored in the register, speculating the circuit structure and implementation details, etc., and introduces hidden dangers that cannot be ignored. To ensure the security of chip testing, encryption measures can be introduced during scan testing.
[0003] In order to effectively resist the scan chain bypass attack, some security scanning measures have been proposed, as listed below: (1) Scan chain structure disorder or confusion, such as inserting additional NOT gates between certain scan registers in series; (2) Cutting off the scan chain after testing the chip to physically remove the test mode; (3) Clearing the scan register when switching from normal working mode to test mode; (4) Entering a reserved password verification (lock and key, L&K) before using the scan chain test; (5) Adding a set of dynamically changing passwords to each test vector for verification; (6) Encryption scheme based on physically unclonable function (PUF); (7) Test vector encryption scheme based on linear feedback shift register (LFSR), etc.
[0004] The shortcomings of the above scanning security measures are as follows. The L&K scheme is relatively simple, and the password is only verified once when the chip enters the test mode, so the security strength is limited. Dynamic password verification increases the difficulty of cracking and the cost of attack, and is more secure, but each test vector has an additional data stream, which slightly increases the test time. Metastable circuits such as the ring oscillator of the PUF scheme are affected by the chip working environment (such as temperature, etc.), or the verification fails due to unstable PUF output values. In recent years, there have been reports of algebraic attacks on linear LFSRs and cubic attacks on nonlinear FSRs, and these traditional stream encryption schemes face challenges.
[0005] To this end, this patent proposes a stream cipher encryption scheme based on Rossler chaotic system. The high initial value sensitivity and nonlinearity of chaotic system are used to improve the security of scanning test. Its characteristics are:
[0006] (1) The nonlinear characteristics of chaotic systems help to resist attacks on classical stream ciphers. This scheme uses the strong nonlinear characteristics of chaotic systems to effectively resist algebraic attacks on linear LFSRs and cubic attacks on nonlinear FSRs. In addition, chaotic systems are sensitive to module parameters. Even if a certain parameter is slightly adjusted, the generated random sequence will be very different; it can more effectively prevent brute force cracking.
[0007] (2) This scheme has rich adjustable parameters, diverse combinations of encryption schemes, a wide key space, and can effectively resist brute force cracking.
[0008] (3) There are few multiplications in the differential equations of the Rossler chaotic system, and the combinational logic of the circuit is relatively simple.
[0009] (4) The chaotic sequence generation circuit uses an approximate multiplier instead of a multiplier, which reduces the circuit area by half. Although approximate multiplication reduces the calculation accuracy, the purpose of this module is to generate a pseudo-random sequence and does not require high accuracy of hardware operations.
[0010] (5) The encrypted test vectors and their responses are stored on the test machine, and encryption and decryption operations are completed in the chip test interface circuit. The test machine stores encrypted ciphertext data, which can effectively prevent attackers from inferring detailed information such as the structure and function of the circuit under test through test vectors and their responses leaked by the test factory.
[0011] (6) No password authentication is required during the test, the operation sequence is simpler, and the test time is saved.
[0012] (7) This solution is compatible with the standard JTAG interface and can use existing test equipment and test procedures. Summary of the invention
[0013] In order to make up for the security risks in the above-mentioned chip scanning test, enable the chip to resist attacks launched by the scanning test circuit, and improve the security of chip testing, the present invention provides a chip scanning test encryption circuit based on Rossler chaotic system and a matching test method.
[0014] In a first aspect, an embodiment of the present invention provides a chip scan test encryption circuit based on a Rossler chaotic system, wherein the differential equation group of the chaotic system is:
[0015] ,
[0016] Where x, y, z are three groups of chaotic sequences to be determined, and a, b, c are constants; the characteristics are as follows:
[0017] Rossler chaotic sequence generation module, outputs three sets of chaotic sequences x, y, z;
[0018] A bit reorganization module, whose input is the x, y, z, and whose output is two sets of data Ri and Ro obtained by reorganizing the input bits;
[0019] The internal or boundary scan chain is a chain of scan registers connected in series;
[0020] A test access controller TAP based on the IEEE-1149 protocol mounts the scan chain via an inlet port sc_in and an outlet port sc_out;
[0021] Parallel-to-serial data conversion module, whose parallel inputs are Ri and Ro, and whose serial output ports are sbit_i and sbit_o;
[0022] A two-input XOR gate XOR1 located at the entry position of the scan chain and used for decrypting the input test vector, one input end is connected to the sbit_i, and the other input end is connected to the sc_in;
[0023] A two-input XOR gate XOR2 located at the exit of the scan chain and used for encrypting the output test vector response has one input connected to the sbit_o and the other input connected to the sc_out.
[0024] The Rossler chaotic sequence generation module is implemented using a differential algorithm and includes:
[0025] Initial value x0, y0 and z0 input ports, total bit width is w tot Bit;
[0026] Register groups X, Y, and Z store the current value of the xyz sequence respectively. The input of their clock ports is the pulse signal Rclk, and the total bit width is w tot bits; the xyz sequence is a discrete value at equally spaced time points;
[0027] The four arithmetic operation circuit corresponding to the right side expression of the Rossler differential equation group has an input which is the output terminal Q of the XYZ register group;
[0028] A right shift circuit is used to right shift the output result of the expression operation circuit of the right side of the Rossler differential equation group by an integer dt bit position, so as to progressively derive a step length of Δt=2 -dt The increment of xyz after the time interval, that is, the increment of the next set of xyz values compared to the current value of the XYZ register group;
[0029] The adding circuit adds the output of the XYZ register group to the xyz increment, and its output is the updated next set of xyz sequence values x new ,y new and z new ;
[0030] The selection circuit MUX is implemented by a two-to-one data selector, one of which is connected to the initial values x0, y0 and z0, and the other is connected to the update value x new ,y new and z new The highest truncated w totBit; when the reset terminal TRST (test port defined by IEEE-1149 protocol) inputs the reset level, MUX selects the former, otherwise selects the latter; the reset terminal is connected to TRST
[0031] The output of the selection circuit MUX is connected to the input port D of the X, Y and Z register groups.
[0032] The four arithmetic operation circuits corresponding to the right-hand side expressions of the Rossler differential equation group include:
[0033] Approximate fixed-point multipliers are used instead of fixed-point multipliers to further reduce the circuit area without affecting the chaotic effect;
[0034] In order to ensure the chaotic trajectory effect, the approximate fixed-point multiplier adds an overflow limit function, that is, once the multiplication result exceeds the upper and lower limits of the fixed-point number representation range, the calculation result must be clamped within the upper and lower limits.
[0035] The highest bit of the fixed-point number x / y / z is the sign bit, and the width of the decimal part is wf; according to the value range of Rossler's chaotic solution xyz, the width of the integer part is fixed to 5; so the total width is w tot =wf+6;
[0036] The bit width wf of the decimal part of the fixed-point number, the effective bit width k of the multiplicand of the approximate multiplier, and the aforementioned integer dt are all adjustable parameters of this module. These adjustable parameters can be combined to construct a chaotic sequence with very different xyz values, increasing the difficulty of cracking.
[0037] The Rossler chaotic sequence generation module further includes a perturbation unit inserted between the addition circuit and the gating circuit MUX, including:
[0038] x new / y new / z new The lowest 2 bits of xP / yP / zP are recorded as xP / yP / zP, which flips most frequently and is more pseudo-random, but is truncated and does not enter the X / Y / Z register to directly participate in the recursion; under specific xP / yP / zP values, the lowest bit of the X / Y / Z register group is triggered to flip, which increases the complexity and unpredictability of the x / y / z sequence, making it more difficult to crack;
[0039] The specific xP / yP / zP value is, for example, if all bits of xP are 1, the lowest bit of the X register group is triggered to flip.
[0040] The bit reorganization module comprises:
[0041] The x / y / z fixed-point number sequence output by the Rossler chaotic sequence generation circuit is generated by disrupting the order of high and low bits, cross-combining, and performing logical operations to generate new values, thereby generating a 3×w bit width fixed-point number sequence. tot The pseudo-random sequence is then divided into two groups in the middle, each with a bit width of ws=3×w tot / 2-bit binary codes Ri and Ro;
[0042] The fixed-point number width is w tot When the bits are randomly generated, the pseudo-random sequence is W≤w tot / 3 bits divided into groups of 0~2 W -1 integer, value is 0~2 W -1 has a uniform frequency distribution; increasing the circuit parameter wf can improve the long-range property of the pseudo-random sequence, but the circuit area is large.
[0043] This module increases the difficulty of brute force cracking by reorganizing the bits of the chaotic sequence xyz in random order, and can make the proportion of 0 and 1 in the pseudo-random sequence approximately half and half, making it difficult for attackers to count valid information from it.
[0044] The parallel-to-serial data conversion module comprises:
[0045] A shift register group with a bit width of ws is used to store two groups of outputs Ri and Ro of the bit reorganization module; a shift is triggered in each clock cycle when the TAP is in the shift_dr state (one of the states of the state machine in the IEEE-1149 protocol), or in a clock cycle when the TAP enters the capture_dr state (one of the states of the state machine in the IEEE-1149 protocol) for the first time after being reset;
[0046] The modulo ws counter has a counting range of 0 to ws-1 and is used to control the parallel-to-serial conversion of the shift register groups Si and So; and in the shift_dr state, after one round of counting, the Rclk pulse signal is generated to trigger the XYZ register group of the chaotic sequence generation module to perform a recursion.
[0047] The chip scan test encryption circuit based on Rossler chaotic system also includes an initialization flag cap_init generating circuit; when the TAP is reset and the TAP enters the capture_dr state for the first time, the circuit sets the cap_init signal to enable the modulo ws counter and the Si and So shift register groups at this time;
[0048] Its function is to allow the circuit to be reset and initialized, and before entering the shift_dr state for the first time, the chaotic sequence generation module can trigger a recursion, so that the shift register groups Si and So can load the first group of sequences recursively derived from the initial values x0 / y0 / z0, rather than directly loading the initial values; this can improve the security of the encryption and decryption circuit. Even if the key information such as the initial values x0 / y0 / z0 is obtained through layout reversal, it is difficult to deduce the values of the first batch of Si and So without understanding the details of the chaos generation algorithm and the circuit parameter settings.
[0049] In a second aspect, a chip scanning encryption test method based on a Rossler chaotic system provided by an embodiment of the present invention is as follows:
[0050] Step 1: simulate a chaotic pseudo-random sequence on a computer, including:
[0051] Step 1.1, determine the adjustable parameters of each module, i.e., wf / / k / dt / x0 / y0 / z0 / a / b / c, etc.;
[0052] Step 1.2, run the circuit simulation based on this, recursively perform M time steps, calculate the output x / y / z of the chaotic system at each time step, and then obtain the pseudo-random numbers Ri and Ro corresponding to each time step.
[0053] Step 2, preparing encrypted test vectors and their responses on a computer, which are obtained by bit-by-bit XORing of the original test vectors and their responses with the simulated chaotic pseudo-random sequence; including:
[0054] Step 2.1, divide a test vector and its response into segments, each segment is ws bits long, and there are M segments in total;
[0055] Step 2.2, if the length of the test vector and its response is not divisible by M, add 0 to the beginning of the test vector and add 0 to the end of the vector response so that the length L of these vectors can be divided by M;
[0056] Step 2.3, bitwise XOR the i-th segment (i=0~M-1) test vector with Ri of the i-th time step to obtain the i-th encrypted segment;
[0057] Step 2.4, concatenate the M encrypted segments in order to obtain an encrypted test vector;
[0058] Step 2.5, the method of encrypting the test vector response is similar, the difference is that each segment of data is XORed with Ro;
[0059] In step 2.6, in the test program on the test machine, you only need to replace the plain text of the test vector and its response with the encrypted one, and the timing process involving the state jump of the TAP state machine remains unchanged.
[0060] Step 3, when the TAP state machine is in the shift_dr state, the encrypted test vector is injected from the TDI port, and the test machine obtains the encrypted response of the previous test vector from the TDO port;
[0061] Step 4: On the test machine, compare the response of the encrypted test vector read by the TDO port with the response of the encrypted test vector stored in the test machine. If they are consistent, the test vector passes, otherwise it fails. BRIEF DESCRIPTION OF THE DRAWINGS
[0062] Figure 1 This is the overall circuit schematic diagram of the chip scan test encryption circuit based on the Rossler chaotic system.
[0063] Figure 2 This is the circuit schematic diagram of the Rossler chaotic sequence generation module in the chip scan test encryption circuit.
[0064] Figure 3 In the implementation case, the xyz chaotic trajectory output by the Rossler chaotic sequence generation module (a) and the trajectory calculated numerically by the software (b) are shown.
[0065] Figure 4 It is a pseudo-random sequence generated by the bit reorganization module in the implementation case, with each 5 bits being an integer divided into groups, and the frequency of occurrence being 0 to 31.
[0066] Figure 5 In the implementation case, the simulation timing diagram (a) is before the TAP enters the shift_dr state for the first time after being reset, the simulation timing diagram (b) is when the TAP is in the shift_dr state, and the timing diagram (c) is when three sets of encrypted test vectors are continuously input and encrypted test vector responses are obtained.
[0067] Figure 6 It is the step flow of chip scanning encryption test method based on Rossler chaotic system. DETAILED DESCRIPTION
[0068] Figure 1 This is the overall circuit schematic diagram of the chip scan test encryption circuit based on the Rossler chaotic system. Figure 2 The circuit schematic diagram of the Rossler chaotic sequence generation module in the chip scan test encryption circuit is shown in FIG. The circuit design and subsequent simulation are implemented using Verilog HDL.
[0069] The operation sequence will be explained with the help of the following HDL simulation example. In this example, the fixed-point number decimal width wf is 10 bits, and the total width w with the sign bit is totis 16 bits, so the bit width ws of Si and So shift registers is 24 bits; dt is 4, the initial values of x0, y0, z0 are 1.0, 2.0, 3.0 respectively, and the parameters a, b, c of the differential equation group are 0.25, 0.5, 6.125 respectively. The circuit adopts an approximate multiplier and introduces the perturbation unit.
[0070] The approximate solution obtained by the circuit simulation using the approximate multiplier above, the trajectory reference diagram of the xyz sequence Figure 3 (a); Numerical solution calculated by software using Runge-Kutta method, xyz sequence trajectory reference Figure 3 (b). The design of the approximate multiplier does not affect the chaotic effect, and the approximate solution also shows chaotic phenomena similar to the numerical solution. Due to the sensitivity of the chaotic system to the x / y / z values, the trajectories of the approximate solution and the numerical solution are different. The approximate multiplier uses far fewer logic gates than the ordinary multiplier, which reduces the circuit area and cost; and the purpose of the circuit is to generate a pseudo-random chaotic sequence rather than to obtain an accurate numerical solution, so the approximate multiplier is just right for this application scenario. In addition, given the limitations of software and hardware on fixed-point or floating-point precision and the sensitivity of the chaotic system to the initial values, it is not feasible to calculate the exact solution of the chaotic system.
[0071] Figure 4 In this case, the pseudo-random sequence generated by the bit reorganization module is an integer divided into groups of 5 bits, with a frequency of 0 to 31. It is approximately uniformly distributed, which conforms to the random characteristics.
[0072] Figure 5 (a) is a simulation timing diagram segment before the TAP enters the shift_dr state for the first time after reset; at this time, the aforementioned cap_init signal triggers the chaotic sequence generation module once more, allowing the XYZ register group to perform the first recursion; then it is loaded into the shift register groups Si and So (corresponding to series_i and series_o in the figure) through the bit reorganization module and the parallel-to-serial conversion module, and then a serial pseudo-random sequence sbit_i and sbit_o are generated; sbit_i is XORed with the encrypted test vector sc_in serially sent into the TDI port of the TAP, and the resulting tdi_ori is the decrypted test vector, which is serially sent into the scan chain.
[0073] Figure 5(b) is a simulation timing diagram segment when TAP is in the two shift_dr states switching period; when the modulo ws counter cnt counts to 23 (i.e. 0x17 in the figure), it generates an Rclk pulse, triggering the XYZ register group to perform a recursion; then it is loaded into the shift register group Si and So through the bit reorganization module and the parallel-to-serial conversion module, and then generates a serial pseudo-random sequence sbit_i and sbit_o; sbit_i is XORed with the encrypted test vector sc_in serially input through the TDI port of TAP, and the obtained tdi_ori is the decrypted test vector, which is serially sent to the scan chain; the plaintext tdo_ori of the previous set of test vector responses is serially output from the scan chain exit, and XORed with sbit_o bit by bit to obtain the encrypted test vector response sc_out, which is finally sent to the tester from the TDO port. When the counter counts to ws-1 again, repeat the above steps.
[0074] Figure 5 (c) is a complete timing diagram of continuously inputting three sets of encrypted test vectors and obtaining encrypted test vector responses; the encrypted test vectors injected from the TDI port to the chip under test for these three times are the same, but the actual test vector tdi_ori sent to the internal scan chain after decryption is different due to the dynamic change of the chaotic sequence; the attacker has no way of knowing the actual test vector sent in; that is, the encryption and decryption of the test vector is not only related to the content of the test vector, but also to the position order of its appearance in the test sequence, which increases the difficulty of cracking.
[0075] The steps of the chip scanning encryption test method based on Rossler chaotic system are as follows: Figure 6 ; Among them, the encrypted test vector generated in step 2 is from Figure 1 The TDI port is serially fed into the test circuit; Figure 1 The encrypted test vector response is serially output from the TDO port of the tester, and after being read by the tester, it is compared with the encrypted test vector response generated by step 2 and stored on the tester. In the test program, only the plain text of the test vector and its response needs to be replaced with the encrypted one, and the timing process involving the state jump of the TAP state machine remains unchanged, which has good compatibility and is easy to migrate.
[0076] It should be noted that the above described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.
Claims
1. A chip scan test encryption circuit based on Rossler chaotic system, the differential equation group of the chaotic system is: ， Among them, x, y, z are three groups of chaotic sequences to be solved, a, b, c are constants; the characteristic is that, include: Rossler chaotic sequence generation module, outputs three sets of chaotic sequences x, y, z; A bit reorganization module, whose input is the x, y, z, and whose output is two sets of data Ri and Ro obtained by reorganizing the input bits; The internal or boundary scan chain is a chain of scan registers connected in series; A test access controller TAP based on the IEEE-1149 protocol mounts the scan chain via an entry port sc_in and an exit port sc_out; Parallel-to-serial data conversion module, whose parallel inputs are Ri and Ro, and whose serial output ports are sbit_i and sbit_o; A two-input XOR gate XOR1 located at the entry position of the scan chain and used for decrypting the input test vector, one input end is connected to the sbit_i, and the other input end is connected to the sc_in; A two-input XOR gate XOR2 located at the exit of the scan chain and used for encrypting the output test vector response has one input connected to the sbit_o and the other input connected to the sc_out.
2. According to the chip scanning test encryption circuit based on Rossler chaotic system in claim 1, the chaotic system will sharply amplify the initial small difference after evolution, and the evolution trajectory of the chaotic sequence xyz over time is extremely sensitive to the initial values x0, y0 and z0; characterized in that, The Rossler chaotic sequence generation module is implemented by using a differential algorithm, and the circuit includes: Initial value x0, y0 and z0 input ports, total bit width is w tot Bit; Register groups X, Y, and Z store the current value of the xyz sequence respectively. The input of their clock ports is the pulse signal Rclk, and the total bit width is w tot bits; the xyz sequence is a discrete value at equally spaced time points; The four arithmetic operation circuit corresponding to the right side expression of the Rossler differential equation group has an input which is the output terminal Q of the XYZ register group; A right shift circuit is used to right shift the output result of the expression operation circuit of the right side of the Rossler differential equation group by an integer dt bit position, so as to progressively derive a step length of Δt=2 -dt The increment of xyz after the time interval, that is, the increment of the next set of xyz values compared to the current value of the XYZ register group; The adding circuit adds the output of the XYZ register group to the xyz increment, and its output is the updated next set of xyz sequence values x new ,y new and z new ; The selection circuit MUX is implemented by a two-to-one data selector, one of which is connected to the initial values x0, y0 and z0, and the other is connected to the update value x new ,y new and z new The highest truncated w tot Bit position; when the reset terminal TRST (test port defined by IEEE-1149 protocol) inputs the reset level, MUX selects the former, otherwise selects the latter; the reset terminal is connected to TRST; The output of the selection circuit MUX is connected to the input port D of the X, Y and Z register groups.
3. The Rossler chaotic sequence generation module according to claim 2, characterized in that: The four arithmetic operation circuits corresponding to the right-hand expression of the Rossler differential equation group, the numerical calculation of addition and multiplication, and the decimals are expressed in the form of fixed-point numbers; including: Approximate fixed-point multipliers are used instead of fixed-point multipliers to further reduce the circuit area without affecting the chaotic effect; In order to ensure the chaotic trajectory effect, the approximate fixed-point multiplier adds an overflow limit function, that is, once the multiplication result exceeds the upper and lower limits of the fixed-point number representation range, the calculation result must be clamped within the upper and lower limits. The highest bit of the fixed-point number x / y / z is the sign bit, and the width of the decimal part is wf; according to the value range of Rossler's chaotic solution xyz, the width of the integer part is fixed to 5; so the total width is w tot =wf+6; The bit width wf of the decimal part of the fixed-point number, the effective bit width k of the multiplicand of the approximate multiplier, and the aforementioned integer dt are all adjustable parameters of this module. These adjustable parameters can be combined to construct a chaotic sequence with very different xyz values, increasing the difficulty of cracking.
4. The Rossler chaotic sequence generation module according to claim 2, characterized in that: It also includes a perturbation unit, which is inserted between the adding circuit and the gating circuit MUX, and includes: x new / y new / z new The lowest 2 bits of xP / yP / zP are recorded as xP / yP / zP, which flips most frequently and is more pseudo-random, but is truncated and does not enter the X / Y / Z register to directly participate in the recursion; under specific xP / yP / zP values, the lowest bit of the X / Y / Z register group is triggered to flip, which increases the complexity and unpredictability of the x / y / z sequence, making it more difficult to crack; The specific example of xP / yP / zP value and triggering flipping is that if all bits of xP are 1, the lowest bit of the X register group is triggered to flip.
5. The chip scan test encryption circuit based on Rossler chaotic system according to claim 1, characterized in that: The bit reorganization module increases the difficulty of brute force cracking by reorganizing the bits of the chaotic sequence xyz in random order, and can make the proportion of 0 and 1 in the pseudo-random sequence approximately half and half, making it difficult for attackers to count valid information from it; including: The x / y / z fixed-point number sequence output by the Rossler chaotic sequence generation circuit is generated by disrupting the order of high and low bits, cross-combining, and performing logical operations to generate new values, thereby generating a 3×w bit width fixed-point number sequence. tot The pseudo-random sequence is then divided into two groups in the middle, each with a bit width of ws=3×w tot / 2-bit binary codes Ri and Ro; The fixed-point number width is w tot When the bits are randomly generated, the pseudo-random sequence is W≤w tot / 3 bits divided into groups of 0~2 W -1 integer, value is 0~2 W -1 has a uniform frequency distribution; increasing the circuit parameter wf can improve the long-range property of the pseudo-random sequence, but the circuit area is large.
6. The chip scan test encryption circuit based on Rossler chaotic system according to claim 1, characterized in that: The parallel-to-serial data conversion module comprises: A shift register group with a bit width of ws is used to store two groups of outputs Ri and Ro of the bit reorganization module; a shift is triggered in each clock cycle when the TAP is in the shift_dr state (one of the states of the state machine in the IEEE-1149 protocol), or in a clock cycle when the TAP enters the capture_dr state (one of the states of the state machine in the IEEE-1149 protocol) for the first time after being reset; The modulo ws counter has a counting range of 0 to ws-1 and is used to control the parallel-to-serial conversion of the shift register groups Si and So; and in the shift_dr state, after one round of counting, the Rclk pulse signal is generated to trigger the XYZ register group of the chaotic sequence generation module to perform a recursion.
7. The chip scan test encryption circuit based on Rossler chaotic system according to claim 1, characterized in that: It also includes an initialization flag cap_init generating circuit, which sets the cap_init signal when the TAP enters the capture_dr state for the first time after the TAP is reset, so as to enable the modulo ws counter and the Si and So shift register groups at this time; Its function is to allow the circuit to be reset and initialized, and before entering the shift_dr state for the first time, the chaotic sequence generation module can trigger a recursion, so that the shift register groups Si and So can load the first group of sequences recursively derived from the initial values x0 / y0 / z0, rather than directly loading the initial values; this can improve the security of the encryption and decryption circuit. Even if the key information such as the initial values x0 / y0 / z0 is obtained through layout reversal, it is difficult to deduce the values of the first batch of Si and So without understanding the details of the chaos generation algorithm and the circuit parameter settings.
8. A chip scanning encryption test method based on Rossler chaotic system, characterized in that: include: Chaotic pseudo-random sequences are obtained by simulation on computers; The test vector and its response prepared for encryption on the computer are obtained by performing bit-by-bit XOR of the original test vector and its response with the simulated chaotic pseudo-random sequence; When the TAP state machine is in the shift_dr state, the encrypted test vector is injected through the TDI port (test port defined by the IEEE-1149 protocol), and the test machine obtains the encrypted response of the previous test vector from the TDO port (test port defined by the IEEE-1149 protocol); On the test machine, the response of the encrypted test vector read by the TDO port is compared with the response of the encrypted test vector stored in the test machine. If they are consistent, this test vector passes, otherwise it fails.
9. The chip scanning encryption test method based on Rossler chaotic system according to claim 8 is characterized in that: The chaotic pseudo-random sequence obtained by simulation on the computer includes: Determine the adjustable parameters of each module, i.e., wf / / k / dt / x0 / y0 / z0 / a / b / c, etc.; Based on this, the circuit simulation is run, recursively M time steps, and the output x / y / z of the chaotic system at each time step is calculated, and then the pseudo-random numbers Ri and Ro corresponding to each time step are obtained.
10. The chip scanning encryption test method based on Rossler chaotic system according to claim 8, characterized in that: The encrypted test vector and its response prepared on the computer include: Divide a test vector and its response into segments, each segment is ws bits long, and there are M segments in total; If the length of the test vector and its response is not divisible by M, the beginning of the test vector is padded with 0, and the end of the vector response is padded with 0, so that the length L of these vectors can be divided by M; The i-th segment (i=0~M-1) test vector is bitwise XORed with Ri of the i-th time step to obtain the i-th encrypted segment; The M encrypted fragments are concatenated in order to obtain the encrypted test vector; The method of encrypting the test vector response is similar, except that each segment of data is XORed with Ro; In the test program on the test machine, only the plain text of the test vector and its response needs to be replaced with the encrypted one, and the timing process involving the state jump of the TAP state machine remains unchanged.