Skew correction method for physical layer interface on multi-chip module

Abstract

Systems, devices, and methods are disclosed for implementing a skew correction method for a physical layer interface on a multi-chip module. Circuitry connected to a plurality of communication channels trains each channel to synchronize a local clock of the channel with a corresponding global clock at the beginning of a timing window. Next, in response to determining that all of the plurality of channels have an incorrect sign alignment, the circuitry rotates each channel sign by a single step length. In response to determining that some but not all of the plurality of channels have a correct symbol alignment, the circuitry rotates channel symbols having an incorrect symbol alignment by a single step size. When the end of the timing window has been reached, the circuitry symbol rotates the channel with the correct symbol alignment and adjusts the phase of the corresponding global clock to compensate for lost symbol rotation.

Description

[0001] This application is a divisional application of the invention patent application with application number 202080007371.6, application date April 27, 2020, and invention name “Skew correction method for physical layer interface on multi-chip module”. Background Art

[0002] Description of Related Technology

[0003] Modern semiconductor chips include a variety of circuits and components to facilitate fast and efficient computing. When transferring information between functional blocks in a semiconductor chip, electrical signals are typically sent over metal traces. A transmitter in a first functional block sends an electrical signal over a metal trace. A receiver in a second functional block receives the electrical signal. In some cases, the two functional blocks are within the same die. In other cases, the two functional blocks are on different dies.

[0004] As new systems and devices are developed, the processing speeds of information processing systems and devices continue to increase. When data signals and corresponding clock signals are sent between functional blocks, these signals may become misaligned relative to each other. Realigning the signals typically involves introducing a significant amount of delay. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Advantages of the methods and mechanisms described herein may be better understood by referring to the following description in conjunction with the accompanying drawings, in which:

[0006] Figure 1 is a block diagram of one implementation of a general purpose computer or communication system including a transmitter and a receiver.

[0007] Figure 2 is a block diagram of one implementation of a computing system.

[0008] Figure 3 This is a diagram of one implementation of a physical layer interface connection.

[0009] Figure 4 is a block diagram of one implementation of a circuit system for adjusting the phase of a local clock to achieve synchronous clock domain crossing.

[0010] Figure 5 is a block diagram of one implementation of a circuit for implementing an optional FIFO mode to increase available timing margin for implementing synchronous clock domain crossing.

[0011] Figure 6 is a diagram of one implementation of a circuit used in a deserializer.

[0012] Figure 7 is a timing diagram of one implementation using a barrel shifter in a deserializer to perform symbol lock.

[0013] Figure 8 is a timing diagram for one implementation of a point in time after the barrel shifter has shifted the clock phase by a single step.

[0014] Fig. 9 is a timing diagram for one implementation of a point in time after the barrel shifter has shifted the clock phase by a single step.

[0015] Fig.10 is a state diagram for one implementation of performing link-wide deskew with minimal latency.

[0016] Fig.11 is a diagram of one implementation of a circuit used in a deserializer.

[0017] Fig.12 is a diagram of one implementation of a 2-deep FIFO circuit that increases timing margin to account for clock jitter.

[0018] Fig.13 is a generalized flow chart illustrating one implementation of a method for performing training to align a local clock with a global clock.

[0019] Fig.14 is a generalized flow chart illustrating one implementation of a method for implementing synchronized cross-domain crossing of multiple channels.

[0020] Fig.15 is a generalized flow chart illustrating one implementation of a method for deskewing across multiple channels with reduced latency.

[0021] Fig.16 is a block diagram illustrating one implementation of a non-transitory computer-readable storage medium represented by a storage circuit. DETAILED DESCRIPTION

[0022] In the following description, numerous specific details are set forth to provide a thorough understanding of the methods and mechanisms presented herein. However, it will be appreciated by those of ordinary skill in the art that various implementations may be practiced without these specific details. In some cases, well-known structures, components, signals, computer program instructions, and techniques are not shown in detail to avoid confusion with the methods described herein. It should be understood that for simplicity and clarity of illustration, the elements shown in the figures are not necessarily drawn to scale. For example, the size of some elements may be enlarged relative to other elements.

[0023] Various systems, devices, methods, and computer-readable media for implementing a deskew method for a physical layer interface on a multi-chip module with a synchronous clock domain crossing with reduced latency are disclosed. In one implementation, a circuit connected to a plurality of communication channels trains each channel to synchronize the local clock of the channel with a corresponding global clock at the beginning of a timing window. Next, in response to determining that all of the plurality of channels have incorrect symbol alignment, the circuit rotates each channel symbol by a single step. In response to determining that some but not all of the plurality of channels have correct symbol alignment, the circuit rotates the channel symbol with incorrect symbol alignment by a single step. When the end of the timing window has been reached, the circuit symbol rotates the channel with correct symbol alignment and adjusts the phase of the corresponding global clock to compensate for the lost symbol rotation. The circuit samples a plurality of data signals using a plurality of local clocks to generate a plurality of data sequences in response to determining that all of the plurality of channels have correct symbol alignment.

[0024] In various implementations, techniques for implementing synchronous clock domain crossing with reduced latency are disclosed. In one implementation, a circuit generates a local clock when receiving a global clock and a data signal. The circuit includes a register that samples the local clock with the global clock. The circuit also includes a barrel shifter that generates a phase-shifted version of the local clock with a single unit interval (UI) step size. The circuit also includes control logic that uses the barrel shifter to scan the local clock across all phases until an edge transition is detected. When an edge transition is detected, this indicates that the local clock is aligned with the global clock. The control logic then adjusts the phase of the local clock to meet the setup and hold requirements for sampling the data signal. Next, the data signal is sampled with the phase-adjusted local clock to generate a data sequence.

[0025] Reference now Figure 1 , a block diagram of one implementation of a general purpose computer or communication system 100 including a transmitter 105 and a receiver 110 is shown. In one implementation, the transmitter 105 transmits data to the receiver 110 via a communication channel 115. Depending on the implementation, the communication channel 115 is a cable, a backplane, one or more metal traces, or other type of communication channel. For example, in one implementation, the channel 115 is one or more metal traces between two chips of a multi-chip module. At the physical layer, the communication between the transmitter 105 and the receiver device 110 can be unidirectional or bidirectional according to a given transmission protocol. It should be noted that the system 100 can include any number and type of other devices. In addition, the system 100 can include any number of transmitter-receiver pairs dispersed throughout the system.

[0026] Depending on the implementation, the transmitter 105 and the receiver 110 may be any type of device. For example, in one implementation, the transmitter 105 is a processing unit (e.g., a central processing unit (CPU), a graphics processing unit (GPU)) and the receiver 110 is a memory device. The memory device may be any type of memory, such as a dynamic random access memory (DRAM), a synchronous DRAM (SDRAM), a double data rate (DDR, DDR2, DDR3, etc.), an SDRAM (including a mobile version of SDRAM, such as mDDR3, etc., and / or a low power version of SDRAM, such as LPDDR2, etc.), a RAMBUS DRAM (RDRAM), a static RAM (SRAM), etc. One or more memory devices may be coupled to a circuit board to form a memory module, such as a single inline memory module (SIMM), a dual inline memory module (DIMM), etc. Alternatively, the memory device may be mounted in a system on chip (SoC) or an integrated circuit (IC) in a chip stack configuration, a package stack configuration, or a multi-chip module (MCM) configuration.

[0027] In another implementation, the transmitter 105 is an input / output (I / O) configuration and the receiver 110 is a peripheral device. The peripheral device may include devices for various types of wireless communications, such as wifi, Bluetooth, cellular, global positioning system, etc. The peripheral device may also include additional storage devices, including RAM storage devices, solid-state storage devices, or disk storage devices. The peripheral device may also include user interface devices, such as display screens, including touch screens or multi-touch screens, keyboards or other input devices, microphones, speakers, etc. In other implementations, the transmitter 105 and the receiver 110 are other types of devices. It should be noted that the system 100 can be any type of system, such as IC, SoC, MCM, etc.

[0028] Now go to Figure 2 , a block diagram of one implementation of a computing system 200 is shown. As shown, system 200 represents chips, circuit systems, components, etc. of a desktop computer 210, a laptop computer 220, a server 230, a mobile device 240, etc. Other devices are possible and are contemplated. In the illustrated implementation, system 200 includes any number of pairs of transmitters 202A-N and receivers 203A-N.

[0029] Reference now Figure 3 , a diagram showing one implementation of a physical layer interface connection. The main physical coding sublayer (PCS) 305 is Figure 3 The left side shows that it is connected via channel 340 to Figure 3Slave PCS 380 on the right. In one implementation, master PCS 305 is located on a first integrated circuit (IC) (i.e., chip) of a multi-chip module (MCM), and slave PCS 380 is located on a second IC of the MCM. For example, in one implementation, master PCS 305 is part of an input / output (I / O) semiconductor die, and slave PCS 380 is part of a core composite semiconductor die. In other implementations, master PCS 305 and slave PCS 380 are included together with other types of components or functional units.

[0030] In various implementations, the master PCS 305 includes or is coupled to a phase locked loop (PLL) 310 for generating a clock, which is coupled to a clock transmission module 325 and other modules within the master PCS 305. The master PCS 305 includes an array 315 of N receivers and an array 335 of M transmitters, where N and M are positive integers, and where the values ​​of N and M vary depending on the implementation. A receive clock gating (RXCG) module 320 is coupled to the receiver array 315 and a transmit clock gating (TXCG) module 330 is coupled to the transmitter array 335. In one implementation, a clock is forwarded from the master PCS 305, which is used as a reference clock for the PLL 310. The clock generated by the PLL 310 is forwarded through a channel 340 to be used as a reference clock for the PLL 375 (of the slave PCS 380) and downstream logic. In one implementation, the master PCS 305 and the slave PCS 380 use a half-rate architecture where the clock is half the data rate frequency and data is sampled on both the rising and falling edges of the clock.

[0031] In one implementation, the transmitter array 335 of the master PCS 305 is connected to corresponding channels in the channel 340 that have a width greater than 1000 microns (i.e., micrometers) between the most distant channels. Likewise, in one implementation, the receiver array 315 of the master PCS 305 is connected to corresponding channels in the data packet channel 340 that have a width greater than 1000 microns between the most distant channels. This causes drift between clock edges of different clocks transmitted on the channels of the channel 340.

[0032] In one implementation, synchronous clock domain crossing is achieved across the transmitter array 335 using one or more of the methods and mechanisms described herein. For example, even if the channels of the transmitter array 335 are separated by a distance greater than 1000 microns wide, synchronous clock domain crossing can be achieved using the techniques presented herein while adding a relatively small amount of latency to the interface (compared to conventional methods). In one implementation, to achieve synchronous clock domain crossing, the local clock from the PCS 380 is trained to align with the forwarded controller clock. As used herein, the term "local clock" is defined as a divided-down version of a relatively fast PLL clock. In addition, as used herein, the term "controller clock" is defined as a system-on-chip (SoC) master clock distributed across the channels of a channel (e.g., channel 340).

[0033] In one implementation, the delay is increased in 1 unit interval (UI) granularity to minimize the transmission channel skew between channels. In one implementation, an optional first-in-first-out (FIFO) mode is implemented to increase the timing margin that can be used to achieve synchronous crossing. When FIFO mode is enabled, more delay can be provided at the expense of more latency. However, this provides additional tuning range that can be used to reduce transmission channel skew. In one implementation, before training, the symbol start points are distributed on the various transmission channels of channel 340. After training, the symbol start points on the various transmission channels of channel 340 are aligned within 1 UI of each other.

[0034] Reference now Figure 4 , a block diagram of one implementation of a circuit system 400 for adjusting the phase of a local clock to achieve synchronous clock domain crossing is shown. In one implementation, for a physical layer (PHY) interface, the incoming controller clock is fixed in phase, and the local clock is a divided version of the fast clock generated by a PLL 420 (using a divider 422). The local clock is provided to a clock training unit 425. An example of a clock training unit 425 is shown as control logic within block 405. As shown in block 405, the local clock is phase shifted using a barrel shifter 415. In one implementation, multiple local clocks are trained to align with the corresponding controller clock, and then the trained local clocks are coupled to the 10 / 2 serializer, as shown in block 430.

[0035] In one implementation, a two-stage training method is performed to train the phase of the local clock to match the corresponding controller clock. In the first stage, when the phase relationship between the local clock and the controller clock is unknown, a training step is performed to establish the phase relationship of the local clock of each channel relative to the controller clock. In the second stage of the training method, the phase of each local clock is adjusted relative to the controller clock to meet the setup and hold requirements.

[0036] In one implementation, the controller clock is used to sample the local clock at the synchronization register 417, and the output of the synchronization register 417 is provided to the clock training finite state machine (FSM) 410. The local clock is scanned on all phases using a barrel shifter 415 until the sampler output (i.e., the output of the synchronization register 417) is detected to be from 0 to 1. When the sampler output is detected to be from 0 to 1, this indicates that the local clock is aligned within + / -1 unit interval (UI) of the controller clock. In one implementation, 1 UI is 1 / 10 of the 1x clock and 1 UI is the minimum resolution of the scan clock. In one implementation, additional averaging is performed in the clock training FSM 410 to resolve the increments caused by low-frequency phase offsets. Once the local clock is aligned with the controller clock, the phase of the local clock is adjusted to meet the setup and hold timing requirements. This method is repeated for all channels so that data from different channels are synchronized to the controller clock with relatively low latency. In addition, in one implementation, delays are added between channels to minimize skew caused by transmitters and channels.

[0037] use Figure 4 In the method shown, data is passed from the controller clock domain to the local clock domain with flip-flop to flip-flop timing, thereby reducing the latency present in conventional designs. Timing diagram 440 shows an example of the timing before training of the local clock to the controller clock. Timing diagram 450 shows an example of the timing achieved between the local clock and the controller clock after training and after the local clock has been adjusted relative to the controller clock to meet the setup and hold requirements.

[0038] Reference now Figure 5 , a block diagram of one implementation of a circuit 500 for implementing an optional FIFO mode to increase available timing margin for implementing synchronous clock domain crossings is shown. In one implementation, a computing system has a clock domain crossing between a potentially high jitter controller clock and a channel-generated local clock. The controller clock is used as a parallel data start clock from a master PCS, and the channel-generated local clock (i.e., word clock) is used for parallel data capture in a PHY interface. In one implementation, the synchronous clock domain crossing from the controller clock to the channel-generated local clock is implemented via a clock training algorithm with an optional FIFO buffer. If the expected controller clock jitter is high enough that the timing requirements cannot be met even with a trained interface, in one implementation, a FIFO is used to increase the jitter tolerance. In one implementation, a two-entry FIFO is used to double the jitter tolerance.

[0039] In one implementation, in a default mode, the local clock is adjusted with a 1 UI resolution based on the initial average difference between the controller clock and the local clock to ensure sufficient timing margin for the expected controller clock jitter. In one implementation, in an optional FIFO mode, a half-rate version of the controller clock is used as the write pointer and a half-rate version of the local clock is used as the read pointer. A clock training algorithm determines the initial average write / read pointer separation for the programmable placement of the read pointer. In one implementation, the read pointer placement is adjusted with a 1 UI resolution to ensure sufficient timing margin while also minimizing latency at the parallel data capture interface based on the expected controller clock jitter magnitude. In one implementation, if there is sufficient margin in the pointer separation, the read pointer is further adjusted in 1 UI steps after the initial clock training to reduce channel-to-channel skew. Once the data crosses the local clock domain, the data is serialized and provided to the channel through the transmission channel.

[0040] In one implementation, input data is fed through a flip-flop 510 in the physical coding sublayer (PCS) 505 domain. A controller clock is provided to the clock input of the flip-flop 510. In one implementation, the input data is 10 bits wide. However, in other implementations, the input data may have other bit widths. Similarly, the bit widths of other paths in the circuit 500 may vary in other implementations. The output of the flip-flop 510 is provided in parallel with the flip-flops 515 and 520 in the transmission macro domain 507. The half-rate controller clock is provided as a clock to the clock inputs of the flip-flops 515 and 520. The outputs of the flip-flops 515 and 520 are provided to the input of the multiplexer 525. The output of the multiplexer 525 is coupled to the input of the flip-flop 535. The 1x rate local clock is coupled to the clock input of the flip-flop 535. The output of the flip-flop 535 is provided to a serializer (not shown).

[0041] In one implementation, a high speed 5x rate clock is provided as an input to a word clock barrel shifter 540. In one implementation, the word clock barrel shifter 540 generates 10 unique phases of a local 1x rate clock. The phase adjusted output of the word clock barrel shifter 540 is inverted and then coupled to the clock port of the flip-flop 530. The output of the flip-flop 530 is inverted and then coupled back to the input of the flip-flop 530 to generate a phase adjusted half rate local clock. The phase adjusted half rate local clock is coupled to the select input of the multiplexer 525. The 1x controller clock is inverted and coupled to the clock input of the flip-flop 545. The output of the flip-flop 545 is inverted and then coupled back to the input of the flip-flop 545 to generate the half rate controller clock. It should be noted that ( Figure 5 The flip-flops shown in circuit 500 may be implemented using any type of suitable register (eg, a D-type flip-flop).

[0042] Reference now Figure 6 , a diagram of an implementation of a circuit 600 used in a deserializer is shown. In one implementation, the circuit 600 is implemented as part of 2 to 10 deserializers. The 2 to 10 deserializers receive 2 input bits per input clock cycle and generate 10 output bits per output clock cycle. However, in other implementations, the circuit 600 can be modified to be used with other types of deserializers that receive other numbers of input bits per cycle and / or generate other numbers of output bits per cycle. In one implementation, the circuit 600 performs symbol locking as part of 2 to 10 deserializers with 1 UI granularity of 2 UI clock phases. In one implementation, symbol locking is performed as part of link training of a link between two independent functional units. By using this technique, the incoming deserialized data is realigned with the correct symbol with relatively low latency. In one implementation, using this symbol locking technique involves two aspects. The first aspect is to deserialize the incoming serial data using a barrel-shifted clock phase. The second aspect is to fill the incoming serialized data in different ways to obtain the correct symbol.

[0043] As shown in circuit 600, the incoming serial data is sampled at both edges of the half-rate clock by flip-flops 615A-B to obtain two bits of data, which are then passed to flip-flop 645 through multiplexers 620 and 622. In one implementation, after deserialization, the data is in the local clock domain and will be moved to the controller clock domain again. This is done by Figure 4 In one implementation, the controller clock of the slave PCS is derived from a local PLL that has a reference clock forwarded from the master PCS.

[0044] For operation of the circuit 600, input data is received from the channel 605 and coupled to two sets of flip-flops 615A-B. The clock generation unit 610 generates a first clock with a phase of 0 degrees, which is coupled to the input of the flip-flop 615A. The clock generation unit 610 also generates a second clock with a phase of 180 degrees, which is coupled to the input of the flip-flop 615B. The second clock with a phase of 180 degrees coupled to the input of the flip-flop 615B is 180 degrees out of phase with respect to the first clock with a phase of 0 degrees coupled to the input of the flip-flop 615A. The output of the flip-flop 615A is labeled as data 1 and is coupled to the "1" input of the multiplexers 620 and 622. The output of the flip-flop 615B is labeled as data 0 and is coupled to the "0" input of the multiplexers 620 and 622. The select signals for the multiplexers 620 and 622 are generated by the shift data counter 625, which rolls over on an odd count.

[0045] Logic 630 for checking whether a sign rotation is required generates shift data for rotating the clock. The output from logic 630 is coupled to the shift data counter 625 and the barrel shifter 635. The 5x rate clock is also coupled to the barrel shifter 635. The barrel shifter 635 generates multiple 1x rate clocks with different phases based on the 5x rate clock input. The multiple 1x clocks with different phases generated by the barrel shifter 635 are provided to different flip-flops in the flip-flop 645. The output of the flip-flop 645 is coupled to the input of the flip-flop 650. The flip-flop 650 is clocked by the local clock, and the output 650 of the flip-flop is coupled to the flip-flop 655, which is clocked by the controller clock. In the case of an odd shift, the sample from the "0" flip-flop 645 is delayed, so there is an extra flip-flop 640 to ensure that the data is not overwritten by the incoming bit.

[0046] Reference now Figure 7 , shows a timing diagram 700 for performing symbol lock using a barrel shifter in a deserializer. The timing diagram 700 is intended to illustrate the use of ( Figure 6 ) circuit 600 is an example of the timing of incoming serial data sampled by the multiplexer. In one implementation, the data from the sampler is multiplexed into 2-bit data to achieve 0 / 1 UI delay on the multiplexer selection, as shown in the timing diagram 700. The 2-bit data is filled into a 10-bit register in an interleaved clock phase order. From the 10-bit register, the output is sampled using a local clock. The deserialized data is then analyzed to infer whether the data needs to be rotated to achieve the correct symbol timing. As shown in row 710 of the example of the timing diagram 700, the incoming data is sampled as a7:0 bits and x9:8 bits using the original, non-phase adjusted clock timing, where "a" is the current symbol and "x" is the previous symbol. To obtain the correct symbol, the goal is to sample the incoming data as a9:0 bits. As shown in row 710, the next symbol is sampled as b7:0 bits and a9:8 bits.

[0047] Now turn to Figure 8 , shows a timing diagram 800 at a point in time after the barrel shifter has performed a single step size sign rotation. The timing diagram 800 is intended to represent the timing diagram for one particular implementation after a single step size sign rotation has been performed. Figure 6 The timing diagram 800 is similar to the timing diagram of the circuit 600. Figure 7) timing diagram 700 illustrates the effect of performing a sign rotation. In timing diagram 800, the phase of the odd register clocks has been shifted. Register 9 will receive the phase timing of the previous register 0, register 1 will receive the phase timing of the previous register 2, register 3 will receive the phase timing of the previous register 4, and so on. Therefore, the clocks of half of the registers are shifted right by 2 UI. Although the clocks of half of the registers are shifted right, the local clock remains unchanged. After the phase shift of 2 UI, a8:0 and x9 are the sampled data as shown in row 810. In the case of an odd shift, the sample from flip-flop 0 is delayed, so there is an additional flip-flop 0_delay so that the data is not overwritten by the newly incoming bit a9.

[0048] Reference now Fig. 9 , showing a timing diagram 900 at a point in time after the barrel shifter has performed a second step size sign rotation. The timing diagram 900 is intended to represent the timing diagram for one particular implementation after the clock phase has been shifted by a second sign rotation step size. Figure 6 The timing diagram 900 is similar to the circuit 600 of FIG. Figure 8 The difference between the timing diagram 800 of ( ) illustrates the effect of performing a second sign rotation step. Figure 7 In the example originally shown in timing diagram 700 of ), two symbol rotation steps are required to sample the correct symbol. Accordingly, the first stage clock phase of half the registers is rotated twice by the barrel shifter to obtain the correct symbol. In addition, each uniform rotation causes the local clock to move 2 UI steps. For diagram 900, 2 UI shifts actually occur and the data becomes a9:0, and multiplexers 620 and 622 shift back. Using this technique, the symbol is locked by moving the symbol window by the correct number of UI steps without any delay. As shown in diagrams 800 and 900, the phase is shifted by 1 UI by moving 2 UI every other clock.

[0049] Now turn to Fig.10, a state diagram 1000 of one implementation of performing link wide skew correction with minimal latency is shown. In one implementation, a method for link training in a receiving physical layer (PHY) interface is implemented according to state diagram 1000. The method is performed to determine the position of the symbol eye of each of a plurality of channels to align the symbols on the channels while skew correcting them to achieve synchronous data transmission. "Symbol eye" refers to the data validity period of a symbol based on a bit transition on a link data channel. In conventional methods, a source synchronous clock scheme for skew correction uses an additional stage to simplify the timing of capturing the correct symbol, wherein the additional stage results in a relatively high latency. However, using the method associated with state diagram 1000, the latency is significantly reduced compared to conventional methods. In one implementation, the method associated with state diagram 1000 uses the previously described synchronous clock domain crossing scheme and the symbol locking scheme and 2 to 10 deserializers with a 1 UI granularity of 2 UI clock phases.

[0050] Before link training, each channel is trained using a synchronous clock domain crossing scheme so that the local clock timing to the controller clock is at the beginning of the timing window (i.e., the maximum hold, minimum setup time is met). This step is repeated until the link is established. As used herein, the term "timing window" is defined as the duration for which the corresponding data is valid. The timing window is defined by the leading and trailing edges of the data signal. Then, after the link is established, each channel is checked and one of the following options is used. If all channels do not have the correct symbol, the state diagram 1000 moves from the reset state 1005 to the extraocular state 1015. In the extraocular state 1015, each channel symbol is rotated by 1 step using a barrel shifter, and the controller clock is also rotated by 1 step to maintain the established timing relationship. All channels are then checked. If some channels are symbol locked, the state diagram moves to state 1010. In state 1010, the local clocks of the channels that are not symbol locked are shifted by 1 UI. In one implementation, the channels that are not symbol locked are shifted by 1 UI using a barrel shifter. Since the controller clock is static, the setup time is increased by 1 UI and the hold time is increased by 1 UI for the timing relationship between the controller clock and the local clock. This continues until all channels are symbol locked until the timing margin window. In the event that some channels are still not symbol locked when the timing margin window is reached, the state diagram 1000 moves back to the reset state 1005. Otherwise, if all channels are symbol locked, the state diagram 1000 moves to the locked state 1030.

[0051] If in reset state 1005, some channels are symbol locked, then state diagram 1000 moves to state 1010. From state 1010, state diagram 1000 moves to analyze state 1025. Then, state diagram 1000 moves to begin_end_eye state 1020, where the local clocks are shifted for the channels that are symbol aligned. This method is used until the end of the timing window (i.e., minimum hold time, maximum setup time). At the end of the timing window, all locked channels and controller clocks are rotated to compensate for the missed rotation. If the newly locked channel is locked on the symbol after deskew, the existing locked channels except the most recently locked channel and controller clock are rotated to compensate for the missed rotation.

[0052] Reference now Fig.11 , a diagram 1100 showing one implementation of a symbol eye origin across four communication channels 1105A-D. Channels 1105A-D represent any number of channels included as part of a communication channel. Fig.11 Four channels are shown, but it should be understood that this number is intended as an example for illustration purposes. Other implementations may have other numbers of channels and still use the techniques described herein to align symbol eyes across multiple channels. The symbol eyes for channels 1105A-D are shown as shaded rectangles within channels 1105A-D.

[0053] Due to mismatched trace lengths connected to channels 1105A-D and / or due to other factors, before training, the symbol eye for each channel is typically different for different channels 1105A-D. The IN_EYE starting point for reset is shown at the top of Figure 1100 to indicate that the execution is performed with ( Fig.10 1000 . The control logic will attempt to lock onto the symbol eye of each channel 1105A-D by rotating the local clocks of the misaligned channels. If the control logic reaches the END_EYE point of a channel before locking onto the symbol eyes of all channels, the control logic resets and starts again when the next symbol is received on channels 1105A-D. The goal of the training is to adjust the phase of the local clocks of channels 1105A-D so that the symbol eye of each channel is aligned with the symbol eyes of the other channels.

[0054] Now turn to Fig.12, a diagram of one implementation of a two-entry FIFO circuit 1200 that increases timing margin to account for clock jitter is shown. In one implementation, data is received from a channel and provided to a sampler, where the sampler clock is a fast PLL clock (compared to a word clock). To ensure that the data is sampled correctly, various algorithms are run starting with a clock data recovery (CDR), which establishes a lock between the incoming serial bit stream and the fast PLL clock. In one implementation, after lock is established, the input bit stream is deserialized into parallel data. In one implementation, the input serial bit stream is deserialized into 10-bit parallel data. However, in other implementations, parallel data of other bits are generated.

[0055] In one implementation, after deserialization, the data is in the local clock domain and needs to be moved to the controller clock domain. In one implementation, this is achieved using the previously described synchronous clock domain crossing technology and by using circuit 1200. In one implementation, the clock domain crossing between the local clock (i.e., word clock) and the potential high-jitter controller clock is achieved by two-entry FIFO circuit 1200. A half-rate local clock is used as a write pointer, and a half-rate version of the controller clock is used as a read pointer. Both the write pointer and the local clock are generated by a common high-speed clock. In one implementation, the position of the write pointer is adjusted with 1 UI resolution.

[0056] In one implementation, the input serial data is coupled to the input of the flip-flops 1205A-N. In one implementation, the input data includes 10 input channels. However, it should be understood that in other implementations, by adjusting the number of flip-flops 1205A-N and the bit width of other components of the circuit 1200, the circuit 1200 can support other numbers of input channels. In one implementation, the word clock barrel shifter 1207 receives a high-speed 5x rate clock, which uses the high-speed 5x rate clock to generate a 1x rate clock output with 5 unique phases and 2 UI resolution. These 1x rate clocks with different phases are coupled to the clock ports of the flip-flops 1205A-N. The data inputs of the flip-flops 1205A-N are sampled using the phase-shifted clock.

[0057] In one implementation, the outputs from flip-flops 1205A-N are coupled to an input port of flip-flop 1210. Word clock barrel shifter 1207 also generates a local 1x rate clock, which is coupled to the clock port of flip-flop 1210. The output of flip-flop 1210 is coupled to the input ports of flip-flops 1215 and 1220. The high speed 5x rate clock is also coupled to write pointer generator 1240. Write pointer generator 1240 generates a half rate local clock, which is coupled to the clock port of flip-flop 1215. The half rate local clock of write pointer generator 1240 is negated and coupled to the clock port of flip-flop 1220. The output of flip-flop 1215 is coupled to the “0” input of multiplexer 1225, while the output of flip-flop 1220 is coupled to the “1” input of multiplexer 1225. The half rate controller clock generated by flip-flop 1245 is coupled to the select port of multiplexer 1225. The output channels of multiplexer 1225 are coupled to the input ports of flip-flop 1235. The 1x rate controller clock is coupled to the clock port of flip-flop 1235. The parallel data output from flip-flop 1235 is provided to a controller (not shown) or other components for further processing.

[0058] Reference now Fig.13 , shows one implementation of a method 1300 for performing training to align a local clock with a global clock. For discussion purposes, the steps and Fig.14 However, it should be noted that in various implementations of the described method, one or more of the described elements are performed simultaneously, in a different order than shown, or omitted entirely. Other additional elements are also performed when necessary. Any of the various systems or devices described herein is configured to implement method 1300.

[0059] The circuit receives a global clock signal and a data signal (block 1305). It should be noted that the global clock may also be referred to herein as a "controller clock". In some implementations, the circuit receives multiple global clocks and multiple data signals. In one implementation, the global clock and data signals are generated in a functional unit separate from the receiving functional unit. The circuit also generates a local clock signal (block 1310). For example, in one implementation, the circuit generates the local clock signal using a local PLL.

[0060] The circuit sweeps the local clock across phases in 1 UI steps with a barrel shifter while sampling the local clock with a register clocked by a global clock to detect edge transitions (block 1315). In one implementation, the output of the register is coupled to control logic that detects edge transitions. In one implementation, the control logic includes a finite state machine (FSM). In one implementation, the edge transition is a rising edge transition (i.e., from a low voltage to a high voltage). Next, the control logic determines that the local clock is aligned with the global clock in response to detecting the edge transition (block 1320). Then, the phase of the local clock is adjusted relative to the global clock to meet the setup and hold timing requirements (block 1325). Next, the data signal is sampled using the phase-adjusted local clock (block 1330). Then, the sampled data is provided to a subsequent stage for additional processing and / or storage (block 1335). In one implementation, the sampled data is provided to a deserializer. After block 1335, method 1300 ends.

[0061] Reference now Fig.14 , shows an implementation of a method for implementing synchronous cross-domain crossing of multiple channels. The circuit receives multiple data signals and multiple corresponding global clock signals (block 1405). The circuit also generates multiple local clock signals (block 1410). For example, in one implementation, the circuit generates each local clock signal using a different local PLL. The circuit scans each local clock across phase in 1 UI steps with a barrel shifter, while sampling the local clock with a register clocked by the corresponding global clock to detect edge transitions (block 1415). In one implementation, the output of the register is coupled to control logic that detects edge transitions. In one implementation, the control logic includes a finite state machine (FSM). In one implementation, the edge transition is a rising edge transition (i.e., from logic "0" to logic "1").

[0062] Next, the control logic determines that each local clock is aligned with the corresponding global clock in response to detecting the edge transition (block 1420). Then, the phase of each local clock is adjusted relative to the corresponding global clock to meet the setup and hold timing requirements (block 1425). Next, each data signal is sampled using the corresponding phase-adjusted local clock (block 1430). The sampled data is then provided to a subsequent stage for additional processing and / or storage (block 1435). In one implementation, the sampled data is provided to a deserializer. After block 1435, the method 1400 ends.

[0063] Reference now Fig.15, shows one implementation of a method 1500 for deskewing across multiple channels with reduced latency. Each of the multiple channels is trained to synchronize each local clock with the global clock at the beginning of a timing window (i.e., maximum hold, minimum setup time) (block 1505). In one implementation, performing ( Fig.14 ) method 1400 to implement block 1505. Next, the symbol timing of each channel is checked (block 1510). If none of the channels have the correct symbol alignment (the "no channel" branch of conditional block 1515), each channel symbol is rotated by a single step (block 1520). In one implementation, rotating each channel symbol by a single step involves shifting every other clock (a clock with staggered phases generated by the barrel shifter of the channel) by a single unit interval. The clock with staggered phases generated by the barrel shifter is provided to the first column flip-flop, which deserializes the data samples captured from the channel. After block 1520, method 1500 returns to block 1510.

[0064] If some channels have the correct sign alignment ("some channels" branch of conditional block 1515), then the unlocked channel signs are rotated by a single step (block 1525). In one implementation, using ( Figure 6 ) circuit 600 performs blocks 1520 and 1525. After block 1525, if the end of the timing window has been reached (the "yes" branch of conditional block 1530), all locked lanes and the global clock are rotated to compensate for the missed rotation (block 1535). After block 1535, method 1500 returns to block 1510. If the end of the timing window has not been reached (the "no" branch of conditional block 1530), method 1500 returns to block 1525. If all lanes have correct symbol alignment ("all lanes" of conditional block 1515), method 1500 ends.

[0065] Now turn to Fig.16 , a block diagram of one implementation of a non-transitory computer-readable storage medium 1600 storing a circuit representation 1605 is shown. In one implementation, a circuit fabrication system 1610 processes the circuit representation 1605 stored on the non-transitory computer-readable storage medium 1600 and fabricates any number of integrated circuits 1615A-N based on the circuit representation 1605.

[0066] The non-transitory computer-readable storage medium 1600 may include any of a variety of suitable types of memory devices or storage devices. The medium 1600 may be an installation medium (e.g., a thumb drive, a CD-ROM), a computer system memory or random access memory (e.g., a DRAM, a DDR RAM, a SRAM, an EDO RAM, a Rambus RAM), a non-volatile memory (e.g., a flash memory, a magnetic medium, a hard drive, an optical storage device), a register, or other types of memory elements. The medium 1600 may also include other types of non-transitory memory or any combination thereof. The medium 1600 may include two or more storage media residing in different locations (e.g., in different computer systems connected via a network).

[0067] In various implementations, circuit representation 1605 is specified using any of a variety of suitable computer languages, including hardware description languages ​​such as, but not limited to, VHDL, Verilog, SystemC, SystemVerilog, RHDL, etc. Circuit representation 1605 can be used by circuit fabrication system 1610 to fabricate at least a portion of one or more integrated circuits 1615A-N. The format of circuit representation 1605 can be recognized by at least one circuit fabrication system 1610. In some implementations, circuit representation 1605 includes one or more cell libraries that specify synthesis and / or layout of integrated circuits 1615A-N.

[0068] Circuit manufacturing system 1610 includes any of a variety of suitable components configured to manufacture integrated circuits. This may include, for example, components for depositing semiconductor material (e.g., on a wafer, which may include a mask), removing material, changing the shape of deposited material, modifying material (e.g., by doping the material or modifying the dielectric constant using ultraviolet treatment), etc. Circuit manufacturing system 1610 may also test the manufactured circuits for proper operation.

[0069] In various implementations, the integrated circuits 1615A-N operate according to the circuit design specified by the circuit representation 1605, which may include performing any of the functions described herein. For example, the integrated circuits 1615A-N may include any of the various elements shown in the circuits shown herein and / or in the multiple instances of the circuits shown herein. In addition, the integrated circuits 1615A-N may be combined with other components to perform the various functions described herein. For example, the integrated circuits 1615A-N may be coupled to a voltage power supply circuit system that is configured to provide a supply voltage (e.g., as opposed to including a voltage supply itself). In addition, the functions described herein may be performed by multiple connected integrated circuits.

[0070] As used herein, phrases of the form "circuit representation of a design specifying a circuit ..." do not imply that the circuit in question must be manufactured in order to satisfy the element. Rather, this phrase indicates that the circuit representation describes a circuit that will be configured to perform the indicated action or will include the specified components after manufacture.

[0071] In various implementations, program instructions are used to implement the methods and / or mechanisms described herein. Alternatively, program instructions describing the behavior or design of hardware can be written. In one implementation, such program instructions are represented by a hardware design language (HDL) such as Verilog. In various implementations, program instructions are stored on any of a variety of non-temporary computer-readable storage media. During use, a computing system can access the storage medium to provide program instructions to the computing system for circuit manufacturing, program execution or other purposes. In general, such computing systems include at least one or more memories and one or more processors configured to execute program instructions.

[0072] It should be emphasized that the above implementations are only non-limiting examples of implementations. Once the above disclosure is fully understood, many changes and modifications will be obvious to those skilled in the art. It is expected that the following claims will be understood to include all such changes and modifications.

Claims

1. A circuit comprising: a first circuit configured to synchronize a local clock of each of a plurality of communication channels with a global clock; A second circuit is configured to: In response to determining that one or more of the plurality of communication channels have an incorrect symbol alignment, symbol rotate each of the plurality of channels having the incorrect alignment; and In response to detecting an end of the timing window, symbol timing of each of the plurality of lanes is checked.

2. The circuit of claim 1, wherein: In response to detecting an end of the timing window, the circuit is configured to perform a symbol rotation on each lane of the plurality of lanes having a correct symbol alignment.

3. The circuit of claim 1, wherein: To synchronize the local clock of each of the plurality of communication channels with the global clock, the first circuit is configured to sweep the local clock across a plurality of phases while sampling the local clock with the global clock.

4. The circuit of claim 1, wherein: The first circuit is configured to determine that the local clock is aligned with the global clock in response to detecting an edge transition during the scan of the local clock.

5. The circuit of claim 4, wherein: After the local clock is aligned with the global clock, the phase of the local clock is adjusted to meet setup and hold timing requirements.

6. The circuit of claim 1, wherein: After the local clock is synchronized with the global clock, the circuit is configured to sample data on a communication channel of the plurality of communication channels using the local clock.

7. The circuit of claim 1, wherein: The data sampled on the communication channel using the local clock is transmitted to the deserializer.

8. A method comprising: synchronizing a local clock of each of the plurality of communication channels with a global clock; In response to determining that none of the plurality of communication channels has a proper symbol alignment, performing a symbol rotation on each of the plurality of channels; and In response to detecting an end of the timing window, symbol timing of each of the plurality of lanes is checked.

9. The method of claim 8, wherein: In response to detecting an end of the timing window, the method includes performing a symbol rotation on each lane of the plurality of lanes having a correct symbol alignment.

10. The method of claim 8, wherein: To synchronize a local clock of each of the plurality of communication channels with a global clock, the method includes sweeping the local clock across a plurality of phases while sampling the local clock with the global clock.

11. The method of claim 8, further comprising determining that the local clock is aligned with the global clock in response to detecting an edge transition during the scanning of the local clock.

12. The method of claim 11, wherein: After the local clock is aligned with the global clock, the method includes adjusting a phase of the local clock to meet setup and hold timing requirements.

13. The method of claim 8, wherein: After the local clock is synchronized with the global clock, the method includes sampling data on a communication channel of the plurality of communication channels using the local clock.

14. The method of claim 8, further comprising transmitting data sampled on a communication channel using the local clock to a deserializer.

15. A system comprising: a first functional unit; A channel with multiple communication channels; and a second functional unit coupled to the first functional unit via the channel, wherein the second functional unit is configured to transmit a first global clock and a first data signal to the first functional unit via the channel; Wherein, the first functional unit is configured as: synchronizing a local clock of each of the plurality of communication channels with a global clock; In response to determining that one or more of the plurality of communication channels have an incorrect symbol alignment, symbol rotate each of the plurality of channels having the incorrect alignment; and In response to detecting an end of the timing window, symbol timing of each of the plurality of lanes is checked.

16. The system of claim 15, wherein: In response to detecting an end of the timing window, the first functional unit is configured to perform a symbol rotation on each lane of the plurality of lanes having a correct symbol alignment.

17. The system of claim 15, wherein: To synchronize the local clock of each of the plurality of communication channels with the global clock, the first functional unit is configured to sweep the local clock across a plurality of phases while sampling the local clock with the global clock.

18. The system of claim 15, wherein: The first functional unit is configured to determine that the local clock is aligned with the global clock in response to detecting an edge transition during a scan of the local clock.

19. The system of claim 18, wherein: After the local clock is aligned with the global clock, the phase of the local clock is adjusted to meet setup and hold timing requirements.

20. The system of claim 15, wherein: After the local clock is synchronized with the global clock, the first functional unit is configured to sample data on a communication channel among the plurality of communication channels using the local clock.

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