A low-cost HDMI video optical transmission device and transmission method based on FPGA

Abstract

This invention relates to a low-cost HDMI video optical transmission device and method based on FPGA. It uses an FPGA to encode and decode HDMI video signals, replacing dedicated video encoding and decoding chips. Simultaneously, it designs a novel video transmission frame architecture. At the transmitting end, valid video data is framed into data frames for transmission, and a frame identifier is set in each data frame. At the video recovery end, the data frames are deframed to extract video data based on the frame identifier. Depending on different resolutions, the FPGA's local clock IP core dynamically adjusts to adapt to various resolutions, outputting horizontal and vertical video signals, replacing dedicated pixel clock recovery chips and DDR3 cache chips. The entire solution boasts high transmission efficiency, low transmission latency, and real-time transmission capability. Furthermore, the hardware system is low-cost and small in size, making it suitable for widespread use.

Description

Technical Field

[0001] This invention relates to the field of video transmission, and more specifically to a video optical transmission device and transmission method. Background Technology

[0002] Traditionally, video signals are transmitted using cables. However, during transmission, factors such as cable impedance and length can degrade signal quality, resulting in noisy and unsatisfactory images during video reconstruction at the receiving end. Therefore, optical fibers are now commonly used as the transmission medium. However, ordinary video optical transceivers have the following problems in use:

[0003] The video recovery process uses a traditional caching method: DDR3 dynamically caches about 3 frames of images, which results in a large video transmission delay and cannot meet the low latency requirements of fields such as target tracking.

[0004] Each TMDS high-speed differential signal is transmitted using one optical fiber, which means that at least four optical fibers are needed for one video channel. Wavelength division multiplexers and demultiplexers are required to achieve single-fiber transmission, resulting in low transmission efficiency.

[0005] The video sending end requires a professional video decoding interface chip, the video recovery end requires a professional video encoding chip, and a professional pixel clock recovery chip to match the pixel clock of the video source. The solution is costly and large in size. Summary of the Invention

[0006] To address the shortcomings of existing technologies, this invention provides a low-cost HDMI video optical transmission device and method based on FPGA, which has the advantages of high transmission efficiency, low transmission latency and low hardware cost.

[0007] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0008] A low-cost HDMI video optical transmission device based on FPGA is disclosed. Both the transmitter and receiver of the optical transmission device employ FPGA chips. The transmitter includes a video decoding module, a video de-jitter reconstruction module, a video framing module, a high-speed serial transceiver (GTX), and a high-speed optical module. The receiver includes a high-speed optical module, a high-speed serial transceiver (GTX), a video deframe module, a dynamic clock reconfiguration module, a video timing reconstruction module, and a video encoding module. The transmitter and receiver are connected via optical fiber communication. The video framing module is used to frame valid video data into data frames for transmission and to set frame identifiers in the data frames. The video deframe module is used to deframe the data frames to extract video data based on the frame identifiers.

[0009] The video decoding module deserializes and aligns the serial data from HDMI, and performs data channel synchronization processing on the three differential data sets of HDMI RGB. After synchronization, the data is output according to the decoding rules of the HDMI protocol, including the horizontal signal HS, the vertical signal VS, the data valid signal DE, and the video data DATA.

[0010] The video de-jitter reconstruction module performs video de-jitter and timing establishment on the line signal HS, field signal VS, data valid signal DE, and video data DATA after FPGA decoding through de-jitter filtering and image buffering.

[0011] The data frames output by the video framing module contain end-of-field information code, DE header information code, and resolution information code.

[0012] The video framing module and the video deframing module adopt asynchronous FIFO. The write clock of the video framing module FIFO is the video pixel clock, and the read clock is the user clock of the high-speed serial transceiver GTX. The write clock of the video deframing module FIFO is the user clock of the high-speed serial transceiver GTX, and the read clock is the pixel clock multiplied by the local crystal oscillator.

[0013] The dynamic clock reconfiguration module calls the clock IP core, configures the clock parameters according to the timing relationship of DRP, and dynamically multiplies the frequency according to different resolutions to achieve the required pixel clock.

[0014] The video encoding module encodes the field signal, line signal, and valid data signal output by the video timing reconstruction module into TMDS according to the HDMI protocol. The encoded data is then converted from parallel to serial, and the converted TMDS high-speed differential signal is output to the HDMI connector.

[0015] This invention also provides a low-cost HDMI video optical transmission method based on FPGA. An HDMI video signal is introduced at the transmitting end, and after video decoding, jitter reduction and reconstruction, and frame assembly processing are performed by the FPGA, a high-speed serial transceiver (GTX) is used for parallel-to-serial conversion, which is then connected to a high-speed optical module to complete electro-optical conversion. The signal is then connected to the receiving end via an optical interface and optical fiber. The receiving end sends the optical signal to the high-speed optical module, which is then connected to the high-speed serial transceiver (GTX). The high-speed serial data stream is converted into a parallel data stream, and after video frame de-framing, dynamic clock reconfiguration, video timing reconstruction, and video encoding processing by the FPGA, an HDMI video signal is output.

[0016] The video decoding process is as follows: the serial data of HDMI is deserialized to obtain the correct data after deserialization; according to the HDMI protocol, control characters are transmitted regularly during the idle period, and byte alignment is achieved by judging whether the control characters are received stably; after byte alignment, the three groups of differential data of HDMI RGB are synchronized; after synchronization, the data is output according to the decoding rules of the HDMI protocol, and the horizontal signal HS, the vertical signal VS, the data valid signal DE, and the video data DATA are output.

[0017] The specific process of de-shaking and reconstructing the video is as follows:

[0018] First, the resolution of the horizontal signal HS and the vertical signal VS is detected, and the corresponding timing information is output according to the different resolutions based on the VESA standard.

[0019] Two dual-port RAMs are used to store video data in a ping-pong manner. The first-level RAM stores the odd-numbered lines of video data for each frame, and the second-level RAM stores the even-numbered lines of video data for each frame. The data valid signal DE output by the video decoder is used as the write enable for the RAM. During the process, the high-level time of the data valid signal DE is judged. When the high-level time does not match the line valid time corresponding to the resolution, the line data is considered to be incorrect, and an error mark DE-ERR is output.

[0020] Based on the aforementioned resolution detection results, a VESA-compliant line signal HS2, field signal VS2, and data valid signal DE2 are generated after a 1-line delay. The RAM to be read is selected based on the aforementioned error identifier DE-ERR, and the data of the erroneous line is filled by reading the data of the previous line.

[0021] During video framing and deframing, an asynchronous FIFO is used to solve the cross-clock domain problem. During framing, the FIFO's write clock is the video pixel clock, and the read clock is the user clock of the high-speed serial transceiver GTX. During deframing, the FIFO's write clock is the user clock of the high-speed serial transceiver GTX, and the read clock is the pixel clock multiplied by the local crystal oscillator.

[0022] The specific processing steps for framing the video are as follows:

[0023] When the rising edge of the valid data signal DE and the falling edge of the valid field signal VS are detected, the FIFO write enable is turned on and the corresponding fixed identifier is written. When the count of the valid field signal VS being low reaches a set value, the FIFO write enable is turned on and data containing resolution information and the fixed identifier is written. When the valid data signal DE is high, the FIFO write enable is turned on and video data is written. At other times, the FIFO write enable is turned off. When the FIFO is not empty, the read enable is turned on and the predetermined length of data read is put into the GTX transmission data. When the FIFO is empty, the GTX transmission data is fixed and the K code identifier is sent.

[0024] During the video frame assembly process, 8'hff in the video data is replaced with 8'hfe, and 8'hff is used as a fixed identifier for resolution information.

[0025] The specific processing steps for video frame decoding are as follows:

[0026] According to the video framing architecture of the transmitter, when a fixed identifier of resolution information appears in the parallel data stream converted by the high-speed serial transceiver GTX at the receiver, the video resolution information is parsed out. Based on different resolution information, the required clock frequency is multiplied by the local crystal oscillator. When a K-code identifier is detected in the GTX parallel data stream, the FIFO write enable is turned off; otherwise, the write enable is turned on, and video data is written.

[0027] During video frame decoding, line validity information is obtained based on the parsed resolution information. When the FIFO's readable data is greater than the number of valid lines, the FIFO read enable is turned on. If the data read from the FIFO is 24'h00ff00, it indicates that a falling edge of the field valid signal has been detected, and the output field valid signal and data valid signal are set low, while the FIFO read enable is turned off. If the data read from the FIFO is 24'hff0000, it indicates that a rising edge of the data valid signal has been detected, and the field valid signal is set high. Then, the FIFO's readable data is checked again. If it is greater than the number of valid lines, the FIFO read enable is turned on, and the data valid signal is set high; otherwise, the FIFO read enable is turned off, and the data valid signal is set low.

[0028] The processing for video temporal reconstruction is as follows:

[0029] When the rising edge of the field valid signal in the deframed data is detected, the field enable is set high; when the falling edge of the field valid signal is detected, the field enable is set low; when no high level of the field valid signal is detected for more than one frame, the field enable is set low.

[0030] When the field enable level is high and the valid data signal in the deframed data is high, the deframed video data is sent to the synchronization FIFO;

[0031] When the rising edge of the field valid signal in the deframed data is detected, the VESA standard timing signal at that resolution is generated after a delay of 1 line, based on the current resolution. The line, field, and data valid signals are then used as the read enable of the synchronization FIFO, and the read data is the valid video data.

[0032] In the optical transmission method, the FPGA obtains the communication status of the optical path in the following three ways:

[0033] Method 1: The IIC interface acquires the received optical power of the optical module in real time. When the received optical power is less than the set threshold, the optical path communication is considered abnormal.

[0034] Method 2: 8B / 10B encoding / decoding DC balanced signal and polarity signal error indication of the high-speed serializer GTX;

[0035] Method 3: Check the K28.5 synchronization code every 10ms; if it is not detected, the optical path communication is abnormal.

[0036] When an optical path communication anomaly is detected, a scrolling color bar at the current resolution is output to inform the user of the current optical path status.

[0037] According to the above technical solution, the present invention can achieve the following beneficial effects:

[0038] 1. This invention uses FPGA to decode and encode video signals, replacing professional video interface chips. The entire solution only includes a power chip, FPGA, and optical module core chip, which greatly reduces the cost, size, and power consumption of the product. The device panel only has HDMI video interface, power interface, and optical fiber interface. The interface is simple and easy to use. The structure is small in size and the hardware cost is low, making it convenient for field operations and commercial promotion.

[0039] 2. This invention performs de-jitter filtering and image buffering on the input video signal to avoid glitches caused by poor video transmission quality at the video source, which can lead to screen flickering at the video output, thus improving the fault tolerance and reliability of the transmission scheme.

[0040] 3. This invention designs a brand-new video transmission architecture. At the video recovery end, the FPGA local clock IP core is used to dynamically adjust and adapt to various resolutions according to different resolutions, outputting horizontal and vertical video signals, replacing the DDR3 cache chip or pixel clock recovery chip at the video receiver end in the traditional solution; it uses a single optical fiber to transmit HDMI video with a resolution of 1080P@60Hz and below, and the transmission delay from the video signal source end to the recovery end is controlled at about 1ms. The low latency feature is suitable for real-time tracking and other fields, while reducing cost, size and power consumption.

[0041] 4. Design a custom frame structure for transmission, use unique frame identifiers for video information to ensure correct timing reconstruction at the receiving end, transmit only video data when DE is valid, and improve the reliability and bandwidth utilization of the communication system. Attached Figure Description

[0042] Figure 1 The HDMI video optical transmission architecture of this invention embodiment;

[0043] Figure 2 HDMI byte alignment process during video decoding;

[0044] Figure 3 RGB data channel synchronization process. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0046] like Figure 1 The diagram shows a transmission architecture for an FPGA-based HDMI video optical transmission device according to this embodiment. The optical transmission device includes a transmitter and a receiver, both of which use FPGA chips. The transmitter and receiver are connected via optical fiber communication.

[0047] The transmitter introduces the video signal through an HDMI connector. After hot-swapping protection using diodes, it is connected to the HR BANK of the FPGA chip. In this embodiment, the FPGA chip is Xilinx's XC7A200T-2FGG484, selected based on logic resources and cost considerations. After the FPGA performs video decoding, video de-jitter reconstruction, and video frame assembly on the HDMI video, a high-speed serial transceiver (GTX) is used to convert the parallel data stream into a high-speed serial data stream, which is then connected to a high-speed optical module to complete the electro-optical conversion. The signal is then output through an FC optical interface and connected to the receiver.

[0048] The receiver sends the optical signal to the high-speed optical module through the FC optical interface, and then connects to the FPGA high-speed serial transceiver GTX. The high-speed serial data stream is converted into a parallel data stream. The receiver performs video deframe, dynamic clock reconfiguration, video timing reconstruction and video encoding on the parallel data stream, and then outputs the video signal through the HDMI connector with hot-swap protection via diodes.

[0049] Specifically, the transmitter's functional modules are divided into a video decoding module, a video de-jittering and reconstruction module, and a video framing module.

[0050] The video decoding module is used to decode and process the data, as follows:

[0051] (1) The serial data of HDMI is deserialized through the primitives IDELAY2 and ISERDES2. The serial-to-parallel ratio of HDMI is 1:10. ISERDES2 is cascaded to achieve a 1:10 conversion. The reference clock of IDELAY2 is 200M, that is, 1 tap is 78ps. IDELAY2 selects VAR_LOAD mode to facilitate dynamic adjustment of data delay and obtain the correct data after deserialization.

[0052] (2) According to the HDMI protocol, it transmits four 10-bit control characters when it is idle. Byte alignment is achieved by determining whether the control characters are received stably. For the specific control process, please refer to the appendix. Figure 2 :

[0053] (3) HDMI has three sets of differential data (RGB). Due to factors such as PCB wiring, it is not possible to guarantee that the three sets of data are completely synchronized. Therefore, data channel synchronization processing is required for the three sets of differential data (RGB).

[0054] (4) After synchronization is completed, the data is output according to the 8B10B decoding rules of the HDMI protocol, including horizontal signal HS, vertical signal VS, data valid signal DE, and video data DATA.

[0055] The data channel synchronization process is as follows (refer to...) Figure 3 The synchronous processing flow is illustrated using red data processing as an example:

[0056] 1) Determine whether the byte alignment of the data after deserializing the three sets of RGB data is complete. Otherwise, wait until the byte alignment is complete. If the byte alignment is complete, proceed to the next step.

[0057] 2) Write the R channel data into the dual-port RAM, and at the same time start reading the RAM. Determine whether there is any control character in the read data. If not, continue to execute this step. If yes, proceed to the next step.

[0058] 3) When the rising edge of the control character POS marks the R channel data as ready, if POS is high and the G and B data are ready, it indicates that the data of the three channels are synchronized; otherwise, proceed to the next step.

[0059] 4) Close the read operation. First, cache the prepared channel data and check if the G and B channel data are ready. If not, continue this step; otherwise, continue to step 2.

[0060] Follow the steps above until the data from all three channels is synchronized.

[0061] The function of the video de-jitter reconstruction module is as follows: After TMDS decoding by the FPGA, the line signal HS, field signal VS, data valid signal DE, and video data DATA are processed for video de-jitter and timing establishment. The specific processing is as follows:

[0062] (1) First, the resolution of the horizontal signal HS and the vertical signal VS is detected. According to the VESA standard, the corresponding timing information is output according to the different resolutions, such as vertical front shoulder, vertical active, horizontal front shoulder, horizontal active, etc.

[0063] (2) Two dual-port RAMs are used to store video data in a ping-pong manner. To meet the maximum resolution of 1920*1080, the RAM size is set to 4Kb. The first-level RAM stores the odd-numbered lines of video data for each frame, and the second-level RAM stores the even-numbered lines of video data for each frame. The write enable of the RAM is the data valid signal DE1 output by the video decoding module. At the same time, the high-level time of the data valid signal DE is judged. When the high-level time does not match the line valid time corresponding to the resolution, the line data is considered to be wrong, and the error mark DE-ERR is output.

[0064] (3) Based on the aforementioned resolution detection results, delay by 1 line to generate a line signal HS2, a field signal VS2, and a data valid signal DE2 that conform to the VESA standard. Based on the aforementioned error identifier DE-ERR, determine whether to read the data in the first-level RAM or the second-level RAM. For example, if a DE valid time error occurs in the current third line of data, the data in the second-level RAM, i.e. the second line, should be read to fill the data in the third line.

[0065] The video stabilization achieved through the above method can avoid problems such as incorrect high and low level timings or incorrect number of signal edges caused by poor video signal quality, which can lead to video flickering.

[0066] The function of the video framing module is to perform video framing by combining the field signal (VS), valid data signal (DE), resolution information, etc., after the initial processing of video decoding and de-jitter.

[0067] During video framing, an asynchronous FIFO is used to solve the cross-clock domain problem. The write clock of the video framing module FIFO is the video pixel clock, and the read clock is the user clock of the high-speed serial transceiver GTX.

[0068] During video framing, because the RGB video data contains the value 8'hff, the RGB video data is processed. For example, when 8'hff appears in the red video data (RED), it is replaced with 8'hfe. Similarly, in the blue and green video data, 8'hff in the video data is replaced with 8'hfe. This ensures that there is no 8'hff in the RGB data, that is, 8'hff is used as a special identifier.

[0069] The specific processing of video framing is as follows:

[0070] When the rising edge of the valid data signal DE is detected, the FIFO write enable is turned on, and a fixed identifier 24'hff0000 is written; when the falling edge of the valid field signal VS is detected, the FIFO write enable is turned on, and a fixed identifier 24'h00ff00 is written; when the count of the valid field signal VS being low is equal to 10, the FIFO write enable is turned on, and a fixed identifier {resolution information, 8'hff} containing resolution information is written; when the high level of the valid data signal DE is detected, the FIFO write enable is turned on, and video data is written; at other times, the FIFO write enable is turned off; when the FIFO is not empty, the read enable is turned on, and the read 24-bit data is put into the GTX transmission data; when the FIFO is empty, the GTX transmission data is fixed to send the K code identifier, which is fixed to K28.5 in this example.

[0071] To conserve bandwidth of the high-speed serial transceiver GTX, only 24 bits are used for video data transmission. In this embodiment, the GTX selects a line rate of 6.25Gbps, an 8B / 10B encoding method, and a synchronization code of K28.5. The bit width before encoding is 32 bits, and the bit width after encoding is 40 bits. Based on this, the GTX user clock is calculated to be 156.25MHz, which is greater than the 148.5MHz pixel clock of 1080P. Since video transmission only occupies 24 bits, the remaining 8 bits can be used for user transmission of other signals, effectively improving bandwidth utilization.

[0072] The receiver's functional modules include: video frame decoding module, dynamic clock reconfiguration module, video timing reconstruction module, and video encoding module.

[0073] During the video frame decoding process, an asynchronous FIFO is also used to solve the cross-clock domain problem. The write clock of the FIFO in the video frame decoding module is the user clock of the high-speed serial transceiver GTX, and the read clock is the pixel clock multiplied by the local crystal oscillator.

[0074] The specific processing steps of the video frame decoding module are as follows:

[0075] According to the video framing architecture of the transmitter, when 8'hff appears in the lower 8 bits of the parallel data stream converted by the high-speed serial transceiver GTX at the receiver, the video resolution information is parsed out; when the K28.5 synchronization code is detected in the GTX parallel data stream, the FIFO write enable is turned off, otherwise the write enable is turned on and video data is written.

[0076] To ensure the continuity of video data read from the FIFO, the video data needs to be buffered. When the FIFO's readable data is greater than the number of valid lines, the FIFO read enable is turned on, and the valid line information can be obtained from the resolution information analyzed above. If the data read from the FIFO is 24'h00ff00, it indicates that a falling edge of the field valid signal has been detected, and the output field valid signal and data valid signal are set low, and the FIFO read enable is turned off. If the data read from the FIFO is 24'hff0000, it indicates that a rising edge of the data valid signal has been detected, and the field valid signal is set high. At the same time, the FIFO's readable data is checked. If it is greater than the number of valid lines, the FIFO read enable is turned on, and the data valid signal is set high; otherwise, the FIFO read enable is turned off, and the data valid signal is set low.

[0077] Since the FIFO only buffers valid video during video framing at the transmitting end, even if there is a frequency offset between the pixel clock at the receiving end and the pixel clock at the transmitting end, it will not cause the FIFO to be full and result in data loss.

[0078] After the video frame decoding process described above, the dynamic clock reconfiguration module calls the clock IP core and selects DynamicReconfig. It then configures the clock parameters according to the timing relationship of the DRP (Dynamic Reconfigurable Processor) and dynamically multiplies the frequency to achieve the required pixel clock based on different resolutions.

[0079] The processing flow of the video temporal reconstruction module is as follows:

[0080] (1) When the rising edge of the field valid signal output by the aforementioned frame deframe module is detected, the field enable is set high; when the falling edge of the field valid signal is detected, the field enable is set low; when the high level of the field valid signal is not detected for more than one frame, the field enable is set low.

[0081] (2) When the field enable is high and the data valid signal output by the aforementioned frame deframe module is high, the video data output by the aforementioned frame deframe module is sent into the synchronization FIFO;

[0082] (3) When the rising edge of the field valid signal output by the aforementioned frame de-framing module is detected, the VESA standard timing signal at the current resolution is generated after a delay of 1 line, and the line, field and data valid signals are generated. The data valid signal is used as the read enable of the synchronous FIFO, and the read data is the valid video data.

[0083] The video encoding module functions as follows: it encodes the field signal, line signal, and valid data signal output by the video timing reconstruction module into TMDS according to the HDMI protocol, and performs a 10:1 parallel-to-serial conversion on the encoded 10-bit data; it uses two OSERDES2 primitives cascaded together with the sampling mode set to DDR; and outputs a high-speed TMDS differential signal to the HDMI connector after conversion.

[0084] In addition, the FPGA obtains the communication status of the optical link in three ways. When an optical path anomaly is detected, it outputs a scrolling color bar at the current resolution to inform the user of the current optical path status:

[0085] Method 1: The IIC interface acquires the received optical power of the optical module in real time. When the received optical power is less than the set threshold, the optical path communication is considered abnormal.

[0086] Method 2: 8B / 10B encoding / decoding DC balanced signal and polarity signal error indication for the high-speed serializer GTX;

[0087] Method 3: Check the K28.5 synchronization code every 10ms. If it is not detected, the optical path is abnormal.

[0088] Based on the above transmission scheme, the transmission delay is calculated as follows: According to the video transmission data stream, the delay at the transmitting end after the video de-jitter timing reconstruction module reads 1 line of RAM data + the receiving end video frame decoding module stores 1 line of FIFO data + the video timing reconstruction module delays 1 line of FIFO data reading + other logic processing delays (estimated at 1 line) = 4 lines. The delay is calculated to be approximately 30μs at the maximum resolution of 1080P and approximately 76μs at the minimum resolution of 640*480@60Hz. It can be seen that the transmission delay is very small, which is very suitable for low-latency solutions in the field of real-time tracking.

[0089] This embodiment uses an FPGA to transmit video signals in a simple and reliable frame structure. At the video transmitting end, a frame architecture with a unique frame type identifier, including field tail information code, DE header information code, and resolution information code, is designed. Only video data when DE is valid is transmitted, improving bandwidth utilization and communication transmission reliability. At the video recovery end, based on the resolution information code, the required clock frequency is multiplied using a local crystal oscillator to deframe and recover the field and DE signals of the video. Then, based on the resolution information, the video is reconstructed in time to recover stable line, field, and DE signals.

[0090] The HDMI video optical transmission equipment and transmission method using the above transmission architecture have the following characteristics:

[0091] (1) Supports real-time transmission of HDMI video at 1080P@60Hz and below, based on dynamic reconfiguration clock to adapt to different display devices and thus has resolution adaptive characteristics;

[0092] (2) The logic resources of FPGA are used to decode and encode video signals, replacing professional encoding and decoding chips. The whole solution only has power chip, FPGA chip and optical module core chip. The panel interface is simple and easy to use. The structural size can be 65mm*65mm. The hardware cost is controlled at around 100 yuan, which is convenient for field operations and commercial promotion.

[0093] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A low-cost HDMI video optical transmission device based on FPGA, characterized in that, Both the transmitter and receiver of the optical transmission device employ FPGA chips. The transmitter includes a video decoding module, a video de-jitter reconstruction module, a video framing module, a high-speed serial transceiver (GTX), and a high-speed optical module. The receiver includes a high-speed optical module, a high-speed serial transceiver (GTX), a video deframe module, a dynamic clock reconfiguration module, a video timing reconstruction module, and a video encoding module. The transmitter and receiver are connected via optical fiber communication. The video framing module is used to frame valid video data into data frames for transmission and to set frame identifiers in the data frames. The video deframe module is used to deframe the data frames to extract video data based on the frame identifiers. The video framing module and the video deframing module adopt asynchronous FIFO. The write clock of the video framing module FIFO is the video pixel clock, and the read clock is the user clock of the high-speed serial transceiver GTX. The write clock of the video deframing module FIFO is the user clock of the high-speed serial transceiver GTX, and the read clock is the pixel clock multiplied by the local crystal oscillator. The dynamic clock reconfiguration module calls the clock IP core, configures the clock parameters according to the timing relationship of DRP, and dynamically multiplies the frequency according to different resolutions to achieve the required pixel clock. The video framing module performs the following specific processing for framing the video: When the rising edge of the valid data signal DE and the falling edge of the valid field signal VS are detected, the FIFO write enable is turned on and the corresponding fixed identifier is written; when the count of the valid field signal VS being low reaches the set value, the FIFO write enable is turned on and data containing resolution information and fixed identifier is written; when the high level of the valid data signal DE is detected, the FIFO write enable is turned on and video data is written. At other times, the FIFO write enable is off; when the FIFO is not empty, the read enable is on, and the read data of a predetermined length is put into the GTX transmission data. When the FIFO is empty, the GTX transmission data is always sent with a K-code identifier.

2. The low-cost HDMI video optical transmission device based on FPGA according to claim 1, characterized in that, The video decoding module deserializes and aligns the serial data from HDMI, and performs data channel synchronization processing on the three differential data sets of HDMI RGB. After synchronization, the data is output according to the decoding rules of the HDMI protocol, including the horizontal signal HS, the vertical signal VS, the data valid signal DE, and the video data DATA.

3. The low-cost HDMI video optical transmission device based on FPGA according to claim 1, characterized in that, The video de-jitter reconstruction module performs video de-jitter and timing establishment on the line signal HS, field signal VS, data valid signal DE, and video data DATA after FPGA decoding through de-jitter filtering and image buffering.

4. The low-cost HDMI video optical transmission device based on FPGA according to claim 1, characterized in that, The data frames output by the video framing module contain end-of-field information code, DE header information code, and resolution information code.

5. A low-cost HDMI video optical transmission device based on FPGA according to claim 1, characterized in that, The video encoding module encodes the field signal, line signal, and valid data signal output by the video timing reconstruction module into TMDS according to the HDMI protocol. The encoded data is then converted from parallel to serial, and the converted TMDS high-speed differential signal is output to the HDMI connector.

6. A low-cost HDMI video optical transmission method based on FPGA, characterized in that, An HDMI video signal is introduced at the transmitting end. After video decoding, jitter reduction and reconstruction, and frame assembly processing are performed by an FPGA, a high-speed serial transceiver GTX is used to convert the data from parallel to serial, and then connected to a high-speed optical module to complete the electro-optical conversion. The signal is then connected to the receiving end through an optical interface and optical fiber. The receiving end sends the optical signal to the high-speed optical module, and then to the high-speed serial transceiver GTX. The high-speed serial data stream is converted into a parallel data stream, and after video frame de-framing, dynamic clock reconfiguration, video timing reconstruction and video encoding processing by the FPGA, the HDMI video signal is output. During video framing and deframing, an asynchronous FIFO is used to solve the cross-clock domain problem. During framing, the FIFO's write clock is the video pixel clock, and the read clock is the user clock of the high-speed serial transceiver GTX. During deframing, the FIFO's write clock is the user clock of the high-speed serial transceiver GTX, and the read clock is the pixel clock multiplied by the local crystal oscillator. The specific processing steps for framing the video are as follows: When the rising edge of the valid data signal DE and the falling edge of the valid field signal VS are detected, the FIFO write enable is turned on and the corresponding fixed identifier is written; when the count of the valid field signal VS being low reaches the set value, the FIFO write enable is turned on and data containing resolution information and fixed identifier is written; when the high level of the valid data signal DE is detected, the FIFO write enable is turned on and video data is written. At other times, the FIFO write enable is off; when the FIFO is not empty, the read enable is on, and the read data of a predetermined length is put into the GTX transmission data. When the FIFO is empty, the GTX transmission data is always sent with a K-code identifier. The specific processing steps for video frame decoding are as follows: According to the video framing architecture of the transmitting end, when a fixed identifier of resolution information appears in the parallel data stream converted by the high-speed serial transceiver GTX at the receiving end, the video resolution information is parsed out, and the required clock frequency is multiplied by the local crystal oscillator according to different resolution information. When a K-code identifier is detected in the GTX parallel data stream, the FIFO write enable is turned off; otherwise, the write enable is turned on, and video data is written.

7. The low-cost HDMI video optical transmission method based on FPGA according to claim 6, characterized in that, The video decoding process is as follows: The serial data from the HDMI is deserialized to obtain the correct data. According to the HDMI protocol, control characters are transmitted regularly when the device is idle. Byte alignment is achieved by determining whether the control characters are received stably. After byte alignment, the three sets of differential data of the HDMI RGB are synchronized. After synchronization is complete, the data is output according to the decoding rules of the HDMI protocol, including horizontal signal HS, vertical signal VS, data valid signal DE, and video data DATA.

8. The low-cost HDMI video optical transmission method based on FPGA according to claim 7, characterized in that, The specific process of de-shaking and reconstructing the video is as follows: First, the resolution of the horizontal signal HS and the vertical signal VS is detected, and the corresponding timing information is output according to the different resolutions based on the VESA standard. Use two dual-port RAMs to store video data in a ping-pong configuration. The first-level RAM stores the odd-numbered lines of video data for each frame, and the second-level RAM stores the even-numbered lines of video data for each frame. The data valid signal DE output by the video decoder is used as the write enable for the RAM. During the process, the high-level time of the data valid signal DE is judged. When the high-level time does not match the line valid time corresponding to the resolution, the line data is considered to be incorrect, and the error mark DE-ERR is output. Based on the aforementioned resolution detection results, a VESA-compliant line signal HS2, field signal VS2, and data valid signal DE2 are generated after a 1-line delay. The RAM to be read is selected based on the aforementioned error identifier DE-ERR, and the data of the erroneous line is filled by reading the data of the previous line.

9. A low-cost HDMI video optical transmission method based on FPGA according to claim 6, characterized in that, During the video frame assembly process, 8'hff in the video data is replaced with 8'hfe, and 8'hff is used as a fixed identifier for resolution information.

10. A low-cost HDMI video optical transmission method based on FPGA according to claim 6, characterized in that, During video frame decoding, line validity information is obtained based on the parsed resolution information. When the FIFO's readable data is greater than the number of valid lines, the FIFO read enable is turned on. If the data read from the FIFO is 24'h00ff00, it indicates that a falling edge of the field valid signal has been detected, and the output field valid signal and data valid signal are set low, while the FIFO read enable is turned off. If the data read from the FIFO is 24'hff0000, it indicates that a rising edge of the data valid signal has been detected, and the field valid signal is set high. Then, the FIFO's readable data is checked again. If it is greater than the number of valid lines, the FIFO read enable is turned on, and the data valid signal is set high; otherwise, the FIFO read enable is turned off, and the data valid signal is set low.

11. The low-cost HDMI video optical transmission method based on FPGA according to claim 7, characterized in that, The processing for video temporal reconstruction is as follows: When the rising edge of the field valid signal in the deframed data is detected, the field enable is set high; when the falling edge of the field valid signal is detected, the field enable is set low; when no high level of the field valid signal is detected for more than one frame, the field enable is set low. When the field enable level is high and the valid data signal in the deframed data is high, the deframed video data is sent to the synchronization FIFO; When the rising edge of the field valid signal in the deframed data is detected, the VESA standard timing signal at that resolution is generated after a delay of 1 line, based on the current resolution. The line, field, and data valid signals are then used as the read enable of the synchronization FIFO, and the read data is the valid video data.

12. The low-cost HDMI video optical transmission method based on FPGA according to claim 7, characterized in that, In the optical transmission method, the FPGA obtains the communication status of the optical path in the following three ways: Method 1: The IIC interface acquires the received optical power of the optical module in real time. When the received optical power is less than the set threshold, the optical path communication is considered abnormal. Method 2: 8B / 10B encoding / decoding DC balanced signal and polarity signal error indication of the high-speed serializer GTX; Method 3: Check the K28.5 synchronization code every 10ms; if it is not detected, the optical path communication is abnormal. When an optical path communication anomaly is detected, a scrolling color bar at the current resolution is output to inform the user of the current optical path status.

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