Electroplating method of circuit board structure

Abstract

The invention discloses an electroplating method of a circuit board structure. The electroplating method of the circuit board structure comprises the following steps: a preposition step: providing a substrate with a plurality of bases formed on the surface, and defining a circuit area and a connecting area extending from one side of the circuit area on each base; a copper plating step of forming a copper plating layer on the substrate; a shielding film covering step: covering the copper plating layer with a shielding film, and exposing the copper plating layer in the plurality of circuit areas from the shielding film; a first micro-etching step: carrying out micro-etching on the substrate so as to remove the copper plating layer in the plurality of circuit areas; a gold plating step: plating a plurality of gold plating layers on the plurality of circuit areas; and a second microetching step, and performing micro-etching on the substrate to remove the chemical copper layer so as to form the circuit board structure. According to the electroplating method of the circuit board structure, the problem that an existing electroplating method of the circuit board structure is insufficient in precision is solved.

Description

Technical Field

[0001] The invention relates to an electroplating method for a circuit board, in particular to an electroplating method for a circuit board structure. Background Art

[0002] The existing electroplating method of circuit board structure has the problem of insufficient precision. Summary of the invention

[0003] The invention discloses an electroplating method for a circuit board structure, so as to effectively improve the problem of insufficient precision in the existing electroplating method for a circuit board structure.

[0004] One of the embodiments of the present invention discloses a method for electroplating a circuit board structure, which includes: a pre-step of providing a substrate, a plurality of bases formed on a surface of the substrate, and each base defines a circuit area and a connection area extending from one side of the circuit area; a copper plating step of forming a copper plating layer on the substrate by copper plating; a masking film covering step of covering the copper plating layer on the substrate with a masking film, the masking film having a plurality of openings, and the copper plating layer located in a plurality of circuit areas of a plurality of bases is exposed from the plurality of openings; a first micro-etching step of micro-etching the substrate covered with the masking film to remove the copper plating layer located in the plurality of circuit areas and exposed from the openings; a gold plating step of plating a plurality of gold-plated layers on a plurality of circuit areas of a plurality of bases; and a second micro-etching step of micro-etching the substrate to remove the copper plating layer on the substrate, thereby forming a circuit board structure.

[0005] Optionally, in the copper plating step, the thickness of the copper plating layer is between 5 micro inches and 20 micro inches.

[0006] Optionally, in the first micro-etching step, the substrate is micro-etched with a first micro-etching solution, and the first micro-etching solution contains 5 g / L to 35 g / L sulfuric acid.

[0007] Optionally, in the second micro-etching step, the substrate is micro-etched with a second micro-etching solution, and the second micro-etching solution contains 55 g / L to 105 g / L of sodium persulfate.

[0008] Optionally, a gold-plated layer thickness of each gold-plated layer is between 15 micro-inches and 40 micro-inches.

[0009] Optionally, the length of each base is between 2.8 inches and 3.2 inches, and the width of each base is between 1.05 inches and 1.65 inches.

[0010] Optionally, the surface of the circuit area of ​​each base is rectangular, each connection area is a wide side protruding from the circuit area, and the surface of each connection area is trapezoidal.

[0011] Optionally, in each base, a first length of the circuit area is greater than a second length of the connection area, and a first width of the circuit area is greater than a second width of the connection area.

[0012] Optionally, the first length of the line area is between 2.8 inches and 3.2 inches, the first width of the line area is between 0.75 inches and 1.05 inches, the second length of the connecting area is between 0.8 inches and 1.2 inches, and the second width of the connecting area is between 0.3 inches and 0.6 inches.

[0013] Optionally, after the second micro-etching step, there is no copper layer on the circuit board structure.

[0014] In summary, the electroplating method of the circuit board structure provided by the present invention can effectively improve the problem of insufficient precision in the existing electroplating method of the circuit board structure through the technical solution of "the copper plating step, forming the copper plating layer on the substrate by copper plating; the masking film covering step, covering the copper plating layer on the substrate with the masking film, the masking film having a plurality of windows, and the copper plating layer located in the plurality of circuit areas of the plurality of bases is exposed from the plurality of windows; the first micro-etching step, micro-etching the substrate covered with the masking film to remove the copper plating layer located in the plurality of circuit areas and exposed from the windows; the gold plating step, plating a plurality of gold-plated layers in the plurality of circuit areas of the plurality of bases".

[0015] To further understand the features and technical contents of the present invention, please refer to the following detailed description and drawings of the present invention. However, such description and drawings are only used to illustrate the present invention and are not intended to limit the protection scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 For the present invention Figure 1 The figure is a flow chart of the electroplating method of the circuit board structure according to the embodiment of the present invention.

[0017] Figure 2 Schematic diagram of the pre-steps of the electroplating method for a circuit board structure according to an embodiment of the present invention.

[0018] Figure 3 It is a schematic diagram of the copper plating step of the electroplating method of the circuit board structure according to an embodiment of the present invention.

[0019] Figure 4 It is a schematic diagram of a masking film covering step of an electroplating method for a circuit board structure according to an embodiment of the present invention.

[0020] Figure 5 FIG. 4 is a schematic diagram of a first micro-etching step of an electroplating method for a circuit board structure according to an embodiment of the present invention.

[0021] Figure 6 It is a schematic diagram of the gold plating step of the electroplating method of the circuit board structure according to an embodiment of the present invention.

[0022] Figure 7 FIG. 4 is a schematic diagram of a second micro-etching step of the electroplating method for a circuit board structure according to an embodiment of the present invention.

[0023] Figure 8 FIG. 4 is a three-dimensional schematic diagram of a circuit board structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0024] The following is an explanation of the implementation method of the "electroplating method of circuit board structure" disclosed in the present invention through specific embodiments. Those skilled in the art can understand the advantages and effects of the present invention from the contents disclosed in this specification. The present invention can be implemented or applied through other different specific embodiments, and the details in this specification can also be modified and changed based on different viewpoints and applications without departing from the concept of the present invention. In addition, the drawings of the present invention are only simple schematic illustrations and are not depicted according to actual dimensions. It is stated in advance. The following implementation methods will further explain the relevant technical contents of the present invention in detail, but the disclosed contents are not intended to limit the scope of protection of the present invention.

[0025] It should be understood that, although the terms "first", "second", "third", etc. may be used herein to describe various components or signals, these components or signals should not be limited by these terms. These terms are mainly used to distinguish one component from another component, or one signal from another signal. In addition, the term "or" used herein may include any one or more combinations of the associated listed items depending on the actual situation.

[0026] [Plating method for circuit board structure]

[0027] See also Figure 1 As shown, Figure 1 Flow chart of the electroplating method of the circuit board structure of the embodiment of the present invention. The first embodiment of the present invention provides an electroplating method of a circuit board structure. The electroplating method of the circuit board structure may include a pre-step S110, a copper plating step S120, a masking film covering step S130, a first micro-etching step S140, a gold plating step S150 and a second micro-etching step S160. Of course, the electroplating method of the circuit board structure may also include other steps according to the requirements, and the present invention is not limited thereto.

[0028] See also Figure 2 As shown, Figure 2The schematic diagram of the pre-processing step of the electroplating method of the circuit board structure of the embodiment of the present invention is shown in FIG. In the pre-processing step S110, a substrate 1 is provided, a plurality of bases 11 are formed on a surface of the substrate 1, and each of the bases 11 defines a circuit area 11a and a connection area 11b extending from one side of the circuit area.

[0029] In this embodiment, the length of each base 11 is between 2.8 inches and 3.2 inches, and the width of each base 11 is between 1.05 inches and 1.65 inches, but the length and width of each base 11 can be changed according to needs, and the present invention is not limited thereto. In addition, the length and width referred to herein can be regarded as the maximum length and maximum width of each base 11.

[0030] In addition, in this embodiment, the surface of the circuit area 11a of each base 11 is rectangular, each connection area 11b is a wide side protruding from the circuit area 11a, and the surface of each connection area 11b is trapezoidal. More specifically, the surface of each connection area 11b is an isosceles trapezoid, but the present invention is not limited thereto.

[0031] In each of the bases 11 of this embodiment, a first length L1 of the circuit area 11a is greater than a second length L2 of the connection area 11b, and a first width W1 of the circuit area 11a is greater than a second width W2 of the connection area 11b, but the present invention is not limited thereto. Optionally, the first length L1 of the circuit area is between 2.8 inches and 3.2 inches, the first width W1 of the circuit area 11a is between 0.75 inches and 1.05 inches, the second length L2 of the connection area 11b is between 0.8 inches and 1.2 inches, and the second width W2 of the connection area 11b is between 0.3 micro inches and 0.6 inches, but the present invention is not limited thereto.

[0032] In addition, it should be noted that the first length L1 and the second length L2 respectively refer to the dimensions of the line area 11a and the connection area 11b in the length direction, the first width W1 and the second width W2 respectively refer to the dimensions of the line area 11a and the connection area 11b in the width direction, the first length L1 is the length of the base 11, and the sum of the first width W1 and the second width W2 is the width of the base 11.

[0033] See also Figure 3 As shown, Figure 3Schematic diagram of the copper plating step of the electroplating method of the circuit board structure of an embodiment of the present invention. In the copper plating step S120, a copper plating layer 2 is formed on the substrate 1 by copper plating. In the copper plating step S120 of this embodiment, the thickness of the copper plating layer 2 (not numbered in the figure) is between 5 microinches and 20 microinches. Optionally, the thickness of the copper plating layer 2 is between 10 microinches and 15 microinches. In this embodiment, the copper plating layer 2 is formed on one of the surfaces of the substrate 1 as an example, but the present invention is not limited to this. In other embodiments not shown in the present invention, the copper plating layer 2 may also be formed on both surfaces of the substrate 1 or cover the entire substrate 1.

[0034] See also Figure 4 As shown, Figure 4 The present invention is a schematic diagram of the masking film covering step of the electroplating method of the circuit board structure according to an embodiment of the present invention. In the masking film covering step S130, a masking film 3 is covered on the copper layer 2 on the substrate 1, the masking film 3 has a plurality of openings 3a, and the copper layer 2 located in the plurality of circuit areas 11a of the plurality of bases 11 is exposed from the plurality of openings 3a. Specifically, the masking film 3 may partially shield the plurality of circuit areas 11a of the plurality of bases 11, so that the copper layer 2 on each circuit area 11a is partially exposed from the masking film 3. In addition, as long as the masking film 3 has the property of being resistant to etching, the present invention does not limit the specific material of the masking film 3, and the specific appearance of the openings 3a may also vary according to demand.

[0035] See also Figure 5 As shown, Figure 5 Schematic diagram of the first micro-etching step of the electroplating method of the circuit board structure of the embodiment of the present invention. In the first micro-etching step S140, the substrate 1 covered with the masking film 3 is micro-etched to remove the copper layer 2 located in the plurality of circuit areas 11a and exposed from the opening 3a. In the first micro-etching step S140 of the present embodiment, the substrate is micro-etched with a first micro-etching solution, and the first micro-etching solution contains 5 g / L to 35 g / L of sulfuric acid, but the present invention is not limited thereto. Optionally, the first micro-etching solution contains 10 g / L to 30 g / L of sulfuric acid.

[0036] Specifically, the first micro-etching solution micro-etches the copper clad layer 2 located in the circuit area 11 a and exposed from the opening 3 a of the shielding film 3 , and the first micro-etching solution does not micro-etch the copper clad layer 2 shielded by the shielding film 3 .

[0037] See also Figure 6 As shown, Figure 6The schematic diagram of the gold plating step of the electroplating method of the circuit board structure of the embodiment of the present invention. In the gold plating step S150, multiple gold plating layers 4 are plated on the multiple circuit areas 11a of the multiple bases 11. It is worth mentioning that after the first micro-etching step S140, the position of the substrate 1 corresponding to the window 3a of the shielding film 3 is not formed with the copper layer 2, and in the gold plating step S150, the substrate 1 exposed from the window 3a is directly electroplated, so as to form the gold plating layer 4 directly on the circuit area 11a of the substrate 1. In other words, the gold plating layer 4 is directly formed on the circuit area 11a of the substrate 1, and the copper layer 2 is not formed between the gold plating layer 4 and the substrate 1. Therefore, in the gold plating step S150, electroplating can be accurately performed on a specific area of ​​a base with a specific shape.

[0038] In the gold plating step S150 of the present embodiment, a gold plating layer thickness T of each of the gold plating layers 4 is between 15 micro-inches and 40 micro-inches. However, the gold plating layer thickness T of the gold plating layer 4 may vary according to actual needs, and the present invention is not limited thereto. Optionally, the gold plating layer thickness T of each of the gold plating layers 4 is between 20 micro-inches and 35 micro-inches. In addition, in the present embodiment, the surface of each of the gold plating layers 4 may be circular, and the diameter D of the surface of each of the gold plating layers 4 may be between 20,000 micro-inches and 24,000 micro-inches, but the present invention is not limited thereto.

[0039] See also Figure 7 As shown, Figure 7 FIG. 1 is a schematic diagram of the second micro-etching step of the electroplating method for a circuit board structure according to an embodiment of the present invention. In the second micro-etching step S160, the substrate 1 is micro-etched to remove the copper layer 2 on the substrate, thereby forming a circuit board structure 100 (such as Figure 8 It is worth mentioning that after the second micro-etching step S160, the circuit board structure 100 may not have the copper plating layer 2. In addition, before the second micro-etching step S160, the masking film 3 may be removed first.

[0040] In the second micro-etching step S160 of the present embodiment, the substrate 1 is micro-etched with a second micro-etching solution, and the second micro-etching solution contains 55 g / L to 105 g / L of sodium persulfate, but the present invention is not limited thereto. Optionally, the second micro-etching solution contains 60 g / L to 100 g / L of sodium persulfate. It should be noted that in the first micro-etching step S140 and the second micro-etching step S160, the copper layer 2 located in the circuit area 11a and the copper layer 2 in other areas are removed by etching, so the composition of the first micro-etching solution is different from that of the second micro-etching solution.

[0041] In addition, in each of the bases 11, the circuit area 11a formed with the gold-plated layer 4 can be used for setting related chips thereon, and the connection area 11b can be used to connect with the spring of the connector, and the circuit board structure 100 can be used to manufacture a low power compression attached memory module (Low Power Compression Attached Memory Module, LPCAMM), but the present invention is not limited thereto.

[0042] [PCB structure]

[0043] See also Figure 8 As shown, Figure 8 The embodiment of the present invention further provides a circuit board structure 100. The circuit board structure 100 can be obtained by the aforementioned manufacturing method of the circuit board structure, but the present invention is not limited thereto.

[0044] The circuit board structure 100 includes a substrate 1 and a plurality of gold-plated layers 4. The substrate 1 includes a plurality of bases 11 formed on a surface of the substrate 1. Each of the bases 11 defines a circuit region 11a and a connection region 11b extending from one side of the circuit region 11a.

[0045] The length of each of the bases 11 is between 2.8 inches and 3.2 inches, and the width of each of the bases 11 is between 1.05 inches and 1.65 inches.

[0046] The surface of the circuit area 11 a of each of the bases 11 is rectangular, each of the connection areas 11 b is a wide side protruding from the circuit area 11 a , and the surface of each of the connection areas 11 b is trapezoidal.

[0047] In each of the bases 11 , a first length L1 of the circuit region 11 a is greater than a second length L2 of the connection region 11 b , and a first width W1 of the circuit region 11 a is greater than a second width W2 of the connection region 11 b .

[0048] The first length L1 of the line area 11a is between 2.8 inches and 3.2 inches, the first width W1 of the line area 11a is between 0.75 inches and 1.05 inches, the second length L2 of the connection area 11b is between 0.8 inches and 1.2 inches, and the second width W2 of the connection area 11b is between 0.3 inches and 0.6 inches.

[0049] No copper layer is formed on the circuit board structure 100. The plurality of gold-plated layers 4 are formed on the plurality of circuit regions 11a of the plurality of bases 11. The thickness T of each of the gold-plated layers 4 is between 15 micro-inches and 40 micro-inches.

[0050] [Beneficial Effects of Embodiments]

[0051] One of the beneficial effects of the present invention is that the electroplating method of the circuit board structure provided by the present invention can effectively improve the existing electroplating method of the circuit board structure through the technical scheme of "the copper plating step, forming the copper plating layer on the substrate by copper plating; the masking film covering step, covering the copper plating layer on the substrate with the masking film, the masking film having a plurality of windows, and the copper plating layer located in the plurality of circuit areas of the plurality of bases is exposed from the plurality of windows; the first micro-etching step, micro-etching the substrate covered with the masking film to remove the copper plating layer located in the plurality of circuit areas and exposed from the windows; the gold plating step, plating a plurality of gold-plated layers in the plurality of circuit areas of the plurality of bases". If the shape of the base is relatively irregular, it is easy to have the problem of difficulty in accurately electroplating the gold-plated layer on the base.

[0052] The above descriptions are only optional feasible embodiments of the present invention, and are not intended to limit the patent scope of the present invention. Therefore, all equivalent technical changes made using the contents of the specification and drawings of the present invention are included in the protection scope of the present invention.

Claims

1. A method for electroplating a circuit board structure, characterized in that: The electroplating method of the circuit board structure comprises: A pre-step, providing a substrate, a surface of the substrate is formed with a plurality of bases, and each of the bases is defined with a circuit area and a connection area extending from one side of the circuit area; a copper plating step, forming a copper plating layer on the substrate by copper plating; a masking film covering step, covering the copper layer on the substrate with a masking film, wherein the masking film has a plurality of openings, and the copper layer located in the plurality of circuit regions of the plurality of bases is exposed from the plurality of openings; A first micro-etching step is to micro-etch the substrate covered with the masking film to remove the copper layer located in the plurality of circuit regions and exposed from the openings; a gold plating step, plating a plurality of gold plating layers on a plurality of the circuit regions of a plurality of the bases; as well as A second micro-etching step is performed to micro-etch the substrate to remove the copper layer on the substrate, thereby forming a circuit board structure.

2. The electroplating method of a circuit board structure according to claim 1, characterized in that: In the copper plating step, the thickness of the copper plating layer is between 5 micro inches and 20 micro inches.

3. The electroplating method of a circuit board structure according to claim 1, characterized in that: In the first micro-etching step, the substrate is micro-etched with a first micro-etching solution, and the first micro-etching solution contains 5 g / L to 35 g / L of sulfuric acid.

4. The electroplating method of a circuit board structure according to claim 1, characterized in that: In the second micro-etching step, the substrate is micro-etched with a second micro-etching solution, and the second micro-etching solution contains 55 g / L to 105 g / L of sodium persulfate.

5. The electroplating method of a circuit board structure according to claim 1, characterized in that: The thickness of each gold-plated layer is between 15 micro-inches and 40 micro-inches.

6. The electroplating method of a circuit board structure according to claim 1, characterized in that: The length of each of the bases is between 2.8 inches and 3.2 inches, and the width of each of the bases is between 1.05 inches and 1.65 inches.

7. The electroplating method of a circuit board structure according to claim 1, characterized in that: The surface of the circuit area of ​​each of the bases is rectangular, each of the connection areas is a wide side protruding from the circuit area, and the surface of each of the connection areas is trapezoidal.

8. The electroplating method of a circuit board structure according to claim 1, characterized in that: In each of the bases, a first length of the circuit region is greater than a second length of the connection region, and a first width of the circuit region is greater than a second width of the connection region.

9. The electroplating method of a circuit board structure according to claim 8, characterized in that: The first length of the line area is between 2.8 inches and 3.2 inches, the first width of the line area is between 0.75 inches and 1.05 inches, the second length of the connection area is between 0.8 inches and 1.2 inches, and the second width of the connection area is between 0.3 inches and 0.6 inches.

10. The electroplating method of a circuit board structure according to claim 1, characterized in that: After the second micro-etching step, the circuit board structure does not have the copper plating layer.

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