Semiconductor structure and method of manufacturing the same

Abstract

This disclosure provides a semiconductor structure and its fabrication method, relating to the field of semiconductor technology, to solve the technical problem of high resistance in word line structures. The semiconductor structure includes a substrate and multiple word line structures. The substrate includes multiple active structures spaced apart. The multiple word line structures are spaced apart within the substrate along a first direction. Each word line structure extends along a second direction and connects to the multiple active structures arranged along the second direction. Each word line structure includes a barrier layer and a conductive layer. The barrier layer is disposed between the substrate and the conductive layer and at least covers a portion of the outer peripheral surface of the conductive layer. The thickness of the area where the bottom surfaces of the barrier layer and the conductive layer face each other is greater than the thickness of the area where the sides of the barrier layer and the conductive layer face each other. The first direction intersects the second direction. This disclosure can reduce the resistance of the word line structure and also reduce or even avoid gate-induced drain leakage current.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] With the gradual development of storage device technology, Dynamic Random Access Memory (DRAM) has been increasingly used in various electronic devices due to its high density and fast read / write speed.

[0003] Dynamic random access memory (DRAM) typically consists of multiple memory cells, each usually including a transistor and a capacitor. The capacitor stores data, while the transistor controls the reading and writing of data from the capacitor. The gate of the transistor is electrically connected to the word line (WL) of the DRAM, and the voltage across the word line controls the transistor's on / off state. One of the transistor's sources and drains is electrically connected to the bit line (BL), and the other is electrically connected to the capacitor, allowing data to be stored or output via the bit line.

[0004] However, current word line structures cannot simultaneously address both resistance and gate-induced drain leakage (GIDL). Summary of the Invention

[0005] In view of the above problems, this disclosure provides a semiconductor structure and its fabrication method to reduce the resistance of the word line structure and also reduce the gate-induced drain leakage current.

[0006] A first aspect of this disclosure provides a semiconductor structure comprising:

[0007] The substrate includes a plurality of active structures spaced apart.

[0008] A plurality of word line structures are disposed at intervals along a first direction within the substrate; each word line structure extends along a second direction and connects to a plurality of active structures arranged along the second direction; each word line structure includes a barrier layer and a conductive layer, the barrier layer being disposed between the substrate and the conductive layer and at least covering a portion of the outer peripheral surface of the conductive layer, wherein the thickness of the region opposite the bottom surface of the barrier layer and the conductive layer is greater than the thickness of the region opposite the side surface of the barrier layer and the conductive layer; the first direction intersects the second direction.

[0009] In some embodiments, the conductive layer includes a first segment and a second segment, the second segment being disposed at one end of the first segment facing the bottom surface of the substrate, and the outer surface of the second segment being arc-shaped;

[0010] The thickness of the barrier layer is the same along the direction from the top surface of the first segment to the bottom surface of the first segment;

[0011] The thickness of the barrier layer gradually increases along the direction from the top surface of the second segment to the bottom surface of the second segment.

[0012] In some embodiments, the barrier layer includes a first barrier layer and a second barrier layer;

[0013] The first barrier layer covers at least a portion of the outer peripheral surface of the conductive layer, and the second barrier layer is disposed on the first barrier layer, and the second barrier layer covers at least the outer peripheral surface of the second segment.

[0014] In some embodiments, the thickness of the second barrier layer is 1.5 to 2 times the thickness of the first barrier layer.

[0015] In some embodiments, the active structure includes an active region extending along a third direction; wherein the first direction, the second direction, and the third direction intersect.

[0016] Each of the word line structures extends along the second direction and penetrates the active region, with the bottom of the word line structure located in the active region.

[0017] In some embodiments, the active structure includes active pillars, and a plurality of the active pillars are arranged in a multi-row, multi-column array;

[0018] Each of the word line structures extends along the second direction and at least wraps around a portion of the outer peripheral surface of the active column.

[0019] In some embodiments, the top surface of the conductive layer is higher than the top surface of the barrier layer;

[0020] The semiconductor structure further includes an insulating layer disposed on the word line structure, and the insulating layer, the word line structure, and the substrate form an air gap.

[0021] A second aspect of this disclosure provides a method for fabricating a semiconductor structure, comprising:

[0022] A patterned substrate is used to form a plurality of active structures spaced apart within the substrate;

[0023] Multiple word line structures are formed within the substrate at intervals along a first direction; each word line structure extends along a second direction and connects to multiple active structures, which also extend along the second direction; each word line structure includes a barrier layer and a conductive layer, the barrier layer being disposed between the substrate and the conductive layer and at least covering a portion of the outer peripheral surface of the conductive layer, wherein the thickness of the barrier layer relative to the bottom surface of the conductive layer is greater than the thickness of the barrier layer relative to the side surface of the conductive layer; the first direction intersects the second direction.

[0024] In some embodiments, the step of forming a plurality of the word line structures includes:

[0025] A plurality of first trenches are formed, the plurality of first trenches are spaced apart along the first direction, and each first trench extends along the second direction and exposes a plurality of active structures, wherein the plurality of active structures are arranged along the second direction;

[0026] A first barrier material layer is formed, which covers the inner wall of the first trench;

[0027] A second barrier layer is formed, which covers a portion of the first barrier material layer;

[0028] A conductive material layer is formed, which fills the area enclosed by the first barrier material layer and the second barrier layer;

[0029] By removing a portion of the first barrier material layer and the conductive material layer, the remaining first barrier material layer constitutes a first barrier layer, and the first barrier layer and the second barrier layer constitute a barrier layer; the remaining conductive material layer constitutes a conductive layer.

[0030] In some embodiments, the step of forming the second barrier layer includes:

[0031] A metal layer is formed on the bottom wall and part of the sidewall of the first trench using a plasma deposition process, the metal layer covering part of the first barrier material layer; wherein, the thickness of the metal layer gradually increases along the direction from the top surface to the bottom surface.

[0032] The metal layer is nitrided using a rapid nitriding process to form a second barrier layer.

[0033] In some embodiments, the active structure includes an active pillar; the step of removing a portion of the first blocking material layer and the conductive material layer further includes,

[0034] Remove the conductive material layer located on the top surface of the substrate and a portion of the thickness located within the first trench, as well as the first barrier material layer after removing a portion of the material located within the first trench; the remaining conductive material layer constitutes an intermediate conductive material layer, and the remaining first barrier material layer constitutes a first barrier layer.

[0035] A second trench is formed within the intermediate conductive material layer, the second trench extending along a second direction and exposing the substrate; the remaining intermediate conductive material layer constitutes a conductive layer, wherein the conductive layer surrounds at least a portion of the outer peripheral surface of the active pillar.

[0036] In some embodiments, after the step of forming a plurality of the first trenches in the substrate and before the step of forming the first barrier material layer, the method further includes:

[0037] A dielectric layer is formed on the inner wall of the first trench.

[0038] In the semiconductor structure and its fabrication method provided in this disclosure, by making the thickness of the bottom area of ​​the barrier layer and the conductive layer greater than the thickness of the side area of ​​the barrier layer and the conductive layer, the thickness of the barrier layer is reduced, the area of ​​the conductive layer is increased, and the resistance of the word line structure is reduced.

[0039] Furthermore, when a voltage is applied to the word line structure, charge usually accumulates on the bottom surface of the word line structure. Therefore, by increasing the thickness of the area between the bottom surfaces of the barrier layer and the conductive layer, the resistance of the word line structure is reduced, and the gate-induced drain leakage current of the semiconductor structure is also reduced.

[0040] In addition to the technical problems solved by the embodiments of this disclosure, the technical features constituting the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions described above, other technical problems that can be solved by the semiconductor structure and its preparation method provided by the embodiments of this disclosure, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further described in detail in the specific implementation. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 Schematic diagram of the active structure and word line structure of the semiconductor structure provided in the embodiments of this disclosure Figure 1 ;

[0043] Figure 2 Schematic diagram of the active structure and word line structure of the semiconductor structure provided in the embodiments of this disclosure Figure 2 ;

[0044] Figure 3 A schematic diagram of the semiconductor structure provided in the embodiments of this disclosure. Figure 1 ;

[0045] Figure 4 A schematic diagram of the semiconductor structure provided in the embodiments of this disclosure. Figure 2 ;

[0046] Figure 5 A process flow diagram of the method for fabricating a semiconductor structure provided in this disclosure embodiment;

[0047] Figure 6 A schematic diagram illustrating the formation of a first trench in a method for fabricating a semiconductor structure according to an embodiment of this disclosure;

[0048] Figure 7 This is a schematic diagram of the formation of a dielectric layer in a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;

[0049] Figure 8 This is a schematic diagram of the formation of a first barrier material layer in a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;

[0050] Figure 9 This is a schematic diagram of the formation of a metal layer in a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;

[0051] Figure 10 A schematic diagram of the formation of a second barrier layer in a method for fabricating a semiconductor structure according to an embodiment of this disclosure;

[0052] Figure 11 A schematic diagram of the formation of a conductive material layer in a method for fabricating a semiconductor structure according to an embodiment of this disclosure;

[0053] Figure 12 A schematic diagram illustrating the removal of a portion of the conductive material layer in a method for fabricating a semiconductor structure according to an embodiment of this disclosure;

[0054] Figure 13 Schematic diagram of the formation of a conductive layer in the method for fabricating a semiconductor structure provided in this disclosure embodiment. Figure 1 ;

[0055] Figure 14 Schematic diagram of the formation of a conductive layer in the method for fabricating a semiconductor structure provided in this disclosure embodiment. Figure 2 .

[0056] Figure label:

[0057] 100: Substrate; 110: Active structure; 120: Shallow trench isolation structure; 130: First trench;

[0058] 200: Word line structure; 211: First barrier layer; 212: Second barrier layer; 213: First barrier material layer; 220: Conductive layer; 221: First segment; 222: Second segment; 223: Conductive material layer; 224: Second trench;

[0059] 300: Insulating layer; 400: Air gap; 500: Dielectric layer. Detailed Implementation

[0060] As described in the background section, semiconductor structures in related technologies suffer from a high word line resistance. The inventors have discovered that this problem arises because word line structures typically include a barrier layer and a conductive layer disposed on top of the barrier layer. The barrier layer is usually formed on the inner wall of the word line trench using atomic layer deposition (ALD), resulting in good step coverage and uniform thickness throughout. However, the resistivity of the barrier layer is greater than that of the conductive layer, increasing the resistance of the word line structure and degrading the performance of the semiconductor structure. In related technologies, the barrier layer is typically thinned to reduce its resistance; however, excessive thinning of the barrier layer increases the gate-induced drain leakage (GIDL) current in the semiconductor structure.

[0061] To address the aforementioned technical problems, this disclosure provides a semiconductor structure and its fabrication method. By making the thickness of the bottom region of the barrier layer and the conductive layer greater than the thickness of the side region of the barrier layer and the conductive layer, the thickness of the barrier layer is reduced, the area of ​​the conductive layer is increased, and the resistance of the word line structure is reduced.

[0062] Furthermore, when a voltage is applied to the word line structure, charge usually accumulates on the bottom surface of the word line structure. Therefore, by increasing the thickness of the area between the bottom surfaces of the barrier layer and the conductive layer, the resistance of the word line structure is reduced, and the gate-induced drain leakage current of the semiconductor structure is also reduced.

[0063] To make the above-mentioned objects, features, and advantages of the embodiments of this disclosure more apparent and understandable, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0064] This embodiment does not limit the semiconductor structure. The following description will take dynamic random access memory (DRAM) as an example, but this embodiment is not limited to this. Other semiconductor structures are also possible in this embodiment.

[0065] Please refer to the attached document. Figure 1 To be continued Figure 4 This disclosure provides a semiconductor structure including a substrate 100, wherein the substrate 100 serves as a support component of the semiconductor structure for supporting other components disposed thereon. The substrate 100 is a semiconductor substrate, such as a silicon substrate, germanium substrate, silicon carbide (SiC) substrate, silicon germanide (SiGe) substrate, or silicon on insulator (SOI) substrate.

[0066] The substrate 100 includes a plurality of active structures 110, which are spaced apart within the substrate 100. The shape of the active structures 110 can be implemented in various ways. For example, please refer to the appendix. Figure 1 The active structure 110 includes active regions. Multiple active regions are spaced apart within the substrate 100, each extending along a third direction and tilted relative to the horizontal direction. That is, the third direction, the first direction, and the second direction intersect each other. The first direction is an adjacent direction... Figure 1 The X direction is in the middle; the second direction is the auxiliary direction. Figure 1 The Y-direction is in the middle; the third direction is attached. Figure 1 The M direction in the diagram. For another example, please refer to the appendix. Figure 2 The active structure 110 includes active pillars, and multiple active pillars are arranged in a multi-row, multi-column array within the substrate 100. The extension direction of each active pillar is perpendicular to the substrate 100, that is, the height direction of each active pillar is perpendicular to the substrate 100.

[0067] The semiconductor structure also includes multiple word line structures 200; please refer to the appendix for further details. Figure 1 and attached Figure 2 Multiple word line structures 200 are spaced apart within the substrate 100 along a first direction. Each word line structure 200 extends along a second direction and connects to multiple active structures 110 arranged along the second direction. That is, each word line structure 200 connects to active structures 110 located in the same second direction. The first direction intersects the second direction.

[0068] It should be noted that the portion of the active structure 110 used to form the transistor, for example, forms the source region, drain region, and channel region between the source and drain regions of the transistor; wherein, the portion of the word line structure 200 opposite to the channel region of the active structure 110 forms the gate of the transistor. Thus, when a voltage is supplied to each word line structure 200, the word line structure 200 can control multiple transistors arranged along the second direction to simultaneously turn on or off, achieving the advantage of increased integration of the semiconductor structure and facilitating the development of semiconductor structures towards smaller sizes.

[0069] When the active structure 110 includes an active region, each word line structure 200 extends along the second direction and penetrates the active region, with the bottom of the word line structure 200 located within the active region. That is, the portion of the word line structure 200 opposite to the active region has its bottom located within the active region, making the formed gate a buried gate, and consequently, the formed transistor a buried transistor. This extends the channel length, reduces the threshold voltage of the semiconductor structure, reduces short-channel effects, and improves the stability of the semiconductor structure. Furthermore, compared to a planar gate structure, the gate structure can be disposed within the substrate 100, thus reducing the size of the semiconductor structure and increasing its integration density.

[0070] When the active structure 110 includes an active pillar, each word line structure 200 extends along a second direction and at least covers a portion of the outer peripheral surface of the active pillar. Along the extension direction of the active pillar, i.e., along a direction perpendicular to the substrate 100, the active pillar includes a channel region and source and drain regions located on opposite sides of the channel region. Each word line structure 200 extends along the second direction and at least covers a portion of the outer peripheral surface of the channel region of the active pillar. In one example, the word line structure 200 covers the entire outer peripheral surface of the channel regions of multiple active pillars arranged along the second direction, such that the formed transistor is a full-ring gate transistor. In another example, the word line structure 200 covers a portion of the outer peripheral surface of the channel regions of multiple active pillars arranged along the second direction, such that the formed transistor is a half-ring gate transistor.

[0071] Please refer to the attached document. Figure 3 and attached Figure 4 Each word line structure 200 includes a barrier layer 210 and a conductive layer 220. The barrier layer 210 is disposed between the substrate 100 and the conductive layer 220 and at least covers a portion of the outer peripheral surface of the conductive layer 220. The thickness of the bottom surface of the barrier layer 210 and the conductive layer 220 is greater than the thickness of the side surface of the barrier layer 210 and the conductive layer 220.

[0072] This embodiment improves the thickness of the barrier layer 210 so that the thickness of the area between the bottom surface of the barrier layer 210 and the conductive layer 220 is greater than the thickness of the area between the side surface of the barrier layer 210 and the conductive layer 220. This reduces part of the thickness of the barrier layer 210, increases the area of ​​the conductive layer 220, and reduces the resistance of the word line structure 200.

[0073] Furthermore, when a voltage is applied to the word line structure 200, charge usually accumulates on the bottom surface of the word line structure 200. Therefore, by increasing the thickness of the area between the bottom surfaces of the barrier layer 210 and the conductive layer 220, the resistance of the word line structure 200 is reduced, and the gate-induced drain leakage current of the semiconductor structure is also reduced.

[0074] In one possible implementation, please refer to the appendix. Figure 3 and attached Figure 4 The conductive layer 220 includes a first segment 221 and a second segment 222. The second segment 222 is connected to the first segment 221 and is located at the end of the first segment 221 facing the substrate 100, and the outer surface of the second segment 222 is arc-shaped. In other words, the first segment 221 is disposed on the second segment 222.

[0075] It should be noted that when the active structure 110 is an active region, part of the word line structure 200 is located within the active region, and part of the word line structure 200 is located within the shallow trench isolation structure of the adjacent active region. (Appendix) Figure 2 The diagram only shows a schematic of the word line structure 200 within the active region. When the active structure 110 is the active region, with the section perpendicular to the substrate 100 as the longitudinal section, the longitudinal section shape of the first segment 221 is cylindrical, and the longitudinal section shape of the second segment 222 is conical.

[0076] When the active structure 110 is a columnar active column, the longitudinal cross-sectional shape of the first segment 221 is a hollow annular structure, and the first segment 221 surrounds at least the outer peripheral surface of the channel region of the active column. The longitudinal cross-sectional shape of the second segment 222 is a hollow annular structure, and it is connected to the bottom end of the first segment 221.

[0077] A barrier layer 210 is disposed between the conductive layer 220 and the substrate 100, and the barrier layer 210 covers the second segment 222 and at least part of the first segment 221.

[0078] Along the direction from the top surface of the first segment 221 to the bottom surface of the first segment 221, the thickness of the barrier layer 210 is constant; along the direction from the top surface of the second segment 222 to the bottom surface of the second segment 222, the thickness of the barrier layer 210 gradually increases, making the thickness of the lowest end of the barrier layer 210 the largest. In this embodiment, the thickness of the barrier layer 210 is not uniform, but varies linearly. In this way, a conductive layer 220 can be formed at the location of the reduced barrier layer 210, thereby increasing the area of ​​the first segment 221 of the conductive layer 220, thereby reducing the resistance of the word line structure 200 and improving the performance of the semiconductor structure.

[0079] In addition, the thickness of the barrier layer 210 is the greatest at the lowest end, which can reduce or even avoid the risk of the barrier layer 210 being broken down, and reduce the defect of gate-induced drain leakage current in the semiconductor structure.

[0080] In this example, the barrier layer 210 is made of conductive materials such as titanium nitride. Titanium nitride prevents penetration between the conductive material in the word line structure 200 and the substrate 100 while simultaneously providing conductivity, thus ensuring the performance of the semiconductor device. The conductive layer 220 is made of tungsten metal, which has good conductivity and low resistance, improving the performance of the semiconductor structure.

[0081] In one possible implementation, please continue to refer to the appendix. Figure 2 and attached Figure 3 The barrier layer 210 includes a first barrier layer 211 and a second barrier layer 212. The first barrier layer 211 at least covers a portion of the outer peripheral surface of the conductive layer 220, and the second barrier layer 212 is disposed on the first barrier layer 211, and the second barrier layer 212 at least covers the outer peripheral surface of the second segment 222. In one example, the second barrier layer 212 may only cover the outer peripheral surface of the second segment 222. In another example, the second barrier layer 212 covers the outer peripheral surface of the second segment 222 and also covers a portion of the outer peripheral surface of the first segment 221.

[0082] In this embodiment, by reducing the thickness of the barrier layer 210 in the region opposite to the first segment 221 of the conductive layer 220, the area of ​​the first segment 221 can be increased to the maximum extent, thereby reducing the resistance of the word line structure 200.

[0083] In this embodiment, the thickness of the second barrier layer 212 is greater than the thickness of the first barrier layer 211. For example, the thickness of the second barrier layer 212 is 1.5 to 2 times the thickness of the first barrier layer 211; for instance, the thickness of the first barrier layer 211 is 1 nm to 2 nm, and the thickness of the second barrier layer 212 is 2 nm to 3 nm. This configuration maximizes the thickness of the lowest point of the barrier layer 210, reducing or even eliminating the risk of the barrier layer 210 being broken down, and mitigating the gate-induced drain leakage current defect in the semiconductor structure.

[0084] In one possible implementation, the top surface of the conductive layer 220 is higher than the top surface of the barrier layer 210; for example, the distance between the top surface of the conductive layer 220 and the top surface of the substrate 100 ranges from 30 nm to 90 nm, and the distance between the top surface of the barrier layer 210 and the top surface of the substrate 100 ranges from 30 nm to 120 nm.

[0085] The semiconductor structure also includes an insulating layer 300, which is disposed on the word line structure 200, and the insulating layer 300, the word line structure 200 and the substrate 100 form an air gap 400.

[0086] In this embodiment, the insulating layer 300 is made of silicon nitride; the insulating performance of the air gap 400 is higher than that of the insulating layer 300, which can prevent leakage current from forming between the word line structure 200 and the source / drain region, thereby improving the performance of the semiconductor structure.

[0087] In addition, the low dielectric constant of the air gap 400 can reduce the parasitic capacitance formed by the adjacent word line structure 200, thereby improving the performance of the semiconductor structure.

[0088] Please refer to the attached document. Figure 5 The present disclosure provides a method for fabricating a semiconductor structure, comprising the following steps:

[0089] Step S100: Pattern the substrate to form a plurality of active structures spaced apart within the substrate.

[0090] When the active structure 110 is in the active region, please continue to refer to the appendix. Figure 1 A patterning process is used to form trenches within the substrate 100, and the trenches are filled with an insulating material (such as silicon oxide or silicon oxynitride), thereby defining multiple independent active regions on the substrate 100 by shallow trench isolation structures 120. For example, the patterning process can be a self-aligned double patterning (SADP) process or a self-aligned quadruple patterning (SAQP) process.

[0091] When the active structure 110 is an active pillar, a plurality of second partition grooves are formed in the substrate 100 by a patterning process, which are spaced apart along a second direction. Each second partition groove extends along a first direction. In addition, a first partition groove is formed, which is spaced apart along the first direction. Each first partition groove extends along a second direction. The plurality of first partition grooves and the plurality of second partition grooves divide the substrate 100 into a plurality of relatively independent active pillars.

[0092] It should be noted that the depths of the first and second partition trenches can be different. For example, the depth of the second partition trench is greater than the depth of the first partition trench. This allows the bottoms of the active pillars located in the same second direction to be connected together, so that bit lines can be formed in the area where the bottoms of the active pillars located in the same second direction are connected. This ensures that the voltages of the source or drain regions of the multiple active pillars formed later are the same, thus guaranteeing the critical voltage stability of the semiconductor structure and reducing the floating body effect.

[0093] Step S200: A plurality of word line structures are formed in the substrate at intervals along a first direction; each word line structure extends along a second direction and connects to a plurality of active structures, the plurality of active structures extending along the second direction; each word line structure includes a barrier layer and a conductive layer, the barrier layer is disposed between the substrate and the conductive layer and covers at least a portion of the outer peripheral surface of the conductive layer, wherein the thickness of the bottom area of ​​the barrier layer and the conductive layer is greater than the thickness of the side area of ​​the barrier layer and the conductive layer; the first direction and the second direction intersect.

[0094] For example, please refer to the appendix. Figure 6 Multiple first trenches 130 are formed, the depth direction of the first trenches 130 being perpendicular to the substrate 100. The multiple first trenches 130 are spaced apart along a first direction, and each first trench 130 extends along a second direction.

[0095] Each first trench 130 exposes multiple active structures 110 arranged along the second direction. It should be noted that when the active structure 110 is an active region, the first trench 130 can be formed using a patterning process. The first trench 130 extends along the second direction and penetrates multiple active regions and the shallow trench isolation structure 120 located between adjacent active regions. Furthermore, the depth of the portion of the first trench 130 opposite to the active region is less than the depth of the portion of the first trench 130 opposite to the shallow trench isolation structure 120. When the active structure 110 is an active pillar, the first trench 130 can be formed during the formation of the active pillar; that is, the first partition groove can be understood as the first trench 130.

[0096] After the first groove 130 is formed, please refer to the attached document. Figure 7A dielectric layer 500 is formed on the inner wall of the first trench 130. Exemplarily, a thermal diffusion process or an in-situ steam generation (ISSG) process can be used to form the dielectric layer 500 on the inner wall of the first trench 130. The dielectric layer 500 also extends beyond the first trench 130 and covers the top surface of the substrate 100.

[0097] In this embodiment, the material of the dielectric layer 500 includes silicon oxide, but is not limited to it.

[0098] Please refer to the attached document. Figure 8 A first barrier material layer 213 is formed on the inner wall of the first trench 130 using atomic layer deposition (ALD) or supercritical fluid deposition (SFD). It should be noted that when a dielectric layer 500 is present on the inner wall of the first trench 130, the first barrier material layer 213 covers the dielectric layer 500. The thickness of the first barrier material layer 213 ranges from 1 nm to 2 nm.

[0099] In this embodiment, the first barrier material layer 213 is formed by atomic layer deposition or supercritical fluid deposition at a process temperature of 400℃ to 700℃. This allows the first barrier material layer 213 to have a high step coverage, thereby ensuring the uniformity of the thickness of the first barrier material layer 213 and guaranteeing that the quality of the first barrier material layer 213 meets the requirements.

[0100] Subsequently, a second barrier layer 212 is formed, which partially covers the first barrier material layer 213; for example, please refer to the appendix. Figure 9 A metal layer 214 is formed on the bottom wall and part of the sidewall of the first trench 130 using a plasma deposition process. The metal layer 214 covers part of the first barrier material layer 213. The thickness of the metal layer 214 gradually increases along the direction from the top surface to the bottom surface. The metal layer 214 is a titanium layer.

[0101] In this step, the metal is relatively heavy and is affected by gravity during the deposition process. The metal will be deposited towards the bottom of the first trench 130, so that the formed metal layer 214 mainly covers the bottom wall of the first trench 130, and some of the metal layer 214 is deposited on some side walls of the first trench 130.

[0102] Next, please refer to the appendix. Figure 10The metal layer is nitrided using a rapid nitriding process to form a second barrier layer 212. Exemplarily, at a certain radio frequency power and reaction temperature, a nitrogen-containing gas, such as ammonia, is passed into the reaction chamber. The nitrogen-containing gas reacts with the metal layer 214 to form the second barrier layer 212, the material of which includes titanium nitride.

[0103] In this step, at a reaction temperature of 400℃~700℃ and a radio frequency power of 300W~1500W, nitrogen-containing gas is introduced into the reaction chamber at a gas flow rate of 500sccm~4000sccm. This allows the metal layer 214 and the nitrogen-containing gas to react rapidly, thereby quickly forming the second barrier layer 212 on the first barrier material layer 213 and improving the quality of the second barrier layer 212.

[0104] In the process of forming the second barrier layer 212, an inert gas is passed into the reaction chamber to clean up unreacted nitrogen-containing gas or other impurity particles, thereby improving the surface cleanliness of the second barrier layer 212 and thus facilitating the improvement of the bonding strength between the second barrier layer 212 and the conductive layer 220.

[0105] Please refer to the attached document. Figure 11 A conductive material layer 223 is formed, which fills the area enclosed by the first barrier material layer 213 and the second barrier layer 212, and covers the top surface of the first barrier material layer 213 above the substrate 100.

[0106] In this step, the reaction temperature can be controlled to ensure the uniformity of the formed conductive material layer 223. For example, the conductive material layer 223 is deposited in the region enclosed by the first barrier material layer 213 and the second barrier layer 212 at a reaction temperature of 200°C to 500°C.

[0107] This embodiment prepares the barrier layer 210 in two steps, which allows for flexible adjustment of the ratio of the barrier layer to the conductive layer. This reduces the resistance of the word line structure while preventing gate-induced drain current (GIDL).

[0108] Please refer to the attached document. Figure 12 To be continued Figure 14 Part of the first barrier material layer 213 and the conductive material layer 223 are removed, and the remaining first barrier material layer 213 forms the first barrier layer 211. The first barrier layer 211 and the second barrier layer 212 form the barrier layer; the remaining conductive material layer 223 forms the conductive layer 220.

[0109] For example, please refer to the appendix. Figure 12Chemical mechanical polishing (CMP) is used to polish the semiconductor structure to remove the film layer on the top surface of the substrate 100, so that the top surface of the remaining conductive material layer 223 is flush with the top surface of the substrate 100.

[0110] Next, please refer to the appendix. Figure 13 By utilizing the different materials of the conductive material layer 223, the first barrier material layer 213, and the dielectric layer 500, the etching selectivity of the etching process can be reasonably adjusted so that the etching rate of the first barrier material layer 213 is greater than the etching rate of the conductive material layer 223. This removes a first preset thickness of the conductive material layer 223, leaving the remaining conductive material layer 223 to form the conductive layer 220. The material of the conductive layer 220 is tungsten, and its thickness is 10nm to 50nm. Simultaneously, a second preset thickness of the first barrier material layer 213 is removed, leaving the remaining first barrier material layer 213 to form the first barrier layer 211. The first preset thickness is less than the second preset thickness; for example, the first preset thickness ranges from 30nm to 90nm, and the second preset thickness ranges from 30nm to 120nm. This configuration allows the top surface of the conductive layer 220 to be lower than the top surface of the first barrier layer 211. It should be noted that the above formation steps are for the active structure 110 as the active region, and the formed structure is a buried gate structure.

[0111] When the active structure 110 is an active pillar, the above process differs. For example, the conductive material layer 223 located on the top surface of the substrate 100 and a portion of the thickness located within the first trench 130 is removed, as well as the first barrier material layer 213 located within the first trench 130 is removed; the remaining conductive material layer 223 constitutes an intermediate conductive material layer, and the remaining first barrier material layer 213 constitutes a first barrier layer 211.

[0112] Next, please refer to the appendix. Figure 14 The intermediate conductive material layer is further partially removed to form a second trench 224 within the intermediate material layer, the second trench 224 extending along a second direction. The depth direction of the second trench 224 is parallel to the direction perpendicular to the substrate 100, and the second trench 224 exposes the substrate 100 to separate the intermediate conductive material layer, such that the remaining intermediate conductive material layer constitutes the conductive layer 220. The conductive layer 220 surrounds at least a portion of the outer peripheral surface of the active pillar to form a fully surrounding gate structure or a semi-surround gate structure.

[0113] Please continue to refer to section 3 and appendix. Figure 4An insulating layer 300 can be formed on the word line structure 200 using a deposition process. The insulating layer 300 is used to achieve insulation between adjacent word line structures 200, and the top surface of the insulating layer 300 is flush with the top surface of the substrate 100. The deposition process includes any one of the following: chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

[0114] An insulating layer 300, a word line structure 200, and a substrate 100 form an air gap 400. In this embodiment, the insulating layer 300 is made of silicon nitride; the insulating performance of the air gap 400 is higher than that of the insulating layer 300, which can prevent leakage current from forming between the word line structure 200 and the source / drain region, thereby improving the performance of the semiconductor structure.

[0115] In addition, the air gap 400 can reduce the parasitic capacitance between adjacent word line structures 200, thereby improving the performance of the semiconductor structure.

[0116] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0117] In the description of this specification, references to terms such as “one embodiment,” “some embodiments,” “illustrative embodiment,” “example,” “specific example,” or “some examples” refer to specific features, structures, materials, or characteristics described in connection with an embodiment or example that are included in at least one embodiment or example of this disclosure.

[0118] In this specification, the illustrative expressions of the terms used do not necessarily refer to the same implementation or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more implementations or examples.

[0119] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, The steps include the following: A patterned substrate is used to form a plurality of active structures spaced apart within the substrate, the active structures including active pillars, the plurality of active pillars being arranged in a multi-row, multi-column array; Multiple word line structures are formed within the substrate at intervals along a first direction; each word line structure extends along a second direction and connects to multiple active structures, which also extend along the second direction; each word line structure includes a barrier layer and a conductive layer, the barrier layer being disposed between the substrate and the conductive layer and at least covering a portion of the outer peripheral surface of the conductive layer, wherein the thickness of the region opposite the bottom surface of the barrier layer and the conductive layer is greater than the thickness of the region opposite the side surface of the barrier layer and the conductive layer, and the thickness of the lowest end of the barrier layer is the greatest; the first direction intersects the second direction; The steps for forming multiple word line structures include: A plurality of first trenches are formed, the plurality of first trenches are spaced apart along the first direction, and each first trench extends along the second direction and exposes a plurality of active structures, wherein the plurality of active structures are arranged along the second direction; A first barrier material layer is formed, which covers the inner wall of the first trench; A second barrier layer is formed, which covers a portion of the first barrier material layer; A conductive material layer is formed, which fills the area enclosed by the first barrier material layer and the second barrier layer; By removing a portion of the first barrier material layer and the conductive material layer, the remaining first barrier material layer constitutes a first barrier layer, and the first barrier layer and the second barrier layer constitute a barrier layer; the remaining conductive material layer constitutes a conductive layer.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The steps for forming the second barrier layer include: A metal layer is formed on the bottom wall and part of the sidewall of the first trench using a plasma deposition process, the metal layer covering part of the first barrier material layer; wherein, the thickness of the metal layer gradually increases along the direction from the top surface to the bottom surface. The metal layer is nitrided using a rapid nitriding process to form a second barrier layer.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that, The step of removing a portion of the first barrier material layer and the conductive material layer further includes, Remove the conductive material layer located on the top surface of the substrate and a portion of the thickness located within the first trench, as well as the first barrier material layer after removing a portion located within the first trench; The retained conductive material layer constitutes an intermediate conductive material layer, and the retained first barrier material layer constitutes a first barrier layer. A second trench is formed within the intermediate conductive material layer, the second trench extending along a second direction and exposing the substrate; the remaining intermediate conductive material layer constitutes a conductive layer, wherein the conductive layer surrounds at least a portion of the outer peripheral surface of the active pillar.

4. The method for preparing a semiconductor structure according to any one of claims 1-3, characterized in that, After the step of forming a plurality of the first trenches in the substrate and before the step of forming the first barrier material layer, the method further includes: A dielectric layer is formed on the inner wall of the first trench.

5. A semiconductor structure, said semiconductor structure being prepared using the method for preparing a semiconductor structure as described in any one of claims 1-4, characterized in that, include: The substrate includes a plurality of active structures spaced apart, each active structure including an active pillar, the plurality of active pillars being arranged in a multi-row, multi-column array. Multiple word line structures are arranged at intervals along a first direction within the substrate; Each word line structure extends along a second direction and connects to a plurality of active structures arranged along the second direction, and at least covers a portion of the outer peripheral surface of the active pillar; each word line structure includes a barrier layer and a conductive layer, the barrier layer being disposed between the substrate and the conductive layer, and at least covering a portion of the outer peripheral surface of the conductive layer, wherein the thickness of the region opposite the bottom surface of the barrier layer and the conductive layer is greater than the thickness of the region opposite the side surface of the barrier layer and the conductive layer, and the thickness of the lowest end of the barrier layer is the greatest; the first direction intersects the second direction.

6. The semiconductor structure according to claim 5, characterized in that, The conductive layer includes a first segment and a second segment, the second segment being disposed at one end of the first segment facing the bottom surface of the substrate, and the outer surface of the second segment being arc-shaped; The thickness of the barrier layer is the same along the direction from the top surface of the first segment to the bottom surface of the first segment; The thickness of the barrier layer gradually increases along the direction from the top surface of the second segment to the bottom surface of the second segment.

7. The semiconductor structure according to claim 6, characterized in that, The barrier layer includes a first barrier layer and a second barrier layer; The first barrier layer covers at least a portion of the outer peripheral surface of the conductive layer, and the second barrier layer is disposed on the first barrier layer, and the second barrier layer covers at least the outer peripheral surface of the second segment.

8. The semiconductor structure according to claim 7, characterized in that, The thickness of the second barrier layer is 1.5 to 2 times the thickness of the first barrier layer.

9. The semiconductor structure according to any one of claims 5-8, characterized in that, The top surface of the conductive layer is higher than the top surface of the barrier layer; The semiconductor structure further includes an insulating layer disposed on the word line structure, and the insulating layer, the word line structure, and the substrate form an air gap.

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