A semiconductor device structure and a method for manufacturing the same

Abstract

The present invention discloses a semiconductor device structure and a method for preparing the same. The method includes the following steps: forming a shallow trench isolation element on a semiconductor substrate; forming a plurality of bitline structures distributed in an array on the shallow trench isolation element; the bitline structures including bitlines and bitline sidewalls located on opposite sidewalls of the bitlines; depositing a semiconductor material layer on the plurality of bitline structures; partially etching back the top of the semiconductor material layer, and then partially removing the outer layer, middle layer, and semiconductor material layer of the bitline sidewalls using a wet etching process to form a buried contact; depositing a metal fill layer on the buried contact of the bitline structure, and partially etching back the metal fill layer. The present application eliminates the LP process and only partially removes the outer layer and middle layer of the bitline structure sidewalls using a wet etching process after partial etching back, thereby maximizing the area of ​​the top portion of the contact portion, ensuring the contact area of ​​the capacitor, improving process efficiency, and saving costs.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor manufacturing, and in particular relates to a semiconductor device structure and a preparation method thereof. Background Art

[0002] DRAM (Dynamic Random Access Memory) is a type of semiconductor memory widely used in various electronic devices. During DRAM manufacturing, directly connecting the connection terminals between the capacitor (SN, storage node) and the shallow trench isolation (STI) to the storage node contact (SNC) results in insufficient capacitor contact area. Therefore, a landing pad (LP) is added to connect the SN and SNC to increase the capacitor contact area.

[0003] However, the LP process is very complex and includes multiple process steps (up to 30 to 40 process steps) such as LP Patterning, which greatly reduces process efficiency and increases process costs. Summary of the Invention

[0004] In order to solve the problems of complex process, low process efficiency and high cost in the existing technology of DRAM manufacturing using LP process, the present invention proposes a semiconductor device structure and its preparation method. The present invention eliminates the LP process and only adopts the method of wet enlargement to increase the area of ​​the Buried Contact Top part. Since the LP process is omitted, the process steps are reduced, the process efficiency is improved, and the process cost is saved.

[0005] The present invention is achieved through the following technical solutions:

[0006] A semiconductor device structure and a method for manufacturing the same, the method comprising the following steps:

[0007] providing a semiconductor substrate;

[0008] forming a shallow trench isolation member on the semiconductor substrate;

[0009] A plurality of bit line structures distributed in an array are formed on the shallow trench isolation member; the bit line structure comprises a bit line and a bit line sidewall located on opposite sidewalls of the bit line; the bit line sidewall is a three-layer structure, wherein the outer and inner layers are both nitride layers, and the middle layer is an oxide layer;

[0010] depositing a semiconductor material layer on the plurality of bit line structures;

[0011] Partially etching back the top of the semiconductor material layer, and then partially removing the outer layer, the middle layer and the semiconductor material layer of the bit line sidewall using a wet etching process to form a buried contact portion; the top surface of the buried contact portion is located between the top surface of the bit line and the ground;

[0012] A metal filling layer is deposited on the buried contact portion of the bit line structure, and a portion of the metal filling layer is etched back.

[0013] In the preparation of DRAM devices, the LP process is usually used to increase the contact area of ​​the capacitor and realize the connection between the capacitor and the buried contact part. However, the LP process is complex and includes more than 30 process steps, resulting in low preparation process efficiency and high process cost. The present application removes the LP process and only partially removes the outer layer and middle layer of the bit line structure side wall through a wet etching process after partial back etching, thereby maximizing the area of ​​the top part of the contact part and ensuring the contact area of ​​the capacitor. At the same time, due to the cancellation of the LP process, the process steps are greatly reduced, the process efficiency is improved, and the cost is saved.

[0014] In addition, the present application deposits a metal layer above the buried contact portion to reduce resistance and further improve process efficiency.

[0015] As a preferred embodiment, the step of forming a shallow trench isolation on a semiconductor substrate of the present invention further includes:

[0016] etching an isolation trench with a depth of 0.3 to 0.8 μm on the surface of the semiconductor substrate using a dry etching process;

[0017] growing a linear oxide layer on the surface of the isolation trench and filling it with CVD oxygen;

[0018] CMP is used to smooth the surface to form shallow trench isolations.

[0019] The present application adopts the STI process to form a shallow trench isolation member, thereby improving the depth-to-width ratio of the isolation trench and ensuring the performance of the DRAM device.

[0020] As a preferred embodiment, the step of forming a plurality of bit line structures distributed in an array on the shallow trench isolation of the present invention further includes:

[0021] sequentially depositing a metal layer and a mask layer above the shallow trench isolation member;

[0022] Sequentially etching the mask layer and the metal layer from top to bottom to form a plurality of bit lines distributed in an array;

[0023] An insulating material layer is deposited above the plurality of bit lines, and the insulating material layer is etched into bit line sidewalls located on opposite sidewalls of the plurality of bit lines to form a bit line structure.

[0024] As a preferred embodiment, the metal layer of the present invention is made of tungsten; and the mask layer is made of silicon nitride.

[0025] As a preferred embodiment, the top surface of the buried contact portion of the present invention is located at half the height of the bit line structure.

[0026] As a preferred embodiment, the semiconductor substrate of the present invention is a silicon wafer;

[0027] The semiconductor material layer is made of silicon;

[0028] The metal filling layer is made of tungsten.

[0029] As a preferred embodiment, the present invention adopts a partial etching back process or CMP to partially etch back the metal filling layer.

[0030] As a preferred embodiment, the wet etching process of the present invention adopts HF Based Etchant or phosphoric acid method.

[0031] In a second aspect, the present invention provides a semiconductor device structure, which is manufactured using the manufacturing method of the present invention.

[0032] In a third aspect, the present invention provides a DRAM device structure, which is manufactured using the manufacturing method of the present invention.

[0033] The present invention has the following advantages and beneficial effects:

[0034] In the preparation of DRAM devices, an LP process is typically used to increase the contact area of ​​the capacitor and achieve connection between the capacitor and the buried contact portion. However, the LP process is complex, including more than 30 process steps, resulting in low preparation process efficiency and high process cost. Compared with using the LP process to increase the contact area of ​​the capacitor, the semiconductor preparation method provided by the present invention only partially removes the outer and middle layers of the bit line structure sidewall through a wet etching process after partial back etching, thereby maximizing the area of ​​the top portion of the contact portion and ensuring the contact area of ​​the capacitor. At the same time, since the LP process is eliminated, the DRAM device manufacturing process is greatly reduced, the manufacturing process efficiency is improved, and costs are saved.

[0035] The semiconductor manufacturing method proposed by the present invention utilizes the STI process to form shallow trench isolation, thereby improving the depth-to-width ratio of the isolation trench and ensuring the performance of the DRAM device.

[0036] The semiconductor manufacturing method proposed in the present invention has better resistance performance by depositing a metal layer above the contact portion, thereby further improving process efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The drawings described herein are used to provide a further understanding of the embodiments of the present invention, constitute a part of this application, and do not constitute a limitation of the embodiments of the present invention. In the drawings:

[0038] Figure 1 This is a flow chart of the existing LP process.

[0039] Figure 2 This is a cross-sectional diagram of the existing LP process.

[0040] Figure 3 Flowchart of a method according to an embodiment of the present invention.

[0041] Figure 4 It is a cross-sectional view of the implementation process of an embodiment of the present invention.

[0042] Markings and corresponding parts names in the accompanying drawings:

[0043] 101-semiconductor substrate, 102-shallow trench isolation (STI), 103-bit line structure (Bit Line), 110-bit line, 111-metal layer, 112-mask layer, 120-bit line sidewall (NON structure), 104-semiconductor material layer, 105-first buried contact, 106-landing pad (LP), 107-second buried contact, 108-metal filling layer. DETAILED DESCRIPTION

[0044] Hereinafter, the terms "include" or "may include" used in various embodiments of the present invention indicate the presence of the invented function, operation or element, and do not limit the addition of one or more functions, operations or elements. In addition, as used in various embodiments of the present invention, the terms "include", "have" and their cognates are intended only to indicate specific features, numbers, steps, operations, elements, components or combinations of the foregoing, and should not be understood as excluding the presence of one or more other features, numbers, steps, operations, elements, components or combinations of the foregoing or the possibility of adding one or more features, numbers, steps, operations, elements, components or combinations of the foregoing.

[0045] In various embodiments of the present invention, the expression "or" or "at least one of A or / and B" includes any or all combinations of the words listed simultaneously. For example, the expression "A or B" or "at least one of A or / and B" may include A, may include B, or may include both A and B.

[0046] The expressions (such as "first", "second", etc.) used in the various embodiments of the present invention may modify the various constituent elements in the various embodiments, but may not limit the corresponding constituent elements. For example, the above expressions do not limit the order and / or importance of the elements. The above expressions are only used to distinguish one element from other elements. For example, a first user device and a second user device indicate different user devices, although both are user devices. For example, without departing from the scope of the various embodiments of the present invention, a first element may be referred to as a second element, and similarly, a second element may also be referred to as a first element.

[0047] It should be noted that when a component is described as being “connected” to another component, the first component may be directly connected to the second component, and a third component may be “connected” between the first and second components. Conversely, when a component is described as being “directly connected” to another component, it can be understood that there is no third component between the first and second components.

[0048] The terms used in various embodiments of the present invention are only used to describe the purpose of specific embodiments and are not intended to limit the various embodiments of the present invention. As used herein, the singular form is intended to also include the plural form, unless the context clearly indicates otherwise. Unless otherwise limited, all terms used here (including technical terms and scientific terms) have the same meaning as those of ordinary skill in the art generally understood by the various embodiments of the present invention. The terms (such as those defined in generally used dictionaries) will be interpreted as having the same meaning as the contextual meaning in the relevant technical field and will not be interpreted as having idealized meaning or too formal meaning, unless clearly defined in various embodiments of the present invention.

[0049] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with examples and drawings. The exemplary embodiments of the present invention and their descriptions are only used to explain the present invention and are not intended to limit the present invention.

[0050] Example

[0051] During the manufacturing process of DRAM devices, the LP process is usually used to connect the capacitor and the buried contact. The process is as follows: Figure 1-2As shown, a semiconductor substrate 101 (silicon wafer) is provided. First, isolation trenches with a depth of 0.3 to 0.8 μm are etched on the surface of the semiconductor substrate 101 using dry etching. These isolation trenches have right angles and rounded corners, and the aspect ratio of the isolation trenches is approximately 2:1 to 5:1. A linear oxide layer is grown on the surface of the isolation trenches, filled with CVD oxygen, and smoothed using CMP to form shallow trench isolation (STI) 102. Then, a plurality of array-distributed bit line structures 103 are formed on the shallow trench isolation STI 102, wherein the bit line structure 103 includes A metal layer 111 (which may be a metal material with good thermal conductivity such as tungsten) and a mask layer 112 (which may be a nitride, such as silicon nitride) are sequentially deposited above 102, and then the mask layer 112 and the metal layer 111 are sequentially etched from top to bottom to form a plurality of bit lines 110 distributed in an array; finally, an insulating material layer is deposited above the plurality of bit lines 110, and then the insulating material layer is etched into bit line sidewalls 120 located on opposite sidewalls of the plurality of bit lines 110 to form a bit line structure 103, wherein the bit line sidewalls 120 may be a multi-layer structure of nitride-oxide-nitride (i.e., a NON structure, in which the outer and inner layers are both nitride and the middle layer is oxide); finally, a semiconductor material layer 104 (silicon) is deposited on the plurality of bit line structures 103 to obtain the following. Figure 2 Then the semiconductor material layer 104 is partially etched to form a first buried contact portion 105, the top surface of the first buried contact portion 105 can be located between the top and bottom surfaces of the mask layer 112, and the bottom end of the first buried contact portion 105 is connected to the STI 102, to obtain Figure 2 Finally, after forming the first buried contact portion 105, a landing pad 106 is formed above the bit line structure 103 and the first buried contact portion 105, to obtain Figure 2 The structure shown in (c) is as follows; after the landing pad LP is formed, the capacitor (CAP) is connected to the STI 102 through the landing pad LP. The existing method of connecting the capacitor to the buried contact through LP is very complicated because the LP process includes 30 to 40 process steps including the pad patterning process, resulting in low manufacturing process efficiency and high cost. Based on this, the present embodiment provides a method for preparing a semiconductor device structure, which cancels the LP process. The method deposits a polysilicon structure on the mask contact, and then removes part of the insulating material layer through a partial back etching process. The outer nitride and the intermediate oxide of the bit line sidewall are removed through a wet etching process, thereby maximizing the top area of ​​the mask contact and ensuring the contact area of ​​the capacitor. At the same time, since the LP process is not adopted, the process complexity is reduced, the process efficiency is improved, and the process cost is reduced.

[0052] Specific as Figure 3-4As shown, the preparation method proposed in this embodiment includes the following steps:

[0053] Step 1: Provide a semiconductor substrate 101, and form a polysilicon structure on the semiconductor substrate 101 to obtain Figure 4 The structure shown in (a).

[0054] The process is the same as the existing technology, specifically including:

[0055] First, isolation trenches with a depth of 0.3 to 0.8 μm are etched on the surface of the semiconductor substrate 101 using dry etching. These isolation trenches have right angles and rounded corners. A linear oxide layer is grown on the surface of the isolation trenches, filled with CVD oxygen, and smoothed using CMP to form shallow trench isolation (STI) 102.

[0056] Then, a bit line structure 103 is formed on the shallow trench isolation STI 102, wherein the bit line structure 103 includes a metal layer 111 and a mask layer 112 sequentially deposited above the STI 102, and then the mask layer 112 and the metal layer 111 are sequentially etched from top to bottom to form a plurality of bit lines 110 distributed in an array; an insulating material layer is deposited above the plurality of bit lines 110, and then the insulating material layer is etched into bit line sidewalls 120 located on opposite sidewalls of the plurality of bit lines 110 to form the bit line structure 103, and finally a semiconductor material layer 104 is deposited on the plurality of bit line structures 103; specifically, the bit line sidewalls 120 adopt a multi-layer structure in which both the outer and inner layers are nitride layers and the middle layer is an oxide layer, i.e., a NON structure.

[0057] Step 2: partially etch back the polysilicon structure through the polysilicon partial etch back process, and then partially remove the outer nitride layer, the middle oxide layer and the contact part of the bit line structure by the wet etching process to obtain the following: Figure 4 The structure shown in (b).

[0058] Specifically, the top of the semiconductor material layer 104 is partially etched back, and then the outer layer (nitride layer), the middle layer (oxide layer) of the bit line spacer 120 and the semiconductor material layer 104 are removed by a wet etching process, thereby forming a second buried contact portion 107. The second buried contact portion 107 can be located between the top and bottom surfaces of the mask layer 112. Preferably, the top surface of the second buried contact portion 107 is located at half the height of the bit line structure 103; then, the bit line spacer 120 is wet etched to remove the outer nitride layer and the middle oxide layer, thereby maximizing the area of ​​the top of the buried contact portion, and obtaining the following: Figure 4 Preferably, the wet etching process can adopt HF Based Etchant or phosphoric acid method.

[0059] Step 3: deposit a metal filling layer 108 on the bit line structure 103 and the second buried contact portion 107, and then partially etch back the metal filling layer 108 by using an etch-back process or CMP to obtain the following: Figure 4 By depositing a metal layer on the bit line structure 103 and the second buried contact portion 107, the metal layer can be made of a material with good thermal conductivity such as tungsten to reduce obstruction and further improve process efficiency.

[0060] In the fabrication of DRAM devices, an LP process is typically used to increase the contact area of ​​capacitors and achieve connection between the capacitors and buried contacts. However, the LP process is complex, involving more than 30 steps, resulting in low fabrication efficiency and high process costs. The fabrication method proposed in the embodiments of the present invention utilizes a wet etching process only on the top of the contacts to increase the area of ​​the top portion of the contacts, thereby enabling DRAM fabrication without the LP process. Because the fabrication method proposed in the embodiments of the present invention does not utilize the LP process, all LP-related processes are eliminated during the DRAM fabrication process. For example, both patterning processes are eliminated, effectively reducing process complexity, improving process efficiency, and lowering process costs.

[0061] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for preparing a semiconductor device structure, characterized in that: The method comprises the following steps: providing a semiconductor substrate; forming a shallow trench isolation member on the semiconductor substrate; A plurality of bit line structures distributed in an array are formed on the shallow trench isolation member; the bit line structure comprises a bit line and a bit line sidewall located on opposite sidewalls of the bit line; the bit line sidewall is a three-layer structure, wherein the outer and inner layers are both nitride layers, and the middle layer is an oxide layer; depositing a semiconductor material layer on the plurality of bit line structures; Partially etching back the top of the semiconductor material layer, and then partially removing the outer layer, the middle layer and the semiconductor material layer of the bit line sidewall using a wet etching process to form a buried contact portion; the top surface of the buried contact portion is located between the top surface of the bit line and the ground; A metal filling layer is deposited on the buried contact portion of the bit line structure, and the metal filling layer is partially etched back to make the top surface of the metal filling layer flush and lower than the top surface of the bit line.

2. The method for preparing a semiconductor device structure according to claim 1, wherein: The step of forming a shallow trench isolation member on the semiconductor substrate further includes: etching an isolation trench with a depth of 0.3 to 0.8 μm on the surface of the semiconductor substrate using a dry etching process; growing a linear oxide layer on the surface of the isolation trench and filling it with CVD oxygen; CMP is used to smooth the surface to form shallow trench isolation features.

3. The method for preparing a semiconductor device structure according to claim 1, wherein: The step of forming a plurality of bit line structures distributed in an array on the shallow trench isolation element further includes: sequentially depositing a metal layer and a mask layer above the shallow trench isolation member; Sequentially etching the mask layer and the metal layer from top to bottom to form a plurality of bit lines distributed in an array; An insulating material layer is deposited above the plurality of bit lines, and the insulating material layer is etched into bit line sidewalls located on opposite sidewalls of the plurality of bit lines to form a bit line structure.

4. The method for preparing a semiconductor device structure according to claim 3, wherein: The metal layer is made of tungsten; the mask layer is made of silicon nitride.

5. The method for preparing a semiconductor device structure according to claim 1, wherein: A top surface of the buried contact is located at half the height of the bit line structure.

6. A method for preparing a semiconductor device structure according to any one of claims 1 to 5, characterized in that: The semiconductor substrate is a silicon wafer; The semiconductor material layer is made of silicon; The metal filling layer is made of tungsten.

7. A method for preparing a semiconductor device structure according to any one of claims 1 to 5, characterized in that: The metal filling layer is partially etched back using a partial etch-back process or CMP.

8. The method for preparing a semiconductor device structure according to any one of claims 1 to 5, wherein: The wet etching process uses a hydrofluoric acid-based etchant or a phosphoric acid-based etchant.

9. A semiconductor device structure, characterized in that: The invention is prepared by the preparation method according to any one of claims 1 to 8.

10. A DRAM device structure, characterized in that: The invention is prepared by the preparation method according to any one of claims 1 to 8.

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